Instruction conversion method and device

Abstract

The embodiment of the present application provides an instruction conversion method and device, which can balance the load of the scalar execution unit and the vector execution unit of a computer device and improve the utilization rate of the execution unit. The method is applied to a computer device including a first type of execution unit and a second type of execution unit, the first type of execution unit is used to execute a first type of instruction, and the second type of execution unit is used to execute a second type of instruction. The method includes: obtaining an instruction set including at least two instructions according to a source program, and the type of any one of the at least two instructions is a first type or a second type; converting some or all of the first type of instructions in the instruction set into instructions of the second type according to a policy rule, and the policy rule balances the load of the first type of execution unit and the second type of execution unit. The first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction; or, the first type of instruction is a SISD instruction, and the second type of instruction is a SIMD instruction.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction conversion method and device. Background Art

[0002] Generally, when processing computationally intensive tasks (such as encryption and decryption, hashing) that rely on parallelism to improve performance, the use of single instruction multiple data (SISD) technology can bring considerable performance improvements to the program compared to single instruction single data (SISD) technology. For example, in the x86 environment, the RSA 2048 algorithm accelerated by SIMD instructions in OpenSSL v1.0.2 can improve the performance of the RSA 2048 algorithm by 39.1% compared to the RSA 2048 algorithm implemented by SISD instructions in OpenSSL v1.0.1.

[0003] At present, the industry mainly uses SIMD technology to accelerate programs through compiler automation. That is, when compiling the source program, the automatic vectorization option provided by the compiler is used to rely on the compiler to replace all optimizable SIMD instructions in the source program with SIMD instructions.

[0004] However, after all optimizable SISD instructions are replaced with SIMD instructions, the execution unit (PU) (called vector execution unit) of the central processing unit (CPU) used to execute SIMD instructions may run at a high load, while the PU (called scalar execution unit) used to execute SISD instructions is in a light-load state, resulting in uneven loads on the scalar execution unit and the vector execution unit, and low average utilization of the execution unit. Summary of the invention

[0005] The embodiments of the present application provide an instruction conversion method and apparatus, which can balance the load of a scalar execution unit and a vector execution unit of a computer device, improve the utilization rate of the execution unit, and thus improve the performance of the computer device.

[0006] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0007] In the first aspect, an embodiment of the present application provides an instruction conversion method, which can be executed by a computer device or by a component of the computer device, such as a processor, a chip, or a chip system of the computer device. The method is applied to a computer device, which includes a first type of execution unit and a second type of execution unit, the first type of execution unit is used to execute a first type of instruction, and the second type of execution unit is used to execute a second type of instruction, the method comprising: obtaining an instruction set according to a source program, the execution set includes at least two instructions, and the type of any one of the at least two instructions is a first type or a second type; according to a policy rule, converting some or all of the first type of instructions in the instruction set into a second type of instruction, and the policy rule makes the load of the first type of execution unit and the second type of execution unit balanced. Wherein, the first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction; or, the first type of instruction is a SISD instruction, and the second type of instruction is a SIMD instruction.

[0008] In an embodiment of the present application, when executing instruction conversion, some or all of the first type of instructions can be converted into second type of instructions according to the strategy rules, and the strategy rules can balance the load of the first type of execution unit and the second type of execution unit. Therefore, the present application can balance the load of the first type of execution unit and the second type of execution unit, improve the utilization rate of the execution unit, and thus improve the performance of the computer device.

[0009] In some possible designs, the policy rule indicates that the first type of instruction in the first instruction relationship subtree is converted into the second type of instruction, and the first instruction relationship subtree is a subtree of the instruction relationship tree composed of at least two instructions included in the above instruction set. Based on this possible design, instruction conversion can be performed according to the instruction relationship tree to reduce the complexity of the instruction conversion strategy.

[0010] In some possible designs, the instruction set includes a first instruction set, an initial set of the first instruction set includes at least two first instructions, the first instruction is a first type of instruction for implementing a first operation, the policy rule indicates that part of the first instructions in the first instruction set are converted into M second instructions, the second instruction is a second type of instruction for implementing the first operation, and M is a positive integer. Based on this possible design, the instructions for implementing each operation in the instruction set can be converted separately according to the operation implemented by the instruction, so as to improve the accuracy of the instruction conversion, thereby more effectively achieving load balancing between the first type of execution unit and the second type of execution unit.

[0011] In some possible designs, the policy rule indicates that part of the first instructions in the first instruction set are converted into M second instructions, including: the policy rule indicates that when the first instruction and the second instruction are executed in parallel, part of the first instructions in the first instruction set are converted into M second instructions. Based on this possible design, when the first instruction and the second instruction are executed in parallel, part of the first instructions in the first set are converted into M second instructions, so that both the first type of execution unit and the second type of execution unit can be used.

[0012] In some possible designs, the ratio of M to K is determined by a first value and a second value, K is the number of the first instructions in another part of the first instruction set, the first value is determined by a first duration and a first quantity, the second value is determined by a second duration and a second quantity, the first duration is the duration used by a first execution unit to execute a first instruction, the first quantity is the number of first execution units included in the computer device, the second duration is the duration used by a second execution unit to execute a second instruction, and the second quantity is the number of second execution units included in the computer device. Based on this possible design, the number of converted second instructions and first instructions can be determined in combination with the hardware characteristics of the computer device, so that instruction conversion can be performed more finely according to the hardware differences of different computer devices, thereby improving the accuracy of load balancing.

[0013] In some possible designs, the ratio of M to K is determined by the first value and the second value, including: the ratio of M to K is determined by the first value, the second value, and an instruction relationship tree consisting of at least two instructions included in the above instruction set. Based on this possible design, the number of the converted second instructions and the first instruction can be determined in combination with the hardware characteristics of the computer device and the characteristics of the instruction set, further improving the accuracy of load balancing.

[0014] In some possible designs, the first value, the first duration, and the first quantity satisfy the following formula:

[0015]

[0016] in, is the first value, T1 is the first duration, is the first quantity.

[0017] In some possible designs, the first duration is determined by a first number and a first time difference, where the first number is the number of first operations implemented by a first instruction, and the first time difference is the time difference between the duration used to implement n first operations using the first instruction and the duration used to implement m first operations using the first instruction, where n and m are positive integers, and n is greater than m.

[0018] In some possible designs, the first duration, the first number, and the first time difference satisfy the following formula:

[0019]

[0020] Among them, T1 is the first duration, For the first number, is the first time difference, is the time taken to implement n first operations using the first instruction, The time taken to implement m first operations using the first instruction.

[0021] In some possible designs, the second value, the second duration, and the second quantity satisfy the following formula:

[0022]

[0023] in, is the second value, T2 is the second duration, is the second quantity.

[0024] In some possible designs, the second duration is determined by a second number and a second time difference, where the second number is the number of first operations implemented by a second instruction, and the second time difference is the time difference between the duration used to implement n times the first operation using the second instruction and the duration used to implement m times the first operation using the second instruction, where n and m are positive integers, and n is greater than m.

[0025] In some possible designs, the second duration, the second number, and the second time difference satisfy the following formula:

[0026]

[0027] Among them, T2 is the second duration, For the second number, is the second time difference, is the time taken to implement the first operation n times using the second instruction, The time taken to implement the first operation m times using the second instruction.

[0028] In some possible designs, the above-mentioned instruction set includes a second instruction set, the initial set of the second instruction set includes at least one third instruction, the third instruction is an instruction of the first type for implementing the second operation, the policy rule indicates that when the third numerical value is less than or equal to the fourth numerical value, all third instructions in the second instruction set are converted into fourth instructions, the fourth instruction is an instruction of the second type for implementing the second operation, the third numerical value is determined by a third duration and a third quantity, the fourth numerical value is determined by a fourth duration and a fourth quantity, the third duration is the duration used by a third execution unit to execute a third instruction, the third quantity is the number of third execution units included in the computer device, the fourth duration is the duration used by a fourth execution unit to execute a fourth instruction, and the fourth quantity is the number of fourth execution units included in the computer device.

[0029] Based on this possible design, instructions implementing various operations in the instruction set can be converted separately according to the operations implemented by the instructions, thereby improving the accuracy of instruction conversion, thereby more effectively achieving load balancing between the first type of execution unit and the second type of execution unit.

[0030] In some possible designs, the policy rule indicates that when the third numerical value is less than or equal to the fourth numerical value, all third instructions in the third instruction set are converted into fourth instructions, including: when the policy rule indicates that the third instruction and the fourth instruction are not executed in parallel, and the third numerical value is less than or equal to the fourth numerical value, all third instructions in the third instruction set are converted into fourth instructions.

[0031] In some possible designs, the instruction conversion method further includes: when the instruction set includes instructions of the first type, storing the instructions of the first type in the instruction set to the first instruction cache. Based on this possible design, classified storage of different types of instructions can be implemented, so that when obtaining instructions, instructions of the required type can be obtained based on the classified storage.

[0032] In some possible designs, the instruction conversion method further includes: obtaining status information of a first microinstruction cache queue, the first microinstruction cache queue being used to cache micro-operations of instructions of the first type; and determining the number of instructions of the first type to be obtained from the first instruction cache according to the status information of the first microinstruction cache queue. Based on this possible design, the status information of the microinstruction cache queue can be obtained in real time, and the number of instructions of the corresponding type taken out from each type of instruction cache can be dynamically adjusted according to the status information, thereby improving the parallel operation efficiency of the first type of execution unit and the second type of execution unit, thereby further improving the performance of the computer device.

[0033] In some possible designs, the status information of the first microinstruction cache queue is used to indicate the amount of free space in the first microinstruction cache queue; based on the status information of the first microinstruction cache queue, the number of first type of instructions to be obtained from the first instruction cache is determined, including: determining the number of free space in the first microinstruction cache queue as the number of first type of instructions to be obtained from the first instruction cache.

[0034] In some possible designs, the instruction conversion method further includes: when the instruction set includes the second type of instruction, storing the second type of instruction in the instruction set to the second instruction cache. Based on this possible design, classified storage of different types of instructions can be implemented, so that when obtaining instructions, the required type of instruction can be obtained based on the classified storage.

[0035] In some possible designs, the instruction conversion method further includes: obtaining status information of a second microinstruction cache queue, the second microinstruction cache queue being used to cache micro-operations of the second type of instructions; and determining the number of the second type of instructions to be obtained from the second instruction cache according to the status information of the second microinstruction cache queue. Based on this possible design, the status information of the microinstruction cache queue can be obtained in real time, and the number of corresponding types of instructions taken from each type of instruction cache can be dynamically adjusted according to the status information, thereby improving the parallel operation efficiency of the first type of execution unit and the second type of execution unit, thereby further improving the performance of the computer device.

[0036] In some possible designs, the status information of the second microinstruction cache queue is used to indicate the amount of free space in the second microinstruction cache queue; based on the status information of the second microinstruction cache queue, the number of second type instructions to be obtained from the second instruction cache is determined, including: determining the number of free space in the second microinstruction cache queue as the number of second type instructions to be obtained from the second instruction cache.

[0037] In a second aspect, a communication device is provided for implementing any one of the above-mentioned methods. In some implementations, the communication device may be the computer device in the above-mentioned first aspect, or a device including the above-mentioned computer device, or a device included in the above-mentioned computer device. The communication device includes a module, unit, or means corresponding to the above-mentioned method, and the module, unit, or means may be implemented by hardware, software, or by hardware executing the corresponding software implementation. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions. For example, an acquisition module and a conversion module.

[0038] An acquisition module is used to acquire an instruction set according to a source program, the instruction set includes at least two instructions, and the type of any one of the at least two instructions is a first type or a second type; a conversion module is used to convert some or all of the first type of instructions in the instruction set into second type of instructions according to a policy rule, and the policy rule makes the load of the first type of execution unit and the second type of execution unit of the computer device balanced. The first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction; or the first type of instruction is a SISD instruction, and the second type of instruction is a SIMD instruction.

[0039] Among them, the specific implementation method of the communication device can refer to the behavioral function of the computer device in the instruction conversion method provided by the first aspect or any possible design of the first aspect.

[0040] In a third aspect, a communication device is provided, which may be the computer device in the first aspect, or a device including the computer device, or a device included in the computer device. In a possible implementation, the communication device may include at least one processor, and the processor may be used to support the communication device to implement the functions involved in the first aspect or any possible design of the first aspect. For example: a processor is used to obtain an instruction set according to a source program, the instruction set includes at least two instructions, and the type of any one of the at least two instructions is a first type or a second type. The processor can also be used to convert part or all of the first type of instructions in the instruction set into a second type of instruction according to a policy rule, and the policy rule makes the load of the first type of execution unit and the second type of execution unit balanced. Among them, the first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction; or, the first type of instruction is a SISD instruction, and the second type of instruction is a SIMD instruction; in another possible implementation, the processor is used to couple with a memory, and after reading the instructions in the memory, execute the method described in any of the above aspects according to the instructions.

[0041] Among them, the specific implementation method of the communication device can refer to the behavioral function of the computer device in the instruction conversion method provided by the first aspect or any possible design of the first aspect.

[0042] In a fourth aspect, a communication device is provided, comprising: a memory and at least one processor; the memory is used to store computer instructions, and when the processor executes the instructions, the communication device executes the method described in any one of the above aspects. The communication device can be the computer device in the first aspect, or a device including the computer device, or a device included in the computer device.

[0043] In a fifth aspect, a communication device is provided, comprising: an interface circuit and at least one processor, the interface circuit may be a code / data read / write interface circuit, the interface circuit is used to receive computer execution instructions (computer execution instructions are stored in a memory, may be read directly from the memory, or may pass through other devices) and transmit them to the processor; the processor is used to run the computer execution instructions to execute the method described in any of the above aspects. The communication device may be the computer device in the first aspect, or a device including the computer device, or a device included in the computer device.

[0044] In a sixth aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium, and when the instructions are executed on a communication device, the communication device can execute the method described in any one of the above aspects. The communication device can be the computer device described in the first aspect, or a device including the computer device, or a device included in the computer device.

[0045] In a seventh aspect, a computer program product comprising instructions is provided, which, when executed on a communication device, enables the communication device to execute the method described in any one of the above aspects. The communication device may be the computer device described in the first aspect, or a device comprising the computer device, or a device included in the computer device.

[0046] In an eighth aspect, a communication device is provided (for example, the communication device may be a chip or a chip system), the communication device including at least one processor for implementing the functions involved in any of the above aspects. In some possible designs, the communication device also includes a memory for storing necessary program instructions and / or data. When the communication device is a chip system, it may be composed of a chip, or may include a chip and other discrete devices.

[0047] In a ninth aspect, an embodiment of the present application provides a chip, the chip comprising at least one processor and a communication interface, the communication interface is coupled to the at least one processor, and the at least one processor is used to run a computer program or instruction to implement the method described in the first aspect or various possible implementations of the first aspect. The communication interface is used to communicate with other modules outside the chip.

[0048] The chip provided in the embodiment of the present application may also include a memory, and the memory is used to store computer programs or instructions.

[0049] It can be understood that any of the communication devices, chips, computer-readable media, computer program products, etc. provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of a CPU instruction pipeline of a single-issue CPU provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram of a CPU instruction pipeline of a multi-issue CPU provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of a CPU instruction pipeline of an out-of-order multi-issue processor provided in an embodiment of the present application;

[0053] Figure 4 A schematic diagram of a SISD technology provided in an embodiment of the present application;

[0054] Figure 5 A schematic diagram of a SIMD technology provided in an embodiment of the present application;

[0055] Figure 6 A schematic diagram of a compilation process of a compiler provided in an embodiment of the present application;

[0056] Figure 7 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0057] Figure 8 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0058] Fig. 9 A flowchart of an operation evaluation method provided in an embodiment of the present application;

[0059] Fig.10 A flowchart of an instruction conversion method provided in an embodiment of the present application;

[0060] Fig.11 A schematic diagram of the structure of an instruction relationship tree provided in an embodiment of the present application;

[0061] Fig.12 A flowchart of another instruction conversion method provided in an embodiment of the present application;

[0062] Fig.13 A flowchart of another instruction conversion method provided in an embodiment of the present application;

[0063] Fig.14 A schematic diagram of a CPU instruction pipeline provided in an embodiment of the present application;

[0064] Fig.15 A schematic diagram of the structure of a computer device provided in an embodiment of the present application;

[0065] Fig.16 A schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to facilitate understanding of the technical solutions of the embodiments of the present application, a brief introduction to the related technologies of the present application is first given as follows.

[0067] First, single-issue CPU:

[0068] like Figure 1 As shown, when an instruction is executed, a single-issue CPU can only take out one instruction from the instruction cache in each clock cycle, can only decode one instruction, can only execute one instruction, and can only write back one operation result.

[0069] For a single-issue CPU, due to data dependency, conditional transfer, resource conflicts and other reasons, the expected value of its instruction-level parallelism cannot reach 1, that is, it is impossible to execute one instruction per clock cycle on average.

[0070] Second, multi-launch CPU:

[0071] In order to take advantage of the parallelism between pipelines and improve CPU processing performance, the current mainstream CPU microarchitecture mainly adopts multi-issue pipeline technology, that is, the CPU is usually a multi-issue CPU.

[0072] For example, Figure 2 The three-issue CPU shown can fetch three instructions from the instruction cache simultaneously in each clock cycle, decode three instructions simultaneously, execute three instructions simultaneously, and write back three operation results simultaneously.

[0073] Third, out-of-order multi-issue processor:

[0074] In order to alleviate the CPU stall problem caused by data dependency, conditional transfer and resource conflict, and further improve the parallelism between pipelines, the out-of-order execution paradigm is widely used in high-performance microprocessors.

[0075] Specifically, in the field of computer engineering, out-of-order execution is a paradigm used in high-performance CPUs to utilize instruction cycles to avoid certain types of delay consumption. In this paradigm, in order to avoid CPU stalls caused by the unavailability of the operand of the next instruction, the processor, based on components such as the microinstruction buffer, instead processes instructions that can be executed immediately, thereby executing instructions in a non-programmed order.

[0076] Based on this, an out-of-order multi-issue processor can be understood as a multi-issue processor that adopts an out-of-order execution paradigm. For example, an out-of-order multi-issue processor can select executable instructions to run first through the following steps. Its CPU instruction pipeline is as follows: Figure 3 shown.

[0077] Step 1: Get instructions from the instruction cache;

[0078] Step 2: Decode the instruction to get multiple micro-operations (micro-ops), and send the multiple micro-operations to the instruction queue (also called execution buffer or reservation station);

[0079] Step 3: The instruction sequence sends the executable instruction micro-operations with complete operands to the corresponding processing unit (PU) in sequence.

[0080] In this step, even if the micro-operation of a certain instruction is located at the front of the instruction sequence, if its operands are not ready, execution cannot begin. Therefore, the execution order of instructions in the instruction sequence is inconsistent with the program, that is, out of order.

[0081] Step 4: Each execution unit obtains and executes executable micro-operations from the instruction sequence to obtain execution results, which are cached in a queue.

[0082] Step 5: Write the execution result in the sequence back to the register.

[0083] In this step, the execution result of a certain instruction is written into the register only after the execution results of the instructions preceding the instruction in the program are written into the register.

[0084] Fourth, SISD, SIMD:

[0085] like Figure 4 As shown, for SISD, one instruction can only operate on one data stream at a time, and generally, SISD uses 64-bit general registers. Instructions using SISD technology may be referred to as SISD instructions, and execution units for executing SISD instructions may be referred to as scalar execution units.

[0086] like Figure 5 As shown, for SIMD, one instruction can operate on multiple data streams at the same time to realize the functions of multiple SIMD instructions. Generally, SIMD uses SIMD-specific registers with a maximum length of 128 bits or 512 bits. Instructions using SIMD technology can be called SIMD instructions, and the execution unit used to execute SIMD instructions can be called a vector execution unit.

[0087] Currently, the function of using SIMD instructions to accelerate programs is mainly achieved through the automatic vectorization method of the compiler vectorization option. Figure 6As shown, a compiler is a computer program that can convert a source program (i.e., a program to be compiled) written in a high-level programming language into another programming language, i.e., a target language. Among them, vectorization refers to converting optimizable SISD instructions into corresponding SIMD instructions.

[0088] Compilers are divided into front-end and back-end in terms of logical structure: the front-end is mainly composed of parts related to the source program but not to the target machine (i.e. the device used to run the program), usually including lexical, grammatical, semantic analysis and intermediate code generation, etc. The back-end is mainly composed of parts related to the target machine, including code optimization and target code generation related to the target machine, etc.

[0089] It is worth noting that the Tree SSA optimization framework used to support the compiler to achieve automatic vectorization of the source program is deployed in the back end. SSA refers to static single assignment.

[0090] Taking the GNU compiler collection (GCC) as an example, based on the SSA optimization framework, the following compiler optimization options can be used to achieve automatic vectorization of corresponding functions of the source program:

[0091] Use the -ftree-loop-vectorize option to automatically vectorize loop code in the source program;

[0092] Use the -ftree-slp-vectorize option to use super word level parallelism (SLP) technology to automatically vectorize ordinary serial code in the source program;

[0093] Use the -ftree-vectorize or -O3 option to enable the -ftree-loop-vectorize and -ftree-slp-vectorize options simultaneously, thus achieving automatic vectorization of loop codes and normal serial codes in the source program.

[0094] The automatic vectorization method based on the compiler vectorization option will replace all SISD instructions in the source program that are determined to be optimizable by the compiler after analysis with SIMD instructions. However, after all optimizable SISD instructions are replaced with SIMD instructions, the vector execution unit may run at a high load, while the scalar execution unit is in a light load state, resulting in uneven loads on the scalar execution unit and the vector execution unit, and low average utilization of the execution unit.

[0095] In order to solve the above technical problems, an embodiment of the present application provides an instruction conversion method, which is applied to a computer device, and the computer device includes a first type of execution unit and a second type of execution unit, the first type of execution unit is used to execute a first type of instruction, and the second type of execution unit is used to execute a second type of instruction. In this method, the computer device obtains an instruction set, and the instruction set includes at least two instructions, and the type of any one of the at least two instructions is the first type or the second type; the computer device converts part or all of the first type of instructions in the instruction set into the second type of instructions according to the policy rules, and the policy rules make the load of the first type of execution unit and the second type of execution unit balanced. This method will be described in detail in subsequent embodiments and will not be repeated here.

[0096] It should be noted that, in the embodiment of the present application, the first type and the second type are different types, for example, the first type of instruction is a SIMD instruction, the second type of instruction is a SISD instruction, and accordingly, the first type of execution unit is a vector execution unit, and the second type of execution unit is a scalar execution unit. Alternatively, the first type of instruction is a SISD instruction, the second type of instruction is a SIMD instruction, and accordingly, the first type of execution unit is a scalar execution unit, and the second type of execution unit is a vector execution unit.

[0097] In an embodiment of the present application, when executing instruction conversion, some or all of the first type of instructions can be converted into second type of instructions according to the strategy rules, and the strategy rules can balance the load of the first type of execution unit and the second type of execution unit. Therefore, the present application can balance the load of the first type of execution unit and the second type of execution unit, improve the utilization rate of the execution unit, and thus improve the performance of the computer device.

[0098] The implementation of the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

[0099] like Figure 7 As shown, it is a schematic diagram of the structure of a communication device 700 provided in an embodiment of the present application. The communication device 700 may be a computer device or a chip or a system on a chip in a computer device. Figure 7 As shown, the communication device 700 includes a processor 701 , a transceiver 702 and a communication line 703 .

[0100] Furthermore, the communication device 700 may further include a memory 704. The processor 701, the memory 704 and the transceiver 702 may be connected via a communication line 703.

[0101] The processor 701 is a central processing unit (CPU), a general processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 701 may also be other devices with processing functions, such as circuits, devices, or software modules, without limitation. Optionally, the processor 701 may be a random order multi-issue processor.

[0102] The transceiver 702 is used to communicate with other devices or other communication networks. The other communication networks may be Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The transceiver 702 may be a module, a circuit, a transceiver or any device capable of achieving communication.

[0103] The communication line 703 is used to transmit information between the components included in the communication device 700.

[0104] The memory 704 is used to store instructions, where the instructions may be computer programs.

[0105] Among them, the memory 704 can be a read-only memory (ROM) or other types of static storage devices that can store static information and / or instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and / or instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage devices, etc., without limitation.

[0106] It should be noted that the memory 704 can exist independently of the processor 701, or can be integrated with the processor 701. The memory 704 can be used to store instructions or program codes or some data, etc. The memory 704 can be located in the communication device 700, or can be located outside the communication device 700, without limitation. The processor 701 is used to execute the instructions stored in the memory 704 to implement the multipath communication method provided in the following embodiments of the present application.

[0107] In one example, the processor 701 may include one or more CPUs, such as Figure 7 CPU0 and CPU1 in.

[0108] As an optional implementation, the communication device 700 includes multiple processors, for example, Figure 7 In addition to the processor 701, a processor 707 may also be included.

[0109] As an optional implementation, the communication device 700 further includes an output device 705 and an input device 706. Exemplarily, the input device 706 is a keyboard, a mouse, a microphone, a joystick, and the like, and the output device 705 is a display screen, a speaker, and the like.

[0110] It should be noted that the communication device 700 can be a desktop computer, a portable computer, a network server, a mobile phone, a tablet computer, a wireless terminal, an embedded device, a chip system or a Figure 7 In addition, Figure 7 The structure shown in the figure does not constitute a limitation on the communication device, except Figure 7 In addition to the components shown, the communication device may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0111] like Figure 8 , which is a schematic diagram of the structure of a processor 701 provided in an embodiment of the present application. The processor 701 includes a first instruction cache (IR) 7011a, a second IR 7011b, a scheduler 7012, an instruction fetch unit 7013, a decoding unit 7017, an instruction issue unit 7014, a first microinstruction cache queue 7015a, a second microinstruction cache queue 7015b, a first type of execution unit 7016a, and a second type of execution unit 7016b.

[0112] It is understandable that the processor 701 may include a plurality of first-type execution units 7016a, a plurality of second-type execution units 7016b, Figure 8The description is merely illustrative and takes the example of including a first-type execution unit 7016a and a second-type execution unit 7016b.

[0113] The first IR 7011a is used to store the first type of instructions, and the second IR 7011b is used to store the second type of instructions. Optionally, the first type of instructions and the second type of instructions can be stored in order by using the instruction type bit and / or the instruction location cache table.

[0114] The scheduler 7012 is used to monitor the status of the first microinstruction cache queue 7015a and the second microinstruction cache queue 7015b (such as the dequeue rate and the number of micro-operations in the queue), and output an instruction fetch strategy to the instruction fetch unit 7013 based on the status. The instruction fetch strategy can be, for example, the number of first type instructions to be fetched or the number of second type instructions to be fetched.

[0115] The first microinstruction cache queue 7015 a and the second microinstruction cache queue 7015 b are used to feed back the status of the current queue to the scheduler 7012 .

[0116] Optionally, the first microinstruction cache queue 7015a may be a microinstruction cache queue corresponding to each existing first-class execution unit, or a microinstruction cache queue shared by all first-class execution units. Similarly, the second microinstruction cache queue 7015b may be a microinstruction cache queue corresponding to each existing second-class execution unit, or a microinstruction cache queue shared by all second-class execution units.

[0117] The instruction fetch unit 7013, the decoding unit 7017, the instruction issuing unit 7014, the first type of execution unit 7016a, and the second type of execution unit 7016b can refer to the relevant descriptions in the prior art and are not described in detail in this step.

[0118] In the embodiment of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices.

[0119] In addition, the actions, terms, etc. involved in the various embodiments of the present application can refer to each other without limitation. The message name or parameter name in the message exchanged between the various devices in the embodiments of the present application is only an example, and other names can also be used in the specific implementation without limitation.

[0120] It is understandable that in the embodiment of the present application, the computer device can perform some or all of the steps in the embodiment of the present application, and these steps or operations are only examples. The embodiment of the present application can also perform other operations or variations of various operations. In addition, the various steps can be performed in different orders presented in the embodiment of the present application, and it is possible that not all operations in the embodiment of the present application need to be performed.

[0121] In the embodiment of the present application, before the computer device executes the instruction conversion, the computer device may first use Fig. 9 The method shown is used to evaluate the instruction implementation. Fig. 9 As shown, the evaluation method may include the following steps:

[0122] S901. A computer device determines one or more operations to be evaluated.

[0123] The operation may be understood as a calculation on data, for example, the operation may be an addition operation or a multiplication operation, etc. Each operation in the one or more operations to be evaluated may be implemented on the computer device by either a SISD instruction or a SIMD instruction.

[0124] S902: The computer device determines whether there is any unevaluated operation.

[0125] If one or more operations in S901 are evaluated, the evaluation is terminated; if there are unevaluated operations in S901, the following step S903 is executed.

[0126] S903: The computer device determines whether instruction 1 and instruction 2 can be executed in parallel on the computer device.

[0127] Instruction 1 is a SISD instruction for implementing operation i, instruction 2 is a SIMD instruction for implementing operation i, and operation i is the operation to be evaluated. It can be understood that operation i belongs to one or more operations to be evaluated in S901.

[0128] Optionally, whether instruction 1 and instruction 2 can be executed in parallel on the computer device can be understood as whether the computer device supports the parallel execution of instruction 1 and instruction 2 on the computer device.

[0129] If instruction 1 and instruction 2 can be executed in parallel on the computer device, execute the following step S904a; or, if instruction 1 and instruction 2 cannot be executed in parallel on the computer device, execute the following step S904b.

[0130] S904a, determine the quantity ratio of instruction 1 and instruction 2.

[0131] The number ratio of instruction 1 to instruction 2 is the number ratio (or combination ratio) of instruction 1 to instruction 2 that should be used to implement any operation i at the best performance. Optionally, the number ratio is the ratio of value 1 to value 2.

[0132] For a value of 1: the number of times operation i can be performed by one instruction 1 The number of scalar execution units included in the computer device for executing instruction 1 And time difference 1 is determined, which is the time it takes to use instruction 1 to implement n operations i The time taken to implement m operations i using instruction 2 The time difference between them, n and m are positive integers, and n is greater than m.

[0133] Optional, Satisfies the following formula:

[0134]

[0135] in, is the value 1. It can be understood as the time taken by a scalar execution unit used to execute instruction 1 to execute an instruction 1.

[0136] For a value of 2: the number of times operation i can be performed by one instruction 2 The number of scalar execution units included in the computer device for executing instruction 1 And time difference 1 is determined, which is the time it takes to use instruction 1 to implement n operations i The time taken to implement m operations i using instruction 2 The time difference between.

[0137] Optional, Satisfies the following formula:

[0138]

[0139] in, The value is 2. It can be understood as the time taken by a vector execution unit used to execute instruction 2 to execute an instruction 2.

[0140] Optional, above It can be measured by binding the core and clearing the pipeline of the performance monitoring unit (PMU) of the computer device.

[0141] That is to say, the ratio of the number of instructions 1 and 2 satisfies the following formula:

[0142]

[0143] S904b. The computer device determines the best instruction implementation method for operation i.

[0144] Optionally, the computer device may determine the best implementation method by comparing the values ​​1 and 2. For example, the computer device determines the instruction implementation method corresponding to the smaller value between the values ​​1 and 2 as the best instruction implementation method for operation i.

[0145] Exemplarily, if the value 1 is less than the value 2, the computer device may determine the SISD instruction as the best instruction implementation for operation i, that is, when instruction 1 and instruction 2 cannot be executed in parallel, instruction 1 is selected to implement operation i.

[0146] S905. The computer device records the evaluation results.

[0147] Optionally, if the computer device executes S904a and then S905, the evaluation result may be the ratio of the number of instructions 1 and instruction 2 corresponding to operation i, for example, the evaluation result is [operation i: 10:11], indicating that the ratio of the number of SISD instructions and SIMD instructions for implementing operation i is 10:11. Alternatively, if the computer device executes S904b and then S905, the evaluation result may be the best instruction implementation method corresponding to operation i, for example, the evaluation result is [operation i: SISD], indicating that the best instruction for implementing operation i is the SISD instruction.

[0148] It can be understood that after S905 , the computer device may continue to execute step S902 to finally complete the evaluation of all operations determined in S901 .

[0149] Based on this method, the optimal ratio of SISD instructions to SIMD instructions for implementing a certain operation can be evaluated in combination with the hardware characteristics of the computer device, or the optimal instruction implementation method for implementing a certain operation can be evaluated, so that program optimization or instruction conversion can be performed based on the evaluation results obtained in the subsequent evaluation, thereby better balancing the load of the scalar execution unit and the vector execution unit and improving the performance of the computer device.

[0150] Combine the following Figures 1 to 9 , the instruction conversion method provided in the embodiment of the present application is described in detail.

[0151] Fig.10 A flowchart of an instruction conversion method provided in an embodiment of the present application is provided. The instruction conversion method is applied to a computer device, and the computer device includes a first type of execution unit and a second type of execution unit. The first type of execution unit is used to execute a first type of instruction, and the second type of execution unit is used to indicate a second type of instruction. The first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction; or the first type of instruction is a SISD instruction, and the second type of instruction is a SIMD instruction. Fig.10 As shown, the instruction conversion method may include the following steps:

[0152] S1001. A computer device obtains an instruction set according to a source program.

[0153] The instruction set includes at least two instructions, and the type of any one of the at least two instructions is the first type or the second type, that is, any one of the instructions is a SISD instruction or a SIMD instruction.

[0154] It can be understood that any instruction included in the instruction set can be converted from an instruction of the first type to an instruction of the second type, or can be converted from an instruction of the second type to an instruction of the first type.

[0155] Optionally, the computer device obtains the instruction set according to the source program by: the computer device compiles the source program based on an existing compilation method to obtain the instruction set. Exemplarily, after the computer device compiles the source program based on an existing compilation method to obtain the first assembly file of the program, the instruction that can be converted into an instruction type in the first assembly file is determined as an instruction in the instruction set, for example, the instruction that can be converted into an instruction type is a SISD instruction that can be optimized into a SIMD instruction, and / or a SIMD instruction that can be converted into a SISD instruction.

[0156] Optionally, the existing compilation method can be an automatic vectorization compilation method using a vectorization option, that is, all optimizable SISD instructions are converted into SIMD instructions when compiling the source program. In this scenario, the first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction. Accordingly, the first type of execution unit is a vector execution unit, and the second type of execution unit is a scalar execution unit. Alternatively, the existing compilation method can be a compilation method that does not use a vectorization option, that is, instruction optimization is not performed when compiling the source program. In this scenario, the first type of instruction is a SISD instruction, and the second type of instruction is a SIMD instruction. Accordingly, the first type of execution unit is a scalar execution unit, and the second type of execution unit is a vector execution unit.

[0157] S1002: The computer device converts part or all of the first type of instructions in the instruction set into second type of instructions according to the policy rule.

[0158] The policy rule balances the load between the first type of execution unit and the second type of execution unit.

[0159] It can be understood that the instruction conversion method provided in the embodiment of the present application can also be understood as a source program compilation method that is different from the prior art.

[0160] In an embodiment of the present application, when executing instruction conversion, some or all of the first type of instructions can be converted into second type of instructions according to the strategy rules, and the strategy rules can balance the load of the first type of execution unit and the second type of execution unit. Therefore, the present application can balance the load of the first type of execution unit and the second type of execution unit, improve the utilization rate of the execution unit, and thus improve the performance of the computer device.

[0161] The following introduces the policy rules provided in the embodiments of the present application, and the manner in which a computer device performs instruction conversion according to the policy rules.

[0162] In a first possible implementation, the policy rule indicates that the first type of instruction in the first instruction relationship subtree is converted into the second type of instruction, and the first instruction relationship subtree is a subtree of the instruction relationship tree composed of at least two instructions included in the above instruction set. It can be understood that the first instruction relationship subtree may include one or more instruction relationship subtrees.

[0163] Optionally, in this implementation, the computer device converts some or all of the first type of instructions in an instruction set into instructions of the second type according to a policy rule, which may include: the computer device establishes an instruction relationship tree of at least two instructions included in the instruction set according to data relevance, etc., and converts the first type of instructions in a first instruction relationship subtree in the instruction relationship tree into instructions of the second type according to the policy rule.

[0164] Optionally, the first instruction relationship subtree may be an instruction relationship subtree including more instructions of the first type in the instruction relationship tree.

[0165] Exemplarily, assuming that the first type of instruction is a SIMD instruction, and the second type of instruction is a SISD instruction, the above instruction set includes four instructions, and the four instructions are: a+b=c, a / b=d, c*d=f, h+i=j, and the four instructions are all implemented by SIMD instructions. The instruction relationship tree constructed by the computer device can be as follows: Fig.11 At this time, the first relationship subtree selected by the computer device according to the policy rule may be the left subtree, that is, a+b=c, a / b=d, c*d=f are converted into SISD instructions.

[0166] In a second possible implementation, the policy rule indicates that part of the first instructions in the first instruction set is converted into M second instructions, where M is a positive integer. The first instruction set is an instruction subset included in the above instruction set, and the instruction subsets included in the instruction set are classified according to the operations implemented by the instructions, that is, all instructions included in an instruction subset of the instruction set implement the same operation, and instructions included in different instruction subsets implement different operations.

[0167] The initial set of the first instruction set includes at least two first instructions, the first instruction is an instruction of a first type for implementing a first operation, and the second instruction is an instruction of a second type for implementing the first operation. That is, the strategy can be applied to an instruction subset including at least two first type instructions.

[0168] Optionally, after obtaining the instruction set, the computer device may divide the at least two instructions included in the instruction set into one or more instruction subsets according to the operations implemented by the instructions, and then perform instruction conversion according to the policy rule. Fig.11 In the example shown, the computer device can divide the instruction set into three instruction subsets, for example, instruction subset 1: {a+b=c, h+i=j}, instruction subset 2: {a / b=d}, instruction subset 3: {c*d=f}. If instruction subset 1 includes two instructions of the first type, the policy rule can be used to perform instruction conversion on the instructions in instruction subset 1.

[0169] Further optionally, the policy rule instructs that part of the first instructions in the first instruction set be converted into M second instructions, which may include: the policy rule instructs that part of the first instructions in the first instruction set be converted into M second instructions when the first instruction and the second instruction are executed in parallel.

[0170] Optionally, the first instruction and the second instruction are executed in parallel can be understood as: the computer device supports the first instruction and the second instruction in parallel, and the initial set of the first instruction set includes at least two first instructions. This is because when the initial set of the first instruction set includes one first instruction, if the first instruction is converted into a second instruction, the first instruction will not exist in the entire instruction set, and therefore there will be no situation where the first instruction and the second instruction are executed in parallel.

[0171] Optionally, the ratio of M to K is determined by a first value and a second value, and K is the number of another part of first instructions in the first instruction set, that is, K is the number of first instructions in the first instruction set that are not converted into second instructions.

[0172] For the first value: the first value is determined by the first duration and the first quantity, the first duration is the duration used by a first execution unit to execute a first instruction, and the first quantity is the number of first execution units included in the computer device. It can be understood that since the first instruction is a first type of instruction for implementing the first operation, the first execution unit is a first type of execution unit for executing the first instruction.

[0173] Optionally, the first value, the first duration, and the first quantity satisfy the following formula:

[0174]

[0175] in, is the first value, T1 is the first duration, is the first quantity.

[0176] Optionally, the first duration is determined by the first number and a first time difference, the first number being the number of first operations implemented by a first instruction, and the first time difference being the time difference between the duration used to implement n first operations using the first instruction and the time used to implement m first operations using the first instruction, where n and m are positive integers, and n is greater than m.

[0177] Optionally, the first duration, the first number, and the first time difference satisfy the following formula:

[0178]

[0179] Among them, T1 is the first duration, For the first number, is the first time difference, is the time taken to implement n first operations using the first instruction, The time taken to implement m first operations using the first instruction.

[0180] For the second value: the second value is determined by the second duration and the second number, the second duration is the duration used by a second execution unit to execute a second instruction, and the second number is the number of second execution units included in the computer device. It can be understood that since the second instruction is a second type of instruction for implementing the first operation, the second execution unit is a second type of execution unit for executing the second instruction.

[0181] Optionally, the second value, the second duration, and the second quantity satisfy the following formula:

[0182]

[0183] in, is the second value, T2 is the second duration, is the second quantity.

[0184] Optionally, the second duration is determined by a second number and a second time difference, the second number being the number of first operations implemented by a second instruction, and the second time difference being the time difference between the duration used to implement n times the first operation using the second instruction and the time used to implement m times the first operation using the second instruction, n and m are positive integers, and n is greater than m.

[0185] Optionally, the second duration, the second number, and the second time difference satisfy the following formula:

[0186]

[0187] Among them, T2 is the second duration, For the second number, is the second time difference, is the time taken to implement the first operation n times using the second instruction, The time taken to implement the first operation m times using the second instruction.

[0188] Finally, the ratio γ of M to K is:

[0189]

[0190] In combination with the above description, it can be understood that the first value and the second value can be the value of the first value and the second value when the computer device executes Fig. 9 The evaluation result obtained during the operation evaluation shown is that when performing instruction conversion on the first instruction set, the computer device can query the evaluation result corresponding to the first operation stored therein.

[0191] Further optionally, the ratio of M to K is determined by the first value and the second value, which may include: the ratio of M to K is determined by the first value, the second value, and the instruction relationship tree composed of at least two instructions included in the above instruction set. That is to say, when the computer device determines the ratio of M to K, or determines the value of M and K, it not only considers the first value and the second value, but also considers the instruction relationship tree composed of at least two instructions included in the above instruction set, that is, the computer device determines the ratio of M to K in combination with the first value, the second value and the instruction relationship tree.

[0192] In a third possible implementation, the policy rule indicates that when the third value is greater than or equal to the fourth value, all third instructions in the second instruction set are converted to fourth instructions; when the third value is less than or equal to the fourth value, the third instructions in the second instruction set are not converted to fourth instructions. The second instruction set is an instruction subset included in the above instruction set, and the instruction subsets included in the instruction set are classified according to the operations implemented by the instructions, that is, all instructions included in an instruction subset of the instruction set implement the same operation, and instructions included in different instruction subsets implement different operations.

[0193] The initial set of the second instruction set includes at least one third instruction, the third instruction is an instruction of the first type for implementing the second operation, and the fourth instruction is an instruction of the second type for implementing the second operation. In other words, the strategy can be applied to an instruction subset including at least one instruction of the first type. Fig.11 In the example shown, the second instruction set may be instruction subset 2: {a / b=d} or instruction subset 3: {c*d=f}.

[0194] Optionally, for the third numerical value: the third numerical value is determined by the third duration and the third quantity, the third duration is the duration used by a third execution unit to execute a third instruction, and the third quantity is the number of third execution units included in the computer device. It can be understood that since the third instruction is a first type of instruction for implementing the third operation, the third execution unit is a first type of execution unit for executing the third instruction. Among them, the relationship between the third numerical value, the third duration, and the third quantity can refer to the relevant description of the first numerical value mentioned above.

[0195] Optionally, the third duration is determined by the third number and the third time difference, the third number is the number of second operations implemented by a third instruction, the third time difference is the time difference between the time taken to implement the second operation n times using the third instruction and the time taken to implement the second operation m times using the third instruction, n and m are positive integers, n is greater than m. The relationship between the third duration, the third number, and the third time difference can refer to the relevant description of the first duration mentioned above.

[0196] Optionally, for the fourth numerical value: the fourth numerical value is determined by the fourth duration and the fourth quantity, the fourth duration is the duration used by a fourth execution unit to execute a fourth instruction, and the fourth quantity is the number of fourth execution units included in the computer device. It can be understood that since the fourth instruction is a second type of instruction for implementing the second operation, the fourth execution unit is a second type of execution unit for executing the fourth instruction. Among them, the relationship between the fourth numerical value, the fourth duration, and the fourth quantity can refer to the relevant description of the above-mentioned second numerical value.

[0197] Optionally, the fourth duration is determined by a fourth number of times and a fourth time difference, the fourth number of times being the number of times a fourth instruction implements the second operation, the fourth time difference being the time difference between the time taken to implement the second operation n times using the fourth instruction and the time taken to implement the second operation m times using the fourth instruction, n and m being positive integers, n being greater than m. The relationship between the fourth duration, the fourth number of times, and the fourth time difference may refer to the relevant description of the second duration mentioned above.

[0198] Further optionally, the policy rule indicates that when the third numerical value is greater than or equal to the fourth numerical value, all third instructions in the second instruction set are converted into fourth instructions, which may include: the policy rule indicates that when the third instruction and the fourth instruction are not executed in parallel and the third numerical value is greater than or equal to the fourth numerical value, all third instructions in the second instruction set are converted into fourth instructions.

[0199] Optionally, the third instruction and the fourth instruction are not executed in parallel can be understood as: the computer device does not support the third instruction and the fourth instruction to be executed in parallel, or the initial set of the second instruction set includes only one third instruction. This is because when the initial set of the second instruction set includes one third instruction, if the third instruction is converted to a fourth instruction, the third instruction will not exist in the entire instruction set, and therefore there will be no situation where the third instruction and the fourth instruction are executed in parallel.

[0200] It can be understood that the sizes of the third value and the fourth value can reflect the performance of implementing the second operation using the first type of instructions and the performance of implementing the second operation using the second type of instructions. The smaller the value, the better the performance. Therefore, this strategy rule can be considered to select an instruction type with better performance to implement the second operation.

[0201] In combination with the above description, it can be understood that the third value and the fourth value can be the value of the computer device when executing Fig. 9 When the operation shown is evaluated, when recording the evaluation result, if the computer device records the instruction implementation method corresponding to the smaller value between the third value and the fourth value, when performing instruction conversion on the second instruction set, the computer device only needs to query the instruction implementation method corresponding to the second operation stored therein. If the instruction implementation method is of the first type, it means that the third value is less than or equal to the fourth value, and the computer device does not convert the third instruction in the second instruction set into the fourth instruction according to the policy rule; or, if the instruction implementation method is of the second type, it means that the third value is greater than or equal to the fourth value, and the computer device converts all the third instructions in the second instruction set into the fourth instruction according to the policy rule.

[0202] Next, a method for a computer device to perform instruction conversion according to the policy rules in the second implementation manner and / or the policy rules in the third implementation manner is described. Fig.10 Step S1002 shown is described in detail.

[0203] like Fig.12 As shown, Fig.10 Step S1002 shown may include the following steps:

[0204] S1002a. The computer device constructs an instruction relationship tree of at least two instructions included in the instruction set.

[0205] Exemplarily, based on the above example, the instruction relationship tree constructed by the computer device can be as follows: Fig.11 shown.

[0206] S1002b. The computer device divides the instruction set into one or more instruction subsets according to the operation type.

[0207] Among them, all instructions included in an instruction subset of the instruction set implement the same operation, and instructions included in different instruction subsets implement different operations.

[0208] For example, based on Fig.11 In the example shown, the computer device can divide the instruction set into three instruction subsets, for example, respectively: instruction subset 1: {a+b=c, h+i=j}, instruction subset 2: {a / b=d}, instruction subset 3: {c*d=f}.

[0209] S1002c. The computer device predicts the instruction conversion scheme of each instruction subset according to the policy rules.

[0210] Optionally, for an instruction subset including at least two first-type instructions, and when the first-type instructions and the second-type instructions for implementing the operations corresponding to the instruction subset can be executed in parallel, the computer device can predict the instruction conversion scheme of the instruction subset according to the policy rules provided in the above-mentioned second possible implementation manner. That is, the computer device can predict the ratio of the number of second-type instructions to the number of first-type instructions included in the instruction subset after conversion according to the policy rules.

[0211] For example, assuming that the first type of instruction and the second type of instruction that implement the addition operation can be executed in parallel, the computer device can predict the instruction conversion scheme of the above instruction subset 1 according to the policy rules provided by the second possible implementation method. Fig. 9 The evaluation method shown obtains that the ratio of the number of first type instructions and second type instructions of addition operations is 1:1, and the computer device can predict that the instruction conversion scheme of instruction subset 1 is: converting a first type addition instruction of instruction subset 1 into a second type addition instruction.

[0212] Optionally, for an instruction subset that includes only one instruction of the first type, or when the first type of instruction and the second type of instruction used to implement the operation corresponding to the instruction subset cannot be executed in parallel, the computer device may predict the instruction conversion scheme of the instruction subset according to the policy rule provided in the third possible implementation manner. That is, the computer device may predict whether to convert the first type of instruction in the instruction subset according to the policy rule.

[0213] For example, assuming that the first type of instructions implementing multiplication and division operations and the second type of instructions cannot be executed in parallel, the computer device can predict the instruction conversion scheme of the above instruction subset 2 and instruction subset 3 according to a policy rule of the third possible implementation method. Fig. 9If the instruction implementation method for the multiplication operation and the division operation obtained by the evaluation method shown is the second type of instruction, the computer device can predict that the instruction conversion scheme of instruction subset 2 and instruction subset 3 is: converting the first type of instructions in instruction subset 2 and instruction subset 3 into the second type of instructions.

[0214] S1002d: The computer device performs instruction conversion by combining the instruction relationship tree and the instruction conversion schemes of each instruction subset.

[0215] Optionally, the computer device may combine the instruction relationship tree in S1002a to convert part or all of the first type of instructions in the instruction set in S1002a into second type of instructions with the goal of satisfying the instruction conversion schemes of each instruction subset predicted in S1002c as much as possible.

[0216] Exemplarily, based on the above example, the instruction conversion scheme of instruction subset 1 is to convert one of the first type of instructions into an instruction of the second type, and the conversion schemes of instruction subset 2 and instruction subset 3 are to convert all of the first type of instructions into instructions of the second type. Fig.11 As shown in the instruction relationship tree, since the instructions of the same instruction relationship subtree are generally required to be of the same type, the computer device can convert a+b=c in instruction subset 1 from a first type of instruction to a second type of instruction, and at the same time convert a / b=d and c*d=f from a first type of instruction to a second type of instruction.

[0217] Optionally, after the computer device completes the instruction conversion, it can output a second assembly file of the source program according to the result of the instruction conversion. At this point, it can be considered that the source program compilation process provided by the embodiment of the present application is completed.

[0218] In one implementation scenario of the present application, when executing the source program, the computer device loads the second assembly file. Fig.10 or Fig.12 Based on the method shown, Fig.13 As shown, after executing instruction conversion, if the instruction set includes instructions of the first type, the instruction conversion method may further include the following steps S1003a-S1005a; if the instruction set includes instructions of the second type, the instruction conversion method may further include the following steps S1003b-S1005b:

[0219] S1003a. The computer device stores the first type of instructions in a first instruction cache.

[0220] S1004a. The computer device obtains status information of the first microinstruction cache queue.

[0221] The first microinstruction cache queue is used to cache micro-operations of instructions of the first type.

[0222] Optionally, from the perspective of the processor of the computer device, the step S1004a may be that the first microinstruction cache queue sends the state information of the first microinstruction cache queue to the scheduler. Correspondingly, the scheduler receives the state information from the first microinstruction cache queue.

[0223] S1005a. The computer device determines the number of first type instructions to be obtained from the first instruction cache according to the status information of the first microinstruction cache queue.

[0224] Optionally, the status information of the first microinstruction cache queue can be used to indicate the amount of free space in the first microinstruction cache queue. Accordingly, the computer device determines the number of first-type instructions to be obtained from the first instruction cache based on the status information of the first microinstruction cache queue, which may include: determining the amount of free space in the first microinstruction cache queue as the number of first-type instructions to be obtained from the first instruction cache.

[0225] Optionally, from the perspective of the processor of the computer device, step S1005a may be that the scheduler determines the number of first-type instructions to be obtained from the first instruction cache according to the state information of the first microinstruction cache queue. Afterwards, the scheduler sends the number to the instruction fetch unit, and the instruction fetch unit fetches the corresponding number of first-type instructions from the first instruction cache.

[0226] S1003b: The computer device stores the second type of instructions in the second instruction cache.

[0227] S1004b, the computer device obtains status information of the second microinstruction cache queue.

[0228] The second microinstruction cache queue is used to cache micro-operations of instructions of the second type.

[0229] Optionally, from the perspective of the processor of the computer device, the step S1004b may be that the second microinstruction cache queue sends the status information of the second microinstruction cache queue to the scheduler. Correspondingly, the scheduler receives the status information from the second microinstruction cache queue.

[0230] S1005b: The computer device determines the number of second type instructions to be obtained from the second instruction cache according to the status information of the second microinstruction cache queue.

[0231] Optionally, the status information of the second microinstruction cache queue can be used to indicate the amount of free space in the second microinstruction cache queue. Accordingly, the computer device determines the number of second-type instructions to be obtained from the second instruction cache based on the status information of the second microinstruction cache queue, which may include: determining the amount of free space in the second microinstruction cache queue as the number of second-type instructions to be obtained from the second instruction cache.

[0232] Optionally, from the perspective of the processor of the computer device, step S1005b may be that the scheduler determines the number of second type instructions to be obtained from the second instruction cache according to the state information of the second microinstruction cache queue. Afterwards, the scheduler sends the number to the instruction fetch unit, and the instruction fetch unit fetches the corresponding number of second type instructions from the second instruction cache.

[0233] For example, taking the first type of instruction as a SISD instruction and the second type of instruction as a SIMD instruction as an example, using Fig.13 After the method shown, the processor instruction pipeline of the computer device can be as follows Fig.14 shown.

[0234] Based on this solution, the status information of the microinstruction cache queue can be obtained in real time, and the number of corresponding types of instructions taken out from each type of instruction cache can be dynamically adjusted according to the status information, thereby improving the parallel operation efficiency of the first type of execution unit and the second type of execution unit, thereby further improving the performance of the computer device.

[0235] In summary, in this application, the computer device can first execute Fig. 9 The evaluation method shown evaluates each operation, and when executing instruction conversion of the source program, the instruction conversion scheme is predicted according to the evaluation result, and then the instruction conversion is completed in combination with the instruction relationship tree. When the source program is executed, the first type of instructions and the second type of instructions can be classified and stored, and the number of corresponding types of instructions taken out from the first instruction cache and the second instruction cache can be dynamically adjusted.

[0236] Understandably, Fig. 9 The evaluation method shown and Fig.13 The method of classified storage and dynamically adjusting the index quantity shown can be independent of Fig.10 The methods shown are performed individually.

[0237] The above method is described below with a specific example. Assume that the source program of an application is mainly used to implement multiple 32-bit unsigned integer addition operations. Part of the code in the source program is as follows:

[0238] for(unsigned int i=0;i <len;i=i+4)

[0239] {

[0240] result[0]=bn[i]+bn[0];

[0241] result[1]=bn[i+1]+bn[0];

[0242] result[2]=bn[i+2]+bn[0];

[0243] result[3]=bn[i+3]+bn[0];

[0244] …

[0245] }

[0246] Before compiling the source program, the computer device can execute Fig. 9 The method shown calculates the ratio of the number of SISD instructions to the number of SIMD instructions when implementing a 32-bit unsigned integer addition operation, assuming here that the ratio is 10:11.

[0247] Assume that after the computer device compiles the source file based on the existing automatic vectorization compilation method, the SIMD instructions of the 32-bit unsigned addition operation part in the first assembly file generated after the source code is vectorized, that is, the instructions set obtained by the computer device include the following instructions:

[0248] add d15, d11, d10;

[0249] add d16, d12, d10;

[0250] add d17, d13, d10;

[0251] add d18, d14, d10;

[0252] Among them, d10-d18 are 128-bit SIMD dedicated registers, d10 stores bn[0], d11-d14 store bn[i]-bn[i+3] in each loop, and d15-d18 store the addition operation results to result[0]-result[3].

[0253] For the above-mentioned SIMD instructions, the computer device determines a conversion scheme based on the instruction relationship tree formed by the above-mentioned SIMD instructions and the above-mentioned evaluated ratio of 10:11 between SISD instructions and SIMD instructions when implementing 32-bit unsigned integer addition operations, so that the number of SISD instructions and SIMD instructions after conversion meets 10:11 as much as possible. It can be understood that since there is no correlation between the above-mentioned 4 SIMD instructions, in this example, the computer device can determine the conversion scheme only based on the number ratio. For example, the computer device determines to convert 2 of the above-mentioned 4 SIMD instructions into SISD instructions based on the number ratio. Exemplarily, the converted instructions can be as follows:

[0254] add x3, x1, x0;

[0255] add x4, x2, x0;

[0256] add d13, d11, d10;

[0257] add d14, d12, d10;

[0258] The first two instructions are converted SISD instructions, and the last two instructions are unconverted SIMD instructions. x0-x4 are 64-bit general registers, d10-d14 are 128-bit SIMD special registers, bn[0] is stored in d10 and x0 respectively, x1 and x2 store bn[i] and bn[i+1] in each loop, d11 and d12 store bn[i+2] and bn[i+3] in each loop, x3 and x4 store the addition results result[0] and result[1] respectively, and d13 and d14 store the addition results result[2] and result[3] respectively.

[0259] Subsequently, when executing the source program, the computer device may execute Fig.13 The method shown obtains the status information of the microinstruction cache queue in real time, dynamically adjusts the number of corresponding types of instructions taken out from the first instruction cache and the second instruction cache, and improves the efficiency of the parallel operation of the scalar execution unit and the vector execution unit.

[0260] In the various embodiments of the present application, unless otherwise specified or provided for in any logical conflict, the terms and / or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

[0261] It can be understood that in each of the above embodiments, the methods and / or steps implemented by a computer device may also be implemented by components (such as chips or circuits) that can be used in a computer device.

[0262] The above is an introduction to the scheme provided by the embodiment of the present application. Accordingly, the embodiment of the present application also provides a communication device, which is used to implement the above-mentioned various methods. The communication device can be a computer device in the above-mentioned method embodiment, or a device including the above-mentioned computer device, or a component that can be used for a computer device. It can be understood that in order to realize the above-mentioned functions, the communication device includes a hardware structure and / or software module corresponding to each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0263] The embodiment of the present application can divide the computer device into functional modules according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0264] For example, taking the communication device as the computer device in the above method embodiment, Fig.15 The schematic diagram of the structure of a computer device 150 is shown. The computer device 150 includes an acquisition module 1501 and a conversion module 1502. Optionally, the computer device 150 also includes a control module 1503.

[0265] Among them, the acquisition module 1501 is used to acquire an instruction set according to the source program, and the instruction set includes at least two instructions, and the type of any instruction of the at least two instructions is the first type or the second type; the conversion module 1502 is used to convert part or all of the first type of instructions in the instruction set into the second type of instructions according to the policy rules, and the policy rules balance the load of the first type of execution unit and the second type of execution unit. Among them, the first type of instruction is SIMD instruction, and the second type of instruction is SISD instruction; or, the first type of instruction is SISD instruction, and the second type of instruction is SIMD instruction. For specific implementation, please refer to Fig.10 The detailed description of step S1001 to step S1002 in the illustrated embodiment is omitted here.

[0266] The specific implementation of the computer device 150 can be found in Fig. 9 , Fig.10 , Fig.12 ,or Fig.13 The behavior function of the computer device in the method shown. For specific implementation, please refer to Fig. 9 Detailed description of steps S901 to S905 shown in FIG. Fig.10 Detailed description of steps S1001 to S1002 shown in FIG. Fig.12 Detailed description of steps S1001 to S1002d shown, or Fig.13 The detailed description of steps S1001 to S1005a or steps S1001 to S1005b shown is not repeated here.

[0267] Optionally, in a specific implementation, when the above instruction set includes instructions of the first type, the control module 1503 is configured to store the instructions of the first type in the instruction set into the first instruction cache.

[0268] Optionally, the control module 1503 is also used to obtain status information of a first microinstruction cache queue, which is used to cache micro-operations of instructions of the first type; the control module 1503 is also used to determine the number of instructions of the first type to be obtained from the first instruction cache based on the status information of the first microinstruction cache queue.

[0269] Optionally, in a specific implementation, the status information of the first microinstruction cache queue is used to indicate the amount of free space in the first microinstruction cache queue, and the control module 1503 is also used to determine the number of first type of instructions to be obtained from the first instruction cache based on the status information of the first microinstruction cache queue, which may include: the control module 1503 is also used to determine the number of free space in the first microinstruction cache queue as the number of first type of instructions to be obtained from the first instruction cache.

[0270] Optionally, in a specific implementation, when the above instruction set includes instructions of the second type, the control module 1503 is configured to store the instructions of the second type in the instruction set into the second instruction cache.

[0271] Optionally, the control module 1503 is also used to obtain status information of a second microinstruction cache queue, which is used to cache micro-operations of second type instructions; the control module 1503 is also used to determine the number of second type instructions to be obtained from the second instruction cache based on the status information of the second microinstruction cache queue.

[0272] Optionally, in a specific implementation, the status information of the second microinstruction cache queue is used to indicate the amount of free space in the second microinstruction cache queue; the control module 1503 is also used to determine the number of second type instructions to be obtained from the second instruction cache based on the status information of the second microinstruction cache queue, and may include: the control module 1503 is also used to determine the number of free space in the second microinstruction cache queue as the number of second type instructions to be obtained from the second instruction cache.

[0273] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0274] Optionally, the computer device 150 may also include a processing module and a storage module ( Fig.15 The storage module is used to store data and / or instructions, and the processing module can read the data or instructions in the storage module to implement the methods corresponding to the above embodiments.

[0275] It is understandable that the above-mentioned modules can be set up independently or integrated, and the embodiments of the present application are not limited to this.

[0276] In one possible embodiment, the computer device 150 is presented in the form of various functional modules divided in an integrated manner. The "module" here may refer to a specific ASIC, a circuit, a processor and a memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions. In a simple embodiment, a person skilled in the art can imagine that the computer device 150 can be used Figure 7 The form of the communication device 700 is shown.

[0277] for example, Figure 7 The processor 701 in the communication device 700 shown in the figure can call the computer execution instruction stored in the memory 704 to make the communication device 700 execute the above method embodiment. Fig. 9 , Fig.10 , Fig.12 ,or Fig.13 The method shown.

[0278] Specifically, Fig.15 The functions / implementation processes of the acquisition module 1501, the conversion module 1502, and the control module 1503 can be Figure 7 The processor 701 in the communication device 700 shown calls the computer execution instructions stored in the memory 704 to implement.

[0279] Since the computer device 150 provided in this embodiment can execute the above-mentioned instruction conversion method, the technical effects that can be obtained can refer to the above-mentioned method embodiment and will not be repeated here.

[0280] Optionally, an embodiment of the present application further provides a communication device (for example, the communication device may be a chip or a chip system), the communication device including a processor for implementing the method in any of the above method embodiments. In one possible design, the communication device also includes a memory. The memory is used to store necessary program instructions and data, and the processor can call the program code stored in the memory to instruct the communication device to execute the method in any of the above method embodiments. Of course, the memory may not be in the communication device. In another possible design, the communication device also includes an interface circuit, which is a code / data read / write interface circuit, which is used to receive computer execution instructions (computer execution instructions are stored in the memory, may be read directly from the memory, or may pass through other devices) and transmit them to the processor. When the communication device is a chip system, it can be composed of a chip, or it can include a chip and other discrete devices, which is not specifically limited in the embodiment of the present application.

[0281] Optionally, the embodiment of the present application further provides a chip, Fig.16 1 is a schematic diagram of the structure of a chip 160 provided in an embodiment of the present application. The chip 160 includes one or more than two (including two) processors 1610 and a communication interface 1630 .

[0282] Optionally, the chip 160 further includes a memory 1640, which may include a read-only memory and a random access memory, and provides operation instructions and data to the processor 1610. A portion of the memory 1640 may also include a non-volatile random access memory (NVRAM).

[0283] In the embodiment of the present application, the processor 1610 can execute by calling the operation instruction stored in the memory 1640 (the operation instruction can be stored in the operating system). Fig. 9 , Fig.10 , Fig.12 ,or Fig.13 The corresponding operations in the method shown.

[0284] Optionally, the processor 1610, the communication interface 1630 and the memory 1640 are coupled together via a bus system 1620, wherein the bus system 1620 may include a power bus, a control bus and a status signal bus in addition to a data bus. Fig.16 Various buses are labeled as bus system 1620.

[0285] The processor 1610 controls the processing operation of the computer device. The method disclosed in the above embodiment of the present application can be applied to the processor 1610, or implemented by the processor 1610. The processor 1610 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 1610. The above processor 1610 can be a general processor, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (application-specific integrated circuit, ASIC), a field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor can be combined and executed. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1640, and the processor 1610 reads the information in the memory 1640 and completes the steps of the above method in combination with its hardware.

[0286] In a possible implementation, the communication interface 1630 is used to perform the steps of receiving and sending of the computer device. The processor 1610 is used to perform the processing steps of the computer device.

[0287] The embodiment of the present application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be completed by a computer program to instruct the relevant hardware, and the program can be stored in the above computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be an internal storage unit of the terminal (including the data sending end and / or the data receiving end) of any of the above embodiments, such as the hard disk or memory of the terminal. The above computer-readable storage medium can also be an external storage device of the above terminal, such as a plug-in hard disk equipped on the above terminal, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. Further, the above computer-readable storage medium can also include both the internal storage unit of the above terminal and an external storage device. The above computer-readable storage medium is used to store the above computer program and other programs and data required by the above terminal. The above computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0288] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0289] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0290] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0291] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0292] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0293] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for converting instructions, characterized in that: The method is applied to a computer device, the computer device comprising a first type of execution unit and a second type of execution unit, the first type of execution unit is used to execute a first type of instruction, and the second type of execution unit is used to execute a second type of instruction; the method comprises: Acquire an instruction set according to a source program, the instruction set including at least two instructions, and a type of any one of the at least two instructions is the first type or the second type; Part or all of the first type of instructions in the instruction set are converted into the second type of instructions according to a policy rule, wherein the policy rule balances the load of the first type of execution unit and the second type of execution unit, the first type of instruction is a single instruction multiple data SIMD instruction, and the second type of instruction is a single instruction single data SISD instruction, or the first type of instruction is a SISD instruction and the second type of instruction is a SIMD instruction, wherein: The policy rule indicates that the first type of instruction in the first instruction relationship subtree is converted into the second type of instruction, and the first instruction relationship subtree is a subtree of the instruction relationship tree composed of the at least two instructions; or The policy rule indicates that part of the first instructions in a first instruction set is converted into M second instructions, the instruction set includes the first instruction set, an initial set of the first instruction set includes at least two first instructions, the first instruction is an instruction of the first type for implementing a first operation, the second instruction is an instruction of the second type for implementing the first operation, and M is a positive integer; or, The policy rule indicates that when the third numerical value is less than or equal to the fourth numerical value, all third instructions in the second instruction set are converted into fourth instructions, the instruction set includes the second instruction set, the initial set of the second instruction set includes at least one third instruction, the third instruction is an instruction of the first type for implementing the second operation, and the fourth instruction is an instruction of the second type for implementing the second operation, the third numerical value is determined by a third duration and a third quantity, and the fourth numerical value is determined by a fourth duration and a fourth quantity, the third duration is the duration used by a third execution unit to execute one of the third instructions, the third quantity is the number of the third execution units included in the computer device, the fourth duration is the duration used by a fourth execution unit to execute one of the fourth instructions, and the fourth quantity is the number of the fourth execution units included in the computer device.

2. The method according to claim 1, characterized in that The policy rule instructs converting part of the first instructions in the first instruction set into M second instructions, including: The policy rule indicates that when the first instruction and the second instruction are executed in parallel, part of the first instructions in the first instruction set are converted into M second instructions.

3. The method according to claim 1 or 2, characterized in that: The ratio of M to K is determined by a first value and a second value, K is the number of the other part of the first instructions in the first instruction set, the first value is determined by a first duration and a first quantity, the second value is determined by a second duration and a second quantity, the first duration is the duration used by a first execution unit to execute a first instruction, the first quantity is the number of the first execution units included in the computer device, the second duration is the duration used by a second execution unit to execute a second instruction, and the second quantity is the number of the second execution units included in the computer device.

4. The method according to claim 3, characterized in that: The ratio of M to K is determined by the first value and the second value, including: The ratio of M to K is determined by the first value, the second value, and an instruction relationship tree formed by the at least two instructions.

5. The method according to claim 3, characterized in that: The first value, the first duration, and the first quantity satisfy the following formula: in, is the first value, T1 is the first duration, is the first quantity.

6. The method according to claim 3, characterized in that The first duration is determined by a first number and a first time difference, wherein the first number is the number of times the first operation is implemented by a first instruction, and the first time difference is the time difference between the duration used to implement the first operation n times using the first instruction and the duration used to implement the first operation m times using the first instruction, where n and m are positive integers, and n is greater than m.

7. The method according to claim 6, characterized in that The first duration, the first number of times, and the first time difference satisfy the following formula: Wherein, T1 is the first duration, is the first number of times, is the first time difference, is the time taken to implement the first operation n times using the first instruction, The time length used to implement the first operation m times using the first instruction.

8. The method according to claim 3, characterized in that The second value, the second duration, and the second number satisfy the following formula: in, is the second value, T2 is the second duration, is the second number.

9. The method according to claim 3, characterized in that: The second duration is determined by a second number and a second time difference, wherein the second number is the number of times the first operation is implemented by a second instruction, and the second time difference is the time difference between the duration used to implement the first operation n times using the second instruction and the duration used to implement the first operation m times using the second instruction, where n and m are positive integers, and n is greater than m.

10. The method according to claim 9, characterized in that The second duration, the second number of times, and the second time difference satisfy the following formula: Wherein, T2 is the second duration, For the second number, is the second time difference, is the time taken to implement the first operation n times using the second instruction, The time length used to implement the first operation m times using the second instruction.

11. The method according to claim 1, characterized in that: The policy rule indicates that when the third value is less than or equal to the fourth value, all third instructions in the third instruction set are converted into fourth instructions, including: The policy rule indicates that the third instruction and the fourth instruction are not executed in parallel, and when the third value is less than or equal to the fourth value, all the third instructions in the third instruction set are converted into the fourth instruction.

12. The method according to claim 1, characterized in that The method further comprises: In a case where the instruction set includes the first type of instructions, the first type of instructions in the instruction set are stored in a first instruction cache.

13. The method according to claim 12, characterized in that The method further comprises: Acquire status information of a first microinstruction cache queue, where the first microinstruction cache queue is used to cache micro-operations of instructions of the first type; The number of instructions of the first type to be obtained from the first instruction cache is determined according to the status information of the first microinstruction cache queue.

14. The method according to claim 13, characterized in that The state information of the first microinstruction cache queue is used to indicate the amount of free space in the first microinstruction cache queue; Determining the number of instructions of the first type to be obtained from the first instruction cache according to the state information of the first microinstruction cache queue includes: The amount of free space in the first microinstruction cache queue is determined as the amount of the first type of instructions to be obtained from the first instruction cache.

15. The method according to claim 1 or 12, characterized in that: The method further comprises: In a case where the instruction set includes the second type of instructions, the second type of instructions in the instruction set are stored in a second instruction cache.

16. The method according to claim 15, characterized in that The method further comprises: Acquire status information of a second microinstruction cache queue, where the second microinstruction cache queue is used to cache micro-operations of the second type of instructions; The number of instructions of the second type to be obtained from the second instruction cache is determined according to the status information of the second microinstruction cache queue.

17. The method according to claim 16, characterized in that The state information of the second microinstruction cache queue is used to indicate the amount of free space in the second microinstruction cache queue; Determining the number of the second type of instructions to be obtained from the second instruction cache according to the state information of the second microinstruction cache queue includes: The amount of free space in the second microinstruction cache queue is determined as the amount of the second type of instructions to be obtained from the second instruction cache.

18. A communication device, characterized in that: The communication device comprises: a processor; The processor is used to read the computer-executable instructions in the memory and execute the computer-executable instructions, so that the communication device performs the method according to any one of claims 1 to 17.

19. A communication device, characterized in that: The communication device comprises: a processor and a memory; The memory is used to store computer-executable instructions. When the processor executes the computer-executable instructions, the communication device executes the method according to any one of claims 1 to 17.

20. A communication device, characterized in that: The communication device comprises: a processor and an interface circuit; The interface circuit is used to receive computer execution instructions and transmit them to the processor; The processor is configured to execute the computer-executable instructions so as to enable the communication device to perform the method according to any one of claims 1 to 17.

21. A computer-readable storage medium, characterized in that: The method comprises instructions, which, when executed on a communication device, enable the communication device to execute the method according to any one of claims 1 to 17.

22. A chip, characterized in that: The chip includes a processor and a communication interface, wherein the communication interface is coupled to the processor, the communication interface is used to communicate with other modules outside the chip, and the processor is used to run a computer program or instruction to implement the method as described in any one of claims 1-17.

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