Light-emitting driving circuit, scanning driving circuit and display device

Abstract

This disclosure relates to a light-emitting driving circuit, a scanning driving circuit, and a display device. The light-emitting driving circuit includes: a driving circuit configured to output a light-emitting driving signal to a first output terminal and a switching signal to a first node in response to a clock signal and a first carry signal; and a first masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the light-emitting driving signal, and the switching signal. The masking clock signal is a signal that remains at a first level during a normal mode and changes periodically during a low-power mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0086579, filed on July 14, 2020, the entire purpose of which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] Embodiments of the present invention relate to a display device, and more specifically, to a display device including a driving circuit for driving the display device. Background Technology

[0004] Organic light-emitting diodes (OLEDs) are display devices that use organic light-emitting diodes (OLEDs) to display images. These OLEDs generate light through the recombination of electrons and holes. Such OLEDs can have fast response times and can be driven with low power consumption.

[0005] An organic light-emitting display device provides pixels connected to data lines and scan lines. Each pixel may include an organic light-emitting diode (OLED) and a circuit unit for controlling the amount of current flowing into the OLED. The circuit unit controls the amount of current flowing through the OLED from a first driving voltage to a second driving voltage in response to a data signal. Light with a predetermined brightness can be generated corresponding to the amount of current flowing through the OLED.

[0006] As the use of display devices increases, a single display device can display multiple different images. Summary of the Invention

[0007] The present invention provides an embodiment of a light-emitting driving circuit and a scanning driving circuit that can reduce power consumption, as well as a display device including the light-emitting driving circuit and the scanning driving circuit.

[0008] An embodiment of the present invention provides a light-emitting driving circuit, comprising: a driving circuit configured to output a light-emitting driving signal to a first output terminal and a switching signal to a first node in response to a plurality of clock signals and a first carry signal; and a masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the light-emitting driving signal, and the switching signal. The masking clock signal is a signal that remains at a first level during a normal mode and changes periodically during a low-power mode.

[0009] In an embodiment, the masking circuit may include: a first masking transistor configured to transmit the masking clock signal to the second output terminal in response to the switching signal; and a second masking transistor configured to electrically connect the second output terminal to a first voltage terminal receiving a first voltage in response to the light emission driving signal.

[0010] In an embodiment, when the second masking transistor is turned off and the first masking transistor is turned on, the masking circuit can output the masking clock signal as the second carry signal.

[0011] In an embodiment, the driving circuit may include: a first transistor configured to transmit the first carry signal to a second node in response to a first clock signal among the plurality of clock signals; a second transistor configured to electrically connect the first output terminal to the first voltage terminal in response to a signal from the second node; a third transistor configured to electrically connect the first node to a second voltage terminal receiving a second voltage in response to a signal from the second node; and a fourth transistor configured to electrically connect the first output terminal to the second voltage terminal in response to the switching signal.

[0012] In one embodiment, the driving circuit may further include a capacitor connected between the second node and an input terminal configured to receive a second clock signal among the plurality of clock signals.

[0013] In an embodiment of the present invention, a scan driving circuit includes: a driving circuit configured to output a scan signal to a first output terminal and a switch signal to a first node in response to a plurality of scan clock signals and a first carry signal; and a masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the scan signal, and the switch signal. The masking clock signal is a signal that remains at a first level during a normal mode and changes periodically during a low-power mode.

[0014] In one embodiment, the driving circuit may be electrically connected to a first voltage terminal receiving a first voltage and a second voltage terminal receiving a second voltage. In another embodiment, the masking circuit may include: a first masking transistor configured to electrically connect the second voltage terminal to the second output terminal in response to the switching signal; and a second masking transistor configured to transmit the masking clock signal to the second output terminal in response to the scan signal.

[0015] In an embodiment, when the first masking transistor is turned off and the second masking transistor is turned on, the masking circuit can output the masking clock signal as the second carry signal.

[0016] In an embodiment, the driving circuit may include: a first transistor configured to transmit the first carry signal to a second node in response to a first scan clock signal among the plurality of scan clock signals received through a first input terminal; a second transistor configured to electrically connect the first output terminal to a second input terminal in response to a signal from the second node, the second input terminal being configured to receive a second scan clock signal among the plurality of scan clock signals; a third transistor configured to electrically connect the first node to the first input terminal in response to a signal from the second node; a fourth transistor configured to electrically connect the first node to a first voltage terminal receiving a first voltage in response to the first scan clock signal; and a fifth transistor configured to electrically connect a second voltage terminal receiving a second voltage to the first output terminal in response to a switching signal from the first node.

[0017] In one embodiment, the driving circuit may further include a capacitor connected between the second node and the first output terminal.

[0018] In an embodiment of the present invention, a display device includes: a display panel comprising a plurality of pixels respectively connected to one of a plurality of data lines, one of a plurality of scan lines, and one of a plurality of light-emitting lines; a data driving circuit configured to drive the plurality of data lines; a scan driving circuit configured to drive the plurality of scan lines; a light-emitting driving circuit configured to drive the plurality of light-emitting lines; and a driving controller configured to receive an image signal and a control signal and control the data driving circuit, the scan driving circuit, and the light-emitting driving circuit to display an image on the display panel. In an embodiment, the driving controller may divide the display panel into a first display area and a second display area based on the image signal, and output a first masking signal indicating the start position of the second display area. In an embodiment, the light-emitting driving circuit may include a plurality of light-emitting driving stages, each configured to drive a corresponding light-emitting line among the plurality of light-emitting lines. Each of the plurality of light-emitting driving stages includes: a first driving circuit configured to output a light-emitting driving signal to a first output terminal and output a first switching signal to a first node in response to a plurality of clock signals from the driving controller and a first carry signal; and a first masking circuit configured to output a second carry signal to a second output terminal in response to a first masking clock signal, the light-emitting driving signal, and the first switching signal. The first masking clock signal is maintained at a first level during normal mode and changes periodically during low-power mode.

[0019] In an embodiment, the first masking circuit may include: a first masking transistor configured to transmit the first masking clock signal to the second output terminal in response to the first switching signal; and a second masking transistor configured to electrically connect the second output terminal to a first voltage terminal receiving the first voltage in response to the light-emitting driving signal.

[0020] In an embodiment, when the second masking transistor is turned off and the first masking transistor is turned on, the first masking circuit can output the first masking clock signal as the second carry signal.

[0021] In an embodiment, the second carry signal output from the j-th light-emitting driver stage among the plurality of light-emitting driver stages can be provided as the first carry signal of the (j+k)-th light-emitting driver stage, where each of j and k is a positive integer.

[0022] In an embodiment, the first driving circuit may include: a first transistor configured to transmit the first carry signal to a second node in response to a first clock signal among the plurality of clock signals; a second transistor configured to electrically connect the first output terminal to a first voltage terminal receiving a first voltage in response to a signal from the second node; a third transistor configured to electrically connect the first node to a second voltage terminal receiving a second voltage in response to a signal from the second node; and a fourth transistor configured to electrically connect the first output terminal to the second voltage terminal in response to a first switching signal.

[0023] In an embodiment, the first driving circuit may further include a capacitor connected between the second node and the input terminal, wherein the input terminal receives a second clock signal among the plurality of clock signals.

[0024] In an embodiment, the scan driving circuit may include multiple driving stages configured to drive a corresponding scan line among the plurality of scan lines. Each of the plurality of driving stages includes: a second driving circuit configured to output a scan signal to a third output terminal and output a second switch signal to a second node in response to a plurality of scan clock signals and a third carry signal from the driving controller; and a second masking circuit configured to output a fourth carry signal to a fourth output terminal in response to a second masking clock signal, the scan signal, and the second switch signal. The second masking clock signal is a signal that remains at the first level during normal mode and changes periodically during low-power mode.

[0025] In one embodiment, the second driving circuit may be electrically connected to a third voltage terminal receiving a third voltage and a fourth voltage terminal receiving a fourth voltage. In another embodiment, the second masking circuit may include: a third masking transistor configured to electrically connect the fourth voltage terminal to the fourth output terminal in response to the second switching signal; and a fourth masking transistor configured to transmit the second masking clock signal to the fourth output terminal in response to the scan signal.

[0026] In an embodiment, when the third masking transistor is turned off and the fourth masking transistor is turned on, the second masking circuit can output the second masking clock signal as the fourth carry signal.

[0027] In an embodiment, the fourth carry signal output from the j-th drive stage among the plurality of drive stages can be provided as the third carry signal of the (j+k)-th drive stage, where each of j and k is a positive integer. Attached Figure Description

[0028] The above and other features of the present invention will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, wherein:

[0029] Figure 1 This is a perspective view of a display device according to an embodiment of the concept of the present invention;

[0030] Figure 2 This is a block diagram of a display device according to an embodiment of the present invention;

[0031] Figure 3 This is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0032] Figure 4 It is used to describe Figure 3 The timing diagram of the operations of the pixels shown;

[0033] Figure 5 This is a block diagram of a light-emitting driving circuit according to an embodiment of the present invention.

[0034] Figure 6 This exemplarily illustrates the difference between normal mode and low power mode. Figure 5 The diagram shows the light-emitting driving signal output by the light-emitting driving circuit shown in the figure;

[0035] Figure 7 An example is shown of the light emission drive signal during low power mode;

[0036] Figure 8 This is a circuit diagram showing the j-th light-emitting driving stage inside a light-emitting driving circuit according to an embodiment of the concept of the present invention;

[0037] Figure 9 This is an example illustrating the situation during normal mode. Figure 8 The timing diagram of the operation of the j-th light-emitting driving stage is shown below;

[0038] Figure 10 This is an example illustrating the situation during low power mode. Figure 8 The timing diagram of the operation of the j-th light-emitting driving stage is shown below;

[0039] Figure 11 This is a block diagram of a scan drive circuit according to an embodiment of the present invention.

[0040] Figure 12 This is a circuit diagram illustrating the j-th driving stage in a scan driving circuit according to an embodiment of the present invention;

[0041] Figure 13 This is an example illustrating the situation during normal mode. Figure 12 The timing diagram of the operation of the j-th driver level shown; and

[0042] Figure 14 This is an example illustrating the situation during low power mode. Figure 12 The timing diagram of the operation of the j-th driver level is shown. Detailed Implementation

[0043] Embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0044] In this disclosure, when an element (or region, layer, portion, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, it means that the element may be directly disposed on / connected to / coupled to the other element, or that a third element may be disposed between them. Other terms used to describe the relationship between elements should be interpreted in a similar manner.

[0045] The term "and / or" includes all combinations that one or more related configurations can define.

[0046] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, without departing from the scope of embodiments of the inventive concept, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, singular terms may include plural forms.

[0047] Spatial relative terms, such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., are used herein to readily describe the relationship of one element or feature to another element or feature(s), as illustrated in the figures. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is rotated, an element described as “below” or “below” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both orientations of “above” and “below”.

[0048] It should be understood that the terms “comprising” or “having” are intended to specify the presence of the said feature, integer, step, operation, element, component or combination thereof in this disclosure, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0049] Figure 1 This is a perspective view of a display device DD according to an embodiment of the present invention.

[0050] refer to Figure 1 As an example of a display device DD according to an embodiment of the inventive concept, a portable terminal is shown. Portable terminals may include, for example, tablet computers, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, watch-type electronic devices such as smartwatches, etc. However, the inventive concept is not limited thereto. For example, the inventive concept can be applied to large electronic devices such as televisions or external billboards, and also to small and medium-sized electronic devices such as personal computers, laptop computers, kiosks, car navigation system units, and cameras. It should be understood that these are merely examples, and the inventive concept can be adopted in other electronic devices.

[0051] like Figure 1 As shown, the display surface on which the first image IM1 and the second image IM2 are displayed is parallel to a plane defined by a first direction DR1 and a second direction DR2. The display device DD includes a plurality of regions separated on the display surface. The display surface includes a display area DA in which the first image IM1 and the second image IM2 are displayed, and a non-display area NDA disposed adjacent to the display area DA. A border may be provided in the non-display area NDA. Therefore, the non-display area NDA may also be referred to as a border area. As an example, the display area DA may have a quadrilateral shape. The non-display area NDA surrounds the display area DA. Additionally, as an example, the display device DD may include a partially curved shape. As a result, at least one region of the display device DD may have a curved shape.

[0052] The display area DA of the display device DD includes a first display area DA1 and a second display area DA2. In a specific application, a first image IM1 can be displayed in the first display area DA1, and a second image IM2 can be displayed in the second display area DA2. For example, the first image IM1 can be a moving image (e.g., the first image IM1 can correspond to video), and the second image IM2 can be a still image or text information with a long change cycle (e.g., text information that is not frequently refreshed).

[0053] According to an embodiment, the display device DD can drive a first display area DA1 in which moving images are displayed at a normal frequency, and can drive a second display area DA2 in which still images are displayed at a frequency lower than the normal frequency. The display device DD can reduce power consumption by reducing the driving frequency of the second display area DA2.

[0054] The size of each of the first display area DA1 and the second display area DA2 can be a preset size and can be changed by an application. Although an embodiment in which the first display area DA1 displays a moving image and the second display area DA2 displays a still image has been described above, the inventive concept is not limited thereto. For example, in an embodiment, the first display area DA1 can display a still image and the second display area DA2 can display a moving image, and in such an embodiment, when the first display area DA1 displays a still image and the second display area DA2 displays a moving image, the first display area DA1 can be driven at a lower frequency, and the second display area DA2 can be driven at a normal frequency.

[0055] Figure 2 This is a block diagram of a display device DD according to an embodiment of the present invention.

[0056] refer to Figure 1 and Figure 2 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0057] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates an image data signal DATA by converting the data format of the image signal RGB to meet the interface specifications of the data drive circuit 200. The drive controller 100 outputs an illumination control signal ECS, a scan control signal SCS, and a data control signal DCS.

[0058] The data drive circuit 200 receives the data control signal DCS and the image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1, DL2 to DLm (hereinafter referred to as DL1 to DLm), where m is a positive integer, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0059] Voltage generator 300 generates voltages for the operation of display panel DP. In an embodiment, voltage generator 300 generates a first drive voltage ELVDD, a second drive voltage ELVSS, and an initialization voltage VINT. In an embodiment, voltage generator 300 can operate under the control of drive controller 100.

[0060] The display panel DP includes a scan driving circuit SD, a light-emitting driving circuit EDC, scan lines SL0, SL1, SL2, SL3 to SLn (hereinafter referred to as SL0 to SLn), light-emitting lines EML1, EML2, EML3 to EMLn (hereinafter referred to as EML1 to EMLn), data lines DL1 to DLm, and pixels PX, where n is a positive integer. In an embodiment, the scan driving circuit SD is arranged on a first side of the display panel DP, and the light-emitting driving circuit EDC is arranged on a second side of the display panel DP opposite to the first side of the display panel DP. That is, the scan driving circuit SD and the light-emitting driving circuit EDC can be spaced apart in a first direction DR1, and a pixel PX is disposed between the scan driving circuit SD and the light-emitting driving circuit EDC. However, the inventive concept is not limited to this. For example, in an embodiment, the scan driving circuit SD and the light-emitting driving circuit EDC can be disposed adjacent to the first side of the display panel DP.

[0061] Scan lines SL0 to SLn extend from the scan drive circuit SD in the first direction DR1 and are spaced apart from each other in the second direction DR2. Emitting lines EML1 to EMLn extend from the emitting drive circuit EDC in the opposite direction to the first direction DR1 and are spaced apart from each other in the second direction DR2.

[0062] Data lines DL1 to DLm extend from the data drive circuit 200 in the opposite direction to the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0063] Each pixel PX is electrically connected to three corresponding scan lines SL0 to SLn. Additionally, each pixel PX is electrically connected to one corresponding light-emitting line EML1 to EMLn and one corresponding data line DL1 to DLm. For example, as... Figure 2As shown, the pixel PX in the first row can be connected to scan lines SL0, SL1, and SL2, as well as the light-emitting line EML1. Additionally, the pixel PX in the second row can be connected to scan lines SL1, SL2, and SL3, as well as the light-emitting line EML2.

[0064] Each of the multiple pixels PX includes an organic light-emitting diode (ED) (see Figure 3 ) and the pixel circuit unit PXC that controls the light emission of the organic light-emitting diode ED (see Figure 3 The pixel circuit unit (PXC) may include multiple transistors T1 to T7 and a capacitor Cst. The scan drive circuit (SD) may include transistors formed using the same process as the pixel circuit unit (PXC).

[0065] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0066] The scan drive circuit SD receives the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD can output scan signals to scan lines SL0 to SLn. The circuit configuration and operation of the scan drive circuit SD will be described in more detail below.

[0067] The light-emitting driver circuit EDC receives the light-emitting control signal ECS from the driver controller 100. In response to the light-emitting control signal ECS, the light-emitting driver circuit EDC can output the light-emitting control signal to the light-emitting lines EML1 to EMLn.

[0068] According to an embodiment, the drive controller 100 divides the display panel DP into a first display area DA1 based on the image signal RGB (see [reference]). Figure 1 ) and the second display area DA2 (see Figure 1 The signal includes at least one masking clock signal, which indicates the start position of the second display area DA2. The at least one masking clock signal may be included in the illumination control signal ECS. Furthermore, the at least one masking clock signal may be included in the scan control signal SCS.

[0069] According to the embodiment, the scan driving circuit SD can drive the scan lines SL0 to SLn corresponding to the first display area DA1 at a first driving frequency, and can drive the scan lines corresponding to the second display area DA2 at a second driving frequency different from the first driving frequency in response to the scan control signal SCS.

[0070] According to the embodiment, the light-emitting driving circuit EDC can drive the light-emitting lines EML1 to EMLn that correspond to the first display area DA1 at a first driving frequency, and can drive the light-emitting lines that correspond to the second display area DA2 at a second driving frequency that is different from the first driving frequency in response to the light-emitting control signal ECS.

[0071] Figure 3 This is an equivalent circuit diagram of pixel PXij according to an embodiment of the present invention.

[0072] Figure 3 An example is shown connecting to, such as Figure 2 The equivalent circuit diagram shown is for the pixel PXij of the i-th data line DLi among the multiple data lines DL1 to DLm, the (j-1)-th scan line SLj-1, the j-th scan line SLj and the (j+1)-th scan line SLj+1 among the scan lines SL0 to SLn, and the j-th light-emitting line EMLj among the light-emitting lines EML1 to EMLn, where i and j are positive integers.

[0073] In an embodiment, the pixel circuit unit PXC of pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Each of the first transistors T1 to the seventh transistor T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the inventive concept is not limited thereto. For example, in an embodiment, at least one of the first transistors T1 to the seventh transistor T7 may be an N-type transistor, and the remainder of the first transistors T1 to the seventh transistor T7 may be P-type transistors. Furthermore, the circuit configuration of pixel PXij according to the inventive concept is not limited to... Figure 3 The configuration shown is illustrated. For example, in one embodiment, pixel PXij can be connected to two corresponding scan lines among scan lines SL0 to SLn. Figure 3 The pixel circuit unit PXC shown is just an example, and the configuration of the pixel circuit unit PXC can be modified and implemented in various ways.

[0074] refer to Figure 3 The display device DD according to the embodiment (see Figure 1 The pixel PXij includes at least one organic light-emitting diode (OLED). Here, an example of a pixel PXij including one OLED is used. However, the inventive concept is not limited thereto.

[0075] For ease of explanation, Figures 3 to 4In the description, the (j-1)th scan line SLj-1, the jth scan line SLj, the (j+1)th scan line SLj+1 and the jth light-emitting line EMLj are respectively referred to as the first scan line SLj-1, the second scan line SLj, the third scan line SLj+1 and the light-emitting line EMLj.

[0076] The first scan line SLj-1, the second scan line SLj, and the third scan line SLj+1 can respectively transmit the first scan signal SCj-1, the second scan signal SCj, and the third scan signal SCj+1. The first scan signal SCj-1 can turn on / off the fourth transistor T4. The second scan signal SCj can turn on / off the second transistor T2 and the third transistor T3. The third scan signal SCj+1 can turn on / off the seventh transistor T7.

[0077] The light-emitting line EMLj can transmit a light-emitting drive signal EMj that controls the emission of the organic light-emitting diodes ED included in pixel PXij. The light-emitting drive signal EMj transmitted by the light-emitting line EMLj can have a waveform different from the first scan signal SCj-1, the second scan signal SCj, and the third scan signal SCj+1. The data line DLi transmits a data signal Di. The data signal Di can have a waveform similar to the image signal RGB (see image signal RGB) input to the display device DD. Figure 2 The corresponding voltage levels are: the first driving voltage line VL1, the second driving voltage line VL2, and the third driving voltage line VL3, which can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT.

[0078] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the organic light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted by the data line DLi according to the switching operation of the second transistor T2, and supply the drive current Id to the organic light-emitting diode ED.

[0079] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the second scan line SLj. The second transistor T2 can be turned on according to the second scan signal SCj received through the second scan line SLj, and transmit the data signal Di transmitted from the data line DLi to the first electrode of the first transistor T1.

[0080] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the second scan line SLj. The third transistor T3 can be turned on according to the second scan signal SCj received through the second scan line SLj, and connects the gate electrode and the second electrode of the first transistor T1, thereby diode-connecting the first transistor T1.

[0081] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third drive voltage line VL3 through which the initialization voltage VINT is transmitted, and a gate electrode connected to the first scan line SLj-1. The fourth transistor T4 can be turned on according to the first scan signal SCj-1 received through the first scan line SLj-1, and transmits the initialization voltage VINT to the gate electrode of the first transistor T1, thereby performing an initialization operation for initializing the voltage of the gate electrode of the first transistor T1.

[0082] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light-emitting line EMLj.

[0083] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the organic light-emitting diode ED, and a gate electrode connected to the light-emitting line EMLj.

[0084] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously according to the light-emitting drive signal EMj received through the light-emitting line EMLj. As a result, the first drive voltage ELVDD can be compensated by the first transistor T1 connected to the diode and transmitted to the organic light-emitting diode ED.

[0085] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the third scan line SLj+1.

[0086] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the organic light-emitting diode ED can be connected to the second driving voltage line VL2 configured to transmit the second driving voltage ELVSS. The structure of pixel PXij according to the embodiment is not limited to... Figure 3 The structure shown is illustrated. For example, in an embodiment, various modifications can be made to the number of transistors and capacitors included in a pixel PXij and their interconnections.

[0087] Figure 4It is used to describe Figure 3 The timing diagram shows the operation of pixel PXij. (Reference) Figure 3 and Figure 4 The operation of the display device DD according to an embodiment will be described.

[0088] refer to Figure 3 and Figure 4 During the initialization period within a frame F, a low-level first scan signal SCj-1 is supplied through the first scan line SLj-1. In response to the low-level first scan signal SCj-1, the fourth transistor T4 is turned on, and through the fourth transistor T4, the initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 to initialize the first transistor T1.

[0089] Next, when a low-level second scan signal SCj is supplied via the second scan line SLj during the data programming and compensation cycle, the third transistor T3 is turned on. The first transistor T1 is connected to a diode through the turned-on third transistor T3 and is biased in the forward direction. Additionally, the second transistor T2 is turned on via the second scan signal SCj. Then, a compensation voltage (Di-Vth) is applied to the gate electrode of the first transistor T1, subtracted from the threshold voltage (Vth) of the first transistor T1, from the data signal Di supplied via the data line DL1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage (Di-Vth).

[0090] A first driving voltage ELVDD and a compensation voltage (Di-Vth) are applied to the two ends of capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in capacitor Cst.

[0091] Simultaneously, the seventh transistor T7 is turned on by supplying a low-level third scan signal SCj+1 via the third scan line SLj+1. A portion of the drive current Id can flow out through the seventh transistor T7 as a bypass current Ibp.

[0092] Even if the organic light-emitting diode (OLED) emits light when the minimum current of the first transistor T1 used to display a black image flows as the drive current, the black image may not be displayed correctly. Therefore, the seventh transistor T7 in the pixel PXij according to an embodiment of the present invention can divert a portion of the minimum current of the first transistor T1, which is a bypass current Ibp, to a current path other than the current slot on the OLED side. Here, the minimum current of the first transistor T1 refers to the current when the first transistor T1 is turned off because its gate-source voltage (Vgs) is less than the threshold voltage (Vth). In this way, the minimum drive current (e.g., approximately 10 pA or less) when the first transistor T1 is turned off is transmitted to the OLED and displayed as a black image. When the minimum drive current used to display a black image flows, the effect of the bypass transmission of the bypass current Ibp may be significant. However, when a large drive current is used to display images such as normal images or white images, the effect of the bypass current Ibp may be small. Therefore, when the drive current for displaying a black image flows, the luminous current Ied of the organic light-emitting diode ED, which is the amount of current from the drive current Id minus the bypass current Ibp drawn through the seventh transistor T7, can have a minimum current amount to reliably display a black image. Thus, the seventh transistor T7 can be used to achieve an image with corrected black brightness, thereby improving contrast. In this embodiment, the bypass signal is a low-level third scan signal SCj+1, but it is not limited to this.

[0093] Next, during the light emission cycle, the light emission drive signal EMj supplied from the light emission line EMLj changes from a high level to a low level. During the light emission cycle, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level light emission drive signal EMj. Then, a drive current Id corresponding to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD is generated, and the drive current Id is supplied to the organic light-emitting diode ED through the sixth transistor T6, so that the light emission current Ied flows in the organic light-emitting diode ED.

[0094] Figure 5 This is a block diagram of an EDC (Electronic Light-Emitting Drive) circuit according to an embodiment of the present invention.

[0095] refer to Figure 5 The light-emitting driver circuit EDC includes light-emitting driver stages EST1, EST2, EST3, EST4 to ESTn (hereinafter referred to as EST1 to ESTn), where n is a positive integer.

[0096] Each of the light-emitting driver stages EST1 to ESTn Figure 2The drive controller 100 shown receives a light emission control signal ECS. The light emission control signal ECS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3. Each of the light emission driver stages EST1 to ESTn receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 2 The voltage generator 300 shown is provided.

[0097] The third clock signal CLK3 is used to drive some stages of the LED driver stages EST1 to ESTn at normal frequency and the remaining stages of the LED driver stages EST1 to ESTn at low frequency. The third clock signal CLK3 can be provided to all LED driver stages EST1 to ESTn in the LED driver circuit EDC. The output signals of some of the LED driver stages EST1 to ESTn can be masked to a predetermined level by the third clock signal CLK3. The third clock signal CLK3 can be called the masking clock signal.

[0098] In this embodiment, the light-emitting driver stages EST1 to ESTn output light-emitting driver signals EM1, EM2, EM3, EM4 to EMn (hereinafter referred to as EM1 to EMn). The light-emitting driver signals EM1 to EMn can be provided to... Figure 2 The pixel PX shown.

[0099] The LED driver stage EST1 can receive the start signal FLM as the first carry signal. Each of the LED driver stages EST2 through ESTn is cascaded, with the second carry signal output from the preceding LED driver stage being received as the first carry signal. For example, LED driver stage EST2 receives the second carry signal ECR1 output from LED driver stage EST1 as the first carry signal. LED driver stage EST3 receives the second carry signal ECR2 output from LED driver stage EST2 as the first carry signal. LED driver stage EST4 receives the second carry signal ECR3 output from LED driver stage EST3 as the first carry signal. LED driver stage ESTn receives the second carry signal ECRn-1 output from LED driver stage ESTn-1 as the first carry signal. Figure 5 In the middle, the j-th luminescent driving stage ESTj (reference) Figure 8 The diagram illustrates receiving a second carry signal from the (j-1)th light-emitting driver stage ESTj-1 (not shown) as the first carry signal, but the inventive concept is not limited thereto. In an embodiment, a second carry signal ECRj (refer to) output from the j-th light-emitting driver stage ESTj can be provided. Figure 8 ) is the first carry signal of the (j+k)th light-emitting driver stage ESTj+k (not shown), where j and k are positive integers.

[0100] Figure 6 This exemplarily illustrates the operation from normal mode N-MODE and low power mode L-MODE. Figure 5 The diagram shows the output signals EM1, EM2, ..., EM1920, EM1921, ... to EMn of the light-emitting drive circuit EDC, where n is 3840.

[0101] refer to Figure 5 and Figure 6 During normal N-MODE, the third clock signal CLK3 remains high. During normal N-MODE, in each of frames F1, F2, and F3, the light-emitting driver stages EST1 to ESTn sequentially output light-emitting driver signals EM1 to EMn. When light-emitting driver signals EM1 to EMn are high, the fifth transistor T5 (see...)... Figure 3 ) and the sixth transistor T6 (see Figure 3 The light-emitting drive signals EM1 through EMn transition from high to low, and the fifth transistor T5 and the sixth transistor T6 turn on, allowing power to be supplied to the organic light-emitting diode ED (see...). Figure 3 Supply drive current Id (see) Figure 3 ).

[0102] During the low-power mode (L-MODE), the third clock signal CLK3 changes from high to low in each frame. For example, although the third clock signal CLK3 is kept high in the fourth frame (F4), the light-emitting drive signals EM1 to EM1920 can be driven sequentially at high levels. When the third clock signal CLK3 is changed low in the fourth frame (F4), the light-emitting drive signals EM1921 to EM3840 are masked low. For example, when the light-emitting drive signal EM1921 is kept low in the fourth frame (F4), the fifth transistor T5 (see...) can be driven... Figure 3 ) and the sixth transistor T6 (see Figure 3 ) Remains on. When the fifth transistor T5 (see Figure 3 ) and the sixth transistor T6 (see Figure 3 When the organic light-emitting diode (ED) remains on, it is in the on state. Figure 3 It can remain in the glowing state of the previous frame, i.e., the third frame F3.

[0103] like Figure 6 As shown, in this embodiment, the third clock signal CLK3 (masking clock signal) remains at a first level during normal mode (N-MODE) and periodically changes between a first level and a second level during low-power mode (L-MODE). As further described below, this driving scheme allows the embodiment to reduce power consumption without degrading the display quality of the display device DD.

[0104] Figure 7 An example is shown of the light-emitting drive signals EM1 to EMn during low-power mode L-MODE, where n is 3840.

[0105] refer to Figure 7 During the low-power mode (L-MODE), the frequency of the light-emitting drive signals EM1 to EM1920 is 120Hz, and the frequency of the light-emitting drive signals EM1921 to EM3840 is 1Hz.

[0106] For example, the light-emitting drive signals EM1 to EM1920 correspond to Figure 1 The first display area DA1 of the display device DD shown is shown, and the light-emitting drive signals EM1921 to EM3840 correspond to... Figure 1 The second display area DA2 is shown in the diagram. The first display area DA1, which displays moving images, is driven by light-emitting drive signals EM1 to EM1920 at a normal frequency (e.g., 120Hz), while the second display area DA2, which displays still images, is driven by light-emitting drive signals EM1921 to EM3840 at a low frequency (e.g., 1Hz). Since only the second display area DA2, which displays still images, is driven at a low frequency, it is possible to reduce the display device's DD (see [reference]). Figure 1 This reduces power consumption while maintaining display quality. For example, in one embodiment, the first display area DA1 and the second display area DA2 are driven at different frequencies, respectively, so that moving and still images are properly displayed in the respective display areas DA1 and DA2 without reducing display quality or consuming additional unnecessary power.

[0107] Figure 8 This is a circuit diagram illustrating the j-th light-emitting driving stage ESTj in the light-emitting driving circuit EDC according to an embodiment of the present invention.

[0108] Figure 8 Exemplary Figure 5 The j-th light-emitting driver level ESTj is shown among the light-emitting driver levels EST1 to ESTn, where j is a positive integer. Figure 5 Each of the plurality of light-emitting driving stages EST1 to ESTn shown may include, with Figure 8 The j-th light-emitting driver stage ESTj shown has the same circuit configuration. Hereinafter, the j-th light-emitting driver stage ESTj will be referred to as light-emitting driver stage ESTj.

[0109] refer to Figure 8The light-emitting driver stage ESTj includes a driver circuit EC and a masking circuit MSC, a first input terminal IN1 to a fourth input terminal IN4, a first voltage terminal V1, a second voltage terminal V2, a first output terminal OUT1, and a second output terminal OUT2.

[0110] The driving circuit EC includes transistors M1 to M10 and capacitors C1 to C3. Each of transistors M1 to M10 is shown and described as a P-type transistor, but the inventive concept is not limited thereto. For example, in an embodiment, some or all of transistors M1 to M10 may be N-type transistors.

[0111] The driver circuit EC receives the first clock signal CLK1, the second clock signal CLK2, the first carry signal ECRj-1, and the third clock signal CLK3 through its first input terminal IN1 to its fourth input terminal IN4. The driver circuit EC receives the first voltage VGL and the second voltage VGH through its first voltage terminal V1 and second voltage terminal V2, respectively. The driver circuit EC outputs the light-emitting drive signal EMj through its first output terminal OUT1 and the second carry signal ECRj through its second output terminal OUT2.

[0112] The first carry signal ECRj-1 received through the third input terminal IN3 can be a signal output from the light-emitting driver stage ESTj-1 (not shown). Figure 5 The first carry signal ECRj-1 of the light-emitting driver stage EST1 shown can be the start signal FLM.

[0113] Figure 5 In the light-emitting driver stages EST1 to ESTn shown, the first input IN1 of each of the light-emitting driver stages (e.g., odd-numbered light-emitting driver stages) receives the first clock signal CLK1, and its second input IN2 receives the second clock signal CLK2.

[0114] Additionally, the first input terminal IN1 of some of the light-emitting driver stages EST1 to ESTn (e.g., even-numbered light-emitting driver stages) receives the second clock signal CLK2, and its second input terminal IN2 receives the first clock signal CLK1.

[0115] Transistor M1 is connected between the third input terminal IN3 and the second node N2, and includes a gate electrode connected to the first input terminal IN1. Transistor M1 can send a first carry signal ECRj-1 to the second node N2 in response to a first clock signal CLK1. Transistor M2 is connected between the third node N3 and the first input terminal IN1, and includes a gate electrode connected to the second node N2. Transistor M3 is connected between the third node N3 and the first voltage terminal V1, and includes a gate electrode connected to the first input terminal IN1.

[0116] Transistors M5 and M4 are connected in series between the second voltage terminal V2 and the second node N2. The gate electrode of transistor M5 is connected to the third node N3, and the gate electrode of transistor M4 is connected to the second input terminal IN2.

[0117] Transistor M6 is connected between one end of capacitor C2 and the second input terminal IN2, and includes a gate electrode connected to the third node N3. Transistor M7 is connected between one end of capacitor C2 and the first node N1, and includes a gate electrode connected to the second input terminal IN2. Transistor M8 is connected between the second voltage terminal V2 and the first node N1, and includes a gate electrode connected to the second node N2. Transistor M8 can electrically connect the first node N1 to the second voltage terminal V2 receiving the second voltage VGH in response to a signal from the second node N2.

[0118] Transistor M9 is connected between the second voltage terminal V2 and the first output terminal OUT1, and includes a gate electrode connected to the first node N1. Transistor M9 can electrically connect the first output terminal OUT1 to the second voltage terminal V2 in response to a switching signal received at the first node N1. Transistor M10 is connected between the first output terminal OUT1 and the first voltage terminal V1, and includes a gate electrode connected to the second node N2.

[0119] Capacitor C1 is connected between the second node N2 and the second input terminal IN2. Capacitor C2 is connected between the third node N3 and the first electrode of transistor M6. Capacitor C3 is connected between the second voltage terminal V2 and the first node N1.

[0120] The masking circuit MSC includes a first masking transistor MT11 and a second masking transistor MT12. Each of the masking transistors MT11 and MT12 is shown and described as a P-type transistor, but the inventive concept is not limited thereto. For example, in an embodiment, one or both of the masking transistors MT11 and MT12 may be N-type transistors.

[0121] The masking circuit MSC can mask the second carry signal ECRj output from the second output terminal OUT2 in response to the third clock signal CLK3 received through the fourth input terminal IN4, the signal of the first node N1, and the light-emitting drive signal EMj output through the first output terminal OUT1. That is, the masking circuit MSC can selectively output the second carry signal ECRj to the second output terminal OUT2. The signal of the first node N1 can be a switching signal complementary to the light-emitting drive signal EMj output through the first output terminal OUT1. That is, the drive circuit EC can output a switching signal to the first node N1. In an embodiment, the drive circuit EC can output the light-emitting drive signal EMj to the first output terminal OUT1 and output a switching signal to the first node N1 in response to the clock signal and the first carry signal ECRj-1 input to the drive circuit EC.

[0122] The first masking transistor MT11 is connected between the fourth input terminal IN4 and the second output terminal OUT2, and includes a gate electrode connected to the first node N1. The first masking transistor MT11 can transmit the third clock signal CLK3 (masking clock signal) received through the fourth input terminal IN4 to the second output terminal OUT2 in response to the signal (switching signal) of the first node N1.

[0123] The second masking transistor MT12 is connected between the second output terminal OUT2 and the first voltage terminal V1, and includes a gate electrode connected to the first output terminal OUT1. The second masking transistor MT12 can electrically connect the second output terminal OUT2 to the first voltage terminal V1 in response to the light-emitting drive signal EMj output through the first output terminal OUT1.

[0124] Figure 9 This is an example illustrating the situation during normal mode N-MODE. Figure 8 The timing diagram shown is for the operation of the j-th light-emitting driver stage ESTj.

[0125] refer to Figure 6 , Figure 8 and Figure 9 The first clock signal CLK1 and the second clock signal CLK2 are signals having the same frequency and transitioning to an active level (e.g., low level) in different horizontal portions (e.g., the (j-3)th horizontal portion Hj-3, the (j-2)th horizontal portion Hj-2, the (j-1)th horizontal portion Hj-1, the jth horizontal portion Hj, and the (j+1)th horizontal portion Hj+1 described below). The horizontal portion is the pixel PX in a row on the first direction DR1 of the display panel DP during its period (see...). Figure 2 (Time period)

[0126] When the first carry signal ECRj-1 transitions from low to high in the (j-3)th level portion Hj-3 and the first clock signal CLK1 is low, transistor M1 turns on. When transistor M1 turns on, the second node N2 rises to the voltage level of the first carry signal ECRj-1. When the signal of the second node N2 transitions to high, transistors M8 and M10 turn on. Furthermore, when the signal of the second node N2 transitions to high, transistor M4 turns on, causing the signal of the third node N3 to transition to low. Transistor M10 can electrically connect the first output terminal OUT1 to the first voltage terminal V1 in response to the signal of the second node N2.

[0127] When the second clock signal CLK2 is low at the (j-2)th level (Hj-2), transistor M7 is turned on, causing the signal at the first node N1 to go low. When the signal at the first node N1 is low, transistor M9 is turned on, so the second voltage VGH can be output as the light-emitting drive signal EMj.

[0128] When the signal at the first node N1 is low, the first masking transistor MT11 in the masking circuit MSC is turned on, and the second masking transistor MT12 in the masking circuit MSC is turned off by the high-level light-emitting drive signal EMj. Since the third clock signal CLK3 remains high during the normal mode N-MODE, the high-level third clock signal CLK3 can be output as the second carry signal ECRj. For example, in an embodiment, when the first masking transistor MT11 is turned on and the second masking transistor MT12 is turned off, the masking circuit MSC outputs the third clock signal CLK3 (masking clock signal) as the second carry signal ECRj.

[0129] When the first clock signal CLK1 is low in the (j+1)th level portion Hj+1, if the first carry signal ECRj-1 is low, then the second node N2 transitions to a low level corresponding to the first carry signal ECRj-1. When the signal of the second node N2 transitions to a low level, transistors M8 and M10 are turned on, thereby causing the signal of the first node N1 to transition to a high level, and the light-emitting drive signal EMj transitions to a low level. Additionally, when the signal of the first node N1 transitions to a high level, the first masking transistor MT11 is turned off, and the second masking transistor MT12 is turned on by the low-level light-emitting drive signal EMj. Through the second masking transistor MT12, the second output terminal OUT2 is electrically connected to the first voltage terminal V1, thereby enabling the output of the low-level second carry signal ECRj.

[0130] As described above, the j-th light-emitting driver stage ESTj can output the light-emitting driver signal EMj and the second carry signal ECRj in response to the first carry signal ECRj-1 and the first clock signal CLK1 to the third clock signal CLK3 during normal mode N-MODE.

[0131] Figure 10 This is an example illustrating the situation during low power mode (L-MODE). Figure 8 The timing diagram shown is for the operation of the j-th light-emitting driver stage ESTj.

[0132] refer to Figure 6 , Figure 8 and Figure 10 During low-power mode (L-MODE), the second display area DA2 will be driven at a low frequency (see...). Figure 1 At the beginning of the clock cycle, the third clock signal CLK3 changes from high to low.

[0133] When the first carry signal ECRj-1 transitions from low to high in the (j-3)th level portion Hj-3 and the first clock signal CLK1 is low, transistor M1 turns on. When transistor M1 is on, the second node N2 rises to the voltage level of the first carry signal ECRj-1. When the signal of the second node N2 transitions to high, transistors M8 and M10 turn on. Furthermore, when the signal of the second node N2 transitions to high, transistor M4 turns on, thereby causing the signal of the third node N3 to transition to low.

[0134] When the second clock signal CLK2 is low in the (j-2)th horizontal portion Hj-2, transistor M7 is turned on, causing the signal of the first node N1 to go low. When the signal of the first node N1 is low, transistor M9 is turned on, so that the second voltage VGH can be output as the light-emitting drive signal EMj.

[0135] When the signal of the first node N1 is low, the first masking transistor MT11 in the masking circuit MSC is turned on, and the second masking transistor MT12 in the masking circuit MSC is turned off by the high-level light emission drive signal EMj. If the third clock signal CLK3 is low during the low power mode L-MODE, the low-level third clock signal CLK3 can be output as the second carry signal ECRj.

[0136] When the first clock signal CLK1 is low in the (j+1)th level portion Hj+1, if the first carry signal ECRj-1 is low, then the second node N2 transitions to a low level corresponding to the first carry signal ECRj-1. When the signal of the second node N2 transitions to a low level, transistors M8 and M10 are turned on, thereby causing the signal of the first node N1 to transition to a high level, and the light-emitting drive signal EMj transitions to a low level. Additionally, when the signal of the first node N1 transitions to a high level, the first masking transistor MT11 is turned off, and the second masking transistor MT12 is turned on by the low-level light-emitting drive signal EMj. Through the second masking transistor MT12, the second output terminal OUT2 is electrically connected to the first voltage terminal V1, thereby enabling the output of the low-level second carry signal ECRj.

[0137] As described above, if the operating mode is low power mode (L-MODE) and the third clock signal CLK3 is low, then the j-th light-emitting driver stage ESTj can output a low-level second carry signal ECRj.

[0138] The (j+1)th light-emitting driver stage ESTj+1 (not shown) receives the low-level second carry signal ECRj output from the j-th light-emitting driver stage ESTj as the first carry signal. The second node N2 in the (j+1)th light-emitting driver stage ESTj+1 is kept at a low level and the transistor M10 is turned on, so that the light-emitting driver signal EMj can be switched to a high level.

[0139] As described above, when the third clock signal CLK3 transitions to a low level in the (j-2) level portion Hj-2 during the low power mode L-MODE, the second carry signal ECRj output from the j-th light-emitting driver stage ESTj remains at a low level, and the light-emitting driver signal EMj+1 output from the (j+1)-th light-emitting driver stage ESTj+1 remains at a low level.

[0140] In this embodiment, after the third clock signal CLK3 goes low, the light-emitting drive signal is not activated by going high after the third horizontal period 3H.

[0141] For example, when Figure 1 The starting position of the second display area DA2 shown corresponds to the position of the light-emitting drive signal EM1921 (see [link]). Figure 6 If the third clock signal CLK3 goes low in the 1918th horizontal cycle H1918, the light-emitting drive signal EM1921 can remain low and will not be activated by a high level. Figure 6As shown, while the third clock signal CLK3 remains low, the light-emitting drive signals EM1921 to EM3840 can remain low without being activated by a high level. Therefore, during low-power mode (L-MODE), Figure 1 The first display area DA1 shown can be driven at a normal frequency (e.g., 120Hz), and Figure 1 The second display area DA2 shown can be driven at a low frequency (e.g., 1 Hz). Since the first display area DA1, which displays moving images, is driven at a normal frequency, while the second display area DA2, which displays still images, is driven at a frequency lower than the normal frequency, the power consumption of the display device DD may be reduced.

[0142] Figure 11 This is a block diagram of a scan drive circuit SD according to an embodiment of the present invention.

[0143] refer to Figure 11 The scan drive circuit SD includes drive stages ST0, ST1, ST2, ST3 to STn (hereinafter referred to as ST0 to STn), where n is a positive integer.

[0144] Each drive level from ST0 to STn Figure 2 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal SFLM, a first scan clock signal SCLK1, a second scan clock signal SCLK2, and a third scan clock signal SCLK3. Each drive stage ST0 to STn receives a first voltage SVGL and a second voltage SVGH. The first voltage SVGL and the second voltage SVGH can be obtained from... Figure 2 The voltage generator 300 shown is provided.

[0145] The third scan clock signal SCLK3 is used to drive some stages ST0 to STn at normal frequency and the remaining stages ST0 to STn at low frequency. The third scan clock signal SCLK3 can be provided to all stages ST0 to STn in the scan drive circuit SD. The third scan clock signal SCLK3 can be called the masking clock signal.

[0146] In this embodiment, the driver stages ST0 to STn output scan signals SC0, SC1, SC2, SC3 to SCn (hereinafter referred to as SC0 to SCn). Scan signals SC0 to SCn can be provided to... Figure 2 The pixel PX shown.

[0147] Driver stage ST0 can receive the start signal SFLM as a carry signal. Each of driver stages ST1 to STn is cascaded, where the second carry signal output from the previous driver stage is received as the first carry signal. From the j-th driver stage STj (see...) Figure 12 The second carry signal CRj output can be provided as the first carry signal of the (j+k)th driver stage STj+k (not shown), where each of j and k is a positive integer. For example, driver stage ST1 receives the second carry signal CR0 output from driver stage ST0 as the first carry signal, driver stage ST2 receives the second carry signal CR1 output from driver stage ST1 as the first carry signal, driver stage ST3 receives the second carry signal CR2 output from driver stage ST2 as the first carry signal, and driver stage STn receives the second carry signal CRn-1 output from driver stage ST3 as the first carry signal. Figure 11 In the middle, the j-th driver level STj (reference) Figure 12 The diagram shows the second carry signal being received from the (j-1)th drive stage STj-1 (not shown) as the first carry signal, but the concept of the present invention is not limited thereto.

[0148] Figure 12 This is a circuit diagram illustrating the j-th drive stage STj in a scan drive circuit SD according to an embodiment of the present invention.

[0149] Figure 12 An example is shown Figure 11 The j-th driver STj is shown in the driver levels ST0 to STn, where j is a positive integer. Figure 11 Each of the plurality of driver levels ST0 to STn shown can have the same circuit configuration as the j-th driver level STj. Hereinafter, the j-th driver level STj will be referred to as driver level STj.

[0150] refer to Figure 12 The driver stage STj includes a driver circuit DC and a masking circuit MSC2, a first input terminal IN11 to a fourth input terminal IN14, a first voltage terminal V11, a second voltage terminal V12, a first output terminal OUT11, and a second output terminal OUT12.

[0151] The driving circuit DC includes transistors M11 to M17 and capacitors C11 and C12. Each of transistors M11 to M17 is shown and described as a P-type transistor, but the inventive concept is not limited thereto. For example, in an embodiment, some or all of transistors M11 to M17 may be N-type transistors.

[0152] The DC drive circuit receives the first scan clock signal SCLK1, the second scan clock signal SCLK2, the first carry signal CRj-1, and the third scan clock signal SCLK3 through its first input terminal IN11 to its fourth input terminal IN14. The DC drive circuit also receives the first voltage SVGL and the second voltage SVGH through its first voltage terminal V11 and second voltage terminal V12. Finally, the DC drive circuit outputs the scan signal SCj through its first output terminal OUT11 and the second carry signal CRj through its second output terminal OUT12.

[0153] The first carry signal CRj-1 received through the third input terminal IN13 can be the second carry signal output from the driver stage STj-1. Figure 11 The first carry signal CRj-1 (not shown) of the drive stage ST0 shown in the figure can be the start signal SFLM.

[0154] Figure 11 In the driver stages ST0 to STn shown, each of the driver stages (e.g., odd-numbered driver stages) receives a first scan clock signal SCLK1 at its first input IN11 and a second scan clock signal SCLK2 at its second input IN12. Conversely, in the driver stages ST0 to STn, each of the driver stages (e.g., even-numbered driver stages) receives a second scan clock signal SCLK2 at its first input IN11 and a first scan clock signal SCLK1 at its second input IN12.

[0155] Transistor M11 is connected between the third input terminal IN13 and the second node N12, and includes a gate electrode connected to the first input terminal IN11. Transistor M11 can transmit a first carry signal CRj-1 to the second node N12 in response to a first scan clock signal SCLK1 received through the first input terminal IN11. Transistors M12 and M13 are connected in series between the second voltage terminal V12 and the second node N12. The gate electrode of transistor M12 is connected to the first node N11, and the gate electrode of transistor M13 is connected to the second input terminal IN12.

[0156] Transistor M14 is connected between first node N11 and first input terminal IN11, and includes a gate electrode connected to second node N12. Transistor M14 can electrically connect first node N11 to first input terminal IN11 in response to a signal from second node N12. Transistor M15 is connected between first node N11 and first voltage terminal V11, and includes a gate electrode connected to first input terminal IN11. Transistor M15 can connect first node N11 to first voltage terminal V11 receiving first voltage SVGL in response to a first scan clock signal SCLK1.

[0157] Transistor M16 is connected between the second voltage terminal V12 and the first output terminal OUT11, and includes a gate electrode connected to the first node N11. Transistor M16 can connect the second voltage terminal V12, which receives the second voltage SVGH, to the first output terminal OUT11 in response to a switching signal at the first node N11. Transistor M17 is connected between the first output terminal OUT11 and the second input terminal IN12, and includes a gate electrode connected to the second node N12. Transistor M17 can electrically connect the first output terminal OUT11 to the second input terminal IN12, which receives the second scan clock signal SCLK2, in response to a signal at the second node N12.

[0158] Capacitor C11 is connected between the second node N12 and the first output terminal OUT11. Capacitor C12 is connected between the second voltage terminal V12 and the first node N11.

[0159] The masking circuit MSC2 includes a first masking transistor MT21 and a second masking transistor MT22. Each of the masking transistors MT21 and MT22 is shown and described as a P-type transistor, but the inventive concept is not limited thereto. For example, in an embodiment, some or all of the masking transistors MT21 and MT22 may be N-type transistors.

[0160] The masking circuit MSC2 can mask the second carry signal CRj output from the second output terminal OUT12 in response to the third scan clock signal SCLK3 received through the fourth input terminal IN14, the signal of the first node N11, and the scan signal SCj output through the first output terminal OUT11. That is, the masking circuit MSC2 can selectively output the second carry signal CRj to the second output terminal OUT12. The signal of the first node N11 can be a switching signal. That is, the driving circuit DC can output a switching signal to the first node N11. In an embodiment, in response to the clock signal input to the driving circuit DC and the first carry signal CRj-1, the driving circuit DC can output the scan signal SCj to the first output terminal OUT11 and output a switching signal to the first node N11.

[0161] The first masking transistor MT21 is connected between the second voltage terminal V12 and the second output terminal OUT12, and includes a gate electrode connected to the first node N11. In response to a signal (switching signal) from the first node N11, the first masking transistor MT21 electrically connects the second output terminal OUT12 to the second voltage terminal V12.

[0162] The second masking transistor MT22 is connected between the second output terminal OUT12 and the fourth input terminal IN14, and includes a gate electrode connected to the first output terminal OUT11. The second masking transistor MT22 can transmit a third scan clock signal SCLK3 (masking clock signal) to the second output terminal OUT12 in response to the scan signal SCj output through the first output terminal OUT11. In an embodiment, when the first masking transistor MT21 is off and the second masking transistor MT22 is on, the masking circuit MSC2 can output the third scan clock signal SCLK3 (masking clock signal) as the second carry signal CRj.

[0163] Figure 13 This is an example illustrating the situation during normal mode N-MODE. Figure 12 The timing diagram of the operation of the j-th driver level STj is shown.

[0164] refer to Figure 12 and Figure 13 The first scan clock signal SCLK1 and the second scan clock signal SCLK2 are signals with the same frequency that transition to an active level (e.g., low level) in different horizontal portions (e.g., the (j-1)th horizontal portion Hj-1, the jth horizontal portion Hj, and the (j+1)th horizontal portion Hj+1). The horizontal portion is during which pixels PX in a row along the first direction DR1 of the display panel DP are driven (see...). Figure 2 (Time period)

[0165] When the first carry signal CRj-1 transitions from high to low in the (j-1)th level portion Hj-1 and the first scan clock signal SCLK1 is low, transistor M11 is turned on. When transistor M11 is turned on, the second node N12 transitions to low, which is the voltage level of the first carry signal CRj-1. When the signal of the second node N12 transitions to low, transistors M14 and M17 are turned on. When transistor M14 is turned on, the first node N11 transitions to low, thereby turning on transistor M16. Additionally, when transistor M17 is turned on, the second scan clock signal SCLK2 is high, allowing the high-level scan signal SCj to be output through the first output terminal OUT11. When the signal of the first node N11 is low, the first masking transistor MT21 in the masking circuit MSC2 is turned on, allowing the second carry signal CRj to be output at a high level.

[0166] When the second scan clock signal SCLK2 is at a low level in the j-th level Hj, the second node N12 is changed to a lower low level through capacitor C11, and transistor M17 is turned on, so that a low-level scan signal SCj can be output.

[0167] Since the third scan clock signal SCLK3 remains at a high level in normal mode, when the low-level scan signal SCj is output, the second masking transistor MT22 in the masking circuit MSC2 is turned on, so the low-level second carry signal CRj can be output through the second output terminal OUT12.

[0168] Figure 14 This is an example illustrating the situation during low power mode (L-MODE). Figure 12 The timing diagram of the operation of the j-th driver level STj is shown.

[0169] refer to Figure 12 and Figure 14 In low-power mode (L-MODE), the second display area DA2 needs to be driven at a low frequency (see...). Figure 1 At the beginning of the scan, the third scan clock signal SCLK3 changes from high level to low level.

[0170] When the first carry signal CRj-1 transitions from high to low in the (j-1)th level portion Hj-1 and the first scan clock signal SCLK1 is low, transistor M11 is turned on. When transistor M11 is turned on, the second node N12 transitions to low, which is the voltage level of the first carry signal CRj-1. When the signal of the second node N12 transitions to low, transistors M14 and M17 are turned on. When transistor M14 is turned on, the first node N11 transitions to low, thereby turning on transistor M16. Additionally, when transistor M17 is turned on, the second scan clock signal SCLK2 is high, allowing the high-level scan signal SCj to be output through the first output terminal OUT11. When the signal of the first node N11 is low, the first masking transistor M21 in the masking circuit MSC2 is turned on, allowing the second carry signal CRj to be output at a high level.

[0171] When the second scan clock signal SCLK2 is at a low level in the j-th level Hj, the second node N12 is changed to a lower low level through capacitor C11, and transistor M17 is turned on, so that a low-level scan signal SCj can be output.

[0172] When the third scan clock signal SCLK3 changes from low to high in low-power mode (L-MODE), the second masking transistor MT22 in the masking circuit MSC2 turns on when the low-level scan signal SCj is output. This allows the high-level second carry signal CRj to be output through the second output terminal OUT12. Therefore, the second carry signal CRj is not activated by the low level.

[0173] In the (j+1)th driver stage STj+1, where the second carry signal CRj is received as the first carry signal, because the second node N12 remains high when the first scan clock signal SCLK1 transitions to a low level in the (j+1)th horizontal portion Hj+1, transistors M14 and M17 are not turned on in this embodiment. As a result, the third scan signal SCj+1 and the second carry signal CRj output from the (j+1)th driver stage STj+1 remain high.

[0174] As described above, when the third scan clock signal SCLK3 transitions to a high level in the j-th level portion Hj under low power mode L-MODE, the second carry signal CRj output from the j-th driver stage STj remains at a high level, and the third scan signal SCj+1 output from the (j+1)-th driver stage STj+1 remains at a high level.

[0175] In this embodiment, after the third scan clock signal SCLK3 goes high, the scan signal is not activated by going high after the first horizontal period 1H.

[0176] For example, when Figure 1 As shown, when the starting position of the second display area DA2 corresponds to the scan signal SC1921, if the third scan clock signal SCLK3 goes high in the 1920th horizontal period H1920, the scan signal SC1921 can remain high without being activated by a low level. As described above, although the third scan clock signal SCLK3 remains high, scan signals SC1921 to SC3840 can remain high without being activated by a low level.

[0177] refer to Figure 13 and Figure 14 In this embodiment, the third scan clock signal SCLK3 (masking clock signal) remains at a first level during normal mode (N-MODE) and periodically changes between a first level and a second level during low-power mode (L-MODE). As described herein, this driving scheme allows embodiments to reduce power consumption without degrading the display quality of the display device DD.

[0178] refer to Figures 5 to 10 The described light-emitting driver circuit EDC and Figures 11 to 14 The scan drive circuit SD shown herein, during low power mode L-MODE, Figure 1 The first display area DA1 shown can be driven at a normal frequency (e.g., 120Hz) and Figure 1The second display area DA2 shown can be driven at a low frequency (e.g., 1Hz). Since the first display area DA1, which displays moving images, is driven at a normal frequency, while the second display area DA2, which displays still images, is driven at a frequency lower than the normal frequency, the power consumption of the display device DD can be reduced without compromising the display quality of the first display area DA1 and the second display area DA2.

[0179] According to the embodiment, a display device having this configuration can drive a first display area displaying moving images and a second display area displaying still images at different driving frequencies. For example, the light-emitting driving circuit of the display device can use a lower driving frequency than that used to drive the first display area displaying moving images to drive the second display area displaying still images. Therefore, power consumption can be reduced without compromising display quality.

[0180] While the concept of the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A light-emitting driving circuit, wherein, The light-emitting driving circuit includes: The driving circuit is configured to output a light-emitting driving signal to a first output terminal and a switching signal to a first node in response to multiple clock signals and a first carry signal; and The masking circuit is configured to output a second carry signal to the second output terminal in response to the masking clock signal, the light-emitting drive signal, and the switching signal. The masking clock signal is a signal that remains at a first level during normal mode and changes periodically during low-power mode. The masking circuit includes: A first masking transistor is configured to transmit the masking clock signal to the second output terminal in response to the switching signal; and The second masking transistor is configured to electrically connect the second output terminal to a first voltage terminal configured to receive a first voltage in response to the light-emitting driving signal.

2. The light-emitting driving circuit according to claim 1, wherein, When the second masking transistor is turned off and the first masking transistor is turned on, the masking circuit outputs the masking clock signal as the second carry signal.

3. The light-emitting driving circuit according to claim 1, wherein, The driving circuit includes: The first transistor is configured to transmit the first carry signal to the second node in response to a first clock signal among the plurality of clock signals; The second transistor is configured to electrically connect the first output terminal to the first voltage terminal in response to a signal from the second node; A third transistor is configured to electrically connect the first node to a second voltage terminal configured to receive a second voltage in response to a signal from the second node; and A fourth transistor is configured to electrically connect the first output terminal to the second voltage terminal in response to the switching signal.

4. The light-emitting driving circuit according to claim 3, wherein, The driving circuit also includes: A capacitor is connected between the second node and the input terminal of the second clock signal, which receives one of the plurality of clock signals.

5. A scanning drive circuit, wherein, The scanning drive circuit includes: The driving circuit is configured to output a scan signal to a first output terminal and a switch signal to a first node in response to a plurality of scan clock signals and a first carry signal; and The masking circuit is configured to output a second carry signal to a second output terminal in response to a masking clock signal, the scan signal, and the switch signal. The masking clock signal is a signal that remains at a first level during normal mode and changes periodically during low-power mode. The driving circuit is electrically connected to a first voltage terminal configured to receive a first voltage and a second voltage terminal configured to receive a second voltage. The masking circuit includes: A first masking transistor is configured to electrically connect the second voltage terminal to the second output terminal in response to the switching signal; and The second masking transistor is configured to transmit the masking clock signal to the second output terminal in response to the scan signal.

6. The scanning drive circuit according to claim 5, wherein, When the first masking transistor is turned off and the second masking transistor is turned on, the masking circuit outputs the masking clock signal as the second carry signal.

7. The scanning drive circuit according to claim 5, wherein, The driving circuit includes: The first transistor is configured to transmit the first carry signal to the second node in response to a first scan clock signal among the plurality of scan clock signals received through the first input terminal; The second transistor is configured to electrically connect the first output terminal to the second input terminal in response to a signal from the second node, and the second input terminal is configured to receive a second scan clock signal among the plurality of scan clock signals; The third transistor is configured to electrically connect the first node to the first input terminal in response to a signal from the second node; A fourth transistor is configured to electrically connect the first node to a first voltage terminal configured to receive a first voltage in response to the first scan clock signal; and The fifth transistor is configured to electrically connect a second voltage terminal, configured to receive a second voltage, to the first output terminal in response to the switching signal of the first node.

8. The scanning drive circuit according to claim 7, wherein, The driving circuit also includes: A capacitor connected between the second node and the first output terminal.

9. A display device, wherein, The display device includes: The display panel includes multiple pixels that are respectively connected to one of multiple data lines, one of multiple scan lines, and one of multiple light-emitting lines; A data driving circuit is configured to drive the multiple data lines; A scan driving circuit is configured to drive the multiple scan lines; A light-emitting driving circuit is configured to drive the plurality of light-emitting lines; and The drive controller is configured to receive image signals and control signals and control the data drive circuit, the scanning drive circuit, and the light-emitting drive circuit to display an image on the display panel, wherein: The drive controller divides the display panel into a first display area and a second display area based on the image signal, and outputs a first masking signal indicating the start position of the second display area; and The light-emitting driving circuit includes multiple light-emitting driving stages, each configured to drive a corresponding light-emitting line among the multiple light-emitting lines, wherein each of the multiple light-emitting driving stages includes: A first driving circuit is configured to output a light-emitting driving signal to a first output terminal and output a first switching signal to a first node in response to a plurality of clock signals and a first carry signal from the driving controller; and A first masking circuit is configured to output a second carry signal to a second output terminal in response to a first masking clock signal, the light-emitting drive signal, and the first switching signal, wherein the first masking clock signal is maintained at a first level during normal mode and changes periodically during low-power mode.

10. The display device according to claim 9, wherein, The first masking circuit includes: A first masking transistor is configured to transmit a first masking clock signal to a second output terminal in response to a first switching signal; and The second masking transistor is configured to electrically connect the second output terminal to a first voltage terminal configured to receive a first voltage in response to the light-emitting driving signal.

11. The display device according to claim 10, wherein, When the second masking transistor is turned off and the first masking transistor is turned on, the first masking circuit outputs the first masking clock signal as the second carry signal.

12. The display device according to claim 9, wherein, The second carry signal output from the j-th light-emitting driver stage among the plurality of light-emitting driver stages is provided as the first carry signal of the (j+k)-th light-emitting driver stage, where each of j and k is a positive integer.

13. The display device according to claim 9, wherein, The first driving circuit includes: The first transistor is configured to transmit the first carry signal to the second node in response to a first clock signal among the plurality of clock signals; The second transistor is configured to electrically connect the first output terminal to a first voltage terminal configured to receive a first voltage in response to a signal from the second node; A third transistor is configured to electrically connect the first node to a second voltage terminal configured to receive a second voltage in response to a signal from the second node; and The fourth transistor is configured to electrically connect the first output terminal to the second voltage terminal in response to the first switching signal.

14. The display device according to claim 13, wherein, The first driving circuit further includes: A capacitor is connected between the second node and the input terminal, the input terminal being configured to receive a second clock signal among the plurality of clock signals.

15. The display device according to claim 9, wherein, The scan driving circuit includes multiple driving stages, each driving stage being configured to drive a corresponding scan line among the multiple scan lines, wherein each of the multiple driving stages includes: The second driving circuit is configured to output a scan signal to a third output terminal and output a second switch signal to a second node in response to a plurality of scan clock signals and a third carry signal from the driving controller; and The second masking circuit is configured to output a fourth carry signal to a fourth output terminal in response to a second masking clock signal, the scan signal, and the second switch signal, wherein the second masking clock signal is a signal that remains at the first level during the normal mode and changes periodically during the low power mode.

16. The display device according to claim 15, wherein, The second driving circuit is electrically connected to a third voltage terminal configured to receive a third voltage and a fourth voltage terminal configured to receive a fourth voltage, and the second masking circuit includes: A third masking transistor is configured to electrically connect the fourth voltage terminal to the fourth output terminal in response to the second switching signal; and The fourth masking transistor is configured to transmit the second masking clock signal to the fourth output terminal in response to the scan signal.

17. The display device according to claim 16, wherein, The second masking circuit is configured to output the second masking clock signal as the fourth carry signal when the third masking transistor is turned off and the fourth masking transistor is turned on.

18. The display device according to claim 15, wherein, The fourth carry signal output from the j-th drive stage among the plurality of drive stages is provided as the third carry signal of the (j+k)-th drive stage, where each of j and k is a positive integer.

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