Integrated circuit structure and method of manufacturing the same

Abstract

The present disclosure provides an integrated circuit structure and a method of fabricating the same. The dielectric isolation structure can reduce capacitive coupling and crosstalk between conductive features. The method includes forming a first conductive structure on a substrate; forming a first dielectric structure on the first conductive structure; converting sidewall portions of the first conductive structure into a first dielectric portion; removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure; forming an interlayer dielectric (ILD) layer such that sidewalls of the first dielectric structure are covered by the ILD layer; forming a strengthening column in the ILD layer, the strengthening column being removable by energy; forming a capping dielectric layer on the strengthening column; and performing a thermal treatment process to convert the strengthening column into a dielectric isolation structure having a spacer layer surrounding an air gap.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 16 / 930,913, filed July 16, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to an integrated circuit structure and its fabrication method. In particular, it relates to an integrated circuit structure with a dielectric isolation structure and its fabrication method. This integrated circuit structure can reduce capacitive coupling and crosstalk between conductive features. Background Technology

[0003] Integrated circuit (IC) architecture is crucial for many modern applications. With advancements in electronic technology, the size of semi-integrated circuit architectures has become increasingly smaller, while simultaneously providing better functionality and containing a larger number of ICs. Due to the miniaturization of IC architectures, different types and sizes of IC architectures implementing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of IC architectures.

[0004] However, the manufacturing and integration of integrated circuit structures involve many complex steps and operations. Therefore, the integration within integrated circuit structures becomes even more complex. This increased complexity and integration can lead to defects, causing signal interference between conductive components. Therefore, improvements to the manufacturing process of integrated circuit structures are needed to address these defect problems.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a method for fabricating an integrated circuit structure. The method includes: forming a first conductive structure on a substrate; forming a first dielectric structure above the first conductive structure; converting a sidewall portion of the first conductive structure into a first dielectric portion; removing the first dielectric portion to form the remaining portion of the first conductive structure, such that the width of the first dielectric structure is greater than the width of the remaining portion of the first conductive structure; forming an inter-dielectric (ILD) layer covering the sidewalls of the first dielectric structure; forming a reinforcement pillar in the ILD layer, the reinforcement pillar being made of an energy-removable material; forming a capping dielectric layer on the reinforcement pillar; and performing a heat treatment to transform the reinforcement pillar into a dielectric isolation structure having a liner layer surrounding an air gap.

[0007] In one embodiment, the step of converting the sidewall portion of the first conductive structure further includes: performing a heat treatment process on the first conductive structure to form a first dielectric portion on the opposite sidewall of the remaining portion of the first conductive structure, wherein the material of the first dielectric portion is different from the material of the first dielectric structure.

[0008] In one embodiment, the heat treatment process is an oxidation process or a nitriding process, and the first dielectric portion is covered by the first dielectric structure.

[0009] In one embodiment, the preparation method further includes: forming an inter-dielectric layer that covers the sidewall of the first dielectric structure, and forming a first air gap between the inter-dielectric layer and the remainder of the first conductive structure.

[0010] In one embodiment, a bottom surface of the first air gap is higher than a bottom surface of the rest of the first conductive structure.

[0011] In one embodiment, the interlayer dielectric layer extends on and directly contacts a lower sidewall of the remainder of the first conductive structure.

[0012] In one embodiment, the fabrication method further includes: forming a second conductive structure on the substrate; forming a second dielectric structure on the second conductive structure; forming a second dielectric portion on the sidewall portion of the second conductive structure during the formation of the first dielectric portion of the first conductive structure; and removing the second dielectric portion such that the distance between the remaining portion of the first conductive structure and the remaining portion of the second conductive structure is greater than the distance between the first dielectric structure and the second dielectric structure.

[0013] In one embodiment, the preparation method further includes: forming an inter-dielectric layer that covers the sidewall of the first dielectric structure, and forming a first air gap between the inter-dielectric layer and the remainder of the first conductive structure.

[0014] In one embodiment, a bottom surface of the first air gap is higher than a bottom surface of the rest of the first conductive structure.

[0015] In one embodiment, the interlayer dielectric layer covers the sidewalls of the second dielectric structure, and a second air gap is formed between the interlayer dielectric layer and the remainder of the second conductive structure.

[0016] One embodiment of this disclosure provides a method for fabricating an integrated circuit structure. The method includes: forming a conductive layer on a substrate; forming a dielectric layer on the conductive layer; patterning the dielectric layer and the conductive layer to form a first dielectric structure, a second dielectric structure, a first conductive structure, and a second conductive structure, wherein a first opening is formed between the first dielectric structure and the second dielectric structure, and a second opening is formed between the first dielectric structure and the second dielectric structure; partially removing the first conductive structure and the second conductive structure to form an enlarged second opening; forming an interlayer dielectric layer covering the sidewalls of the first dielectric structure and the sidewalls of the second dielectric structure; forming a reinforcement pillar in the interlayer dielectric layer, the reinforcement pillar being made of an energy-removable material; forming a capping dielectric layer on the reinforcement pillar; and performing a heat treatment process to convert the reinforcement pillar into a dielectric isolation structure, the dielectric isolation structure having a padding layer surrounding an air gap.

[0017] In some embodiments, the width of the enlarged second opening is greater than the width of the first opening.

[0018] In some embodiments, the preparation method further includes: after forming the enlarged second opening, depositing an interlayer dielectric layer in the first opening, such that the upper sidewall of the first conductive structure is separated from the interlayer dielectric layer through a first air gap.

[0019] In some embodiments, the upper sidewall of the second conductive structure is separated from the interlayer dielectric layer by a second air gap, wherein the interface between the first air gap and the interlayer dielectric layer is completely covered by the first dielectric structure, and the interface between the second air gap and the interlayer dielectric layer is completely covered by the second dielectric structure.

[0020] In some embodiments, the interlayer dielectric layer is deposited in the first opening and the enlarged second opening, and the first air gap is surrounded by the upper sidewall of the first conductive structure, the first dielectric structure, and the interlayer dielectric layer.

[0021] In one embodiment, the bottom surface of the interlayer dielectric layer is higher than the bottom surface of the first conductive structure.

[0022] One embodiment of this disclosure provides an integrated circuit structure. The integrated circuit structure includes: a plurality of conductive structures disposed above a substrate; a plurality of dielectric structures disposed on the plurality of conductive structures; an interlayer dielectric (ILD) layer disposed on the sidewalls of the plurality of dielectric structures and the sidewalls of the plurality of conductive structures, wherein an air gap is formed between the ILD layer, the dielectric structures, and the conductive structures; and a dielectric isolation structure having a padding layer that surrounds the air gap.

[0023] In one embodiment, the width of the air gap gradually decreases along the dielectric structure toward the substrate.

[0024] In one embodiment, the lower sidewall of the conductive structure is in direct contact with the interlayer dielectric layer.

[0025] In one embodiment, the conductive structure and the air gap are completely covered by the dielectric structure, and a portion of the bottom surface of the dielectric structure is in direct contact with the interlayer dielectric layer.

[0026] This disclosure provides a method for fabricating an integrated circuit structure, including converting a sidewall portion of a conductive structure into a dielectric portion and removing the dielectric portion. When removing the dielectric portion, the width of the dielectric portion on the conductive structure is greater than the width of the remaining portion of the conductive structure, while the height of the conductive structure remains the same. In other words, the aspect ratio of the conductive structure becomes higher; that is, this disclosure allows for the fabrication of a high aspect ratio conductive structure as a conductive via.

[0027] Forming air gaps on the sidewalls of conductive features and dielectric isolation structures between conductive features helps prevent crosstalk (i.e., signal interference) between adjacent conductive structures, and may improve the performance of the integrated circuit structure. Furthermore, since the ILD layer is formed on the opposite sidewalls of the conductive structure after the conductive structure is formed, pinch-off problems near the top of the conductive structure and the generation of voids or seams in the conductive structure can be prevented. Additionally, this fabrication method includes converting the reinforcing pillars into dielectric isolation structures comprising a liner with closed air gaps, which can reduce capacitive coupling and crosstalk between conductive features.

[0028] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0029] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0030] Figure 1 A schematic flowchart illustrating a method for fabricating an integrated circuit structure according to some embodiments of this disclosure is shown.

[0031] Figures 2 to 10 Examples of some embodiments of this disclosure Figure 1 The cross-sectional schematic diagram of each stage of the fabrication process to form an integrated circuit structure.

[0032] Figure 11 A schematic cross-sectional view illustrating an integrated circuit structure according to some embodiments of this disclosure is shown.

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 10: Preparation method

[0035] 71: Reinforcing Column

[0036] 72: Dielectric isolation structure

[0037] 72A: Air gap

[0038] 72B: Padding layer

[0039] 73: Cover dielectric layer

[0040] 100a: Integrated Circuit Structure

[0041] 100b: Integrated Circuit Structure

[0042] 101: Base

[0043] 103: Dielectric layer

[0044] 105: Conductive plug

[0045] 107: Conductive layer

[0046] 107a: Conductive structure

[0047] 107a': The rest of the conductive structure

[0048] 107a”: The rest of the conductive structure

[0049] 107b: Conductive structure

[0050] 107b': The remainder of the conductive structure

[0051] 107b”: The rest of the conductive structure

[0052] 109: Dielectric layer

[0053] 109a: Dielectric structure

[0054] 109b: Dielectric structure

[0055] 110: Opening

[0056] 111a: Masking pattern

[0057] 111b: Masking pattern

[0058] 113a: Dielectric section

[0059] 113a': Dielectric section

[0060] 113b: Dielectric section

[0061] 113b': Dielectric section

[0062] 115: Interlayer Dielectric (ILD) Layer

[0063] 150: Air gap

[0064] 160: Air gap

[0065] 210: Opening

[0066] 213a: Dielectric section

[0067] 213b: Dielectric section

[0068] 310: Opening

[0069] 310': Enlarged opening

[0070] 1000: First Area

[0071] 1107a: The remainder of the conductive structure

[0072] 1107b: The remainder of the conductive structure

[0073] 1310: Opening

[0074] 2000: Second Region

[0075] D1: Distance

[0076] D2: Distance

[0077] S11: Steps

[0078] S13: Steps

[0079] S15: Steps

[0080] S17: Steps

[0081] S19: Steps

[0082] S21: Steps

[0083] S23: Steps

[0084] S25: Steps

[0085] W1: Width

[0086] W2: Width

[0087] W4: Width Detailed Implementation

[0088] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0089] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0090] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0091] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at different scales. In the drawings, some layers / features may be omitted for simplicity.

[0092] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0093] Figure 1 A schematic flowchart illustrating a method 10 for fabricating an integrated circuit structure according to some embodiments of this disclosure is shown. Figure 1 As shown, preparation method 10 includes steps S11, S13, S15, S17, S19, S21, S23, and S25.

[0094] Figure 1 Steps S11 to S25 will be briefly explained first, which are combined with Figures 2 to 8 A more detailed description would follow. For example... Figure 1As shown, the integrated circuit structure fabrication method 10 first performs step S11, performing, for example, a deposition process to form a conductive layer on a substrate and a dielectric layer above the conductive layer. In some embodiments, the substrate may include active microelectronic components and passive microelectronic components, and the microelectronic components can be electrically connected to other electronic components above the conductive layer through the conductive layer. Next, step S13 is performed, performing a patterning process on the dielectric layer and the conductive layer, forming multiple dielectric structures and multiple conductive structures. In some embodiments, the patterning process is performed on the dielectric layer and the conductive layer using a mask on the dielectric layer. Then, after the patterning process, a dielectric structure and a conductive structure are formed, and the sidewalls of the dielectric structure and the sidewalls of the conductive structure are coplanar.

[0095] Then, in step S15, a portion of the sidewall of the conductive structure is converted into a dielectric portion. In some embodiments, the dielectric portion is formed by performing a heat treatment process.

[0096] Next, step S17 is performed to remove the dielectric portion of the conductive structure, such that the width of the dielectric structure is greater than the width of the remaining portion of the conductive structure. In some embodiments, step S19 is performed to form an interlayer dielectric (ILD) that covers the sidewalls of the dielectric structure. In some embodiments, an air gap is formed between the interlayer dielectric and the remaining portion of the conductive structure.

[0097] Then, in step S21, a reinforcing pillar is formed in the interlayer dielectric layer, the material of which can be removed by an energy process. Then, in step S23, a capping dielectric layer is formed above the reinforcing pillar. Then, in step 25, the reinforcing pillar is transformed into a dielectric isolation structure, which includes a liner layer that seals the air gap.

[0098] Figures 2 to 8 Examples of some embodiments of this disclosure Figure 1 The method for fabricating an integrated circuit structure 100a is shown in the cross-sectional schematic diagram of each stage of the fabrication process.

[0099] like Figure 2As shown, a substrate 101 is provided. In some embodiments, substrate 101 may include a semiconductor substrate, such as a silicon substrate. In some embodiments, substrate 101 includes an elemental semiconductor material, such as germanium (Ge). In some embodiments, substrate 101 includes a compound semiconductor material, such as gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. In some embodiments, substrate 101 includes an alloy semiconductor material, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. Additionally, substrate 101 may be a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be implanted using SIMOX, wafer bonding, and / or other suitable methods.

[0100] Additionally, substrate 101 can be part of an integrated circuit (IC) chip, which is a variety of passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), side-diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (finFETs), other suitable IC components, or combinations thereof.

[0101] Depending on the IC manufacturing stage, substrate 101 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, insulating features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For example, such as Figure 2 As shown, a dielectric layer 103 is formed on a substrate 101. In some embodiments, the dielectric layer 103 is made of the following materials: silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), other suitable dielectric materials, and / or combinations thereof.

[0102] For clarity, base 261 has been simplified. It should be understood that multiple additional features may be added to base 101, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0103] In the depicted embodiment, a plurality of conductive plugs 105 are formed in the substrate 101 and the dielectric layer 103. The conductive plugs 105 penetrate the dielectric layer 103 and the substrate 101. However, in other embodiments, the substrate 101 is not penetrated by the conductive plugs 105. In some embodiments, the conductive plugs 105 are used to form electrical connections between elements in the substrate 101 and other elements on the dielectric layer 103.

[0104] In some embodiments, the conductive plug 105 is made of copper (Cu), aluminum (Al), silver (Ag), tungsten (W), other conductive materials, and / or combinations thereof. The conductive plug 105 can be formed by etching and deposition. Additionally, according to some embodiments, the conductive plug 105 may be a through-silicon via (TSV) or a through-substrate via (TSV).

[0105] Furthermore, the substrate 101 includes a first region 1000 and a second region 2000. In some embodiments, the pattern density of the first region 1000 of the substrate 100 is greater than the pattern density of the second region 2000. Therefore, in these embodiments, the first region 1000 may be referred to as a pattern-dense region, such as a cell region in DRAM, and the second region 2000 may be referred to as a pattern-sparse region, such as a peripheral circuit region in DRAM.

[0106] Please refer to the following: Figure 2 A conductive layer 107 is formed on the dielectric layer 103, and a dielectric layer 109 is formed on the conductive layer 107. The corresponding steps are illustrated in the diagram below. Figure 1 Step S11 of the preparation method 10 shown. In some embodiments, the conductive layer 107 is made of doped polycrystalline silicon (polysilicon), tungsten (W), aluminum (Al), copper (Cu), other conductive materials, and / or combinations thereof. In some embodiments, the dielectric layer 109 is made of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), other suitable dielectric materials, and / or combinations thereof. Furthermore, the conductive layer 107 and the dielectric layer 109 can be formed by a CVD process, a PVD process, an ALD process, a spin coating process, a sputtering process, or other applicable processes.

[0107] Because crosstalk (i.e., signal interference) between adjacent conductive features is more severe in the first region 1000 (i.e., the densely patterned region) than in the second region 2000 (i.e., the sparsely patterned region), the following processes are performed in the first region 1000. Of course, these are merely examples and are not intended to be limiting. For instance, in some other embodiments, the following processes are performed in the second region 2000.

[0108] refer to Figure 2 and Figure 3 A patterning process is performed on the dielectric layer 109 and the conductive layer 107. The corresponding step is to draw the pattern as shown in the diagram. Figure 1 Step S13 in the preparation method 10 shown. In some embodiments, such as Figure 2 As shown, the patterning process involves forming a mask pattern on the dielectric layer 109. The mask pattern includes a mask pattern 111a and a mask pattern 111b, with an opening 110 formed between the mask patterns 111a and 111b. The mask patterns 111a and 111b can be formed by depositing a mask layer (not shown) over the dielectric layer 109. Then, a patterned photoresist layer (not shown) can be formed on the mask layer.

[0109] The patterned photoresist layer can be formed by a deposition process and a patterning process. The deposition process for forming the pattern can include a CVD process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process, or other suitable processes. The patterning process for forming the patterned photoresist layer can include a lithography process and an etching process. The lithography process can include a photoresist coating (e.g., spin coating), a soft baking process, a mask alignment process, an exposure process, a post-exposure baking process, a development process, and a rinsing and drying process (e.g., hard baking). The etching process can include a dry etching process (e.g., reactive ion etching, RIE), a wet etching process, and / or other etching methods.

[0110] In some embodiments, the mask layer is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The mask layer can be formed by a deposition process, which may include a CVD process, an HDPCVD process, a spin coating process, a sputtering process, or other suitable processes. After the patterned photoresist layer is formed, it is used as a mask to etch the mask layer. This forms mask patterns 111a, 111b and an opening 110 between the mask patterns 111a, 111b. The patterned photoresist layer can then be removed.

[0111] Then, as Figure 3As shown, the dielectric layer 109 and the conductive layer 107 are etched using mask patterns 111a and 111b as an etching mask. Therefore, an opening 210 is formed between dielectric structures 109a and 109b, and an opening 310 is formed between conductive structures 107a and 107b. In some embodiments, a top surface of the dielectric layer 103 is exposed through the opening 310. In some embodiments, steps S11 and S13 are also performed in the second region 2000, where the conductive structure 107a is formed on the conductive plug 105 in the second region 2000.

[0112] It should be understood that the etching processes for the dielectric layer 109 and the conductive layer 107 are performed using the same mask. Therefore, according to some embodiments, the sidewalls of the conductive structure 107a and the dielectric structure 109a are substantially coplanar, and the sidewalls of the conductive structure 107b and the dielectric structure 109b are substantially coplanar. In this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0113] In some embodiments, the top surfaces of conductive structures 107a and 107b are completely covered by dielectric structures 109a and 109b. In some embodiments, such as Figure 3 As shown in the cross-sectional view, the width of dielectric structure 109a is substantially the same as the width of conductive structure 107a, and is defined as width W1. The width of dielectric structure 109b is substantially the same as the width of conductive structure 107b. After forming openings 210 and 310, the mask including mask patterns 111a and 111b is removed.

[0114] refer to Figure 4 The sidewall portions of conductive structure 107a and conductive structure 107b are converted into dielectric portions 113a and 113b. The corresponding steps are illustrated in the diagram below. Figure 1 Step S15 of the preparation method 10 shown. As a result, a dielectric portion 113a is formed on the opposite sidewall of the remaining portion 107a' of the conductive structure, and a dielectric portion 113b is formed on the opposite sidewall of the remaining portion 107b' of the conductive structure.

[0115] In some embodiments, dielectric portion 113a is covered by dielectric structure 109a, and dielectric portion 113b is covered by dielectric structure 109b. In some embodiments, dielectric portion 113a protrudes from the sidewall of dielectric structure 109a, and dielectric portion 113b protrudes from the sidewall of dielectric structure 109b. However, dielectric portions 113a and 113b are at least partially covered by dielectric structures 109a and 109b, respectively.

[0116] Furthermore, in some embodiments, the dielectric portions 113a and 113b are formed by performing a heat treatment process, which includes an oxidation process, a nitriding process, other suitable processes, and / or combinations thereof. Additionally, for high etch selectivity during the etching process, the dielectric portions 113a and 113b are made of different materials from the dielectric structures 109a and 109b. Therefore, the gas applied during the heat treatment process will be selected based on the material properties of the dielectric structures 109a and 109b.

[0117] For example, when the dielectric structures 109a and 109b are made of silicon oxide, nitrogen can diffuse into the sidewall surfaces of the conductive structures 107a and 107b during the heat treatment process (i.e., nitriding process), and the dielectric portions 113a and 113b will be made of, for example, silicon nitride nitride.

[0118] Furthermore, when the dielectric structures 109a and 109b are made of silicon nitride, oxygen can diffuse into the sidewall surfaces of the conductive structures 107a and 107b during the heat treatment process (i.e., oxidation process), and the dielectric portions 113a and 113b can be made of silicon oxide (SiO2), tungsten oxide (WO), aluminum oxide (Al2O3), copper oxide (CuO), or combinations thereof, depending on the material of the conductive structures 107a and 107b.

[0119] refer to Figure 5 Remove dielectric portions 113a and 113b. The corresponding steps are illustrated in the diagram below. Figure 1 Step S17 of the preparation method 10 shown. In some embodiments, the dielectric portions 113a, 113b are removed by an etching process. The etching process may include a dry etching process (e.g., reactive ion etching, RIE), a wet etching process, and / or other etching methods.

[0120] In some embodiments, the materials of the dielectric portions 113a and 113b and the dielectric structures 109a and 109b are selected to give the dielectric portions 113a and 113b high etch selectivity, meaning that the etch rate of the dielectric portions 113a and 113b is greater than the etch rate of the dielectric structures 109a and 109b. Therefore, while the dielectric portions 113a and 113b are removed by the etching process, the dielectric structures 109a and 109b remain substantially intact.

[0121] After removing the dielectric portions 113a and 113b, an enlarged opening 310' is formed. It should be understood that the distance D2 between the remaining portions of the conductive structures 107a' and 107b' (i.e., the width of the enlarged opening 310') is greater than the distance D1 between the dielectric structures 109a and 109b (i.e., the width of the opening 310), and a width W1 of the dielectric structure 109a is greater than a width W2 of the remaining portions of the conductive structure 107a'. Similarly, the width of the dielectric structure 109b is greater than the width of the remaining portions of the conductive structure 107b'.

[0122] refer to Figure 6 According to some embodiments, after removing the dielectric portions 113a and 113b, a second heat treatment process can be performed on the sidewalls of the remaining portions of the conductive structures 107a' and 107b'. This second heat treatment process is optional. For example, in some embodiments, if the desired width of the remaining portions of the conductive structures 107a' and 107b' is achieved after removing the dielectric portions 113a and 113b, the second heat treatment process can be omitted.

[0123] Still referencing Figure 6 After performing the second heat treatment process, portions of the sidewalls of the remaining portions 107a' and 107b' of the conductive structure are transformed to form dielectric portions 213a and 213b. Therefore, dielectric portions 213a and 213b are formed on the sidewalls of the remaining portions 107a' and 107b' of the conductive structure, respectively. In some embodiments, the width W3 of the remaining portion 107a' of the conductive structure is smaller than the width W2 of the remaining portion 107a' of the conductive structure before performing the second heat treatment process (e.g., ...). Figure 5 As shown), and the width W2 is smaller than the width W1 of the dielectric structure 109a.

[0124] Following this second heat treatment process, according to some embodiments, the dielectric portions 213a and 213b are removed by an etching process. Then, another heat treatment process may be selectively performed until the desired width of the remaining portions 107a” and 107b” of the conductive structure is achieved.

[0125] refer to Figure 7 Once the desired width is reached, the remaining portions 1107a and 1107b of a conductive structure are obtained. In some embodiments, the remaining portions 1107a and 1107b of the conductive structure are a through-silicon via (TSV) or a through-substrate via (TSV). In some embodiments, the width W4 of the remaining portion 1107a of the conductive structure is smaller than the width W1 of the dielectric structure 109a. Similarly, the width of the remaining portion 1107b of the conductive structure is smaller than the width W1 of the dielectric structure 109b.

[0126] Furthermore, in some embodiments, the remaining portions 1107a, 1107b of the conductive structure are separated by an opening 1310, which is larger than... Figure 6 The enlarged opening 310' is wide. It should be understood that the remaining portions 1107a and 1107b of the conductive structure are completely covered by the dielectric structures 109a and 109b, respectively, and the conductive plug 105 is covered by the remaining portions 1107a and 1107b of the conductive structure.

[0127] In some embodiments, steps S15 and S17 are performed in the first region 1000, and the second region 2000 is covered by a hard mask; therefore, the conductive structure 107a on the conductive plug 105 in the second region 2000 remains consistent with... Figure 3 The same as shown. In other words, the aspect ratio of the conductive structures 1107a and 1107b used as conductive paths in the first region 1000 is higher than that in the second region 2000.

[0128] Reference Figure 8 An inter-layer dielectric (ILD) layer 115 is formed to cover the sidewalls of dielectric structures 109a and 109b. The corresponding steps are illustrated in the diagram below. Figure 1 Step S19 in the fabrication method 10 shown. Due to the width W1 of the dielectric structure 109a (reference... Figure 7 The width W4 of the dielectric layer 115 is greater than that of the remaining portion 1107a of the conductive structure, so the ILD layer 115 forms an air gap 150 between the dielectric structure 109a, the remaining portion 1107a of the conductive structure, and the ILD layer 115. Similarly, an air gap 150 is provided between the dielectric structure 109b, the remaining portion 1107b of the conductive structure, and the ILD layer 115.

[0129] It should be understood that the lower sidewalls of the remaining portions 1107a and 1107b of the conductive structure are in direct contact with the ILD layer 115, such that the bottom surface of the air spacer 150 is higher than the bottom surface of the remaining portions 1107a and 1107b of the conductive structure. In some embodiments, the ILD layer 115 is formed in the opening 210 and the enlarged opening 1310, the opening 210 being completely filled by the ILD layer 115 and the enlarged opening 1310 being partially filled by the ILD layer 115. According to some embodiments, the width of each air spacer 150 gradually decreases along the dielectric structure 109a and 109b toward the substrate 101.

[0130] Additionally, the ILD layer 115 is fabricated using a deposition process, such as a CVD process, a flowable CVD (FCVD) process, an HDPCVD process, an ALD process, a spin-coating process, other applicable processes, or combinations thereof. In some embodiments, the ILD layer 115 is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. For example, low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), and polyimide.

[0131] After the deposition process forms the ILD layer 115, a planarization process can be performed to remove a portion of the ILD layer 115 and a portion of the dielectric structures 109a and 109b in order to correct defects formed in the dielectric structures 109a and 109b during the previous etching process.

[0132] Reference Figure 9 The process involves forming a reinforcement pillar 71 in the ILD layer 115, where the material used to manufacture the reinforcement pillar 71 can be removed via an energy-based process. The corresponding steps are illustrated in... Figure 1 Step S21 in the fabrication method 10 shown. In some embodiments, step S21 includes forming an opening (not shown) in the ILD layer 115 by photolithography and etching processes, and filling the opening with a possible amount of fabrication material removed from the reinforcing pillar 71 to form the reinforcing pillar 71.

[0133] refer to Figure 10 A capping dielectric layer 73 is formed on the reinforcing pillar 71. The corresponding steps are illustrated in the diagram below. Figure 1 The preparation method 10 shown includes step S23; and the reinforcing pillar 71 is converted into a dielectric isolation structure 72 having a padding layer 72B, which surrounds an air gap 72A. After the process of converting the reinforcing pillar 71 into the dielectric isolation structure 72, an integrated circuit structure 100a is obtained. In some embodiments, the probable amount of decomposable material includes a thermally decomposable material. In some other embodiments, the probable amount of decomposable material includes a photon-decomposable material, an electron beam-decomposable material, or other applicable energy-decomposable material. In some embodiments, the energy-decomposable material includes a base material and a decomposable pore-forming material, which is substantially removed upon exposure to an energy source (e.g., heat).

[0134] In some embodiments, the base material includes: monohydrosilsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylene ether (PAE), porous SiLK, or porous silica (SiO2), and the decomposable pore-forming material includes a pore-forming organic compound that can provide pores in subsequent processes for the space initially occupied by the energy-decomposable material.

[0135] Figure 11 A cross-sectional schematic diagram illustrating some embodiments of the integrated circuit structure 100b of this disclosure is shown. The integrated circuit structure 100b is similar to... Figure 10 The integrated circuit structure 100a is similar to the one in other aspects, except for the different profile of the air gap. Figure 10 same.

[0136] like Figure 11 As shown, the ILD layer 115 is in direct contact with the bottom surfaces of the dielectric structures 109a and 109b, and the area occupied by each air spacer 160 of the integrated circuit structure 100b is smaller than the area occupied by each air spacer 150 of the integrated circuit structure 100a. It should be understood that when the material of the ILD layer 115 is selected to have better step coverage (e.g., a step coverage ratio higher than...),... Figure 8 When the material of the ILD layer 115 has a better step coverage, the profile of the air gap 160 can be obtained.

[0137] Embodiments of integrated circuit structures and methods for forming the same are provided. The method for forming an integrated circuit structure (e.g., integrated circuit structures 100a, 100b, 100c) includes performing one or more repeated thermal processing steps to convert sidewall portions of conductive structures 107a, 107b into dielectric portions (e.g., dielectric portions 113a, 113b, 213a, 213b), and removing the dielectric portions such that the width of each dielectric structure (e.g., dielectric structures 109a, 109b) is greater than the width of the remaining portions of the conductive structures (e.g., conductive structures 107a', 107b', 107a”, 107b”, 1107a, 1107b). As a result, after forming an ILD layer 115 to cover the sidewalls of the dielectric structures, air spacers (e.g., air spacers 150, 160, 170) are formed between the ILD layer 115 and the remaining portions of the conductive structures.

[0138] Forming air gaps on the sidewalls of conductive features and dielectric isolation structures between conductive features helps prevent crosstalk (i.e., signal interference) between adjacent conductive structures, and may improve the performance of the integrated circuit structure. Furthermore, since the ILD layer is formed on the opposite sidewalls of the conductive structure after the conductive structure is formed, pinch-off problems near the top of the conductive structure and the generation of voids or seams in the conductive structure can be prevented. Additionally, this fabrication method includes converting the reinforcing pillars into dielectric isolation structures comprising a liner with closed air gaps, which can reduce capacitive coupling and crosstalk between conductive features.

[0139] This disclosure provides a method for fabricating an integrated circuit structure. The method includes: forming a first conductive structure on a substrate; forming a first dielectric structure above the first conductive structure; converting a sidewall portion of the first conductive structure into a first dielectric portion; removing the first dielectric portion to form the remaining portion of the first conductive structure, such that the width of the first dielectric structure is greater than the width of the remaining portion of the first conductive structure; forming an inter-dielectric (ILD) layer covering the sidewalls of the first dielectric structure; forming a reinforcing pillar of energy-removable material in the ILD layer; forming a capping dielectric layer on the reinforcing pillar; and performing a heat treatment to transform the reinforcing pillar into a dielectric isolation structure having a liner layer surrounding an air gap.

[0140] This disclosure provides a method for fabricating an integrated circuit structure. The method includes: forming a conductive layer on a substrate; forming a dielectric layer on the conductive layer; patterning the dielectric layer and the conductive layer to form a first dielectric structure, a second dielectric structure, a first conductive structure, and a second conductive structure, wherein a first opening is formed between the first dielectric structure and the second dielectric structure, and a second opening is formed between the first dielectric structure and the second dielectric structure; partially removing the first conductive structure and the second conductive structure to form an enlarged second opening; forming an interlayer dielectric layer covering the sidewalls of the first dielectric structure and the sidewalls of the second dielectric structure; forming a reinforcement pillar in the interlayer dielectric layer, the reinforcement pillar being made of an energy-removable material; forming a capping dielectric layer on the reinforcement pillar; and performing a heat treatment process to convert the reinforcement pillar into a dielectric isolation structure, the dielectric isolation structure having a padding layer surrounding an air gap.

[0141] One embodiment of this disclosure provides an integrated circuit structure. The integrated circuit structure includes: a plurality of conductive structures disposed on a substrate; a plurality of dielectric structures disposed on the plurality of conductive structures; an interlayer dielectric (ILD) layer disposed on the sidewalls of the plurality of dielectric structures and the sidewalls of the plurality of conductive structures, wherein an air gap is formed between the ILD layer, the dielectric structures, and the conductive structures; and a dielectric isolation structure having a padding layer that surrounds the air gap.

[0142] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0143] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating an integrated circuit structure, comprising: A first conductive structure is formed on a substrate; A first dielectric structure is formed on the first conductive structure; The sidewall portion of the first conductive structure is converted into a first dielectric portion; Remove the first dielectric portion to form the remaining portion of a first conductive structure, wherein the width of the first dielectric structure is greater than the width of the remaining portion of the first conductive structure; An inter-dielectric layer is formed to cover the sidewalls of the first dielectric structure; A reinforcing pillar is formed in the interlayer dielectric layer, and the reinforcing pillar is made of an energy-removable material; A capping dielectric layer is formed on the reinforcing pillar; as well as A heat treatment process is performed to transform the reinforcing post into a dielectric isolation structure having a liner layer that surrounds an air gap.

2. The method for fabricating an integrated circuit structure as described in claim 1, wherein the step of converting the sidewall portion of the first conductive structure further includes: A heat treatment process is performed on the first conductive structure to form a first dielectric portion on the opposite sidewall of the remaining portion of the first conductive structure, wherein the material of the first dielectric portion is different from the material of the first dielectric structure.

3. The method for fabricating an integrated circuit structure as described in claim 2, wherein the heat treatment process is an oxidation process or a nitriding process, and the first dielectric portion is covered by the first dielectric structure.

4. The method for fabricating an integrated circuit structure as described in claim 1, further comprising: An inter-dielectric layer is formed, which covers the sidewall of the first dielectric structure, and a first air gap is formed between the inter-dielectric layer and the rest of the first conductive structure.

5. The method for fabricating an integrated circuit structure as described in claim 4, wherein a bottom surface of the first air gap is higher than a bottom surface of the rest of the first conductive structure.

6. The method for fabricating an integrated circuit structure as described in claim 4, wherein the interlayer dielectric layer extends on and directly contacts a lower sidewall of the remaining portion of the first conductive structure.

7. The method for fabricating an integrated circuit structure as described in claim 1, further comprising: A second conductive structure is formed on the substrate; A second dielectric structure is formed on the second conductive structure; During the formation of the first dielectric portion of the first conductive structure, a second dielectric portion is formed on the sidewall portion of the second conductive structure; and The remaining portion of the second conductive structure is formed by removing the second dielectric portion, such that the distance between the remaining portion of the first conductive structure and the remaining portion of the second conductive structure is greater than the distance between the first dielectric structure and the second dielectric structure.

8. The method for fabricating an integrated circuit structure as described in claim 7, further comprising: An inter-dielectric layer is formed to cover the sidewall of the first dielectric structure, and a first air gap is formed between the inter-dielectric layer and the rest of the first conductive structure.

9. The method for fabricating an integrated circuit structure as described in claim 8, wherein a bottom surface of the first air gap is higher than a bottom surface of the rest of the first conductive structure.

10. The method for fabricating an integrated circuit structure as described in claim 8, wherein the interlayer dielectric layer covers the sidewall of the second dielectric structure, and a second air gap is formed between the interlayer dielectric layer and the remaining portion of the second conductive structure, wherein the first air gap and the second air gap are completely covered by the first dielectric structure and the second dielectric structure, respectively.

11. A method for fabricating an integrated circuit structure, comprising: A conductive layer is formed on a substrate; A dielectric layer is formed on the conductive layer; Patterning the dielectric layer and the conductive layer forms a first dielectric structure, a second dielectric structure, a first conductive structure, and a second conductive structure, wherein a first opening is formed between the first dielectric structure and the second dielectric structure, and a second opening is formed between the first dielectric structure and the second dielectric structure. Partially removing the first conductive structure and the second conductive structure forms an enlarged second opening; The formation of an inter-dielectric layer is to cover the sidewalls of the first dielectric structure and the sidewalls of the second dielectric structure; A reinforcing pillar is formed in the interlayer dielectric layer, and the reinforcing pillar is made of an energy-removable material; A capping dielectric layer is formed on the reinforcing pillar; as well as A heat treatment process is performed to transform the reinforcing post into a dielectric isolation structure having a liner layer that surrounds an air gap.

12. The method for fabricating an integrated circuit structure as described in claim 11, wherein the width of the enlarged second opening is greater than the width of the first opening.

13. The method for fabricating an integrated circuit structure as described in claim 11, further comprising: After the enlarged second opening is formed, an interlayer dielectric layer is deposited in the first opening, so that the upper sidewall of the first conductive structure is separated from the interlayer dielectric layer through a first air gap.

14. The method for fabricating an integrated circuit structure as described in claim 13, wherein the upper sidewall of the second conductive structure is separated from the interlayer dielectric layer by a second air gap, wherein the interface between the first air gap and the interlayer dielectric layer is completely covered by the first dielectric structure, and the interface between the second air gap and the interlayer dielectric layer is completely covered by the second dielectric structure.

15. The method for fabricating an integrated circuit structure as claimed in claim 13, wherein the interlayer dielectric layer is deposited in the first opening and the enlarged second opening, and the first air gap is surrounded by the upper sidewall of the first conductive structure, the first dielectric structure, and the interlayer dielectric layer.

16. The method for fabricating an integrated circuit structure as described in claim 11, wherein the bottom surface of the interlayer dielectric layer is higher than the bottom surface of the first conductive structure.

17. An integrated circuit structure, comprising: Multiple conductive structures are disposed on a substrate; Multiple dielectric structures are disposed on the multiple conductive structures; An interlayer dielectric layer is disposed on the sidewalls of the plurality of electrical structures and the sidewalls of the plurality of conductive structures, wherein the interlayer dielectric layer, the dielectric structure and the conductive structure form an air gap; A reinforcing pillar is formed in the interlayer dielectric layer, and the reinforcing pillar is made of an energy-removable material; A capping dielectric layer is formed on the reinforcing pillar; and A dielectric isolation structure, which is transformed from the reinforcing pillar, has a liner layer and the liner layer surrounds an air gap.

18. The integrated circuit structure of claim 17, wherein the width of the air gap gradually decreases along the dielectric structure toward the substrate.

19. The integrated circuit structure of claim 17, wherein the lower sidewall of the conductive structure is in direct contact with the interlayer dielectric layer.

20. The integrated circuit structure of claim 17, wherein the conductive structure and the air gap are completely covered by the dielectric structure, and a portion of the bottom surface of the dielectric structure is in direct contact with the interlayer dielectric layer.

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