Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to semiconductor devices and methods of manufacturing the same. One method includes: forming a gate structure on a semiconductor substrate; forming an etch stop layer on the gate structure and an interlayer dielectric (ILD) layer on the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer to the etch stop layer, such that sidewalls of the etch stop layer are exposed in the gate contact opening; oxidizing the exposed sidewalls of the etch stop layer; after oxidizing the exposed sidewalls of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Technological advancements in IC materials and design have led to several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (e.g., the number of interconnect devices per chip area) has typically increased, while geometry (e.g., the smallest component (or line) that can be produced using manufacturing processes) has decreased. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. Summary of the Invention

[0003] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a gate structure on a semiconductor substrate; forming an etch stop layer on the gate structure and forming an interlayer dielectric (ILD) layer on the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, such that sidewalls of the etch stop layer are exposed in the gate contact opening; oxidizing the exposed sidewalls of the etch stop layer; after oxidizing the exposed sidewalls of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

[0004] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a gate structure between gate spacers; sequentially depositing an etch stop layer and an interlayer dielectric (ILD) layer over the gate structure; performing a first etching process to form a gate contact opening in the ILD layer, at least until the etch stop layer is exposed; after performing the first etching process, performing an oxygen plasma treatment to form a treated region in the etch stop layer and around a bottom portion of the gate contact opening, while leaving the remaining region of the etch stop layer untreated; after performing the oxygen plasma treatment, performing a second etching process to extend the gate contact opening toward the gate structure, wherein, in the second etching process, the treated region of the etch stop layer has higher etch resistance than the untreated region of the etch stop layer; and after performing the second etching process, forming a gate contact in the gate contact opening.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a gate structure located on a substrate; an etch stop layer located on the gate structure; an interlayer dielectric (ILD) layer located on the etch stop layer; and a gate contact extending through the ILD layer and the etch stop layer to be electrically connected to the gate structure, wherein the etch stop layer has a first oxidized region laterally surrounding the gate contact and a first unoxidized region laterally surrounding the first oxidized region. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figures 1 to 20B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0008] Figures 21-24 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure according to some other embodiments of the present disclosure are shown.

[0009] Figures 25 to 43B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0010] Figures 44-47 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure according to some other embodiments of the present disclosure are shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptors used herein may be interpreted accordingly. As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally mean within twenty percent, or ten percent, or five percent of a given value or range. The numerical values ​​given herein are approximate, meaning that the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred unless explicitly stated otherwise.

[0013] This disclosure generally relates to integrated circuit structures and methods of forming them, and more specifically, to the fabrication of transistors (e.g., FinFETs, Gate All-Around (GAA) transistors) and gate contacts located above the gate structure of the transistors. It should also be noted that embodiments are presented in the form of multi-gate transistors. Multi-gate transistors include those transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices can include p-type metal-oxide-semiconductor devices or n-type metal-oxide-semiconductor devices. Due to the fin-like structure of certain examples, these specific examples may be presented herein and referred to as FinFETs. FinFETs have gate structures formed on three sides of a channel region (e.g., around the upper portion of the channel region in a semiconductor fin). Embodiments of a class of multi-gate transistors (referred to as GAA devices) are also presented herein. GAA devices include any device in which its gate structure or a portion thereof is formed on four sides of a channel region (e.g., around a portion of the channel region). Devices presented herein also include embodiments having channel regions configured in one or more nanosheet channels, one or more nanowire channels, and / or other suitable channel configurations.

[0014] After the front-end process (FEOL) for manufacturing the transistor is completed, gate contacts are formed over the transistor's gate structure. Forming the gate contacts typically involves depositing an interlayer dielectric (ILD) layer over a gate dielectric cap covering a high-k / metal gate (HKMG) structure, forming gate contact openings extending through the ILD layer and the gate dielectric cap using one or more etching processes, and then depositing one or more metal layers in the gate contact openings to serve as the gate contacts. In some embodiments, an additional etch stop layer (also known as an intermediate contact etch stop layer (MCESL)) is formed uniformly over the gate dielectric cap before forming the ILD layer. MCSELs have different etch selectivity than the ILD layer, thus slowing down the etch process that etches through the ILD layer.

[0015] After etching the gate contact openings through the ILD layer, another etching process (sometimes referred to as a liner removal (LRM) process, since the MCSEL and gate dielectric cap can be combined as a liner above the top surface of the gate structure) is performed to penetrate the MCSEL and gate dielectric cap. However, LRM etching can result in lateral etching in the MCSEL and / or gate dielectric cap. This is because the etching duration of the LRM etching is controlled to allow sufficient etch volume to penetrate the MCSEL and gate dielectric cap at every target location throughout the wafer. However, lateral etching extends the lateral dimension of the gate contact openings in the MCSEL and / or gate dielectric cap, causing the profile of the gate contact openings in the MCSEL and / or gate dielectric cap to bend, which in turn can increase the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact). Therefore, this disclosure provides additional plasma treatment for sidewall oxidation on the MCSEL and / or gate dielectric cap in various embodiments. Because sidewall oxidation creates oxide regions with different material compositions in the MCESL and / or gate dielectric cap, it has different etch selectivity than the unoxidized regions in the MCESL and / or gate dielectric cap. The oxide regions in the MCESL and / or gate dielectric cap allow for suppression or slowing of lateral etching during penetration of the MCESL and / or gate dielectric cap, which in turn reduces the risk of leakage current.

[0016] Figures 1 to 20B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type FinFETs) and n-type transistors (e.g., n-type FinFETs). Similar reference numerals are used throughout the various views and illustrative embodiments to denote similar elements. It should be understood that... Figure 1-20BAdditional operations are provided before, during, and after the illustrated process, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable.

[0017] Figure 1 A perspective view of the initial structure is shown. This initial structure includes a substrate 12. The substrate 12 may be a semiconductor substrate (also referred to as a wafer in some embodiments), which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. According to some embodiments of this disclosure, the substrate 12 includes a bulk silicon substrate and an epitaxial silicon-germanium (SiGe) layer or germanium layer (without silicon) on the bulk silicon substrate. The substrate 12 may be doped with p-type or n-type impurities. Isolation regions 14, such as shallow trench isolation (STI) regions, may be formed to extend into the substrate 12. The portion of the substrate 12 located between adjacent STI regions 14 is referred to as a semiconductor strip 102.

[0018] STI region 14 may include an inner oxide liner (not shown). The inner oxide liner may be formed from a thermal oxide formed by thermal oxidation of a surface layer of substrate 12. The inner oxide liner may also be a deposited silicon oxide layer formed using methods such as atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), and chemical vapor deposition (CVD). STI region 14 may also include a dielectric material situated on the inner oxide liner, and this dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0019] refer to Figure 2 The STI region 14 is recessed such that the top portion of the semiconductor strip 102 protrudes above the top surface of the adjacent STI region 14 to form a protruding fin 104. This etching can be performed using a dry etching process, wherein NH3 and NF3 are used as etching gases. Plasma can be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 14 is performed using a wet etching process. For example, the etching chemicals may include diluted HF.

[0020] In the exemplary embodiments described above, the fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used to pattern the fins.

[0021] The material of the protruding fin 104 can also be replaced with a material different from that of the substrate 12. For example, if the protruding fin 104 is used in an n-type transistor, it can be formed of Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs). On the other hand, if the protruding fin 104 is used in a p-type transistor, it can be formed of Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb).

[0022] refer to Figure 3A and Figure 3B A dummy gate structure 106 is formed on the top surface and sidewalls of the protruding fin 104. Figure 3B It shows the contents Figure 3A A cross-sectional view obtained from the vertical plane of line BB in the diagram. The formation of the dummy gate structure 106 includes sequentially depositing a gate dielectric layer and a dummy gate electrode layer on fin 104, followed by patterning the gate dielectric layer and the dummy gate electrode layer. As a result of patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 located above the gate dielectric layer 108. The gate dielectric layer 108 can be any acceptable dielectric layer (e.g., silicon oxide, silicon nitride, etc., or combinations thereof), and the gate dielectric layer 108 can be formed using any acceptable process (e.g., thermal oxidation, spin coating, CVD, etc.). The dummy gate electrode 110 can be any acceptable electrode layer, such as polysilicon, metal, etc., or combinations thereof. The gate electrode layer can be deposited using any acceptable deposition process, such as CVD, plasma-enhanced CVD (PECVD), etc. Each dummy gate structure 106 spans one or more protruding fins 104. The dummy gate structure 106 also has a longitudinal direction perpendicular to the longitudinal direction of the corresponding protruding fin 104.

[0023] A mask pattern can be formed over the dummy gate electrode layer to assist in patterning. In some embodiments, the hard mask pattern includes a bottom mask 112 over a uniform-thickness polysilicon layer and a top mask 114 over the bottom mask 112. The hard mask pattern is made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable materials. In some embodiments, the bottom mask 112 comprises silicon nitride, and the top mask 114 comprises silicon oxide. By using the mask pattern as an etching mask, the dummy electrode layer is patterned into the dummy gate electrode 110, and the uniform-thickness gate dielectric layer is patterned into the gate dielectric layer 108.

[0024] Next, as Figure 4 As shown, a gate spacer 116 is formed on the sidewall of the dummy gate structure 106. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 12. The spacer material layer may be a conformal layer that is subsequently etched back to form the gate spacer 116. In some embodiments, the spacer material layer comprises multiple layers, such as a first spacer layer 118 and a second spacer layer 120 formed over the first spacer layer 118. The first spacer layer 118 and the second spacer layer 120 are each made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. By way of example and not limitation, the first spacer 118 and the second spacer 120 may be formed by sequentially depositing two different dielectric materials over the dummy gate structure 106 using a process such as: CVD process, subatmospheric pressure CVD (SACVD) process, flowable CVD process, ALD process, PVD process, or other suitable processes. An anisotropic etching process is then performed on the deposited spacer layers 118 and 120 to expose portions of fin 104 not covered by dummy gate structure 106 (e.g., in the source / drain regions of fin 104). The portion of spacer layers 118 and 120 directly above the dummy gate structure 106 can be completely removed by this anisotropic etching process. The portions of spacer layers 118 and 120 on the sidewalls of dummy gate structure 106 can be retained to form gate sidewall spacers, which are referred to as gate spacers 116 for simplicity. In some embodiments, the first spacer layer 118 is formed of silicon oxide, which has a lower dielectric constant than silicon nitride, and the second spacer layer 120 is formed of silicon nitride, wherein silicon nitride has higher etch resistance than silicon oxide for subsequent etching processes (e.g., etching the source / drain recesses in fin 104). In some embodiments, the gate spacer 116 can be used to offset subsequently formed doped regions (e.g., source / drain regions). The gate spacer 116 can be further used to design or modify the source / drain region profile.

[0025] exist Figure 5 In this process, after the gate spacer 116 is formed, a source / drain structure 122 is formed in the source / drain region of the fin 104 that is not covered by the dummy gate structure 106 and the gate spacer 116. In some embodiments, the formation of the source / drain structure 122 includes recessing the source / drain region of the fin 104 and then epitaxially growing semiconductor material in the recessed source / drain region of the fin 104.

[0026] A suitable selective etching process can be used to recess the source / drain regions of the fin 104. This suitable selective etching process etches the semiconductor fin 104 but hardly etches the gate spacer 116 and the top mask 114 of the dummy gate structure 106. For example, recessing the semiconductor fin 104 can be performed by dry chemical etching using a plasma source and an etchant gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc., and the etchant gas can be fluorine, chlorine, bromine, or combinations thereof, which etches the semiconductor fin 104 at a faster etch rate than it etches the gate spacer 116 and the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by wet chemical etching (e.g., ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof), which etches the semiconductor fin 104 at a faster etch rate than etching the top mask 114 of the gate spacer 116 and the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by a combination of dry chemical etching and wet chemical etching.

[0027] Once a recess is created in the source / drain region of fin 104, a source / drain epitaxial structure 122 is formed in the source / drain recess in fin 104 using one or more epitaxial processes that provide one or more epitaxial materials on semiconductor fin 104. During the epitaxial growth process, gate spacer 116 confines one or more epitaxial materials in the source / drain region of fin 104. In some embodiments, the lattice constant of epitaxial structure 122 is different from the lattice constant of semiconductor fin 104, such that strain or stress can be applied to the channel region in fin 104 and between epitaxial structures 122 through epitaxial structure 122 to improve carrier mobility and enhance device performance of semiconductor devices. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the composition of semiconductor fin 104.

[0028] In some embodiments, the source / drain epitaxial structure 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure 122 may be in-situ doped during the epitaxial process by introducing dopants, including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations of the foregoing. If the source / drain epitaxial structure 122 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 122. In some exemplary embodiments, the source / drain epitaxial structure 122 in an n-type transistor includes SiP, while the source / drain epitaxial structure 122 in a p-type transistor includes GeSnB and / or SiGeSnB. In embodiments with different device types, a mask (e.g., photoresist) can be formed over the n-type device region while exposing the p-type device region, and a p-type epitaxial structure can be formed on the exposed fin 104 in the p-type device region. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type device region while exposing the n-type device region, and an n-type epitaxial structure can be formed on the exposed fin 104 in the n-type device region. The mask can then be removed.

[0029] Once the source / drain epitaxial structure 122 is formed, an annealing process can be performed to activate the p-type or n-type dopant in the source / drain epitaxial structure 122. The annealing process can be, for example, rapid thermal annealing (RTA), laser annealing, millisecond thermal annealing (MSA), etc.

[0030] Next, in Figure 6In this process, an interlayer dielectric (ILD) layer 126 is formed on substrate 12. In some embodiments, a contact etch stop layer (CESL) 124 may be optionally formed prior to the formation of the ILD layer 126. In some examples, the CESL 124 comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 126. The CESL 124 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials having a different etch selectivity than the CESL 124. The ILD layer 126 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 126, the wafer may undergo a high thermal budget process to anneal the ILD layer 126.

[0031] In some examples, after forming the ILD layer 126, a planarization process can be performed to remove excess material from the ILD layer 126. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 126 (and the CESL layer, if present) overlying the dummy gate structure 106. In some embodiments, the CMP process also removes hard mask layers 112, 114 (e.g., ...). Figure 5 (as shown) and exposes the dummy gate electrode 110.

[0032] Next, as Figure 7 As shown, the remaining dummy gate structure 106 is removed, thereby forming a gate trench GT1 between the respective gate spacers 116. The dummy gate structure 106 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the material in the dummy gate structure 106 at a faster etch rate than it etches other materials (e.g., gate spacers 116, CESL 124, and / or ILD layer 126).

[0033] After that, as Figure 8As shown, alternative gate structures 130 are formed in the gate trench GT1. Gate structures 130 can be the final gate of a FinFET. The final gate structures can all be high-k / metal gate (HKMG) stacks, but other compositions are also possible. In some embodiments, each gate structure 130 forms a gate associated with three sides of the channel region provided by the fin 104. In other words, each gate structure 130 surrounds the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 130 includes a gate dielectric layer 132 lining the gate trench GT1, a work function metal layer 134 formed over the gate dielectric layer 132, and a fill metal 136 formed over the work function metal layer 134 and filling the remaining portion of the gate trench GT1. The gate dielectric layer 132 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, high-k gate dielectrics include dielectric materials having a high dielectric constant (e.g., greater than the dielectric constant of thermally oxidized silicon (about 3.9)). The work function metal layer 134 and / or fill metal layer 136 used in the high-k / metal gate structure 130 may include metals, metal alloys, or metal silicides. The formation of the high-k / metal gate structure 130 may include various deposition processes for forming various gate materials, one or more inner liner layers, and one or more CMP processes for removing excess gate material.

[0034] In some embodiments, the interface layer of the gate dielectric layer 132 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 132 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 132 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0035] The work function metal layer 134 may include a work function metal for providing a suitable work function for the high-k / metal gate structure 130. For an n-type FinFET, the work function metal layer 134 may include one or more n-type work function metals (N-metals). The n-type work function metals may, exemplarily, include, but are not limited to, the following: titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 134 may include one or more p-type work function metals (P-metals). p-type work function metals may include, but are not limited to, the following: titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0036] In some embodiments, the filler metal 136 may include, but is not limited to, the following: tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0037] Then refer to Figure 9 An etch-back process is performed to replace the gate structure 130 and the gate spacer 116, thereby forming a recess R1 on the etched gate structure 130 and the etched gate spacer 116. In some embodiments, because the material replacing the gate structure 130 has a different etch selectivity than the gate spacer 116, a first selective etch-back process can be performed first to etch-back the gate structure 130, thereby lowering the replacement gate structure 130 below the gate spacer 116. Then, a second selective etch-back process is performed to lower the gate spacer 116. As a result, the top surface of the replacement gate structure 130 can be at a different height than the top surface of the gate spacer 116. For example, in... Figure 9 In the illustrated embodiment, the top surface of the replacement gate structure 130 is lower than the top surface of the gate spacer 116. However, in some other embodiments, the top surface of the replacement gate structure 130 may be flush with or higher than the top surface of the gate spacer 116. Furthermore, in some embodiments, the CESL 124 may be etched back during the etch-back of the replacement gate structure 130 and / or the gate spacer 116. In this case, the CESL 124 has a lower top surface than the top surface of the ILD layer 126 (as shown by the dashed line DL1).

[0038] Then, a gate metal cap 138 is formed on top of the replacement gate structure 130 using a suitable process such as CVD or ALD. In some embodiments, the metal cap 138 is formed on the replacement gate structure 130 in a bottom-up manner. For example, the metal cap 138 is selectively grown on the metal surfaces (e.g., the work function metal layer 134 and the fill metal 136), so that the sidewalls of the gate spacers 116 and CESL 124 are substantially free of the metal cap 138. By way of example and not limitation, the metal cap 138 may be a substantially fluorine-free tungsten (FFW) film, and in some embodiments where FFW is formed using chlorine-containing precursors, the amount of fluorine impurities in the metal cap 138 is less than 5 atomic percent and the amount of chlorine impurities is greater than 3 atomic percent. For example, one or more non-fluorine-based tungsten precursors (e.g., but not limited to, tungsten pentachloride (WCl5), tungsten hexachloride (WCl6)) may be used to form FFW films or films including FFW by ALD or CVD. In some embodiments, portions of the metal cap 138 may extend over the gate dielectric layer 132, such that the metal cap 138 may also cover the exposed surface of the gate dielectric layer 132. Since the metal cap 138 is formed in a bottom-up manner, the formation of the metal cap 138 can be simplified, for example, by reducing the repetitive etch-back process for removing unwanted metal material resulting from conformal growth.

[0039] In some embodiments where the metal cap 138 is formed using a bottom-up approach, the growth of the metal cap 138 on the metal surface (i.e., the metal in the gate structure 130) has a different nucleation delay compared to the dielectric surface (i.e., the dielectric in the gate spacer 116 and / or CESL 124). The nucleation delay on the metal surface is shorter than that on the dielectric surface. Therefore, the difference in nucleation delay allows for selective growth on the metal surface. This disclosure utilizes such selectivity in various embodiments to allow metal growth from the gate structure 130 while suppressing metal growth from the spacer 116 and / or CESL 124. As a result, the deposition rate of the metal cap 138 on the gate structure 130 is faster than the deposition rate of the metal cap 138 on the spacer 116 and CESL 124. In some embodiments, the top surface of the resulting metal cap 138 is lower than the top surface of the etched-back gate spacer 116. However, in some other embodiments, the top surface of the metal cap 138 may be flush with or above the top surface of the etched-back gate spacer 116.

[0040] Next, as Figure 10As shown, a dielectric capping layer 140 is deposited on substrate 105 until the recess R1 is overfilled. The dielectric capping layer 140 comprises SiN, SiC, SiCN, SiON, SiCON, combinations thereof, etc., and is formed by a suitable deposition technique, such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), or combinations thereof. A CMP process is then performed to remove the capping layer located outside the recess R1, leaving the portion of the dielectric capping layer 140 located within the recess R1 for use as a gate dielectric capping layer 142. Figure 11 The resulting structure is shown in the figure.

[0041] refer to Figure 12 A source / drain contact 144 is formed, extending through the CESL 124 and the ILD layer 126. The formation of the source / drain contact 144 includes, for example, but not limited to: performing one or more etching processes to form contact openings extending through the ILD layer 126 and CESL 124 to expose the source / drain epitaxial structure 122; depositing one or more metal materials to overfill the contact openings; and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 126 at a faster etch rate than etching the dielectric cap 142 and the gate spacer 116. As a result, selective etching is performed using the dielectric cap 142 and the gate spacer 116 as an etch mask, such that the contact openings (and therefore the source / drain contact 144) are formed to be self-aligned with the source / drain epitaxial structure 122 without the need for additional photolithography processes. In this case, the source / drain contact 144 may be referred to as a self-aligned contact (SAC), and the gate dielectric cap 142 that allows the formation of the self-aligned contact 144 may be referred to as the SAC cap 142. As a result of the formation of the self-aligned contact, each of the SAC caps 142 has opposite sidewalls that respectively contact the source / drain contact 144.

[0042] exist Figure 13 Once the self-aligned source / drain contacts 144 have been formed, an intermediate contact etch stop layer (MCESL) 146 is formed over the source / drain contacts 144 and the SAC cap 142. The MCESL 146 can be formed using a PECVD process and / or other suitable deposition processes. In some embodiments, the MCESL 146 is a silicon nitride layer and / or has a junction with the subsequently formed ILD layer (e.g., ...). Figure 14Other suitable materials with different etching selectivity (as shown). In some embodiments, both the gate dielectric cap 142 and MCESL 146 are silicon nitride (SiN).

[0043] refer to Figure 14 Another ILD layer 148 is formed on top of the MCESL 146. In some embodiments, the ILD layer 148 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials having different etch selectivity than the CESL 124. In some embodiments, the ILD layer 148 is made of silicon oxide (SiO2). x ILD layer 148 can be formed using PECVD or other suitable deposition techniques.

[0044] refer to Figure 15A The ILD layer 148 is patterned to form a gate contact opening O2 extending through the ILD layer 148 using a first etching process (also known as a contact etching process) ET1. In the depicted embodiment, the etching duration of the contact etching process ET1 is controlled to stop approximately at the bottom surface of the MCESL 146, but without penetrating the gate dielectric cap 142. Stopping the contact etching process ET1 before penetrating the gate dielectric cap 142 allows the sidewalls of the MCESL 146 to be oxidized in subsequent processing, which in turn inhibits or slows down lateral etching in subsequent LRM etching, as will be described in more detail below. In some embodiments, the ratio of the depth D2 of a portion of the contact opening O2 within the MCESL 146 (i.e., the recess depth created by the contact etching process ET1) to the total thickness T2 of the MCESL 146 and the underlying gate dielectric cap 142 is in the range of about 2:9 to about 7:9. If the ratio of the recess depth D2 in MCESL 146 to the total thickness T2 of MCESL 146 and dielectric cap 142 is too small, the oxide sidewalls formed in subsequent processing may be too small to suppress lateral etching in the subsequent LRM etching process. If the ratio of the recess depth D2 in MCESL 146 to the total thickness T2 of MCESL 146 and dielectric cap 142 is too large, the gate metal cap 138 and the lower gate structure 130 may be over-etched.

[0045] In some embodiments, a photolithography process is performed prior to the contact etching process ET1 to define a desired top-view pattern of the gate contact opening O2. For example, this photolithography process may include spin-coating a photoresist layer (such as...) over the ILD layer 148. Figure 14(as shown); perform a post-exposure baking process; and develop a photoresist layer to form a patterned mask with a top-view pattern of the gate contact opening O2. In some embodiments, patterning the photoresist to form the patterned mask can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography.

[0046] In some embodiments, the contact etching process ET1 is an anisotropic etching process, such as plasma etching. Taking plasma etching as an example, the contact with... Figure 14 The semiconductor substrate 12 of the illustrated structure is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a mixture of fluorine-containing gas (e.g., C4F8, C5F8, C4F6, CHF3, or similar substances), an inert gas (e.g., argon or helium), and optionally a weak oxidant (e.g., O2 or CO, or similar substances) for a duration sufficient to etch through the ILD layer 148 and cause the exposed portion of the MCESL 146 at the bottom of the gate contact opening O2 to be recessed. The plasma generated in a gas mixture including C4F6, CF4, CHF3, O2, and argon can be used to etch through the ILD layer 148 and cause the exposed portion of the MCESL 146 at the bottom of the gate contact opening O2 to be recessed. The pressure of the plasma etching environment is between approximately 10 mTorr and approximately 100 mTorr, and the plasma is generated by RF power between approximately 50 watts and 1000 watts.

[0047] In some embodiments, the aforementioned etchant and etching conditions of the contact etching process ET1 are selected in such a way that MCESL 146 (e.g., SiN) and gate dielectric cap 142 (e.g., SiN) exhibit better performance than ILD layer 148 (e.g., SiO). x A slower etching rate. Thus, MCESL 146 and the gate dielectric cap 142 can act as detectable etch endpoints, which in turn prevents over-etching and therefore prevents breakthrough or penetration of the gate dielectric cap 142. In other words, the contact etching process ET1 is adapted to etch silicon oxide at a faster etch rate than etching silicon nitride. It has been observed that the etch rate of silicon nitride increases when the etch plasma is generated by a gas mixture containing hydrogen (H2). As a result, according to some embodiments of this disclosure, a hydrogen-free gas mixture is used to perform the contact etching process ET1. In other words, the plasma in the contact etching process ET1 is generated in a hydrogen-free (H2) gas mixture. Thus, the etch rate of silicon nitride remains low in the contact etching process ET1, which in turn allows the etching of silicon oxide (i.e., the ILD material) at a faster etch rate than etching silicon nitride (i.e., the MCESL and gate dielectric cap materials).

[0048] In such Figure 15A In some embodiments shown, the gate contact opening O2 has a tapered sidewall profile due to the anisotropic etching nature. However, in some other embodiments, the etching conditions can be fine-tuned to allow the gate contact opening O2 to have a vertical sidewall profile, such as... Figure 15B As shown.

[0049] After completing the contact etching process ET1, the exposed portions of MCESL 146 and gate dielectric cap 142 are treated in an oxygen-containing environment. This oxidizes the surface layer of the exposed portions of MCESL 146 and gate dielectric cap 142 to form oxidized regions (interchangeably referred to as treated regions) 149 in the MCESL layer 146 and gate dielectric cap 142, while leaving the remaining regions 1462 of the MCESL layer 146 and 1422 of the gate dielectric cap 142 unoxidized (and therefore interchangeably referred to as untreated regions). Figure 16A or Figure 16B The resulting structure is shown in the figure. This processing step may include O2 plasma treatment, in which oxygen-containing gas is introduced into a process chamber, where plasma is generated by the oxygen-containing gas. As an example and not a limitation, [the following will be described]... Figure 15A or Figure 15B The semiconductor substrate 12 with the structure shown is loaded into a plasma tool and exposed to a plasma environment generated by oxygen (O2) gas, or a mixture of O2 gas and one or more of the following gases: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z (Where x, y, and z are greater than 0 and not greater than 9) gases, NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas. The pressure of the plasma processing environment is between approximately 10 mTorr and approximately 100 mTorr, and the plasma is generated by RF power between approximately 50 watts and 1000 watts.

[0050] As a result of O2 plasma treatment, oxidation occurs in the exposed nitride top surface of the gate dielectric cap 142 and the exposed nitride sidewalls of the MCESL 146, resulting in each of the oxidation regions 149 having an oxidation bottom portion 149b and an oxidation sidewall portion 149s, the oxidation bottom portion 149b being in the respective gate dielectric cap 142, and the oxidation sidewall portion 149s extending upward from the oxidation bottom portion 149b into the MCESL 146 and laterally surrounding the oxidation bottom portion 149b.

[0051] In some embodiments, the oxide bottom portion 149b and the oxide sidewall portion 149s have the same thickness (e.g., in the range of about 1 nm to about 3 nm). In some other embodiments, the oxide sidewall portion 149s has a greater thickness than the oxide bottom portion 149b. For example, the thickness ratio of the oxide sidewall portion 149s to the oxide bottom portion 149b can be greater than about 1:1, 2:1, 3:1, 4:1, or 5:1. The thicker oxide sidewall portion 149s allows for higher etch resistance to subsequent LRM etching. The thinner oxide bottom portion 149b allows for a shorter LRM etching duration because the oxide bottom portion 149b will be removed in the LRM etching. In some embodiments, the oxide sidewall portion 149s has a thickness gradient from bottom to top. For example, the oxide sidewall portion 149s can be thicker at the top and thinner at the bottom. By way of example and not limitation, the thickness of the oxide sidewall portion 149s and the oxide bottom portion 149b can be controlled by the RF power and / or bias power used in O2 plasma treatment.

[0052] In some embodiments where the gate contact opening O2 is formed with a tapered sidewall profile, the oxide sidewall portion 149s extends at an obtuse angle relative to the oxide bottom portion 149b, such as... Figure 16A As shown. In some embodiments where the gate contact opening O2 is formed with a vertical sidewall profile, the oxide sidewall portion 149s extends at a vertical angle relative to the oxide bottom 149b, as... Figure 16B As shown.

[0053] In some embodiments where the MCESL 146 and gate dielectric cap 142 are made of SiN, O2 plasma treatment produces oxidized nitride regions (silicon oxynitride (SiO2)). x N y Oxidized nitride region 149, unoxidized nitride region 1422, and unoxidized nitride region 1462, wherein oxidized nitride region 149 is located within MCESL 146 and gate dielectric cap 142 and below gate contact opening O2; unoxidized nitride region 1422 cup-shapedly accommodates the bottom side of oxidized nitride region 149 within gate dielectric cap 142; and unoxidized nitride region 1462 is located within MCESL 146 and laterally surrounds oxidized nitride region 149. Oxidized nitride region 149 can form a distinguishable interface with unoxidized nitride regions 1422 and 1462 because they have different material compositions (e.g., oxidized nitride region 149 has a higher percentage of oxygen atoms than unoxidized nitride regions 1422 and 1462).

[0054] In some embodiments, the oxide region 149 may have an oxygen concentration gradient due to plasma processing. For example, the percentage of oxygen atoms in the oxide region 149 may decrease as the distance from the surface of the gate contact opening O2 increases. More specifically, the percentage of oxygen atoms in the oxidized sidewall portion 149s decreases as the distance from the sidewall of the gate contact opening O2 increases, and the percentage of oxygen atoms in the oxidized bottom portion 149b decreases as the distance from the bottom surface of the gate contact opening O2 increases. In some embodiments where the gate dielectric cap 142 and MCESL 146 are silicon nitride, the oxygen-to-nitrogen ratio in the oxide region may decrease as the distance from the surface of the gate contact opening O2 increases. More specifically, the oxygen-to-nitrogen ratio in the oxidized sidewall portion 149s may decrease as the distance from the sidewall of the gate contact opening O2 increases, and the oxygen-to-nitrogen ratio in the oxidized bottom portion 149b decreases as the distance from the bottom surface of the gate contact opening O2 increases.

[0055] Figure 17 A cross-sectional view of the initial stage of a second etching process (also known as an LRM etching process) ET2 according to some embodiments of the present disclosure is shown. Figure 18 A cross-sectional view of the next stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown, and Figure 19A A cross-sectional view of the final stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown. The etching duration of the LRM etching process ET2 is controlled to allow penetration (or so-called punch-through) of the MCESL 146 and the gate dielectric cap 142, thereby deepening or extending the gate contact opening O2 downwards to the gate metal cap 138 above the gate structure 130. As a result of the LRM etching process ET2, the gate metal cap 138 is exposed at the bottom of the deepened gate contact opening O2.

[0056] In some embodiments, the LRM etching process ET2 is an anisotropic etching process, such as plasma etching (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc.) using etchants and / or etching conditions different from those of the contact etching process ET1. The etchant and / or etching conditions of the LRM etching process ET2 are selected in such a way that the oxidized region 149 exhibits a slower etching rate than the unoxidized regions 1422 and 1462. In other words, in the LRM etching process ET2, the oxidized region 149 has higher etch resistance than the unoxidized regions 1422 and 1462. Thus, the oxidized region 149 can suppress or slow down lateral etching in the MCESL 146 during the LRM etching process ET2. Taking plasma etching as an example, [the process would involve...]. Figure 16AThe semiconductor substrate 12 with the structure shown is loaded into a plasma tool and exposed to RF or microwave power in a fluorine-containing gas (e.g., CHF3, CF4, C2F2, C4F6, C...). x H y F z The plasma etching environment is generated for a duration sufficient to etch through the oxidized bottom portion 149b of the gate dielectric cap 142 and the unoxidized region 1422 below, in a plasma environment consisting of a mixture of hydrogen-containing gas (e.g., H2) and an inert gas (e.g., argon or helium). The pressure of the plasma etching environment is between about 10 mTorr and about 100 mTorr, and the plasma is generated by an RF power between about 50 watts and about 1000 watts.

[0057] The plasma generated by the hydrogen-containing gas mixture can etch silicon nitride at a faster etch rate than etching silicon oxynitride. Therefore, the LRM etching process ET2 using the hydrogen-containing gas mixture etches the oxide region 149 at a slower etch rate than etching the unoxidized regions 1422 and 1462. In this way, the oxide sidewall portions 149s can suppress or slow down lateral etching during the LRM etching process ET2. In some embodiments, the LRM etching process ET2 uses a gas mixture of CHF3 and H2, wherein the flow rate ratio of CHF3 to H2 is from about 1:1 to about 1:100. In some embodiments, the LRM etching process ET2 uses a gas mixture of CF4 and H2, wherein the flow rate ratio of CF4 to H2 is from about 1:1 to about 1:100. Excessively high H2 gas flow rates may cause the etching rate to be too fast when etching through the unoxidized region 1462 of MCESL 146, which in turn may result in a non-negligible curved profile in the unoxidized region 1462. Too low an H2 gas flow rate may result in insufficient etching selectivity between the unoxidized region 1462 and the oxidized sidewall portion 149s.

[0058] like Figure 17 As shown, in the initial stage of the LRM etching process ET2, the plasma etchant etches the oxide bottom portion 149b at a first vertical etch rate A1 and the oxide sidewall portion 149s at a lateral etch rate A2. Due to the anisotropic etching mechanism, the lateral etch rate A2 of the oxide sidewall portion 149s is slower than the first vertical etch rate A1 of the oxide bottom portion 149b. Figure 18The next stage of the LRM etching process ET2, as shown, once the oxide bottom portion 149b is removed by the LRM etching process ET2, exposes the unoxidized region 1422 of the gate dielectric cap 142. Then, the plasma etchant etches the unoxidized region 1422 at a second vertical etch rate A3, which is faster than the first vertical etch rate A1, but still etches the oxide sidewall portion 149s at a lateral etch rate A2, which is much slower than the second vertical etch rate A3. As a result, the oxide sidewall portion 149s suppresses or slows down the lateral etching of the MCESL 146 during penetration of the unoxidized region 1422 of the gate dielectric cap 142, resulting in no or negligible curved profile in the gate contact opening O2, such as... Figure 19A As shown. As a result of the LRM etching process ET2, the oxide region 149 includes an oxide region located in MCESL 146 and an oxide region located in a corresponding gate dielectric cap 142, which extends continuously from the oxide region in MCESL 146 and terminates before reaching the bottom position of the gate contact opening O2.

[0059] In some embodiments, the sidewall O20 of the gate contact opening O2 extends linearly through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the gate dielectric cap 142, and no bending occurs or the bending is negligible. More specifically, the ILD layer 148 has a linear sidewall O21 defining an upper portion of the gate contact opening O2, the MCESL 146 has a linear sidewall O22 defining a middle portion of the gate contact opening O2, and the corresponding gate dielectric cap 142 has a linear sidewall O23 defining a lower portion of the gate contact opening O2. The linear sidewalls O21-O23 are aligned with each other. In some embodiments, the linear sidewall O22 of MCESL 146 is a sidewall of the oxide sidewall portion 149s extending downward from the linear sidewall O21 of ILD layer 148, the linear sidewall O23 of gate dielectric cap 142 is a sidewall of the oxide sidewall portion 149s extending downward from the linear sidewall O22 of MCESL 146, and the sidewall of the unoxidized region 1422 in gate dielectric cap 142 extends downward from the sidewall of the oxide sidewall portion 149s. Figure 19AIn some embodiments shown, the sidewalls of the unoxidized region 1422 in the gate dielectric cap 142 are aligned with the sidewalls of the oxidized sidewall portion 149s. However, in some other embodiments, since the LRM etching process ET2 may cause more lateral etching in the unoxidized region 1422 than in the oxidized sidewall portion 149s, the sidewalls of the unoxidized region 1422 may be slightly laterally recessed relative to the sidewalls of the oxidized sidewall portion 149s (as shown by the dashed line DL2). Even in this case, the gate contact opening O2 still mitigates bending defects compared to the case where the oxidized sidewall portion 149s is not formed, because the bending profile is confined to the unoxidized region 1422.

[0060] In such Figure 19A In some embodiments shown, the gate contact opening O2 has a tapered sidewall profile due to the anisotropic etching nature of the LRM etching process ET2. However, in some other embodiments, the etching conditions of the LRM etching process ET2 and / or the preceding contact etching process ET1 can be fine-tuned to allow the gate contact opening O2 to have a vertical sidewall profile, such as... Figure 19B As shown.

[0061] refer to Figure 20A Then, a gate contact 150 is formed in the gate contact opening O2 to electrically connect the NKMG structure 130 through the gate metal cap 138. By way of example and not limitation, the gate contact 150 is formed by depositing one or more metal materials that overfill the gate contact opening O2, followed by a CMP process to remove excess metal(s) material located outside the gate contact opening O2. As a result of the CMP process, the gate contact 150 has a top surface substantially coplanar with the ILD layer 148. The gate contact 150 may include a metal material, such as copper, aluminum, tungsten, or combinations thereof, and the gate contact 150 may be formed using PVD, CVD, or ALD, etc. In some embodiments, the gate contact 150 may also include one or more barrier / adhesion layers (not shown) to protect the ILD layer 148, MCESL 146, and / or the gate dielectric cap 142 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, or tantalum nitride, and the one or more barrier / adhesion layers may be formed using PVD, CVD, or ALD, etc.

[0062] Gate contact 150 inherits the geometry of the substantially non-bent gate contact opening O2, and therefore gate contact 150 is also substantially non-bent. In other words, the sidewalls of gate contact 150 extend linearly through the entire thickness of ILD layer 148, the entire thickness of MCESL 146, and the entire thickness of gate dielectric cap 142, and there is no bending or the bending is negligible. More specifically, gate contact 150 forms a first linear interface 1501 with ILD layer 148, a second linear interface 1502 with MCESL 146, and a third linear interface 1503 with gate dielectric cap 142. The second linear interface 1502 extends downward from the first linear interface 1501, the third linear interface 1503 extends downward from the second linear interface 1502, and linear interfaces 1501-1503 are aligned with each other. In some embodiments, the third interface 1503 includes an upper interface 1504 and a lower interface 1505. The upper interface 1504 is an oxygen-containing interface formed between the gate contact 150 and the oxide sidewall portion 149s, and the lower interface 1505 is formed between the gate contact 150 and the unoxidized region 1422. The lower interface 1505 is an oxygen-free interface extending downward from the oxygen-containing interface 1504. Figure 20A In some embodiments shown, the oxygen-free interface 1505 is aligned with the oxygen-containing interface 1504. However, in some other embodiments, the oxygen-free interface 1505 may be slightly laterally retracted from the oxygen-containing interface 1503 (as shown by the dashed line DL3) because, in the previous processing, the LRM etch ET2 can cause more lateral etching in the unoxidized region 1422 than in the oxidized sidewall portion 149s. Even in this case, the gate contact 150 still mitigates bending defects compared to the case where the oxidized sidewall portion 149s is not formed, because the bending profile is confined below the oxidized sidewall portion 149s.

[0063] In such Figure 20A In some embodiments shown, the gate contact 150 has a tapered sidewall profile due to the anisotropic etching nature of the LRM etching process ET2. However, in some other embodiments, the etching conditions of the LRM etching process ET2 can be fine-tuned to allow the gate contact opening O2 (and thus the gate contact 150) to have a vertical sidewall profile, such as... Figure 20B As shown.

[0064] Figure 21-24 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure 100a according to some other embodiments of the present disclosure are shown. It should be understood that... Figure 21-24Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of these operations / processes may be interchangeable. In the following embodiments, [the following text may be used in conjunction with...] Figure 1-20B The same or similar configurations, materials, processes and / or operations described herein may be omitted, and detailed descriptions may be omitted.

[0065] In the formation of such Figure 14 Following the structure shown, a contact etching process ET3 is performed to form a gate contact opening O3 extending downward through the ILD layer 148 but without penetrating the MCESL 146. The resulting structure is... Figure 21 As shown in the diagram, as a result of the contact etching process ET3, a recess R3 is formed below the corresponding gate contact opening O3, extending into the MCESL 146 but not through the entire thickness of the MCESL 146. In other words, the etching duration of the contact etching process ET3 is controlled to stop before the gate dielectric cap 142 is exposed. For example, the contact etching process ET3 can be stopped when the MCESL 146 is just exposed. The formation of the recess R3 allows the sidewalls of the MCESL 146 to be oxidized in subsequent processing, which in turn will suppress or slow down lateral etching in subsequent LRM etching, as described above. The process details of the contact etching process ET3 have been discussed above with respect to the contact etching process ET1, so for the sake of brevity, these details will not be repeated here.

[0066] exist Figure 22 In this process, the exposed portions of MCESL 146 are treated in an oxygen-containing environment, causing the surface layer of the exposed portions of MCESL 146 to be oxidized to form oxidized regions 1463 (interchangeably referred to as treated regions) within MCESL 146, while leaving the remaining regions 1462 of MCESL 146 unoxidized (and therefore interchangeably referred to as untreated regions). The treatment steps may include O2 plasma treatment, in which oxygen-containing gas is introduced into a process chamber where plasma is generated by the oxygen-containing gas. Process details regarding O2 plasma treatment have been previously discussed in [section on O2 plasma treatment]. Figure 16A This has already been discussed, so for the sake of brevity, it will not be repeated here.

[0067] As a result of O2 plasma treatment, oxidation occurs in the bottom surface and sidewalls of the recess R3 in the MCESL 146, creating an oxide region 1463 having an oxide bottom portion 1463b and oxide sidewall portions 1463s extending upward from and laterally surrounding the oxide bottom portion 1463b. In some embodiments, the oxide bottom portion 1463b and the oxide sidewall portions 1463s have the same thickness (e.g., in the range of about 1 nm to 3 nm). In some other embodiments, the oxide sidewall portions 1463s have a greater thickness than the oxide bottom portion 1463b. The thicker oxide sidewall portions 1463s allow for higher etch resistance to subsequent LRM etching. The thinner oxide bottom portion 1463b allows for a shorter LRM etching duration. In some embodiments, the oxide sidewall portions 1463s have a thickness gradient from bottom to top. For example, the oxide sidewall portions 1463s may be thicker at the top and thinner at the bottom.

[0068] In some embodiments, the oxide region 1463 may have an oxygen concentration gradient due to plasma processing. For example, the percentage of oxygen atoms in the oxide region 1463 may decrease as the distance from the surface of the recess R3 increases. More specifically, the percentage of oxygen atoms in the oxide sidewall portion 1463s decreases as the distance from the sidewall of the recess R3 increases, and the percentage of oxygen atoms in the oxide bottom portion 1463b decreases as the distance from the bottom surface of the recess R5 increases. In some embodiments where MCESL 146 is silicon nitride, the oxygen-to-nitrogen ratio in the oxide region may decrease as the distance from the surface of the recess R3 increases. More specifically, the oxygen-to-nitrogen ratio in the oxide sidewall portion 1463s may decrease as the distance from the sidewall of the recess R3 increases, and the oxygen-to-nitrogen ratio in the oxide bottom portion 1463b may decrease as the distance from the bottom surface of the recess R3 increases.

[0069] exist Figure 23 In this process, LRM etching process ET4 is performed to penetrate MCESL 146 and the underlying gate point dielectric cap 142, thereby deepening the gate contact opening O3 downwards to the gate metal cap 138. As a result of LRM etching process ET4, the gate metal cap 138 is exposed at the bottom of the deepened gate contact opening O3. As previously mentioned, since the oxide sidewall portions 1463s suppress or slow down lateral etching during LRM etching process ET4, the sidewalls of the gate contact opening O3 extend linearly through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the gate dielectric cap 142, without bending or with negligible bending. The process details of LRM etching process ET4 were discussed earlier regarding LRM etching process ET2, and therefore will not be repeated here for the sake of brevity.

[0070] exist Figure 24 In this process, gate contact 160 is subsequently formed in gate opening O3 to electrically connect through gate metal cap 138 to KHMG structure 130. Details regarding the materials and manufacturing process of gate contact 160 are provided earlier in the section on... Figure 20A The description has already been provided, so for the sake of brevity, it will not be repeated here.

[0071] exist Figure 24 In the illustrated embodiment, the gate contacts 160 are substantially non-bent because they inherit the geometry of the gate contact opening O3. In other words, the sidewalls of the gate contacts 160 extend linearly through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the gate dielectric cap 142, and are non-bent or negligible in bending. More specifically, the gate contacts 160 form an oxygen-containing interface 1601 with the oxidized sidewall portions 1463s in the ILD layer 148 (i.e., the SiO2 layer) and the MCESL 146, and also form an oxygen-free interface 1602 with the unoxidized region 1462 in the MCESL 146 and the gate dielectric cap 142, and the oxygen-free interface 1602 is aligned with the oxygen-containing interface 1601, as shown. Figure 24 As shown. However, in some other embodiments, the oxygen-free interface 1602 can be laterally retracted from the oxygen-containing interface 1601 (as shown by the dashed line DL4) because the LRM etching process ET4 can induce more lateral etching in the unoxidized region 1462 and the unoxidized gate dielectric cap 142 in the MCESL 146 than in the oxidized sidewall portion 1463s. Even in this case, the gate contact 160 still mitigates bending defects compared to the case where the oxidized sidewall portion 1463s is not formed, because the bending profile is confined below the oxidized sidewall portion 1463s.

[0072] Figures 25 to 43B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 200 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type GAA FETs) and n-type transistors (e.g., n-type FAA FETs). Similar reference numerals are used throughout the various views and illustrative embodiments to denote similar elements. It should be understood that... Figures 25 to 43B Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable.

[0073] Figure 25 , Figure 26 , Figure 27 , Figure 28A , Figure 29A , Figure 30A and Figure 31A These are perspective views of some embodiments of an integrated circuit structure 200 during an intermediate stage of manufacturing. Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figures 32-34 , Figure 35A , Figure 36-43B It is along the first tangent (e.g., Figure 28A The first tangent (XX) is a cross-sectional view of some embodiments of the integrated circuit structure 200 during an intermediate stage of manufacturing, the first tangent being along the longitudinal direction of the channel and perpendicular to the top surface of the substrate. Figure 35B It is along the second tangent (e.g., Figure 28A The second tangent (YY) is a cross-sectional view of some embodiments of the integrated circuit structure 200 during an intermediate stage of manufacturing, in the gate region and perpendicular to the longitudinal direction of the channel.

[0074] refer to Figure 25 An epitaxial stack 220 is formed on substrate 210. In some embodiments, substrate 210 may include silicon (Si). Alternatively, substrate 210 may include germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof) or other suitable semiconductor materials. In some embodiments, substrate 210 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Furthermore, alternatively, substrate 210 may include a buried dielectric layer (e.g., a buried oxide (BOX) layer), which is formed, for example, by a method known as oxygen implantation separation (SIMOX) technology, wafer bonding, SEG, or other suitable methods.

[0075] The epitaxial stack 220 includes epitaxial layers 222 having a first composition, into which epitaxial layers 224 having a second composition are intercalated. The first and second compositions can be different. In some embodiments, the epitaxial layer 222 is SiGe, and the epitaxial layer 224 is silicon (Si). However, other embodiments are also possible, including those providing first and second compositions with different oxidation rates and / or etch selectivity. In some embodiments, the epitaxial layer 222 comprises SiGe, and in the case where the epitaxial layer 224 comprises Si, the Si oxidation rate of the epitaxial layer 224 is less than the SiGe oxidation rate of the epitaxial layer 222.

[0076] Epitaxial layer 224, or portions thereof, can form one or more nanosheet channels of a multi-gate transistor. The term nanosheet is used herein to refer to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions having circular or substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions, including, for example, having cylindrical or substantially rectangular cross-sections. The use of epitaxial layer 224 to define one or more channels of a device is further discussed below.

[0077] Note that, as Figure 25 As shown, the three epitaxial layers 222 and 224 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope beyond that specifically described in the claims. It will be appreciated that any number of epitaxial layers can be formed in the epitaxial stack 220, the number of layers depending on the desired number of channel regions for the transistor. In some embodiments, the number of epitaxial layers 224 is between 2 and 10.

[0078] As described in more detail below, epitaxial layer 224 can be used as one or more channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 222 in the channel region(s) can eventually be removed and used to define the vertical distance between adjacent channel regions(s) of the subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Therefore, epitaxial layer 222 can also be referred to as a sacrificial layer, and epitaxial layer 224 can also be referred to as a channel layer.

[0079] For example, the epitaxial growth of the layers of the epitaxial stack 220 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer (e.g., epitaxial layer 224) comprises the same material as the substrate 210. In some embodiments, the epitaxially grown layers 222 and 224 comprise materials different from the substrate 210. As described above, in at least some examples, epitaxial layer 222 comprises an epitaxially grown silicon-germanium (SiGe) layer, and epitaxial layer 224 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 222 or 224 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed, the materials for epitaxial layers 222 and 224 can be selected based on providing different oxidation properties and / or etch selectivity properties. In some embodiments, epitaxial layers 222 and 224 are substantially doped (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 18 cm -3 (the concentration of non-intrinsic dopants), where, for example, no intentional doping is performed during the epitaxial growth process.

[0080] refer to Figure 26 A plurality of semiconductor fins 230 extending from the substrate 210 are formed. In various embodiments, each fin 230 includes a substrate portion 212 formed from the substrate 210 and portions of each epitaxial layer of the epitaxial stack including epitaxial layers 222 and 224. The fins 230 can be fabricated using suitable processes including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 230 can then be patterned using the remaining spacers or mandrels by etching the initial epitaxial stack 220. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0081] exist Figure 25 and Figure 26In the illustrated embodiment, a hard mask (HM) layer 910 is formed on the epitaxial stack 220 prior to patterning the fin 230. In some embodiments, the HM layer includes an oxide layer 912 (e.g., an oxide-lined layer that may include SiO2) and a nitride layer 914 (e.g., an oxide-lined layer that may include Si3N4) formed on the oxide layer. The oxide layer 912 may act as an adhesion layer between the epitaxial stack 220 and the nitride layer 914, and may also act as an etch stop layer for etching the nitride layer 914. In some examples, the HM oxide layer 912 includes thermally grown oxides, chemical vapor deposition (CVD) deposited oxides, and / or atomic layer deposition (ALD) deposited oxides. In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and / or other suitable techniques.

[0082] The fins 230 can then be fabricated using a suitable process including photolithography and etching. The photolithography process may include: forming a photoresist layer (not shown) over the HM layer 910; exposing the photoresist to a pattern; performing a post-exposure baking process; and developing the photoresist to form a patterned mask comprising the photoresist. In some embodiments, the patterned photoresist can be performed using an electron beam lithography process or an extreme ultraviolet (EUV) lithography process utilizing light in the EUV region (having a wavelength of, for example, about 1-200 nm) to form a patterned mask element. The patterned mask can then be used to protect areas of the substrate 210 and the layers formed thereon, while the etching process forms trenches 202 in the unprotected areas, which penetrate the HM layer 910, through the epitaxial stack 220, and into the substrate 210, leaving a plurality of extended fins 230. The trenches 202 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other embodiments of the method of forming fins on a substrate can also be used, including, for example, defining a fin region (e.g., by means of a mask or isolation region) and epitaxially growing an epitaxial stack 220 in the form of fin 230.

[0083] Next, as Figure 27 As shown, an STI region 240 is formed between multiple fins 230. The material and process details of the STI region 240 are similar to those of the previously discussed STI region 14, and therefore will not be repeated for the sake of brevity.

[0084] refer to Figure 28A and Figure 28BA dummy gate structure 250 is formed on the substrate 210 and is at least partially disposed on the fin 230. The portion of the fin 230 located below the dummy gate structure 250 may be referred to as a channel region. The dummy gate structure 250 may also define a source / drain (S / D) region of the fin 230, for example, a region of the fin 230 adjacent to the channel region and located on the opposite side of the channel region.

[0085] The dummy gate formation step first forms a dummy gate dielectric layer 252 over the fin 230. Subsequently, a dummy gate electrode layer 254 and a hard mask, which may include multiple layers 256 and 258 (e.g., oxide layer 256 and nitride layer 258), are formed over the dummy gate dielectric layer 252. The hard mask is then patterned, and subsequently, the dummy gate electrode layer 254 is patterned using the patterned hard mask as an etching mask. In some embodiments, after patterning the dummy gate electrode layer 254, the dummy gate dielectric layer 252 is removed from the S / D region of the fin 230. The etching process may include wet etching, dry etching, and / or combinations thereof. The etching process is selected to selectively etch the dummy gate dielectric layer 252 while substantially not etching the fin 230, the dummy gate electrode layer 254, the oxide mask layer 256, and the nitride mask layer 258. The materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those of the dummy gate dielectric layer 108 and the dummy gate electrode layer 110 discussed earlier, so they will not be repeated for the sake of brevity.

[0086] After the dummy gate structure 250 is formed, gate spacers 260 are formed on the sidewalls of the dummy gate structure 250. For example, a spacer material layer is deposited on the substrate 210. The spacer material layer may be a conformal layer, which is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structure 250. The spacer material layer 260 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material layer 260 includes multiple layers, such as a first spacer layer 262 and a second spacer layer 264 formed on the first spacer layer 262. Figure 28B(As shown in the diagram). For example, a spacer material layer 260 can be formed by depositing a dielectric material on the gate structure 250 using a suitable deposition process. An anisotropic etching process is then performed on the deposited spacer material layer 260 to expose portions of the fin 230 not covered by the dummy gate structure 250 (e.g., in the source / drain regions of the fin 230). This anisotropic etching process can completely remove the portion of the spacer material layer directly above the dummy gate structure 250. The portions of the spacer material layer on the sidewalls of the dummy gate structure 250 can be retained, forming gate sidewall spacers, which are referred to as gate spacers 260 for simplicity. It should be noted that although in Figure 28B In the cross-sectional view, the gate spacer 260 is a multilayer structure, but for simplicity, in Figure 28A In the perspective view, they are shown as a single-layer structure.

[0087] Next, as Figure 29A and Figure 29B As shown, a recess R6 is formed in the semiconductor fin 230 and between the corresponding dummy gate structures 250 by etching the exposed portion of the semiconductor fin 230 extending laterally beyond the gate spacer 260 (e.g., in the source / drain region of the fin 230) using, for example, an anisotropic etching process. This anisotropic etching process uses the dummy gate structures 250 and the gate spacer 260 as etching masks. After the anisotropic etching, the end faces of the sacrificial layer 222 and the channel layer 224 are aligned with the corresponding outermost walls of the gate spacer 260 due to this anisotropic etching. In some embodiments, the anisotropic etching can be performed by dry chemical etching utilizing a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactant gas can be, for example, a fluorine-based gas (e.g., SF6, CH2F2, CH3F, CHF3, etc.), a chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), etc., or a combination of the foregoing.

[0088] Next, in Figure 30A and Figure 30BIn this process, the sacrificial layer 222 is recessed laterally or horizontally using a suitable etching technique to form lateral recesses R7, each of which is vertically located between the respective channel layers 224. This step can be performed using a selective etching process. By way of example and not limitation, the sacrificial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective etching of the sacrificial layer 222. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture) of SiGe at an etch rate faster than that of Si. In some embodiments, selective etching includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, followed by removal of SiGeO by an etchant such as NH4OH. x This etchant selectively etches SiGeO at a faster etch rate than it etches Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes 30 times lower), the channel layer 224 is not significantly etched by the process of laterally recessed sacrificial layer 222. As a result, the channel layer 224 extends laterally beyond the opposite end face of the sacrificial layer 222.

[0089] exist Figure 31A and Figure 31B In the middle, an internal spacer material layer 270 is formed to fill the spacer material layer 270 formed by the reference above. Figure 30A and Figure 30B The recess R7 is left by the lateral etching of the sacrificial layer 222 under discussion. The internal spacer material layer 270 can be a low-k dielectric material, such as SiO2, SiN, SiCN, or SiOCN, and the internal spacer material layer 270 can be formed by a suitable deposition method such as ALD. After the deposition of the internal spacer material layer 270, an anisotropic etching process can be performed to trim the deposited internal spacer material 270, such that only a portion of the deposited internal spacer material 270 filling the recess R7 left by the lateral etching of the sacrificial layer 222 is retained. After the trimming process, for simplicity, the remaining portion of the deposited internal spacer material is referred to as the internal spacer 270. The internal spacer 270 is used to isolate the metal gate from the source / drain regions formed in subsequent processing. Figure 31A and Figure 31B In the example, the sidewall of the inner spacer 270 is aligned with the sidewall of the channel layer 224.

[0090] exist Figure 32In this process, a source / drain epitaxial structure 280 is formed on the source / drain region S / D of the semiconductor fin 230. The source / drain epitaxial structure 280 can be formed by performing an epitaxial growth process that provides epitaxial material on the fin 230. During the epitaxial growth process, a dummy gate structure 250, a gate sidewall spacer 260, and an internal spacer 270 confine the source / drain epitaxial structure 280 to the source / drain region S / D. The material and process details of the source / drain epitaxial structure 280 of the GAA FET are similar to those of the source / drain epitaxial structure 122 of the FinFET discussed previously, and therefore will not be repeated for the sake of brevity.

[0091] exist Figure 33 In this configuration, an interlayer dielectric (ILD) layer 310 is formed on a substrate 210. In some embodiments, a contact etch stop layer (CESL) 300 is also formed prior to the formation of the ILD layer 310. The material and process details for CESL 300 and ILD layer 310 are similar to those for CESL 124 and ILD layer 126, and therefore will not be repeated for brevity. In some examples, a planarization process may be performed after depositing the ILD layer 310 to remove excess material from the ILD layer 310. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 310 (and the CESL layer, if present) covering the dummy gate structure 250 and planarizes the top surface of the integrated circuit structure 200. In some embodiments, the CMP process also removes hard mask layers 256, 258 (e.g., Figure 32 (as shown in the diagram) and exposes the dummy gate electrode layer 254.

[0092] Subsequently, the dummy gate structure 250 (e.g.) is first removed. Figure 33 (As shown), then remove the sacrificial layer 222. In Figure 34The resulting structure is illustrated. In some embodiments, the dummy gate structure 250 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the dummy gate structure 250 at a faster etch rate than etching other materials (e.g., gate sidewall spacers 260, CESL 300, and / or ILD layer 310), thereby forming a gate trench GT2 between the respective gate sidewall spacers 260, wherein the sacrificial layer 222 is exposed in the gate trench GT2. Subsequently, the sacrificial layer 222 in the gate trench GT2 is removed using another selective etching process that etches the sacrificial layer 222 at a faster etch rate than etching the channel layer 224, thereby forming an opening O6 between adjacent channel layers 224. In this way, the channel layer 224 becomes a nanosheet suspended above the substrate 210 and located between the source / drain epitaxial structures 290S / 290D. This step is also referred to as a channel release process. In this intermediate processing step, the openings O6 between the nanosheets 224 can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, depending on the geometry of the nanosheets 224, the nanosheets 224 can be interchangeably referred to as nanowires, nanoplates, and nanorings. For example, in some other embodiments, the channel layer 224 can be trimmed into a substantially circular shape (i.e., cylindrical) due to a selective etching process used to completely remove the sacrificial layer 222. In this case, the resulting channel layer 224 can be referred to as a nanowire.

[0093] In some embodiments, the sacrificial layer 222 is removed using a selective wet etching process. In some embodiments, the sacrificial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective removal of the sacrificial layer 222. In some embodiments, the selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, selective removal includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, followed by removal of SiGeO by an etchant such as NH4OH. x This etchant selectively etches SiGeO at a faster etch rate than it etches Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes 30 times lower), the channel layer 224 may not be significantly etched by the channel release process. It can be noted that the channel release step and the preceding lateral recess sacrificial layer step (such as...) Figure 30A and Figure 30BThe steps shown all use a selective etching process to etch SiGe at a faster etch rate than etching Si, so in some embodiments, the two steps can use the same etchant chemicals. In this case, the etch time / duration of the channel release step is longer than the etch time / duration of the previous lateral recess sacrificial layer step in order to completely remove the sacrificial SiGe layer.

[0094] exist Figure 35A and Figure 35B In this configuration, replacement gate structures 320 are formed in the gate trench GT2 to surround each nanosheet 224 suspended in the gate trench GT2. The gate structure 320 can be the final gate of a GAA FET. The final gate structure can be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each gate structure 320 forms a gate associated with a multi-channel provided by the plurality of nanosheets 224. For example, the high-k / metal gate structure 320 is formed in an opening O6 provided by the release of the nanosheets 224 (e.g., ...). Figure 34 (As shown). In various embodiments, the high-k / metal gate structure 320 includes a gate dielectric layer 322 formed around the nanosheet 224, a work function metal layer 324 formed around the gate dielectric layer 322, and a fill metal 326 formed around the work function metal layer 324 and filling the remainder of the gate trench GT2. The gate dielectric layer 322 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant (~3.9) of thermally heated silicon oxide). The work function metal layer 324 and / or the fill metal layer 326 used in the high-k / metal gate structure 320 may include metals, metal alloys, or metal silicides. The formation of the high-k / metal gate structure 320 may include deposition to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate material. For example, a section taken along the vertical axis of the high-k / metal gate structure 320 Figure 35B As shown in the cross-sectional view, the high-k / metal gate structure 320 surrounds each nanosheet 224 and is therefore referred to as the gate of the GAA FET. The material and process details of the GAA FET gate structure 320 are similar to those of the FinFET gate structure 130, and therefore will not be repeated for the sake of brevity.

[0095] exist Figure 36In this process, an etch-back process is performed to replace the gate structure 320 and the gate spacer 260, thereby forming a recess on the etch-back gate structure 320 and the etch-back gate spacer 260. In some embodiments, because the material replacing the gate structure 320 has a different etch selectivity than the gate spacer 260, the top surface of the replacing gate structure 320 can be at a different height than the top surface of the gate spacer 260. For example, in... Figure 36 In the illustrated embodiment, the top surface of the replacement gate structure 320 is lower than the top surface of the gate spacer 260. However, in some other embodiments, the top surface of the replacement gate structure 320 may be flush with or higher than the top surface of the gate spacer 260. Furthermore, in some embodiments, the CESL 300 may be etched back during the etch-back of the replacement gate structure 320 and / or the gate spacer 260. In this case, the CESL 300 has a top edge lower than the top surface of the ILD layer 310.

[0096] Then, a gate metal cap 330 is formed on top of the replacement gate structure 320 using a suitable process such as CVD or ALD. By way of example and not limitation, the metal cap 330 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic percent fluorine impurities and more than 3 atomic percent chlorine impurities. Process details regarding the formation of the FFW have been discussed previously with respect to the gate metal cap 138, and therefore will not be repeated for the sake of brevity.

[0097] exist Figure 37 In this configuration, a gate dielectric cap 340 is formed over the gate metal cap 330 and the gate spacer 260. Because the top surface of the gate metal cap 330 is lower than the top surface of the gate spacer 260, each gate dielectric cap 340 has a stepped bottom surface, wherein the lower step contacts the top surface of the gate metal cap 330, and the upper step contacts the top surface of the gate spacer 260. The material and process details of the dielectric caps are similar to those of the previously discussed gate dielectric cap 142, and therefore will not be repeated for the sake of brevity.

[0098] exist Figure 38In this process, source / drain contacts 350 extending through CESL 300 and ILD layer 310 are formed. The formation of the source / drain contacts 350 includes, for example, but not limited to: performing one or more etching processes to form contact openings extending through ILD layer 310 and CESL 300 to expose the source / drain epitaxial structure 280; depositing one or more metal materials to overfill the contact openings; and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, one or more etching processes are selective etching processes that etch ILD layer 310 at a faster etch rate than etching dielectric cap 340 and gate spacer 260. As a result, this selective etching is performed using dielectric cap 340 and gate spacer 260 as etch masks, such that the contact openings (and therefore the source / drain contacts 350) are formed to be self-aligned with the source / drain epitaxial structure 280 without the need for additional photolithography processes. In this case, the source / drain contact 350 can be referred to as a self-aligned contact (SAC), and the dielectric cap 340 that allows the self-aligned contact 350 to be formed can be referred to as an SAC cap 340.

[0099] exist Figure 39 In the process, after forming the self-aligned source / drain contacts 350, an intermediate contact etch stop layer (MCESL) 360 is deposited over the source / drain contacts 350 and the SAC cap 340. Subsequently, another ILD layer 370 is deposited over the MCESL 360. In some embodiments, the MCESL 360 is silicon nitride, and the ILD layer 370 is silicon oxide (SiO2). x ).

[0100] refer to Figure 40The ILD layer 370 is patterned to form a gate contact opening O8 extending through the ILD layer 370 using a first etching process (also known as a contact etching process) ET5. The etching duration of the contact etching process ET5 is controlled to stop at approximately the bottom surface of the MCESL 360, but without penetrating the gate dielectric cap 340. Stopping the contact etching process ET5 before penetrating the gate dielectric cap 340 allows the sidewalls of the MCESL 360 to be oxidized in subsequent processes. In some embodiments, the ratio of the depth D8 of the contact opening O8 within the MCESL 360 (i.e., the recess depth created by the contact etching process ET5) to the total thickness T8 of the MCESL 360 and the underlying gate dielectric cap 340 is in the range of about 2:9 to about 7:9. If this ratio is too small, the oxidized sidewalls formed in subsequent processes may be too small to suppress lateral etching in subsequent LRM etching processes. If this ratio is too high, the MCESL 360, gate metal cap 330, and lower gate structure 320 may be over-etched. The process details of contact etching process ET5 are similar to those of contact etching process ET1 discussed earlier, so for the sake of brevity, they will not be repeated.

[0101] exist Figure 41 In the process described above, after the contact etching process ET5 is completed, the exposed portions of MCESL 360 and gate dielectric cap 340 are treated in an oxygen-containing environment. This oxidation of the surface layer of the exposed portions of MCESL 360 and gate dielectric cap 340 forms oxide regions 380 in MCESL 360 and gate dielectric cap 340, while leaving the remaining regions 3602 of MCESL 360 and gate dielectric cap 340 unoxidized. The treatment step may include O2 plasma treatment, in which oxygen-containing gas is introduced into the process chamber, where plasma is generated by the oxygen-containing gas. Process details regarding O2 plasma treatment are discussed earlier in the section on... Figure 16A The discussion has been conducted, so for the sake of brevity, these details will not be repeated.

[0102] As a result of O2 plasma treatment, oxidation occurs on the exposed top surface of the gate dielectric cap 340 and the exposed sidewalls of the MCESL 360, such that the oxidation region 380 has an oxidation bottom portion 380b and an oxidation sidewall portion 380s, the oxidation bottom portion 380b being in the corresponding gate dielectric cap 340, and the oxidation sidewall portion 380s extending upward from the oxidation bottom portion 380b into the MCESL 360 and laterally surrounding the oxidation bottom portion 380b.

[0103] In some embodiments, the oxide bottom portion 380b and the oxide sidewall portion 380s have the same thickness (e.g., in the range of about 1 nm to about 3 nm). In some other embodiments, the oxide sidewall portion 380s has a greater thickness than the oxide bottom portion 380b. For example, the thickness ratio of the oxide sidewall portion 380s to the oxide bottom portion 380b can be greater than about 1:1, 2:1, 3:1, 4:1, or 5:1. The thicker oxide sidewall portion 380s allows for higher etch resistance to subsequent LRM etching. The thinner oxide bottom portion 380b allows for a shorter LRM etching duration because the oxide bottom portion 380b will be removed during the LRM etching. In some embodiments, the oxide sidewall portion 380s has a thickness gradient from bottom to top. For example, the oxide sidewall portion 380s is thicker at the top and thinner at the bottom.

[0104] In some embodiments of the MCESL 360 made of SiN, O2 plasma treatment produces oxidized nitride regions (silicon oxynitride (SiO2)). x N y Oxidized nitride region 380, unoxidized nitride region 3402, and unoxidized region 3602 are defined, wherein oxidized nitride region 380 is located in MCESL 360 and below gate contact opening O8, unoxidized nitride region 3402 is cup-shaped in gate dielectric cap 340 to accommodate the bottom side of oxidized nitride region 380, and unoxidized region 3602 laterally surrounds oxidized region 380 in MCESL 360. In some embodiments, oxidized region 380 may have an oxygen concentration gradient due to plasma processing. For example, the percentage of oxygen atoms in oxidized region 380 may decrease with increasing distance from the surface of gate contact opening O8. More specifically, oxidized sidewall portion 380s has a percentage of oxygen atoms that decreases with increasing distance from the sidewall of gate contact opening O8, and oxidized bottom portion 380b has a percentage of oxygen atoms that decreases with increasing distance from the bottom surface of gate contact opening O8. In some embodiments where the MCESL 360 and the gate dielectric cap 340 are silicon nitride, the oxygen-to-nitrogen atomic ratio in the oxide region 380 may decrease with increasing distance from the surface of the gate contact opening O8. More specifically, the oxide sidewall portion 380s may have an oxygen-to-nitrogen atomic ratio that decreases with increasing distance from the sidewall of the gate contact opening O8, and the oxide bottom portion 380b may have an oxygen-to-nitrogen atomic ratio that decreases with increasing distance from the bottom surface of the gate contact opening O8.

[0105] refer to Figure 42AThe LRM etching process ET6 is performed to penetrate the MCESL 360 and the gate dielectric cap 340, thereby deepening the gate contact opening O8 to the gate metal cap 330 above the gate structure 320. As a result of the LRM etching process ET6, the gate metal cap 340 is exposed at the bottom of the deepened gate contact opening O8. The process details of the LRM etching process ET6 were discussed earlier regarding the LRM etching process ET2, so for the sake of brevity, these details will not be repeated here.

[0106] Because the oxide sidewall portions 380s suppress or slow down lateral etching during the LRM etching process ET6, the sidewalls O80 of the gate contact opening O8 extend linearly through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, and the entire thickness of the gate dielectric cap 340, with no bending or negligible bending. For example, the sidewalls O80 include an oxygen-containing portion O81 formed by the sidewalls of the ILD layer 370 and the oxide sidewall portions 380s, and an oxygen-free portion O82 formed by the unoxidized region 3402 of the gate dielectric cap 340, wherein the oxygen-free sidewalls O82 are aligned with the oxygen-containing sidewalls O81. However, in some other embodiments, the oxygen-free sidewalls O82 may be slightly laterally retracted from the oxygen-containing sidewalls O82 (as shown by dashed line DL5) because the LRM etching ET6 can cause more lateral etching in the unoxidized region 3402 than in the oxide sidewall portions 380s. Even in this case, the gate contact opening O8 still mitigates the bending defect compared to the case where no oxide sidewall portion 380s is formed, because the bending profile is confined below the oxide sidewall portion 380s.

[0107] In such Figure 42A In some of the depicted embodiments, the gate contact opening O8 has a tapered sidewall profile due to the anisotropic etching nature of the LRM etching process ET6. However, in some other embodiments, the etching conditions of the LRM etching process ET6 and / or the preceding contact etching process ET5 can be fine-tuned to allow the gate contact opening O8 to have a vertical sidewall profile, such as... Figure 42B As shown.

[0108] Next, in Figure 43A In this configuration, a gate contact 390 is subsequently formed in the gate contact opening O8 to be electrically connected to the gate structure 320 via a gate metal cap 330. The material and process details of the gate contact 390 are similar to those of the gate contact 150 discussed earlier, and therefore will not be repeated for the sake of brevity.

[0109] Gate contact 390 inherits the geometry of the substantially non-bent gate contact opening O8, and therefore gate contact 390 is also substantially non-bent. In other words, the sidewalls of gate contact 390 extend linearly through the entire thickness of ILD layer 370, the entire thickness of MCESL 360, and the entire thickness of gate dielectric cap 340, and there is no bending or the bending is negligible. More specifically, gate contact 390 forms an oxygen-containing interface 3901 with the oxide sidewall portions 380s in ILD layer 370 (i.e., SiO2 layer) and MCESL 360, and also forms an oxygen-free interface 3902 with the unoxidized region 3402 in gate dielectric cap 340, and the oxygen-free interface 3902 is aligned with the oxygen-containing interface 3901. However, in some other embodiments, the oxygen-free interface 3902 can be laterally retracted from the oxygen-containing interface 3901 (as shown by dashed line DL6) because, in the previous processing, the LRM etching process ET6 can cause more lateral etching in the unoxidized region 3402 in the gate dielectric cap 340 than in the oxide sidewall portion 380s in the lateral etching ratio MCESL 360. Even in this case, the gate contact 390 still mitigates bending defects compared to the case where no oxide sidewall portion 380s is formed, because the bending profile is confined below the oxide sidewall portion 380s.

[0110] In such Figure 43A In some of the depicted embodiments, the gate contact 390 has a tapered sidewall profile due to the anisotropic etching nature of the LRM etching process ET6. However, in some other embodiments, the etching conditions of the LRM etching process ET6 can be fine-tuned to allow the gate contact opening O8 (and thus the gate contact 390) to have a vertical sidewall profile, such as... Figure 43B As shown.

[0111] Figure 44-47 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure 200a according to some other embodiments of the present disclosure are shown. It should be understood that... Figure 44-47 Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of these operations / processes may be interchangeable. In the following embodiments, [the following text may be incomplete and requires further context]. Figure 25-43B The same or similar configurations, materials, processes and / or operations described herein may be omitted, and detailed descriptions may be omitted.

[0112] In the formation of such Figure 39 Following the structure shown, a contact etching process ET7 is performed to form a gate contact opening O9 extending downward through the ILD layer 370 but not through the MCESL 360. The resulting structure is... Figure 44As shown in the diagram. As a result of this contact etching process ET7, a recess R9 is formed below the corresponding gate contact opening O9, extending into the MCESL 360 but not through the entire thickness of the MCESL 360. In other words, the etching duration of the contact etching process ET7 is controlled to stop before the gate dielectric cap 340 is exposed. For example, the contact etching process ET7 may stop as soon as the MCESL 360 is exposed. The formation of the recess R9 allows the sidewalls of the MCESL 360 to be oxidized in subsequent processes, which in turn will suppress or slow down lateral etching in subsequent LRM etching, as described above. The process details of the contact etching process ET7 have been discussed above with respect to the contact etching process ET1, so for the sake of brevity, these details will not be repeated here.

[0113] exist Figure 45 In this process, the exposed portions of the MCESL 360 are treated in an oxygen-containing environment, causing the surface layer of the exposed portions of the MCESL 360 to be oxidized to form oxide regions 3603 in the MCESL 360, while leaving the remaining regions 3602 of the MCESL 360 unoxidized. The treatment steps may include O2 plasma treatment, in which oxygen-containing gas is introduced into a treatment chamber where plasma is generated by the oxygen-containing gas. Process details regarding O2 plasma treatment were previously discussed... Figure 16A The discussion has already taken place, so for the sake of brevity, these details will not be repeated here.

[0114] As a result of O2 plasma treatment, oxidation occurs in the bottom surface and sidewalls of the recess R9 in the MCESL 360, creating an oxide region 3603 having an oxide bottom portion 3603b and oxide sidewall portions 3603s, the sidewall portions 3603s extending upward from the oxide bottom portion 3603b and laterally surrounding it. In some embodiments, the oxide bottom portion 3603b and the oxide sidewall portions 3603s have the same thickness (e.g., in the range of about 1 nm to about 3 nm). In some other embodiments, the oxide sidewall portions 3603s have a greater thickness than the oxide bottom portion 3603b. The thicker oxide sidewall portions 3603s allow for higher etch resistance to subsequent LRM etching. The thinner oxide bottom 3603b allows for a shorter LRM etching duration. In some embodiments, the oxide sidewall portions 3603s have a thickness gradient from bottom to top. For example, the oxidized sidewall portion 1463s can be thicker at the top and thinner at the bottom.

[0115] In some embodiments, due to plasma processing, the oxide region 3603 may have an oxygen concentration gradient. For example, the percentage of oxygen atoms in the oxide region 3603 may decrease with increasing distance from the surface of the recess R9. More specifically, the oxide sidewall portions 3603s have a decreasing percentage of oxygen atoms with increasing distance from the sidewalls of the recess R9, and the oxide bottom portion 3603b has a decreasing percentage of oxygen atoms with increasing distance from the bottom surface of the recess R9. In some embodiments where the MCESL360 is silicon nitride, the oxygen-to-nitrogen ratio in the oxide region may decrease with increasing distance from the surface of the recess R9. More specifically, the oxygen-to-nitrogen ratio of the oxide sidewall portions 3603s may decrease with increasing distance from the sidewalls of the recess R9, and the oxygen-to-nitrogen ratio of the oxide bottom portion 3603b may decrease with increasing distance from the bottom surface of the recess R9.

[0116] exist Figure 46 In this process, LRM etching process ET8 is performed to penetrate MCESL 360 and the underlying gate dielectric cap 340, thereby deepening the gate contact opening O9 down to the gate metal cap 330. As a result of LRM etching process ET8, the gate metal cap 330 is exposed at the bottom of the deepened gate contact opening O9. Because the oxide sidewall portions 3603s suppress or slow down lateral etching during LRM etching process ET8, as discussed earlier, the sidewalls of the gate contact opening O9 extend linearly through the entire thickness of ILD layer 370, the entire thickness of MCESL 360, and the entire thickness of gate dielectric cap 340, without bending or with negligible bending. The process details of LRM etching process ET8 were discussed earlier regarding LRM etching process ET2, so for the sake of brevity, these details will not be repeated here.

[0117] exist Figure 47 In this configuration, a gate contact 390 is subsequently formed in the gate contact opening O9 to electrically connect through the gate metal cap 330 to the KHMG structure 320. Details regarding the materials and manufacturing process of the gate contact 390 are provided earlier in the section on... Figure 20A The details have already been described, so for the sake of brevity, they will not be repeated here.

[0118] exist Figure 47In the illustrated embodiment, the gate contacts 390 are substantially free of bending because they inherit the geometry of the gate contact opening O9. In other words, the sidewalls of the gate contacts 390 extend linearly through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, and the entire thickness of the gate dielectric cap 340, with no bending or negligible bending. More specifically, the gate contacts 390 form an oxygen-containing interface 3901 with the oxidized sidewall portions 3603s in the ILD layer 370 (i.e., the SiO2 layer) and the MCESL 360, and also form an oxygen-free interface 3902 with the unoxidized region 3602 in the MCESL 360 and the gate dielectric cap 340, and the oxygen-free interface 3902 is aligned with the oxygen-containing interface 3901, as shown below. Figure 47 As shown. However, in some other embodiments, the oxygen-free interface 3902 can be laterally retracted from the oxygen-containing interface 3901 (as shown by dashed line DL7) because the LRM etching process ET8 can cause more lateral etching in the unoxidized region 3602 and the unoxidized gate dielectric cap 340 in the MCESL 360 than in the oxide sidewall portion 3603s. Even in this case, the gate contact 390 still mitigates bending defects compared to the case where no oxide sidewall portion 3603s is formed, because the bending profile is confined below the oxide sidewall portion 3603s.

[0119] Based on the above discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor are specific advantages required for all embodiments. One advantage is that the bending profile of the gate contact opening and the gate dielectric cap in the MCESL can be reduced due to the additional oxygen plasma treatment. Another advantage is that the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact) can be reduced. Yet another advantage is that the resistance-capacitance (RC) delay can be improved because the distance from the unbent gate contact to the source / drain contact is greater than the distance from the bent gate contact to the source / drain contact.

[0120] In some embodiments, a method includes: forming a gate structure on a semiconductor substrate; forming an etch stop layer on the gate structure and forming an interlayer dielectric (ILD) layer on the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, such that sidewalls of the etch stop layer are exposed in the gate contact opening; oxidizing the exposed sidewalls of the etch stop layer; after oxidizing the exposed sidewalls of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening. In some embodiments, the sidewalls of the etch stop layer are oxidized using oxygen plasma. In some embodiments, the oxygen plasma is generated by O2 gas. In some embodiments, the oxygen plasma is generated by a mixture of O2 gas and one or more of the following gases: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z The gases include NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas, wherein x, y, and z are greater than 0 and not greater than 9. In some embodiments, the second etching process uses an etchant different from the etchant used in the first etching process. In some embodiments, the first etching process is a plasma etching process using plasma generated from a hydrogen-free gas mixture. In some embodiments, the second etching process is a plasma etching process using plasma generated from a hydrogen-containing gas mixture. In some embodiments, the hydrogen-containing gas mixture is a mixture of a fluorine-containing gas and hydrogen. In some embodiments, the fluorine-containing gas is CHF3 gas, CF4 gas, or a combination thereof. In some embodiments, the second etching process etches the oxidized sidewalls of the etch stop layer at a slower etching rate than etching the unoxidized regions of the etch stop layer.

[0121] In some embodiments, a method includes: forming a gate structure between gate spacers; sequentially depositing an etch stop layer and an interlayer dielectric (ILD) layer over the gate structure; performing a first etch process to form a gate contact opening in the ILD layer, at least until the etch stop layer is exposed; after performing the first etch process, performing an oxygen plasma treatment to form a treated region in the etch stop layer and around the bottom portion of the gate contact opening, while leaving the remaining region of the etch stop layer untreated; after performing the oxygen plasma treatment, performing a second etch process to extend the gate contact opening toward the gate structure, wherein, in the second etch process, the treated region of the etch stop layer has higher etch resistance than the untreated region of the etch stop layer; and after performing the second etch process, forming a gate contact in the gate contact opening. In some embodiments, the method further includes: etching back the gate structure to bring it down below the top of the gate spacer; forming a gate dielectric cap over the etched-back gate structure; and after forming the gate dielectric cap, forming a source / drain contact adjacent to the opposite side of the gate dielectric cap, wherein the etch stop layer is deposited over the source / drain contact and the gate dielectric cap, and the first etch process is performed to expose the gate dielectric cap. In some embodiments, the oxygen plasma treatment forms a processed region in the gate dielectric cap and forms an unprocessed region below the processed region in the gate dielectric cap. In some embodiments, the second etch process penetrates the gate dielectric cap, and the second etch process etches the processed region in the gate dielectric cap at a slower etch rate than etching the unprocessed region in the gate dielectric cap. In some embodiments, the method further includes: forming a gate metal cap over the etched-back gate structure before forming the gate dielectric cap, wherein the second etch process is performed to expose the gate metal cap. In some embodiments, the method further includes etching back the gate spacer, wherein the gate dielectric cap is also formed on the etched back gate spacer.

[0122] In some embodiments, a device includes: a gate structure on a substrate; an etch stop layer on the gate structure; an interlayer dielectric (ILD) layer on the etch stop layer; and a gate contact extending through the ILD layer and the etch stop layer to be electrically connected to the gate structure, wherein the etch stop layer has a first oxide region laterally surrounding the gate contact and a first unoxidized region laterally surrounding the first oxide region. In some embodiments, the device further includes: source / drain contacts on opposite sides of the gate structure; and a gate dielectric cap on the gate structure, having opposite sidewalls respectively contacting the source / drain contacts, wherein the gate contacts further extend through the gate dielectric cap, and the gate dielectric cap has a second oxide region laterally surrounding the gate contact and a second unoxidized region below the second oxide region. In some embodiments, the second oxide region of the gate dielectric cap extends continuously from the first oxide region of the etch stop layer and terminates before reaching the bottommost position of the gate contact. In some embodiments, the second unoxidized region of the gate dielectric cap contacts the gate contact.

[0123] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0124] Example 1. A method of manufacturing a semiconductor device, comprising: forming a gate structure on a semiconductor substrate; forming an etch stop layer on the gate structure and forming an interlayer dielectric (ILD) layer on the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, such that sidewalls of the etch stop layer are exposed in the gate contact opening; oxidizing the exposed sidewalls of the etch stop layer; after oxidizing the exposed sidewalls of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

[0125] Example 2. The method according to Example 1, wherein the sidewalls of the etch stop layer are oxidized using oxygen plasma.

[0126] Example 3. The method according to Example 2, wherein the oxygen plasma is generated by O2 gas.

[0127] Example 4. The method according to Example 2, wherein the oxygen plasma is generated by a mixture of O2 gas and one or more of the following gases: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z Gases, NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas, wherein x, y, and z are greater than 0 and not greater than 9.

[0128] Example 5. The method according to Example 1, wherein the second etching process uses an etchant different from the etchant used in the first etching process.

[0129] Example 6. The method according to Example 1, wherein the first etching process is a plasma etching process using plasma generated from a hydrogen-free gas mixture.

[0130] Example 7. The method according to Example 1, wherein the second etching process is a plasma etching process using plasma generated by a hydrogen-containing gas mixture.

[0131] Example 8. The method according to Example 7, wherein the hydrogen-containing gas mixture is a mixture of fluorine-containing gas and hydrogen.

[0132] Example 9. The method according to Example 8, wherein the fluorine-containing gas is CHF3 gas, CF4 gas, or a combination thereof.

[0133] Example 10. The method according to Example 1, wherein the second etching process etches the oxidized sidewalls of the etch stop layer at a slower etching rate than etching the unoxidized regions of the stop layer.

[0134] Example 11. A method of manufacturing a semiconductor device, comprising: forming a gate structure between gate spacers; sequentially depositing an etch stop layer and an interlayer dielectric (ILD) layer over the gate structure; performing a first etch process to form a gate contact opening in the ILD layer, at least until the etch stop layer is exposed; after performing the first etch process, performing an oxygen plasma treatment to form a treated region in the etch stop layer and around a bottom portion of the gate contact opening, while leaving the remaining region of the etch stop layer untreated; after performing the oxygen plasma treatment, performing a second etch process to extend the gate contact opening toward the gate structure, wherein, in the second etch process, the treated region of the etch stop layer has higher etch resistance than the untreated region of the etch stop layer; and after performing the second etch process, forming a gate contact in the gate contact opening.

[0135] Example 12. The method according to Example 11 further includes: etching back the gate structure to bring it down below the top of the gate spacer; forming a gate dielectric cap on the etched-back gate structure; and after forming the gate dielectric cap, forming a source / drain contact adjacent to the opposite side of the gate dielectric cap, wherein the etch stop layer is deposited on the source / drain contact and the gate dielectric cap, and the first etch process is performed such that the gate dielectric cap is exposed.

[0136] Example 13. The method according to Example 12, wherein the oxygen plasma treatment forms a treated region in the gate dielectric cap, and an untreated region is formed below the treated region in the gate dielectric cap.

[0137] Example 14. The method according to Example 13, wherein the second etching process penetrates the gate dielectric cap, and the second etching process etches the processed area in the gate dielectric cap at a slower etching rate than etching the unprocessed area in the gate dielectric cap.

[0138] Example 15. The method according to Example 12 further includes: forming a gate metal cap on an etched-back gate structure prior to forming a gate dielectric cap, wherein the second etching process is performed to expose the gate metal cap.

[0139] Example 16. The method according to Example 12 further includes: etching back the gate spacer, wherein the gate dielectric cap is also formed on the etched back gate spacer.

[0140] Example 17. A semiconductor device comprising: a gate structure on a substrate; an etch stop layer on the gate structure; an interlayer dielectric (ILD) layer on the etch stop layer; and a gate contact extending through the ILD layer and the etch stop layer to be electrically connected to the gate structure, wherein the etch stop layer has a first oxidized region laterally surrounding the gate contact and a first unoxidized region laterally surrounding the first oxidized region.

[0141] Example 18. The semiconductor device according to Example 17 further includes: source / drain contacts located on opposite sides of the gate structure; and a gate dielectric cap located above the gate structure and having opposite sidewalls that respectively contact the source / drain contacts, wherein the gate contacts further extend through the gate dielectric cap, and the gate dielectric cap has a second oxidized region laterally surrounding the gate contacts and a second unoxidized region located below the second oxidized region.

[0142] Example 19. The semiconductor device according to Example 18, wherein the second oxide region of the gate dielectric cap extends continuously from the first oxide region of the etch stop layer and terminates before reaching the bottommost position of the gate contact.

[0143] Example 20. The semiconductor device according to Example 18, wherein a second unoxidized region of the gate dielectric cap contacts the gate contact.

Claims

1. A method for manufacturing a semiconductor device, comprising: A gate structure is formed on a semiconductor substrate; An etch stop layer is formed on the gate structure, and an interlayer dielectric (ILD) layer is formed on the etch stop layer. A first etching process is performed to form a gate contact opening that extends through the ILD layer into the etch stop layer, such that the sidewalls of the etch stop layer are exposed in the gate contact opening; Oxidize the exposed sidewalls of the etch stop layer; After oxidizing the exposed sidewalls of the etch stop layer, a second etching process is performed to deepen the gate contact opening; as well as The gate contact is formed in the deepened gate contact opening.

2. The method according to claim 1, wherein, The sidewalls of the etch stop layer are oxidized using oxygen plasma.

3. The method according to claim 2, wherein, The oxygen plasma is generated by O2 gas.

4. The method according to claim 2, wherein, The oxygen plasma is generated by a mixture of O2 gas and one or more of the following gases: Ar, He, Ne, Kr, N2, CO, CO2, C x H y F z Gases, NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas, wherein x, y, and z are greater than 0 and not greater than 9.

5. The method according to claim 1, wherein, The second etching process uses an etchant different from the etchant used in the first etching process.

6. The method according to claim 1, wherein, The first etching process is a plasma etching process that uses plasma generated from a hydrogen-free gas mixture.

7. The method according to claim 1, wherein, The second etching process is a plasma etching process that uses plasma generated by a hydrogen-containing gas mixture.

8. The method according to claim 7, wherein, The hydrogen-containing gas mixture is a mixture of fluorine-containing gas and hydrogen.

9. The method according to claim 8, wherein, The fluorine-containing gas is CHF3 gas, CF4 gas, or a combination thereof.

10. The method according to claim 1, wherein, The second etching process etches the oxidized sidewalls of the etch stop layer at a slower etch rate than the etch rate used to etch the unoxidized regions of the stop layer.

11. A method for manufacturing a semiconductor device, comprising: A gate structure is formed between the gate spacers; An etch stop layer and an interlayer dielectric (ILD) layer are sequentially deposited on the gate structure; A first etching process is performed to form a gate contact opening in the ILD layer, at least until the etch stop layer is exposed; After performing the first etching process, an oxygen plasma treatment is performed to form a processing area in the etch stop layer and around the bottom portion of the gate contact opening, while leaving the remaining area of ​​the etch stop layer unprocessed. After performing the oxygen plasma treatment, a second etching process is performed to extend the gate contact opening toward the gate structure, wherein, in the second etching process, the treated area of ​​the etch stop layer has higher etch resistance than the untreated area of ​​the etch stop layer; as well as After performing the second etching process, a gate contact is formed in the gate contact opening.

12. The method of claim 11, further comprising: The gate structure is etched back to bring it down below the top of the gate spacer; A gate dielectric cap is formed on the etched-back gate structure; as well as After forming the gate dielectric cap, source / drain contacts are formed adjacent to the opposite side of the gate dielectric cap. The etch stop layer is deposited on the source / drain contacts and the gate dielectric cap, and the first etch process is performed to expose the gate dielectric cap.

13. The method according to claim 12, wherein, The oxygen plasma treatment forms a treated region in the gate dielectric cap, and an untreated region is formed below the treated region in the gate dielectric cap.

14. The method according to claim 13, wherein, The second etching process penetrates the gate dielectric cap, and the second etching process etches the processed area in the gate dielectric cap at a slower etching rate than etching the unprocessed area in the gate dielectric cap.

15. The method of claim 12, further comprising: Prior to forming the gate dielectric cap, a gate metal cap is formed on the etched-back gate structure, wherein the second etching process is performed to expose the gate metal cap.

16. The method of claim 12, further comprising: The gate spacer is etched back, wherein the gate dielectric cap is also formed on the etched back gate spacer.

17. A semiconductor device, comprising: The gate structure is located on the substrate; An etch stop layer is located above the gate structure; An interlayer dielectric (ILD) layer is located above the etch stop layer; as well as A gate contact extends through the ILD layer and the etch stop layer to be electrically connected to the gate structure, wherein the etch stop layer has a first oxidized region laterally surrounding the gate contact and a first unoxidized region laterally surrounding the first oxidized region.

18. The semiconductor device of claim 17, further comprising: The source / drain contacts are located on opposite sides of the gate structure; as well as A gate dielectric cap is located above the gate structure and has opposite sidewalls that respectively contact the source / drain contacts, wherein the gate contacts also extend through the gate dielectric cap, and the gate dielectric cap has a second oxidized region laterally surrounding the gate contacts and a second unoxidized region located below the second oxidized region.

19. The semiconductor device according to claim 18, wherein, The second oxide region of the gate dielectric cap extends continuously from the first oxide region of the etch stop layer and terminates before reaching the bottommost position of the gate contact.

20. The semiconductor device according to claim 18, wherein, The second unoxidized region of the gate dielectric cap is in contact with the gate contact.

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