Display device

Abstract

A display device is disclosed. The display device of the present invention includes: a pixel unit including a first pixel row and a second pixel row, the first pixel row being connected to a first scan line, and the second pixel row being alternately arranged with the first pixel row and connected to a second scan line; a scan driving unit including a first stage and a second stage, the first stage being connected to the first scan line, and the second stage being connected to the second scan line; and a data driving unit connected to the first pixel row and the second pixel row via the same data line, wherein the first stage is connected to a first clock line, the second stage is connected to a second clock line different from the first clock line, the first start stage in the first stage and the second start stage in the second stage are connected to the same scan start line, each first stage except the first start stage is connected to a first scan line connected to the previous first stage, and each second stage except the second start stage is connected to a second scan line connected to the previous second stage.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] With the development of information technology, the importance of display devices, as the connection medium between users and information, is becoming increasingly prominent. Therefore, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and plasma displays (Plasma displays) is increasing.

[0003] When displaying video on a display device, it is preferable to display at a high frequency to smoothly represent motion. However, when displaying still images, since there is no motion, displaying at a low frequency is acceptable. Furthermore, displaying at a low frequency is advantageous in terms of power consumption.

[0004] However, when the display frequency of the display device changes from a high frequency to a low frequency, there is a problem that flicker may be observed as the brightness decreases period. Summary of the Invention

[0005] The technical problem to be solved is to provide a display device that can prevent visible flickering when the display frequency changes from a high frequency to a low frequency.

[0006] A display device according to an embodiment of the present invention includes: a pixel unit including a first pixel row and a second pixel row, the first pixel row being connected to a first scan line, and the second pixel row being alternately arranged with the first pixel row and connected to a second scan line; a scan driving unit including a first stage and a second stage, the first stage being connected to the first scan line, and the second stage being connected to the second scan line; and a data driving unit connected to the first pixel row and the second pixel row via the same data line, wherein the first stage is connected to a first clock line, the second stage is connected to a second clock line different from the first clock line, a first start stage in the first stage and a second start stage in the second stage are connected to the same scan start line, each of the first stages except the first start stage is connected to a first scan line connected to the previous first stage, and each of the second stages except the second start stage is connected to a second scan line connected to the previous second stage.

[0007] During each first frame time period, the scan drive unit can alternately apply a scan signal with a conduction level to the first scan line and the second scan line.

[0008] During the first subframe time period in each second frame time period, the scan driving unit may apply a first scan signal with a conduction level to the first scan line and a second scan signal with a cutoff level to the second scan line. During the second subframe time period in each second frame time period, the scan driving unit may apply a second scan signal with a conduction level to the second scan line and a first scan signal with a cutoff level to the first scan line.

[0009] The second frame time period can be longer than the first frame time period.

[0010] The second frame time period can be an integer multiple of the first frame time period.

[0011] The display device may apply a first clock signal with a conduction level to the first clock line and a second clock signal with a conduction level to the second clock line during the first frame time period, wherein the first clock signal and the second clock signal may have different phases from each other.

[0012] The display device may apply a first clock signal with a conduction level to the first clock line and maintain a second clock signal with a cutoff level to the second clock line during the first subframe time period. During the second subframe time period, it may apply a second clock signal with a conduction level to the second clock line and maintain a first clock signal with a cutoff level to the first clock line.

[0013] The period of the first clock signal, which applies a conduction level to the first clock line, can be the same for both the first frame time period and the first subframe time period.

[0014] The period of the second clock signal, which applies a conduction level to the second clock line, can be the same for both the first frame time period and the second subframe time period.

[0015] The period of the first scan signal, which applies a conduction level to the first scan line, can be the same for both the first frame time period and the first subframe time period.

[0016] The period of the second scan signal, which applies a conduction level to the second scan line, can be the same for both the first frame time period and the second subframe time period.

[0017] The period of the first clock signal that applies a conduction level to the first clock line during the first subframe time period can be shorter than the period of the first clock signal that applies a conduction level to the first clock line during the first frame time period.

[0018] The period of the second clock signal that applies a conduction level to the second clock line during the second subframe time period can be shorter than the period of the second clock signal that applies a conduction level to the second clock line during the first frame time period.

[0019] The period of the first scan signal that applies a conduction level to the first scan line during the first subframe time period can be shorter than the period of the first scan signal that applies a conduction level to the first scan line during the first frame time period.

[0020] The period of the second scan signal that applies a conduction level to the second scan line during the second subframe time period can be shorter than the period of the second scan signal that applies a conduction level to the second scan line during the first frame time period.

[0021] The data driving unit can be turned off during at least a portion of the first subframe time period and the second subframe time period.

[0022] For the same color, the first data voltage supplied by the data driving unit to the first dot of the first pixel row during the first subframe time period and the second data voltage supplied to the second dot of the second pixel row adjacent to the first dot during the second subframe time period can be the same as each other, and each of the first dot and the second dot can include at least two pixels of different colors.

[0023] When adjacent first and second pixel rows do not display an edge, for the same color, the first data voltage supplied by the data driving unit to the first point of the first pixel row during the first subframe time period and the second data voltage supplied to the second point of the second pixel row adjacent to the first point during the second subframe time period can be the same as each other. When adjacent first and second pixel rows display an edge, for the same color, the first data voltage and the second data voltage can be different from each other, and each of the first point and the second point can include at least two pixels of different colors.

[0024] The display device may further include: a timing control unit that supplies control signals to the scanning drive unit and the data drive unit; the timing control unit includes: a frame memory that stores an input image; an edge enhancement unit that transforms the input image in a manner that emphasizes the edges of the input image; an edge detection unit that detects the edges of the transformed input image; and a common data generation unit that provides the same grayscale to the first point and the second point when adjacent first pixel rows and second pixel rows do not correspond to the detected edges, and provides the grayscale of the transformed input image to the first point and the second point when adjacent first pixel rows and second pixel rows correspond to the detected edges.

[0025] The timing control unit may further include a pattern detection unit, which generates pattern information regarding whether the converted input image corresponds to a pre-stored pattern. When the input image corresponds to the pattern, the display device may operate in a first display mode including the first frame time period. When the input image does not correspond to the pattern, the display device may operate in a second display mode including the second frame time period.

[0026] The display device according to the present invention can prevent flickering when the display frequency is switched from a high frequency to a low frequency. Attached Figure Description

[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0028] Figure 2 This is a diagram used to illustrate pixels according to an embodiment of the present invention.

[0029] Figure 3 This is a diagram illustrating a scanning drive unit according to an embodiment of the present invention.

[0030] Figure 4 This is a diagram illustrating a stage according to an embodiment of the present invention.

[0031] Figure 5 This is a diagram illustrating a driving method of a scanning driving unit according to an embodiment of the present invention.

[0032] Figures 6 to 9 This is a diagram used to illustrate the first frame time period and the second frame time period according to an embodiment of the present invention.

[0033] Figures 10 to 13 This is a diagram illustrating the first frame time period and the second frame time period according to another embodiment of the present invention.

[0034] Figure 14This is a diagram used to illustrate the first frame time period and the second frame time period according to another embodiment of the present invention.

[0035] Figure 15 This is a diagram illustrating the scanning drive unit according to another embodiment of the present invention.

[0036] Figure 16 This is a diagram illustrating a timing control unit according to an embodiment of the present invention.

[0037] Figure 17 This is a diagram illustrating a pixel portion according to an embodiment of the present invention.

[0038] Figure 18 This is a diagram illustrating the pixel portion according to another embodiment of the present invention.

[0039] Figures 19 to 21 This is a diagram illustrating the timing control unit according to another embodiment of the present invention. Detailed Implementation

[0040] Hereinafter, various embodiments of the invention will be described in detail with reference to the accompanying drawings in a manner that enables those skilled in the art to readily implement the invention. The invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0041] To clearly illustrate the invention, irrelevant details have been omitted, and the same reference numerals are used throughout the specification for the same or similar constituent elements. Therefore, the reference numerals described earlier may also be used in other figures.

[0042] Furthermore, for ease of explanation, the dimensions and thicknesses of the components shown in the accompanying drawings are arbitrarily illustrated; therefore, the present invention is not necessarily limited to what is shown in the figures. Thicknesses may be exaggerated to clearly represent multiple layers and regions in the drawings.

[0043] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0044] Reference Figure 1 According to an embodiment of the present invention, the display device 10 may include a timing control unit 11, a data driving unit 12, a scanning driving unit 13, and a pixel unit 14.

[0045] The timing control unit 11 can receive external input signals from an external processor. These external input signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data, etc. The vertical synchronization signal may include multiple pulses, and the time point at which each pulse is generated can indicate the end of the previous frame time period and the beginning of the current frame time period. The interval between adjacent pulses of the vertical synchronization signal can be equivalent to one frame time period. The horizontal synchronization signal may include multiple pulses, and the time point at which each pulse is generated can indicate the end of the previous horizontal period and the beginning of a new horizontal period. The interval between adjacent pulses of the horizontal synchronization signal can be equivalent to one horizontal time period. The data enable signal can indicate that RGB data is supplied during the horizontal time period. RGB data can be supplied in pixel rows during the horizontal time period in response to the data enable signal. The RGB data corresponding to one frame can be referred to as an input image. When the grayscale of consecutive input images is substantially the same, the timing control unit 11 can determine the consecutive input images as still images. When the gray levels of consecutive input images are substantially different, the timing control unit 11 can determine consecutive input images as moving images.

[0046] The data driving unit 12 can provide the pixels with data voltages corresponding to the grayscale of the input image. For example, the data driving unit 12 can sample the grayscale using a clock signal and apply the data voltages corresponding to the grayscale to the data lines DL1 to DLn in units of pixel rows. A pixel row can represent pixels connected to the same scan line. n can be an integer greater than 0.

[0047] The scan drive unit 13 can receive clock signals, scan start signals, etc. from the timing control unit 11 to generate scan signals that will be provided to scan lines SL1, SL2, SL3, ..., SLm. m can be an integer greater than 0.

[0048] The pixel unit 14 includes pixels. Each pixel PXij can be connected to a corresponding data line and scan line. i and j can be integers greater than 0. Pixel PXij can represent a pixel connected to the scan transistor and the i-th scan line and the j-th data line.

[0049] Figure 2 This is a diagram used to illustrate pixels according to an embodiment of the present invention.

[0050] The gate electrode of the first transistor T1 can be connected to the i-th scan line SLi, the first electrode can be connected to the j-th data line DLj, and the second electrode can be connected to the second electrode of the storage capacitor Cst. The first transistor T1 can be named a scan transistor.

[0051] The gate electrode of the second transistor T2 can be connected to the second electrode of the first transistor T1, the first electrode can be connected to the first power line ELVDDL, and the second electrode can be connected to the anode of the light-emitting diode LD. The second transistor T2 can be named the driving transistor.

[0052] The first electrode of the storage capacitor Cst can be connected to the first power line ELVDDL, and the second electrode can be connected to the gate electrode of the second transistor T2.

[0053] In a light-emitting diode (LD), the anode can be connected to the second electrode of the second transistor T2, and the cathode can be connected to the second power supply line ELVSSL. During the light-emitting period of the LD, the first power supply voltage applied to the first power supply line ELVDDL can be greater than the second power supply voltage applied to the second power supply line ELVSSL.

[0054] Although transistors T1 and T2 are shown here as P-type transistors, those skilled in the art can replace at least one transistor with an N-type transistor by inverting the phase of the signal.

[0055] If a scan signal with a conduction level (here, logic low) is applied through the scan line SL1, the first transistor T1 becomes turn-on. At this time, the data voltage applied to the data line DLj is stored in the storage capacitor Cst.

[0056] A drive current corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst flows between the first and second electrodes of the second transistor T2. Therefore, the light-emitting diode LD emits light with a brightness corresponding to the data voltage.

[0057] Next, if a scan signal with a cutoff level (here, a logic high level) is applied through the scan line SL1, the first transistor T1 is turned off, and the data line DLj is electrically disconnected from the second electrode of the storage capacitor Cst. Therefore, even if the data voltage of the data line DLj is changed, the voltage at the second electrode of the storage capacitor Cst will not change.

[0058] The embodiments can be applied not only to Figure 2 The pixel PXij can also be applied to pixels in other pixel circuits.

[0059] Figure 3This is a diagram illustrating a scanning drive unit according to an embodiment of the present invention.

[0060] The scan drive unit 13 may include a first stage ST1, ST3, ... connected to the first scan lines SL1, SL3, ... and a second stage ST2, ST4, ... connected to the second scan lines SL2, SL4, ...

[0061] The first scan lines SL1, SL3, ... can be connected to the first pixel row. For example, the first pixel row can be the odd-numbered pixel row. For example, the first scan lines SL1, SL3, ... can be the odd-numbered scan lines. For example, the first level ST1, ST3, ... can be the odd-numbered level.

[0062] The second scan lines SL2, SL4, ... can be connected to the second pixel row. For example, the second pixel row can be the even-numbered pixel row. For example, the second scan lines SL2, SL4, ... can be the even-numbered scan lines. For example, the second level ST2, ST4, ... can be the even-numbered level.

[0063] Each of stages ST1 to ST4 may include a first input terminal 1001, a second input terminal 1002, a third input terminal 1003, and an output terminal 1004. The first start stage ST1 of the first stages ST1, ST3, ... and the second start stage ST2 of the second stages ST2, ST4, ... can be connected to the same scan start line FLML. For example, the first input terminal 1001 of the first start stage ST1 and the first input terminal 1001 of the second start stage ST2 can be connected to the same scan start line FLML. The output terminal 1004 of the first start stage ST1 can be connected to the first scan line SL1, and the output terminal 1004 of the second start stage ST2 can be connected to the second scan line SL2.

[0064] Each first stage ST3, ... except for the first start stage ST1 can be connected to the first scan line connected to the previous first stage. Each second stage ST4, ... except for the second start stage ST2 can be connected to the second scan line connected to the previous second stage. For example, the first input terminal 1001 of the first stage ST3 can be connected to the first scan line SL1 of the first start stage ST1. And the first input terminal 1001 of the second stage ST4 can be connected to the second scan line SL2 of the second start stage ST2.

[0065] The first stage ST1, ST3, ... can be connected to the first clock lines CKL1, CKL3. The first clock lines CKL1, CKL3 can be alternately connected to the second input terminal 1002 and the third input terminal 1003 of the first stage ST1, ST3, ... The second stage ST2, ST4, ... can be connected to the second clock lines CKL2, CKL4, which are different from the first clock lines CKL1, CKL3. The second clock lines CKL2, CKL4 can be alternately connected to the second input terminal 1002 and the third input terminal 1003 of the second stage ST2, ST4, ...

[0066] Each of stages ST1 to ST4 can be connected to power supply line VHPL and power supply line VLPL. Here, the voltage of power supply line VHPL can be set to a cutoff level (gate cutoff voltage, logic high level). And, the voltage of power supply line VLPL can be set to a conduction level (gate conduction voltage, logic low level).

[0067] Although Figure 3 In one embodiment, the first start stage ST1 and the second start stage ST2 are connected to the same scan start line FLML, but in another embodiment, the first start stage ST1 and the second start stage ST2 may also be connected to different scan start lines.

[0068] Figure 4 This is a diagram illustrating a level according to an embodiment of the present invention.

[0069] exist Figure 4 For ease of explanation, the first starting stage ST1 and the first stage ST3 are shown in the diagram. (See reference...) Figure 4 The first start stage ST1 may include a first drive unit 1210, a second drive unit 1220, and an output unit (buffer) 1230.

[0070] The output unit 1230 controls the voltage supplied to the output terminal 1004 in accordance with the voltages of nodes NP1 and NP2. For this purpose, the output unit 1230 is equipped with transistors M5 and M6.

[0071] Transistor M5 is located between power line VHPL and output terminal 1004, and its gate electrode is connected to node NP1. Transistor M5 controls the connection between power line VHPL and output terminal 1004 in accordance with the voltage applied to node NP1.

[0072] Transistor M6 is located between output terminal 1004 and third input terminal 1003, with its gate electrode connected to node NP2. Transistor M6 controls the connection between output terminal 1004 and third input terminal 1003 in accordance with the voltage applied to node NP2. This output section 1230 is driven as a buffer. Additionally, transistors M5 and M6 can be configured using a structure where multiple transistors are connected in parallel.

[0073] The first drive unit 1210 controls the voltage of node NP3 in accordance with the signals supplied to the first input terminal 1001 to the third input terminal 1003. For this purpose, the first drive unit 1210 is equipped with transistors M2 to M4.

[0074] Transistor M2 is located between the first input terminal 1001 and node NP3, and its gate electrode is connected to the second input terminal 1002. Transistor M2 controls the connection between the first input terminal 1001 and node NP3 in accordance with the signal supplied to the second input terminal 1002.

[0075] Transistors M3 and M4 are connected in series between node NP3 and power line VHPL. Transistor M3 is located between transistor M4 and node NP3, and its gate electrode is connected to the third input terminal 1003. Transistor M3 controls the connection between transistor M4 and node NP3 in accordance with the signal supplied to the third input terminal 1003.

[0076] Transistor M4 is located between transistor M3 and the power line VHPL, and its gate electrode is connected to node NP1. The voltage of transistor M4 and node NP1 correspondingly controls the connection between transistor M3 and the power line VHPL.

[0077] The second drive unit 1220 controls the voltage of node NP1 in accordance with the voltage of the second input terminal 1002 and node NP3. For this purpose, the second drive unit 1220 is equipped with transistor M1, transistor M7, transistor M8, capacitor CP1, and capacitor CP2.

[0078] Capacitor CP1 is connected between node NP2 and output terminal 1004. This capacitor CP1 is charged with a voltage corresponding to the on and off states of transistor M6.

[0079] Capacitor CP2 is connected between node NP1 and power line VHPL. This capacitor CP2 is charged with the voltage applied to node NP1.

[0080] Transistor M7 is located between node NP1 and the second input terminal 1002, and its gate electrode is connected to node NP3. Transistor M7 controls the connection between node NP1 and the second input terminal 1002 in accordance with the voltage of node NP3.

[0081] Transistor M8 is located between node NP1 and power line VLPL, and its gate electrode is connected to the second input terminal 1002. The signal from transistor M8 and the second input terminal 1002 correspondingly controls the connection between node NP1 and power line VLPL.

[0082] Transistor M1 is located between nodes NP3 and NP2, and its gate electrode is connected to the power supply line VLPL. This transistor M1 maintains the electrical connection between nodes NP3 and NP2 while remaining in a conducting state. Additionally, the voltages of transistor M1 and node NP2 correspondingly limit the voltage drop at node NP3. In other words, even if the voltage at node NP2 drops below the voltage of the power supply line VLPL, the voltage at node NP3 will not drop below the voltage of the power supply line VLPL minus the threshold voltage of transistor M1.

[0083] Figure 5 This diagram illustrates a driving method for a scanning driving unit according to an embodiment of the present invention. Figure 5 In this document, the first starting level ST1 is used to explain the operation process for ease of explanation.

[0084] Reference Figure 5 The first clock signals CK1 and CK3 have a period of four horizontal time intervals of 4H, and are supplied in different horizontal time intervals from each other. In other words, the first clock signal CK3 is set to be a signal offset from the first clock signal CK1 by half a cycle (i.e., two horizontal time intervals). Furthermore, the scan start signal FLM supplied to the first input terminal 1001 can be supplied in a manner synchronized with the first clock signal CK1 supplied to the second input terminal 1002. One horizontal period 1H can correspond to the period of the pulse of the horizontal synchronization signal Hsync.

[0085] Supplying a specific signal indicates that the signal is at a conduction level (in this case, a logic low level). Interrupting the supply of a specific signal indicates that the signal is at a cutoff level (in this case, a logic high level).

[0086] Additionally, when a scan start signal (FLM) is supplied, the first input terminal 1001 can be set to a logic low level, and when no scan start signal (FLM) is supplied, the first input terminal 1001 can be set to a logic high level. Furthermore, when a clock signal is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to a logic low level, and when no clock signal is supplied, the second input terminal 1002 and the third input terminal 1003 can be set to a logic high level.

[0087] The detailed operation process is as follows: First, the scan start signal FLM is supplied synchronously with the first clock signal CK1.

[0088] If the first clock signal CK1 is supplied, transistors M2 and M8 are turned on. If transistor M2 is turned on, the first input terminal 1001 is electrically connected to node NP3. Here, since transistor M1 is set to the on state for most of the time, nodes NP2 and NP3 maintain an electrical connection.

[0089] If the first input terminal 1001 is electrically connected to node NP3, the voltage VNP3 of node NP3 and the voltage VNP2 of node NP2 are set to low level by the scan start signal FLM supplied to the first input terminal 1001. If the voltage VNP3 of node NP3 and the voltage VNP2 of node NP2 are set to low level, transistors M6 and M7 are turned on.

[0090] If transistor M6 is turned on, the third input terminal 1003 is electrically connected to the output terminal 1004. Here, the third input terminal 1003 is set to a high-level voltage (i.e., the first clock signal CK3 is not supplied), and accordingly, the high-level voltage is also output to the output terminal 1004. If transistor M7 is turned on, the second input terminal 1002 is electrically connected to node NP1. According to the first clock signal CK1 supplied to the second input terminal 1002, the voltage VNP1 of node NP1 is set to a low level.

[0091] Additionally, if the first clock signal CK1 is supplied, transistor M8 is turned on. If transistor M8 is turned on, the voltage of power line VLPL is supplied to node NP1. Here, the voltage of power line VLPL is set to the same (or similar) voltage as the low level of the first clock signal CK1, thereby node NP1 stably maintains a low voltage level.

[0092] If node NP1 is set to a low voltage, transistors M4 and M5 are turned on. If transistor M4 is turned on, the power supply line VHPL is electrically connected to transistor M3. Here, since transistor M3 is set to the off state, node NP3 maintains a stable low voltage even when transistor M4 is turned on. If transistor M5 is turned on, the voltage of the power supply line VHPL is supplied to output terminal 1004. Here, the voltage of the power supply line VHPL is set to the same (or similar) voltage as the high voltage supplied to the third input terminal 1003, therefore, output terminal 1004 maintains a stable high voltage.

[0093] Subsequently, the supply of the interrupt scan start signal FLM and the first clock signal CK1 is interrupted. If the supply of the first clock signal CK1 is interrupted, transistors M2 and M8 are turned off. At this time, transistors M6 and M7 are kept on in a corresponding state with respect to the voltage stored in capacitor CP1. That is, nodes NP2 and NP3 are kept at a low level by the voltage stored in capacitor CP1.

[0094] With transistor M6 on, output terminal 1004 and third input terminal 1003 remain electrically connected. With transistor M7 on, node NP1 and second input terminal 1002 remain electrically connected. Here, the voltage at second input terminal 1002 is set to a high level in response to an interruption in the supply of the first clock signal CK1, thereby setting node NP1 to a high level as well. If a high level voltage is supplied to node NP1, transistors M4 and M5 are turned off.

[0095] Subsequently, a first clock signal CK3 is supplied to the third input terminal 1003. At this time, since transistor M6 is set to the on state, the first clock signal CK3 supplied to the third input terminal 1003 is supplied to the output terminal 1004. In this case, the output terminal 1004 outputs the first clock signal CK3 as a scan signal SS1 with an on level to the first scan line SL1.

[0096] Furthermore, when the first clock signal CK3 is supplied to the output terminal 1004, the voltage of node NP2 drops to a voltage lower than the voltage of the power supply line VLPL due to the coupling of capacitor CP1. Therefore, transistor M6 stably maintains the on state.

[0097] Furthermore, even if the voltage of node NP2 drops, node NP3 can maintain the voltage of power line VLPL through transistor M1 (e.g., the voltage of power line VLPL minus the threshold voltage of transistor M1).

[0098] After outputting the first scan signal SS1, which is at the conduction level, to the first scan line SL1, the supply of the first clock signal CK3 is interrupted. If the supply of the first clock signal CK3 is interrupted, the output terminal 1004 outputs a high-level voltage. Furthermore, the voltage VNP2 at node NP2 rises approximately to the voltage of the power supply line VLPL, corresponding to the high-level voltage at the output terminal 1004.

[0099] Subsequently, a first clock signal CK1 is supplied. If the first clock signal CK1 is supplied, transistors M2 and M8 are turned on. If transistor M2 is turned on, the first input terminal 1001 is electrically connected to node NP3. At this time, the scan start signal FLM is not supplied to the first input terminal 1001; therefore, the voltage at the first input terminal 1001 is set to a high level. Therefore, if transistor M1 is turned on, nodes NP3 and NP2 are supplied with a high level voltage, while transistors M6 and M7 are turned off.

[0100] If transistor M8 is turned on, the voltage of power line VLPL is supplied to node NP1, thereby turning on transistors M4 and M5. If transistor M5 is turned on, the voltage of power line VHPL is supplied to output terminal 1004. Thereafter, transistors M4 and M5 remain in the on state corresponding to the voltage charged in capacitor CP2, thereby stably supplying the voltage of power line VHPL to output terminal 1004.

[0101] Additionally, transistor M3 is turned on when the first clock signal CK3 is supplied. At this time, since transistor M4 is set to the on state, the voltage of power line VHPL is supplied to nodes NP3 and NP2. In this case, transistors M6 and M7 remain stably in the off state.

[0102] The first stage ST3 receives the output signal (i.e., the scan signal) from the first start stage ST1 to synchronize with the first clock signal CK3. In this case, the first stage ST3 outputs a first scan signal SS3 with a conduction level to the first scan line SL3 to synchronize with the first clock signal CK1. The first stages ST1, ST3, ... repeat the above process and output scan signals with conduction levels to the first scan lines SL1, SL3, ... in sequence.

[0103] Figure 4 and Figure 5 The descriptions of the first-level ST1, ST3, ... can also be applied in the same way to the second-level ST2, ST4, ... Figure 4 and Figure 5 The level and its driving method are merely examples; other levels and their driving methods in the prior art can also be used to constitute embodiments of the present invention.

[0104] Figures 6 to 9 This is a diagram used to illustrate the first frame time period and the second frame time period according to an embodiment of the present invention.

[0105] The display device 10 can operate in a first display mode or a second display mode. The first display mode includes a plurality of first frame time periods FP1, and the second display mode includes a plurality of second frame time periods FP2. The second frame time period FP2 can be longer than the first frame time period FP1. For example, the second frame time period FP2 can be an integer multiple of the first frame time period FP1. For example, the second frame time period FP2 can be 2p times the first frame time period FP1, where p can be an integer greater than 0. Figure 6 In one embodiment, the second frame time period FP2 is twice the first frame time period FP1.

[0106] The first display mode displays input images (frames) at a high frequency, suitable for displaying video, while the second display mode displays input images at a low frequency, suitable for displaying still images. If a still image is detected while displaying video, the display device 10 can switch from the first display mode to the second display mode. Furthermore, if video is detected while displaying a still image, the display device 10 can switch from the second display mode to the first display mode.

[0107] Reference Figure 6 For ease of explanation, the description is based on the j-th data line DLj and pixels PX1j and PX2j. The first pixel PX1j is connected to the j-th data line DLj and the first scan line SL1. The first pixel PX1j belongs to the first pixel row. The second pixel PX2j is connected to the j-th data line DLj and the second scan line SL2. The second pixel PX2j belongs to the second pixel row.

[0108] Within each first frame time period FP1, the data driving unit 12 can sequentially apply data voltages corresponding to the first pixel row and the second pixel row to the data lines. For example, the data driving unit 12 can sequentially apply data voltages DT1, DT2, ..., DT(m-1), DTm to the j-th data line DLj. Assuming the first frame time period FP1 is 1 / 60 second, the first data voltage DT1 can be supplied to the first pixel PX1j at 60Hz. The first pixel PX1j can emit light at its highest brightness at the time when the first data voltage DT1 is applied, and its brightness may gradually decrease due to leakage current. (Refer to...) Figure 6 An illustrative example is shown of the brightness waveform of the first pixel PX1j corresponding to multiple first frame time periods FP1.

[0109] Each second frame time period FP2 can include a first subframe time period SFP1 and a second subframe time period SFP2. The lengths of the first subframe time period SFP1 and the second subframe time period SFP2 can be the same. For example, assuming the second frame time period FP2 is 1 / 30 of a second, then each of the first subframe time period SFP1 and the second subframe time period SFP2 can be 1 / 60 of a second.

[0110] In each first subframe time period SFP1, the data driving unit 12 can sequentially apply the data voltage corresponding to the first pixel row to the data lines. For example, the data driving unit 12 can sequentially apply the data voltages DT1, DT3, ..., DT(m-1) to the j-th data line DLj. In each second subframe time period SFP2, the data driving unit 12 can sequentially apply the data voltage corresponding to the second pixel row to the data lines. For example, the data driving unit 12 can sequentially apply the data voltages DT2, DT4, ..., DTm to the j-th data line DLj.

[0111] Accordingly, the first pixel PX1j can be supplied with a first data voltage DT1 at 30Hz. The first pixel PX1j can emit light at its highest brightness at the time when the first data voltage DT1 is applied, and its brightness may gradually decrease due to leakage current. (Refer to...) Figure 6 An exemplary illustration shows the brightness waveform of the first pixel PX1j corresponding to multiple second frame time periods FP2. Furthermore, the second pixel PX2j can be subjected to a second data voltage DT2 at 30Hz. The second pixel PX2j can emit light at its highest brightness at the time the second data voltage DT2 is applied, and its brightness may gradually decrease due to leakage current. (Refer to...) Figure 6 An illustrative example is shown of the brightness waveform of the second pixel PX2j corresponding to multiple second frame time periods FP2.

[0112] At this time, except in cases where the input image is a special pattern such as a horizontal stripe image, since the first pixel PX1j and the second pixel PX2j are arranged to be adjacent, the first data voltage DT1 and the second data voltage DT2 may usually be the same or similar to each other.

[0113] Because the time points when the first pixel PX1j has the highest brightness and the time points when the second pixel PX2j has the highest brightness are arranged alternately, the user can recognize the average brightness waveform AVG of the first pixel PX1j and the second pixel PX2j as 60Hz. Therefore, even when switching between the first display mode and the second display mode, flickering caused by the difference in brightness waveform can be prevented.

[0114] Reference Figure 7 The control signals in the first frame time period FP1 are shown as an example.

[0115] During the first frame time period FP1, the timing control unit 11 can apply first clock signals CK1 and CK3 with conduction levels to the first clock lines CKL1 and CKL3, and second clock signals CK2 and CK4 with conduction levels to the second clock lines CKL2 and CKL4. The first clock signals CK1 and CK3 and the second clock signals CK2 and CK4 can have different phases from each other. For example, the conduction level clock signals CK1, CK2, CK3, and CK4 can be supplied sequentially in the order of first clock line CKL1, second clock line CKL2, first clock line CKL3, and second clock line CKL4. For example, the period of each of the conduction level clock signals CK1, CK2, CK3, and CK4 can be four horizontal periods.

[0116] Furthermore, the timing control unit 11 can apply a scan start signal FLM with an on-level signal to the scan start line FLML. At this time, the length of the on-level scan start signal FLM can be set to overlap with the on-level first clock signal CK1 and the on-level second clock signal CK2. For example, the length of the on-level scan start signal FLM can be two horizontal cycles.

[0117] During the first frame time period FP1, the scan drive unit 13 can alternately apply scan signals SS1, SS2, SS3, SS4, ... with conduction level to the first scan lines SL1, SL3, ... and the second scan lines SL2, SL4, ...

[0118] Reference Figure 5 The driving method can generate a first scan signal SS1 at the conduction level corresponding to a first clock signal CK3 at the conduction level. Similarly, a second scan signal SS2 at the conduction level can be generated corresponding to a second clock signal CK4 at the conduction level. Likewise, a first scan signal SS3 at the conduction level can be generated corresponding to the first clock signal CK1 at the conduction level. And a second scan signal SS4 at the conduction level can be generated corresponding to a second clock signal CK2 at the conduction level.

[0119] The data driver unit 12 can supply data voltage in a manner synchronized with the scan signals SS1, SS2, SS3, SS4, ... at each conduction level. For example, the data driver unit 12 can supply data voltage in the current horizontal time period in accordance with the grayscale value latched by the data enable signal DE at the logic high level of the previous horizontal time period.

[0120] refer to Figure 8 The control signal for the first subframe time period SFP1 in the second frame time period FP2 is illustrated as an example.

[0121] During the first subframe time period SFP1, the timing control unit 11 can apply the first clock signals CK1 and CK3 with conduction levels to the first clock lines CKL1 and CKL3, and can maintain the second clock signals CK2 and CK4 with cutoff levels on the second clock lines CKL2 and CKL4. In both the first frame time period FP1 and the first subframe time period SFP1, the periods of the first clock signals CK1 and CK3 with conduction levels applied to the first clock lines CKL1 and CKL3 can be the same. For example, the period of each of the first clock signals CK1 and CK3 with conduction levels can be four horizontal periods.

[0122] Furthermore, the timing control unit 11 can apply a scan start signal FLM with an on-level signal to the scan start line FLML. At this time, the length of the on-level scan start signal FLM can be set to overlap with the on-level first clock signal CK1. For example, as shown in the figure, the length of the on-level scan start signal FLM can be two horizontal cycles, but it can also be set to one horizontal cycle.

[0123] During the first subframe time period SFP1, the scan drive unit 13 can apply scan signals SS1, SS3, ... with a conduction level to the first scan lines SL1, SL3, ... and can maintain scan signals SS2, SS4, ... with a cutoff level to the second scan lines SL2, SL4, ... . The periods of the first scan signals SS1, SS3, ... that apply a conduction level to the first scan lines SL1, SL3, ... can be the same for both the first frame time period FP1 and the first subframe time period SFP1.

[0124] The data driving unit 12 can supply data voltage in a manner synchronized with the first scan signals SS1, SS3, ... for each conduction level. Since it is not necessary to supply data voltage in a manner synchronized with the second scan signals SS2, SS4, ..., the period of the data enable signal DE for the conduction level in the first subframe time period SFP1 can be longer than the period of the data enable signal DE for the conduction level in the first frame time period FP1. Accordingly, since the period at which the data driving unit 12 changes the data voltage is increased, it has the advantage of reduced dynamic power of the data driving unit 12.

[0125] refer to Figure 9 An example is shown of the control signals in the second subframe time period SFP2 of the second frame time period FP2.

[0126] During the second subframe time period SFP2, second clock signals CK2 and CK4 with on-level can be applied to the second clock lines CKL2 and CKL4, while first clock signals CK1 and CK3 with off-level can be maintained on the first clock lines CKL1 and CKL3. The periods of the second clock signals CK2 and CK4 with on-level applied to the second clock lines CKL2 and CKL4 can be identical. For example, the period of each of the on-level second clock signals CK2 and CK4 can be four horizontal periods.

[0127] Furthermore, the timing control unit 11 can apply a scan start signal FLM with a conduction level to the scan start line FLML. At this time, the length of the scan start signal FLM with a conduction level can be set to overlap with the second clock signal CK2 with a conduction level. For example, as shown in the figure, the length of the scan start signal FLM with a conduction level can be two horizontal cycles, but it can also be set to one horizontal cycle.

[0128] During the second subframe time period SFP2, the scan drive unit 13 can apply second scan signals SS2, SS4, ... with a conduction level to the second scan lines SL2, SL4, ... and maintain first scan signals SS1, SS3, ... with a cutoff level to the first scan lines SL1, SL3, ... . The periods of the second scan signals SS2, SS4, ... that apply a conduction level to the second scan lines SL2, SL4, ... can be the same for each other during the first frame time period FP1 and the second subframe time period SFP2.

[0129] The data driving unit 12 can supply data voltage in a manner synchronized with the second scan signals SS2, SS4, ... at each conduction level. Since it is not necessary to supply data voltage in a manner synchronized with the first scan signals SS1, SS3, ..., the period of the data enable signal DE at the conduction level in the second subframe time period SFP2 can be longer than the period of the data enable signal DE at the conduction level in the first frame time period FP1. Accordingly, since the period at which the data driving unit 12 changes the data voltage is increased, it has the advantage of reduced dynamic power of the data driving unit 12.

[0130] Figures 10 to 13 This is a diagram illustrating the first frame time period and the second frame time period according to another embodiment of the present invention.

[0131] exist Figure 10 In the embodiment, the brightness waveform and driving method of the first pixel PX1j in the first frame time period FP1 are similar to those of the first pixel PX1j in the first frame time period FP1. Figure 6 The situation is the same. Furthermore, in Figure 10In the embodiment, the brightness waveforms and average brightness waveforms AVG of the first pixel PX1j and the second pixel PX2j in the second frame time period FP2' are compared with... Figure 6 The situation is the same.

[0132] However, Figure 10 The driving method for the second frame time period FP2' in the embodiment and Figure 6 The embodiment differs in that each of the first subframe time period SFP1' and the second subframe time period SFP2' includes a data blank period (BPC). For example, the length of each of the first subframe time period SFP1' and the second subframe time period SFP2' can be the same as the length of each of the first subframe time period SFP1 and the second subframe time period SFP2, and... Figure 10 In this embodiment, the data driving unit 12 can be compared to Figure 6 In cases where the data voltage is supplied for a short period, the data blank period (BPC) can be the remaining time period after the data driver 12 ends the data voltage supply in each of the first subframe period (SFP1') and the second subframe period (SFP2'). During the data blank period (BPC), all or at least a portion of the data driver 12 (gamma amplifier, digital logic) can be turned off, thereby reducing power consumption.

[0133] Reference Figure 11 The example illustrates the control signals during the first subframe time period SFP1' of the second frame time period FP2'. Specifically, Figure 11 The control signals for the period other than the data blank period BPC are shown in the first subframe time period SFP1'.

[0134] During the first subframe time period SFP1', the timing control unit 11 can apply first clock signals CK1 and CK3 with conduction levels to the first clock lines CKL1 and CKL3, and can maintain second clock signals CK2 and CK4 with cutoff levels on the second clock lines CKL2 and CKL4. In this embodiment, the period of the first clock signals CK1 and CK3 with conduction levels applied to the first clock lines CKL1 and CKL3 during the first subframe time period SFP1' can be shorter than the period of the first clock signals CK1 and CK3 with conduction levels applied to the first clock lines CKL1 and CKL3 during the first frame time period FP1. For example, the period of each of the first clock signals CK1 and CK3 with conduction levels can be two horizontal periods.

[0135] The timing control unit 11 can apply a scan start signal FLM with a conduction level to the scan start line FLML. At this time, the length of the scan start signal FLM with a conduction level can be set to overlap with the first clock signal CK1 with a conduction level. For example, the length of the scan start signal FLM with a conduction level can also be set to one horizontal period.

[0136] During the first subframe time period SFP1', the scan drive unit 13 can apply scan signals SS1, SS3, ... with a conduction level to the first scan lines SL1, SL3, ... and can maintain scan signals SS2, SS4, ... with a cutoff level to the second scan lines SL2, SL4, ... The period of the first scan signals SS1, SS3, ... applying a conduction level to the first scan lines SL1, SL3, ... during the first subframe time period SFP1' can be shorter than the period of the first scan signals SS1, SS3, ... applying a conduction level to the first scan lines SL1, SL3, ... during the first frame time period FP1.

[0137] The data drive unit 12 can supply data voltage in a manner synchronized with the first scan signals SS1, SS3, ... at each conduction level.

[0138] Reference Figure 12 The example illustrates the control signals for the data blank time period BPC during the second frame time period FP2'. During the data blank time period BPC, clock signals CK1, CK2, CK3, CK4, scan signals SS1, SS2, SS3, SS4, ... and scan start signal FLM at the cutoff level can be maintained.

[0139] As mentioned earlier, during the data blank period BPC, all or at least a portion of the data drive unit 12 (gamma amplifier, digital logic) can be turned off, thereby reducing power consumption.

[0140] refer to Figure 13 The control signals for the second subframe time period SFP2' within the second frame time period FP2' are illustrated exemplarily. Specifically, Figure 13 The control signals for the time periods other than the data blank time period BPC are shown in the second subframe time period SFP2'.

[0141] During the second subframe time period SFP2', second clock signals CK2 and CK4 with on-state levels can be applied to the second clock lines CKL2 and CKL4, while first clock signals CK1 and CK3 with off-state levels can be maintained on the first clock lines CKL1 and CKL3. The period of the second clock signals CK2 and CK4 with on-state levels applied to the second clock lines CKL2 and CKL4 during the second subframe time period SFP2' can be shorter than the period of the second clock signals CK2 and CK4 with on-state levels applied to the second clock lines CKL2 and CKL4 during the first frame time period FP1. For example, the period of each of the on-state second clock signals CK2 and CK4 can be two horizontal periods.

[0142] Furthermore, the timing control unit 11 can apply a scan start signal FLM with a conduction level to the scan start line FLML. At this time, the length of the scan start signal FLM with a conduction level can be set to overlap with the second clock signal CK2 with a conduction level. For example, the length of the scan start signal FLM with a conduction level can be set to one horizontal period.

[0143] During the second subframe time period SFP2', the scan drive unit 13 can apply second scan signals SS2, SS4, ... with a conduction level to the second scan lines SL2, SL4, ... and can maintain first scan signals SS1, SS3, ... with a cutoff level to the first scan lines SL1, SL3, ... . The period of the second scan signals SS2, SS4, ... applying a conduction level to the second scan lines SL2, SL4, ... during the second subframe time period SFP2' can be shorter than the period of the second scan signals SS2, SS4, ... applying a conduction level to the second scan lines SL2, SL4, ... during the first frame time period FP1.

[0144] The data drive unit 12 can supply data voltage in a manner synchronized with the second scan signals SS2, SS4, ... at each conduction level.

[0145] Figure 14 This is a diagram used to illustrate the first frame time period and the second frame time period according to another embodiment of the present invention.

[0146] exist Figure 14 In the embodiment, the brightness waveform and driving method of the first pixel PX1j in the first frame time period FP1 are similar to those of the first pixel PX1j in the first frame time period FP1. Figure 6 The situation is the same.

[0147] Although Figure 14 The driving method of the second frame time period FP2" and Figure 10The situation is similar, but the difference lies in that each second frame time period FP2" includes four subframe time periods SFP1", SFP2", SFP3", and SFP4". For example, the second frame time period FP2" is four times the first frame time period FP1, which can be 1 / 15 of a second. For example, each of the subframe time periods SFP1", SFP2", SFP3", and SFP4" can be 1 / 60 of a second.

[0148] Although Figure 10 In one embodiment, two rows of pixels form a group, but... Figure 14 In this embodiment, four adjacent pixel rows form a group, and there are differences in this respect. The first pixel PX1j of the first pixel row can receive the data voltage SF1D during the first subframe time period SFP1" and emit light at its highest brightness. The second pixel PX2j of the second pixel row can receive the data voltage SF2D during the second subframe time period SFP2" and emit light at its highest brightness. The third pixel PX3j of the third pixel row can receive the data voltage SF3D during the third subframe time period SFP3" and emit light at its highest brightness. The fourth pixel PX4j of the fourth pixel row can receive the data voltage SF4D during the fourth subframe time period SFP4" and emit light at its highest brightness. Therefore, even if each of pixels PX1j, PX2j, PX3j, and PX4j emits light at 15Hz, the average brightness waveform AVG of the group of pixels PX1j, PX2j, PX3j, and PX4j can be identified as 60Hz.

[0149] Reference Figure 10 and Figure 14 The number of subframe time periods SFP1" to SFP4" included in the second frame time period FP2" can be set in various ways.

[0150] Figure 15 This is a diagram illustrating the scanning drive unit according to another embodiment of the present invention.

[0151] Figure 15 The scan driver unit 13" is for application Figure 14 The driving method and for Figure 3 The scan drive unit 13 has been modified in part. The internal circuit configuration of the scan drive unit 13" and the stages ST1 to ST4 of the scan drive unit 13 can be the same.

[0152] However, compared to being divided into two groups (the odd-numbered level and the even-numbered level) Figure 3 The scan drive unit 13 is different. Figure 15The scan drive unit 13" can be divided into four groups. For example, the first group can include the 4q+1th group ST1, ..., and each group ST1, ... can be alternately connected to clock lines CKL1, CKL5. Here, q can be an integer equal to or greater than 0. The second group can include the 4q+2th group ST2, ..., and each group ST2, ... can be alternately connected to clock lines CKL2, CKL6. The third group can include the 4q+3th group ST3, ..., and each group ST3, ... can be alternately connected to clock lines CKL3, CKL7. The fourth group can include the 4q+4th group ST4, ..., and each group ST4, ... can be alternately connected to clock lines CKL4, CKL8.

[0153] The first input terminals 1001 of the first stages ST1, ST2, ST3, and ST4 of each group can be connected to the scan start line FLML. Since the driving method of the scan drive unit 13" is similar to that of the scan drive unit 13, it will not be described again.

[0154] Figure 16 This is a diagram illustrating a timing control unit according to an embodiment of the present invention. Figure 17 This is a diagram illustrating a pixel portion according to an embodiment of the present invention. Figure 18 This is a diagram illustrating the pixel portion according to another embodiment of the present invention.

[0155] Reference Figure 16 According to an embodiment of the present invention, the timing control unit 11a may include a frame memory 111 and a common data generation unit 112a. The common data generation unit 112a can be used when the display device 10 is in a second display mode. When the display device 10 is in a first display mode, the common data generation unit 112a may not be used, and first line data OLD is used for the first pixel row, and second line data ELD is used for the second pixel row. Hereinafter, the display device 10 will be driven in the second display mode.

[0156] Reference Figure 17 An exemplary pixel section 14 with a pentile structure is shown. For example, pixel section 14 may include: a first pixel row connected to first scan lines SL1, ...; and a second pixel row arranged alternately with the first pixel row and connected to second scan lines SL2, ... Each first pixel row may include a first dot DT1, and each second pixel row may include a second dot DT2. A dot may include at least two pixels of different colors. A dot may be a display unit for displaying combined colors. An external processor may provide grayscale in units of dots.

[0157] The first point DT1 in the first pixel row can include red pixel PX11, green pixel PX12, blue pixel PX13, and green pixel PX14. The second point DT2 in the second pixel row can include blue pixel PX21, green pixel PX22, red pixel PX23, and green pixel PX24. In this case, the most adjacent first point DT1 and second point DT2 in the first and second pixel rows can be referred to as a pair of dots. Here, the adjacency of pixels can be determined based on whether the light-emitting surfaces of their LEDs are adjacent.

[0158] Reference Figure 18 An illustrative example shows a pixel portion 14' of an RGB stripe structure. The first point DT1' may include a red pixel PX11', a green pixel PX12', and a blue pixel PX13'. The first point DT3' may include a red pixel PX14', a green pixel PX15', and a blue pixel PX16'. The second point DT2' may include a red pixel PX21', a green pixel PX22', and a blue pixel PX23'. The second point DT4' may include a red pixel PX24', a green pixel PX25', and a blue pixel PX26'. The adjacent first point DT1' and second point DT2' can form one point pair, and the adjacent first point DT3' and second point DT4' can form another point pair. Hereinafter, for ease of explanation, based on... Figure 17 The pixel part 14 will be explained.

[0159] Frame memory 111 can store the input image IMG1. For example, frame memory 111 can store grayscale values ​​corresponding to at least one frame time period. Frame memory 111 can provide first line data OLD for a first point DT1 of a first pixel row and second line data ELD for a second point DT2 of a second pixel row.

[0160] The common data generation unit 112a can provide common line data CLD for the first point DT1 and the second point DT2. For example, the common line data CLD can be generated based on the first line data OLD and the second line data ELD. For example, the common line data CLD can be the average or median value of the first line data OLD and the second line data ELD. In the common line data CLD, the first point DT1 and the second point DT2 of each point pair can have the same grayscale for the same color.

[0161] The data driving unit 12 can supply a first data voltage to a first point in the first pixel row during a first subframe time period. Furthermore, the data driving unit 12 can supply a second data voltage to a second point in the second pixel row adjacent to the first point during a second subframe time period. In this case, the first data voltage and the second data voltage can be based on the common line data (CLD). Accordingly, for the same color, the first data voltage and the second data voltage can be the same. For example, the same data voltage can be supplied to the first red pixel PX11 and the second red pixel PX23, the same data voltage can be supplied to the first green pixel PX12 and the second green pixel PX22, the same data voltage can be supplied to the first blue pixel PX13 and the second blue pixel PX21, and the same data voltage can be supplied to the first green pixel PX14 and the second green pixel PX24.

[0162] According to this embodiment, the average brightness waveform AVG can be prevented from changing drastically during the second frame time period by supplying the same data voltage to the point pairs of adjacent pixel rows.

[0163] Figures 19 to 21 This is a diagram illustrating the timing control unit according to another embodiment of the present invention.

[0164] Reference Figure 19 The timing control unit 11b may also include an edge detection unit 113 in addition to the timing control unit 11a.

[0165] The edge detection unit 113 can detect edges of the input image IMG1 stored in the frame memory 111. An edge can be a region in the input image IMG1 where the grayscale changes abruptly (such as a border). For example, when the difference between the grayscale of a first pixel row and the grayscale of an adjacent second pixel row is above a reference value, it can be determined that the first and second pixel rows correspond to an edge. The edge detection unit 113 can generate edge information EDI based on the detected edges.

[0166] In cases where adjacent first pixel rows and second pixel rows do not correspond to the detected edge, the common data generation unit 112b can provide the same grayscale (e.g., common line data CLD) to the first point DT1 and the second point DT2. Accordingly, when adjacent first pixel rows and second pixel rows do not display an edge, for the same color, the first data voltage supplied by the data driving unit 12 to the first point DT1 of the first pixel row during the first subframe time period and the second data voltage supplied to the second point DT2 of the second pixel row adjacent to the first point DT1 during the second subframe time period can be the same for each other.

[0167] Furthermore, when adjacent first and second pixel rows correspond to detected edges, the common data generation unit 112b can provide the grayscale of the input image IMG1 to the first point DT1 and the second point DT2. That is, the common data generation unit 112b can provide first line data OLD to the first point DT1 and second line data ELD to the second point DT2. Accordingly, when edges are displayed in adjacent first and second pixel rows, the first data voltage and the second data voltage may be different for the same color. This can prevent image edge blurring.

[0168] Reference Figure 20 The timing control unit 11b' may further include an edge enhancement unit 114 based on the timing control unit 11b.

[0169] The edge enhancement unit 114 can transform the input image IMG1 in a way that emphasizes the edges of the input image IMG1. Accordingly, edge blurring caused by the common line data CLD can be compensated in advance. When adjacent first pixel rows and adjacent second pixel rows correspond to the detected edges, the common data generation unit 112b can provide the grayscale of the input image IMG1 transformed by the edge enhancement unit 114 to the first point DT1 and the second point DT2.

[0170] Reference Figure 21 The timing control unit 11c may also include a pattern detection unit 115 based on the timing control unit 11b'.

[0171] The pattern detection unit 115 can generate pattern information PTI regarding whether the converted input image IMG1 corresponds to a pre-stored pattern. The pre-stored pattern can be the worst pattern, such as a horizontal stripe pattern.

[0172] When the converted input image IMG1 corresponds to a pre-stored pattern, the display device 10 can operate in a first display mode that includes a first frame time period. Furthermore, when the converted input image IMG1 does not correspond to a pre-stored pattern, the display device 10 can operate in a second display mode that includes a second frame time period.

[0173] Accordingly, for the worst pattern in which flickering worsens when the second display mode of the embodiment of the present invention is applied, the display device 10 can be driven in the first mode.

[0174] The accompanying drawings and detailed description of the invention described above are merely examples of the present invention and are intended to illustrate the purpose of the invention only. They are not intended to limit the meaning or scope of the invention as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments exist. Consequently, the true scope of protection of the present invention should be determined by the technical concept outlined in the claims.

Claims

1. A display device comprising: a pixel portion including a first pixel row and a second pixel row, the first pixel row being connected to a first scan line, the second pixel row being arranged alternately with the first pixel row and being connected to a second scan line; a scan driving portion including a first stage and a second stage, the first stage being connected to the first scan line, the second stage being connected to the second scan line; and a data driving portion being connected to the first pixel row and the second pixel row through a same data line, wherein the first stage is connected to a first clock line, the second stage is connected to a second clock line different from the first clock line, a first start stage in the first stage and a second start stage in the second stage are connected to a same scan start line, each of the first stage except the first start stage is connected to a first scan line connected to a previous first stage, each of the second stage except the second start stage is connected to a second scan line connected to a previous second stage, during each of a first frame period, the scan driving portion applies a scan signal of an on level to the first scan line and the second scan line alternately in turn, the display device operating at a first frequency during the first frame period, during a first sub-frame period in each of a second frame period, the scan driving portion applies a scan signal of an on level to the first scan line in turn and maintains a scan signal of an off level to the second scan line, applies a first clock signal of an on level to the first clock line and maintains a second clock signal of an off level to the second clock line, the display device operating at a second frequency lower than the first frequency during the second frame period, during a second sub-frame period in each of the second frame period, the scan driving portion applies a scan signal of an on level to the second scan line in turn and maintains a first scan signal of an off level to the first scan line, applies the second clock signal of an on level to the second clock line and maintains the first clock signal of an off level to the first clock line, the second sub-frame period starting after the first sub-frame period ends during the second frame period, the scan start line receives a scan start signal in the first sub-frame period and the second sub-frame period respectively, a period in which the scan signal of the on level is applied to the first scan line in the first sub-frame period of each of the second frame period in which the display device operates at the second frequency is shorter than a period in which the scan signal of the on level is applied to the first scan line in each of the first frame period in which the display device operates at the first frequency.

2. The display device according to claim 1, wherein the second frame period is longer than the first frame period.

3. The display device according to claim 2, wherein the second frame period is an integer multiple of the first frame period.

4. The display device according to claim 1, wherein A first clock signal with an on level is applied to the first clock line during the first frame time period, and a second clock signal with an on level is applied to the second clock line. The first clock signal and the second clock signal have different phases.

5. The display device as claimed in claim 1, wherein, The period of the first clock signal that applies a conduction level to the first clock line during the first subframe time period is shorter than the period of the first clock signal that applies a conduction level to the first clock line during the first frame time period.

6. The display device as claimed in claim 5, wherein, The period of the second clock signal that applies a conduction level to the second clock line during the second subframe time period is shorter than the period of the second clock signal that applies a conduction level to the second clock line during the first frame time period.

7. The display device as claimed in claim 6, wherein, The period of the scan signal that applies the conduction level to the second scan line during the second subframe time period is shorter than the period of the scan signal that applies the conduction level to the second scan line during the first frame time period.

8. The display device as claimed in claim 6, wherein, The data driving unit is turned off during at least a portion of the first subframe time period and the second subframe time period.

9. The display device as claimed in claim 1, wherein, For the same color, the first data voltage supplied by the data driving unit to the first point of the first pixel row during the first subframe time period and the second data voltage supplied to the second point of the second pixel row adjacent to the first point during the second subframe time period are the same. Each of the first and second points comprises at least two pixels of different colors.

10. The display device as claimed in claim 1, wherein, When no edges are displayed between adjacent first and second pixel rows, for the same color, the first data voltage supplied by the data driving unit to the first point of the first pixel row during the first subframe time period and the second data voltage supplied to the second point of the second pixel row adjacent to the first point during the second subframe time period are the same. When adjacent first and second pixel rows are displayed at edges, for the same color, the first data voltage and the second data voltage are different from each other. Each of the first and second points comprises at least two pixels of different colors.

11. The display device of claim 10, further comprising: The timing control unit supplies control signals to the scan drive unit and the data drive unit. The timing control unit includes: Frame buffer, used to store input images; An edge enhancement section transforms the input image in a manner that emphasizes the edges of the input image; An edge detection unit detects the edges of the transformed input image; and The common data generation section provides the same gray scale to the first point and the second point in a case where the adjacent first pixel row and the second pixel row do not correspond to the detected edge, and provides the converted gray scale of the input image to the first point and the second point in a case where the adjacent first pixel row and the second pixel row correspond to the detected edge.

12. The display device according to claim 11, wherein The timing control section further includes a pattern detection section that generates pattern information on whether the converted input image corresponds to a pattern stored in advance, In a case where the input image corresponds to the pattern, the display device operates in a first display mode including the first frame period, In a case where the input image does not correspond to the pattern, the display device operates in a second display mode including the second frame period.

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