Array substrate, display panel and display device

Abstract

The present application discloses an array substrate, a display panel and a display device. The array substrate includes a substrate and a plurality of bearing insulating layers, which are stacked and formed on one side of the substrate. A patterned device forming layer is formed on the surface of each bearing insulating layer facing away from the substrate. The bearing insulating layer is an inorganic material layer. A flattening layer is provided on the surface of at least one bearing insulating layer facing the substrate to flatten the bearing insulating layer. The surface of the flattening layer facing away from the substrate is a plane. The flattening layer is an organic material layer. The present application provides an array substrate that flattens the bearing insulating layer by providing a flattening layer to avoid stress concentration at the step of the bearing insulating layer. After the bearing insulating layer is flattened, the rigidity and support of the array substrate can be improved, and the impact resistance can be further improved. At the same time, the newly added flattening layer can absorb the impact energy, so that the array substrate has a stronger impact resistance.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, the requirements for the screen-to-body ratio of display devices are getting higher and higher. Flexible display panels have the advantages of bendability, flexibility, light size, and low power consumption. They can form display devices with foldable performance to meet people's extreme pursuit of large-screen displays and enhance user experience.

[0003] As the bending resistance of flexible display panels improves, the thickness of flexible display panels becomes thinner, and the rigidity and supporting capacity of flexible display panels become weaker and weaker. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel and a display device. The array substrate has stronger rigidity and support, and further improves impact resistance.

[0005] An embodiment of a first aspect of the present application provides an array substrate, including:

[0006] substrate;

[0007] A plurality of carrying insulating layers are stacked on one side of the substrate, a patterned device forming layer is formed on the surface of each carrying insulating layer facing away from the substrate, the carrying insulating layer is an inorganic material layer, at least one of the carrying insulating layers is provided with a planarizing layer on the surface facing the substrate to planarize the carrying insulating layer, the surface of the planarizing layer facing away from the substrate is a plane, and the planarizing layer is an organic material layer.

[0008] According to an implementation of the first aspect of the present application, the two adjacent carrying insulating layers along a direction perpendicular to the substrate include a first layer located on a side close to the substrate and a second layer located on a side away from the substrate, and part of the planarization layer is formed between the device forming layer and the second layer located between the first layer and the second layer.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, between two adjacent carrying insulating layers along a direction perpendicular to the substrate, the planarization layer and the device forming layer are arranged in the same layer.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, at least a portion of the carrying insulating layer is patterned, and the array substrate further includes a sub-planarization layer arranged on the same layer as at least a portion of the patterned carrying insulating layer, and the sub-planarization layer is an organic material layer.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, a planarization layer made of multiple layers of different materials is included between two adjacent load-bearing insulating layers along a direction perpendicular to the substrate.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the planarization layer is at least one of polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the device forming layer is used to form a transistor and a capacitor, and includes a conductor layer and a semiconductor layer used to form a transistor and a capacitor;

[0014] Preferably, the semiconductor layer includes at least one of polysilicon and metal oxide; and the conductor layer is made of metal.

[0015] According to any of the aforementioned implementations of the first aspect of the present application, it also includes an additional planarization layer located on a side of the transistor and the capacitor facing away from the substrate, and the additional planarization layer covers the transistor and the capacitor.

[0016] An embodiment of the second aspect of the present application further provides a display panel, comprising any array substrate provided in the first aspect of the present application.

[0017] An embodiment of the third aspect of the present application further provides a display device, comprising any display panel provided in the second aspect of the present application.

[0018] The array substrate provided in the embodiment of the present application includes a substrate, a device forming layer, a bearing insulating layer and a planarization layer, wherein the planarization layer is formed on the side of at least part of the bearing insulating layer facing the substrate, that is, the planarization layer is formed below at least part of the bearing insulating layer, and since the surface of the side of the planarization layer facing away from the substrate is a plane, it is convenient to planarize the bearing insulating layer formed on the planarization layer. Since the bearing insulating layer is an inorganic material layer and the device forming layer is patterned, that is, the device forming layer includes multiple parts located in different layers rather than a whole layer, when the bearing insulating layer is directly formed on the device forming layer, the bearing insulating layer includes a part formed above the device forming layer and a part located in the same layer as the device forming layer, and the bearing insulating layer forms a step around the device forming layer, and the stress during the bending process is easily concentrated on the step position. The array substrate provided in the present application can reduce the risk of stress concentration at the step after the carrying insulating layer is flattened by setting a flattening layer; at the same time, since the carrying insulating layer located on the upper layer is provided with a flattening layer on the side facing the substrate, it can be separated from the carrying insulating layer located on the lower layer by the flattening layer, thereby avoiding the superposition and deposition of multiple carrying insulating layers that are inorganic material layers, thereby reducing the stress between adjacent carrying insulating layers. The flattening layer can absorb impact energy, making the array substrate more impact-resistant. After the carrying insulating layer is flattened, the rigidity and support of the array substrate can also be improved, further improving the impact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0021] Figure 2 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0022] Figure 3 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0023] Figure 4 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0025] Figure 6It is a structural schematic diagram of a display device provided in an embodiment of the present application.

[0026] In the attached figure:

[0027] 10-array substrate; 1-substrate; 11-first supporting layer; 12-first buffer layer; 13-second supporting layer; 14-second buffer layer; 2-carrying insulating layer; 21-first layer; 22-second layer; 3-device forming layer; 31-polysilicon semiconductor layer; 32-metal oxide semiconductor layer; 33-gate; 34-source and drain; 35-capacitor; 4-planarization layer; 5-sub-planarization layer; 6-additional planarization layer; 20-display panel, 7-light-emitting layer; 8-packaging layer; 9-touch layer; 16-support layer; 11-polarizer layer; 12-optical adhesive layer; 13-cover plate; 14-buffer layer; 15-steel sheet; 30-display device. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented when some details in these specific details are not needed. The following description of the embodiment is only for providing a better understanding of the application by illustrating the example of the application.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0030] The inventor has found through research that as the bending resistance of the foldable display panel improves, the thickness of the display panel becomes thinner, and the rigidity and support of the display panel become weaker and weaker. The reason is that in the stacking design of the array substrate in the display panel, on the one hand, some inorganic film layer graphics are complexly designed, which leads to residual stress and defects in the deposition process of the inorganic film material, especially in the step difference area and the hole area; on the other hand, when multiple inorganic film layers are deposited in a superimposed manner, residual stress and defects are easily generated at the interface of adjacent film layers; in this way, when the inorganic film layer with residual stress and defects is impacted by external force, on the one hand, it will deform and accelerate the fragmentation due to the poor support of the display panel; on the other hand, the array substrate will be subjected to the positive stress impact on the light-emitting side of the display panel and the reverse gravitational wave away from the light-emitting side, so that the non-flat area of ​​the array substrate, especially the step difference, is prone to fracture due to stress concentration; after the cracks in the inorganic film layer are generated, they will gradually extend to the nearby film layer during the impact process, causing the nearby film layer to fracture, thereby making the rigidity and support of the array substrate weaker and weaker, causing damage to the electrical stacking structure and ultimately causing bright and dark spot failure problems. Based on the research on the above problems, the inventors provide an array substrate, a display panel and a display device with better anti-bending performance.

[0031] In order to better understand this application, Figures 1 to 6 The array substrate, display panel and display device according to the embodiments of the present application are described in detail.

[0032] See also Figure 1 An embodiment of the present application provides an array substrate 10, including a substrate 1 and a plurality of supporting insulating layers 2 stacked on one side of the substrate 1, a patterned device forming layer 3 is formed on a surface of each supporting insulating layer 2 facing away from the substrate 1, the supporting insulating layer 2 is an inorganic material layer, at least one supporting insulating layer 2 is provided with a planarizing layer 4 on a surface facing the substrate 1 to planarize the supporting insulating layer 2, a surface of the planarizing layer 4 facing away from the substrate 1 is a plane, and the planarizing layer 4 is an organic material layer.

[0033] The array substrate 10 provided in the present application includes a substrate 1, a device forming layer 3, a bearing insulating layer 2 and a planarization layer 4, wherein the planarization layer 4 is formed on the side of at least part of the bearing insulating layer 2 facing the substrate 1, that is, the planarization layer 4 is formed below at least part of the bearing insulating layer 2, and since the surface of the planarization layer 4 on the side facing away from the substrate 1 is a plane, it is convenient to planarize the bearing insulating layer 2 formed on the planarization layer 4. Since the bearing insulating layer 2 is an inorganic material layer and the device forming layer 3 is patterned, that is, the device forming layer 3 includes multiple parts located in different layers rather than a whole layer, when the bearing insulating layer 2 is directly formed on the device forming layer 3, the bearing insulating layer 2 includes a part formed above the device forming layer 3 and a part located in the same layer as the device forming layer 3, and the bearing insulating layer 2 is formed with a step around the device forming layer 3, and the stress during the bending process is easily concentrated on the step position. The array substrate provided in the present application can reduce the risk of stress concentration at the step after the carrying insulating layer 2 is flattened by setting a flattening layer 4; at the same time, since the carrying insulating layer 2 located on the upper layer is provided with a flattening layer 4 on the side facing the substrate 1, it can be separated from the carrying insulating layer 2 located on the lower layer by the flattening layer 4, thereby avoiding the superposition and deposition of multiple layers of inorganic material layers of the carrying insulating layer 2, thereby reducing the stress between adjacent carrying insulating layers 2, and the flattening layer 4 can absorb the impact energy, so that the array substrate 10 has a stronger impact resistance. After the carrying insulating layer 2 is flattened, the rigidity and support of the array substrate 10 can also be improved, and the impact resistance is further improved.

[0034] Compared with the inorganic material layer, the organic material layer has better buffering capacity, the inorganic material layer has better supporting performance and insulation performance, and the inorganic material layer has stronger resistance to high temperature. When preparing the device forming layer 3, a high temperature process is generally required, so the device forming layer 3 needs to be prepared on the supporting insulating layer 2. At this time, the supporting insulating layer 2 needs to use an inorganic material layer to avoid damage to the supporting insulating layer 2. Due to the material properties of the inorganic insulating layer, it is easy to form steps around the device forming layer 3, while the organic material layer can cover the device forming layer 3 and keep the side away from the substrate 1 flat.

[0035] The substrate 1 may be a composite substrate 1, including a first support layer 11, a first buffer layer 12, a second support layer 13 and a second buffer layer 14 stacked in sequence, wherein. The material of the first support layer 11 and the second support layer 13 may be polyimide (PI), and the material of the first buffer layer 12 and the second buffer layer 14 may be silicon oxide (SiOx) or amorphous silicon (a-Si). The preparation process of the substrate 1 may be: coating PI slurry on a glass substrate and baking to form the first support layer 11; preparing the first buffer layer 12 on the first support layer 11 by a chemical vapor deposition (CVD) preparation process; coating PI slurry on the first buffer layer 12 and baking to form the second support layer 13; preparing the second buffer layer 14 on the second support layer 13 by a chemical vapor deposition (CVD) preparation process. Then, a partial device formation layer 3 may be directly prepared on the substrate 1.

[0036] In a possible implementation, Figure 1 As shown, all surfaces of the supporting insulating layer 2 facing the substrate 1 are provided with a planarizing layer 4, so as to improve the absorption of impact energy by the array substrate 10, thereby improving the impact resistance of the array substrate 10 and increasing the bending resistance of the array substrate 10.

[0037] In another possible implementation, if Figure 2 and Figure 3 As shown, a planarization layer 4 is provided on the surface of a portion of the supporting insulating layer 2 facing the substrate 1, so that the amount of planarization layer 4 used can be reduced while ensuring the impact resistance of the array substrate 10, and the stepped deposition of a portion of the supporting insulating layer 2 can be retained to reduce the number of processes for preparing the planarization layer 4 and reduce the cost of using the planarization layer 4.

[0038] In a possible implementation, Figure 3 As shown, two adjacent supporting insulating layers 2 along a direction perpendicular to the substrate 1 include a first layer 21 located on a side close to the substrate 1 and a second layer 22 located on a side away from the substrate 1, and a partial planarization layer 4 is formed between the device forming layer 3 and the second layer 22 located between the first layer 21 and the second layer 22.

[0039] In the above embodiment, in the adjacent planarization layer 4 and device forming layer 3, the planarization layer 4 covers the device forming layer 3, so that the surface of the planarization layer 4 facing away from the substrate 1 is a complete layer, and the carrying insulating layer 2 located on the planarization layer 4 is in complete contact with the planarization layer 4, thereby achieving the planarization of the carrying insulating layer 2 to a great extent. Since the carrying insulating layer 2 is an inorganic material layer, after the carrying insulating layer 2 is planarized, local stress concentration in the array substrate 10 is prevented, and at the same time, the rigidity and support of the array substrate 10 are improved.

[0040] In another possible implementation, if Figure 4 As shown, between two adjacent load-bearing insulating layers 2 along a direction perpendicular to the substrate 1 , the planarization layer 4 and the device forming layer 3 are arranged in the same layer.

[0041] In the above embodiment, a planarization layer 4 and a device forming layer 3 are formed between two adjacent supporting insulating layers 2 in a direction perpendicular to the substrate 1. The planarization layer 4 and the device forming layer 3 are arranged on the same layer. On the one hand, the thickness of the array substrate can be reduced to achieve lightweight and thinness; on the other hand, the material used for the planarization layer 4 can be saved, thereby reducing costs.

[0042] In a possible implementation, Figure 4 As shown, at least a portion of the supporting insulating layer 2 is patterned, and the array substrate 10 further includes a sub-planarization layer 5 disposed on the same layer as the at least partially patterned supporting insulating layer 2 , and the sub-planarization layer 5 is an organic material layer.

[0043] In the above embodiment, at least part of the carrier insulating layer 2 is patterned, specifically, only the area corresponding to the device forming layer 3 formed on the carrier insulating layer 2 is retained in at least part of the carrier insulating layer 2, and the area not corresponding to the device forming layer 3 on the carrier insulating layer 2 is removed, and after the removal, the area not corresponding to the device forming layer 3 on the carrier insulating layer 2 is replaced with the sub-planarization layer 5. That is, the adjacent carrier insulating layer 2 and the device forming layer 3 are patterned, so that the orthographic projection of the carrier insulating layer 2 on the device forming layer 3 adjacent to it in the direction away from the substrate covers the device forming layer 3.

[0044] Since the sub-planarization layer 5 is an organic material layer, in the above embodiment, after the area in the carrying insulating layer 2 that is not covered by the device forming layer 3 adjacent to the carrying insulating layer is replaced with the sub-planarization layer 5, the use of organic material layers in the array substrate 10 is increased, and the absorption of impact energy by the array substrate 10 is improved, thereby improving the impact resistance of the array substrate 10.

[0045] In a feasible embodiment, a planarization layer 4 with different multi-layer materials is included between two adjacent supporting insulating layers 2 along a direction perpendicular to the substrate 1, so that the use of organic material layers in the array substrate 10 is increased, and the array substrate 10's ability to absorb impact energy is improved, thereby improving the impact resistance of the array substrate 10.

[0046] In a feasible implementation, the material of the planarization layer 4 may be at least one of polyimide (PI), polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide.

[0047] Specifically, the material of the planarization layer 4 may also be other high-temperature resistant organic materials, which is not particularly limited in the present application.

[0048] The preparation process of the planarization layer 4 includes: coating an organic material on the device formation layer 3 and baking to form the planarization layer 4 .

[0049] In the array substrate 10 , the preparation process of the bearing insulating layer 2 includes: preparing the planarization layer 4 by using a CVD preparation process.

[0050] The array substrate 10 includes devices such as transistors and capacitors 35. Therefore, the device forming layer 3 includes a semiconductor layer for forming an active layer of the transistor. The material of the semiconductor layer includes at least one of a polycrystalline silicon (such as p-Si) semiconductor layer and a metal oxide (such as IGZO) semiconductor layer, and may also include an amorphous silicon material, etc.; the device forming layer 3 also includes a conductor layer for forming a gate 33, a source and a drain 34 in the transistor, and an upper plate and a lower plate of the capacitor 35. The material of the conductor layer is metal. For example, the metal used to form the gate 33 can be molybdenum (Mo) or titanium (Ti) or silver, etc., and the metal used to form the source and drain 34 can be a stacked titanium / aluminum / titanium composite structure.

[0051] In the array substrate 10, when the material of the transistor is polycrystalline silicon, a layer of amorphous silicon (a-Si) can be deposited on the substrate 1 or the supporting insulating layer 2 by a CVD process, and then a laser annealing (ELA) process is used to generate polycrystalline silicon (P-Si), and then a patterned polycrystalline silicon film layer is formed by a yellow light process (photoresist coating-exposure-development) and dry etching and photoresist removal process.

[0052] In the array substrate 10, the preparation process of the conductor layer includes: depositing a metal layer (such as Mo) by PVD preparation process, and then forming a patterned conductor layer by yellow light process (coating photoresist-exposure-development) and dry etching, and photoresist removal process.

[0053] When preparing the source and drain electrodes 34, blind holes need to be formed at the film layer between the source and drain electrodes 34 and the source and drain regions of the active layer and the gate 33 by yellow light process (coating photoresist-exposure-development) and dry etching and photoresist removal process. Then, a metal film layer (such as Ti / Al / Ti) needs to be deposited at the location where the source and drain electrodes 34 are prepared by PVD preparation process, and then patterned source and drain electrodes 34 are formed by yellow light process (coating photoresist-exposure-development) and dry etching and photoresist removal process.

[0054] In a feasible implementation manner, the array substrate 10 further includes an additional planarization layer 6 located on a side of the device forming layer 3 that is away from the substrate 1 and that is away from the substrate 1 .

[0055] In a feasible implementation manner, the device forming layer 3 includes a conductor layer and a semiconductor layer for forming a transistor and a capacitor 35 , and an additional planarization layer 6 covers the transistor and the capacitor 35 .

[0056] In the above embodiment, the material of the additional planarization layer 6 can be at least one of polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide (PI). The additional planarization layer 6 is used to cover the device formation layer 3 such as the source and drain 34 located at the top of the device formation layer 3 to form a flat surface to facilitate the preparation of subsequent film layers.

[0057] The present application also provides a display panel 20, such as Figure 5 As shown, it includes any one of the array substrates 10 provided in the above embodiments of the present application.

[0058] When the display panel 20 is an OLED display panel, it also includes a light-emitting layer 7 formed on the side of the additional planarization layer 6 away from the substrate 1, including a patterned anode, a pixel defining layer, an auxiliary support layer, etc., and an opening corresponding to the anode is formed on the pixel defining layer to expose the anode. The structure of the anode can be a first indium tin oxide material layer, a silver material layer, and a second indium tin oxide material layer stacked in a direction away from the substrate; the auxiliary support layer is used to support the mask plate to form a common layer, a light-emitting material layer, and a cathode layer, etc. through an evaporation process. The common layer is the entire layer covering the pixel defining layer, including a portion located in the pixel opening and a portion located on the side of the pixel defining layer away from the substrate 1. The common layer includes part or all of an electron injection layer (EIL), an electron transport layer (ETL), a hole blocking layer (HBL), an electron blocking layer (EBL), a hole transport layer (HTL), and a hole injection layer (HIL). The light-emitting material layer includes phosphorescent materials for emitting red and green light and fluorescent materials for emitting blue light.

[0059] The preparation process of the pixel definition layer and the support layer 16 includes: coating raw materials at preset positions respectively, and exposing and developing to form a patterned pixel definition layer or support layer 16 .

[0060] The display panel 20 may also be a liquid crystal display panel, etc., which is not particularly limited in this application.

[0061] In the display panel 20 provided in the present application, the neutral plane of the display panel 20 can be adjusted by adjusting the thickness of each planarization layer and the bearing insulating layer 2 in the array substrate 10, and adjusting the number of planarization layers, thereby improving the bending resistance of the display panel 20. Specifically, the number and thickness information of each film layer can be simulated, and the thickness of each planarization layer and the bearing insulating layer 2 can be adjusted to obtain the best combination, so as to obtain the display panel 20 with high bending resistance, prevent poor display, and improve the display quality.

[0062] The present application also provides a display device 30, such as Figure 6 As shown, it includes the display panel 20 provided in the above embodiment.

[0063] In the display panel 20, an encapsulation layer 8, a touch layer 9, a support layer 16, a polarizer layer 11, an optical adhesive layer 12 and a cover plate 13 etc. may be formed in sequence on the light-emitting layer 7. A support layer 16, a buffer layer 14 and a steel sheet 15 etc. may also be formed on the side of the array substrate 10 away from the light-emitting layer 7 to form a flexible display device with excellent anti-buffering and anti-bending properties.

[0064] The display device may be a mobile terminal such as a mobile phone or a tablet, or may be a display, a television or other device, and this application does not specifically limit this.

[0065] According to the embodiments of the present application as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of carrying insulating layers are stacked on one side of the substrate, a patterned device forming layer is formed on the surface of each carrying insulating layer facing away from the substrate, the carrying insulating layer is an inorganic material layer, at least one of the carrying insulating layers is provided with a planarizing layer on the surface facing the substrate to planarize the carrying insulating layer, the surface of the planarizing layer facing away from the substrate is a plane, and the planarizing layer is an organic material layer.

2. The array substrate according to claim 1, characterized in that: The two adjacent carrying insulating layers along a direction perpendicular to the substrate include a first layer located on a side close to the substrate and a second layer located on a side away from the substrate, and part of the planarization layer is formed between the device forming layer and the second layer located between the first layer and the second layer.

3. The array substrate according to claim 1, characterized in that: Between two adjacent carrying insulating layers along a direction perpendicular to the substrate, the planarization layer and the device forming layer are arranged in the same layer.

4. The array substrate according to claim 1, characterized in that: At least a portion of the supporting insulating layer is patterned, and the array substrate further comprises a sub-planarization layer disposed on the same layer as at least a portion of the patterned supporting insulating layer, and the sub-planarization layer is an organic material layer.

5. The array substrate according to claim 1, characterized in that: The planarization layer made of multiple layers of different materials is included between two adjacent carrying insulating layers along a direction perpendicular to the substrate.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The material of the planarization layer is at least one of polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide.

7. The array substrate according to claim 1, characterized in that: The device forming layer is used to form transistors and capacitors, and includes a conductor layer and a semiconductor layer used to form transistors and capacitors.

8. The array substrate according to claim 7, characterized in that: The semiconductor layer includes at least one of polysilicon and metal oxide; the conductor layer is made of metal.

9. The array substrate according to claim 7, characterized in that: The invention also includes an additional planarization layer located on a side of the transistor and the capacitor facing away from the substrate, wherein the additional planarization layer covers the transistor and the capacitor.

10. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 9.

11. A display device, characterized in that: Comprising the display panel as claimed in claim 10.

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