Storage module and storage system having the same

Abstract

Storage modules and storage systems having storage modules are provided. A storage module can include command / address terminals, data terminals, at least one monitor terminal, a buffer, and a plurality of semiconductor memory devices. The buffer can be configured to receive and buffer data applied through the data terminals and commands / addresses applied through the command / address terminals to generate buffered write data and buffered commands / addresses. The buffer can be configured to buffer the buffered write data and the buffered commands / addresses to generate module data and module commands / addresses and store, and then send at least a portion of the buffered write data as monitor data through the at least one monitor terminal. The plurality of semiconductor memory devices can be configured to receive and store the module data in response to the module commands / addresses.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0091034, filed on July 22, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a storage module and a storage system having the storage module. Background Technology

[0004] A storage system may include a control unit and storage modules. The control unit may be, for example, a central processing unit (CPU) or a graphics processing unit (GPU).

[0005] The storage module may include multiple semiconductor storage devices mounted on a storage board. Additionally, the storage module may include a buffer configured to receive and buffer data and / or commands / addresses sent from the control unit for transmission to the multiple semiconductor storage devices.

[0006] A technique may be needed for external monitoring of data and / or commands / addresses sent from the control unit to the storage module. For example, the technique could be one that enables the storage module to support external devices (e.g., monitoring devices) so that the external devices can more easily monitor the data and / or commands / addresses sent from the control unit. Summary of the Invention

[0007] Example embodiments of this disclosure provide a storage module that can be configured to support external devices so that the external devices can monitor data and / or commands / addresses sent from the control unit, and provide a storage system having the storage module.

[0008] This disclosure is not limited to the foregoing objectives and examples of the embodiments disclosed herein, and other objectives and embodiments will be clearly understood by those skilled in the art based on the following description.

[0009] According to some exemplary embodiments of the present invention, a storage module may include: a first plurality of terminals including a plurality of command / address terminals; a second plurality of terminals including a plurality of data terminals; at least one monitoring terminal; and a buffer configured to receive and buffer a second plurality of bits of data applied through the data terminals to generate buffered write data of the second plurality of bits, and configured to receive and buffer a first plurality of bits of command / address applied through the command / address terminals to generate buffered command / address of the first plurality of bits. The buffer is further configured to buffer the buffered write data of the second plurality of bits and the buffered command / address of the first plurality of bits to generate module data and module command / address, store at least a portion of the buffered write data of the second plurality of bits, and transmit the stored at least a portion of the buffered write data of the second plurality of bits as monitoring data through the at least one monitoring terminal. The storage module further includes a plurality of semiconductor memory devices configured to receive and store the module data in response to the module command / address.

[0010] According to some exemplary embodiments of the present invention, a storage module may include: a first plurality of terminals including a plurality of command / address terminals; a second plurality of terminals including a plurality of data terminals; at least one monitoring terminal; and a buffer configured to receive and buffer data applied through the data terminals and commands / addresses applied through the command / address terminals to generate buffered write data and buffered commands / addresses. The buffer is further configured to buffer the buffered write data and the buffered commands / addresses to generate module data and module commands / addresses. The storage module further includes a storage and processing unit configured to store at least a portion of the buffered write data and to transmit at least a portion of the stored buffered write data as monitoring data through the at least one monitoring terminal. The storage module further includes a plurality of semiconductor memory devices configured to receive and store the module data in response to the module commands / addresses.

[0011] According to some exemplary embodiments of the present invention, a storage system may include a control unit, the control unit including a processor, a clock signal generator, a command / address generator, and a data input and output unit, the processor being configured to execute a program to generate internal commands, internal addresses, and internal data, the clock signal generator being configured to generate a clock signal, the command / address generator being configured to receive the internal commands and the internal addresses in response to the clock signal to generate a first plurality of bits of command / address, and the data input and output unit being configured to receive the internal data to generate a second plurality of bits of data. The storage system may further include a storage module, which may include: a first plurality of terminals, a second plurality of terminals, at least one monitoring terminal, and a buffer. The first plurality of terminals include a plurality of command / address terminals, and the second plurality of terminals include a plurality of data terminals. The buffer is configured to receive and buffer data of the second plurality of bits applied through the data terminals and commands / addresses of the first plurality of bits applied through the command / address terminals to generate buffered write data of the second plurality of bits and buffered commands / addresses of the first plurality of bits. The buffer is also configured to buffer the buffered write data of the second plurality of bits and buffered commands / addresses of the first plurality of bits to generate module data and module commands / addresses. The storage module may further include a storage and processing unit configured to store at least a portion of the buffered write data of the second plurality of bits and to transmit at least a portion of the stored buffered write data of the second plurality of bits as monitoring data through the at least one monitoring terminal. The storage module may further include a plurality of semiconductor memory devices configured to receive and store the module data in response to the module commands / addresses. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the configuration of a storage system according to some example embodiments of the concept of the present invention.

[0013] Figure 2 This is a diagram illustrating the configuration of a control unit according to some example embodiments of the concept of the present invention.

[0014] Figure 3 This is a block diagram illustrating the configuration of a storage module according to some example embodiments of the concept of the present invention.

[0015] Figure 4 This is a block diagram illustrating the configuration of a buffer according to some example embodiments of the concept of the present invention.

[0016] Figure 5 This is a block diagram illustrating the configuration of interface units according to some example embodiments of the concept of the present invention.

[0017] Figure 6 This is a block diagram illustrating the configuration of a second interface unit according to some exemplary embodiments of the present invention.

[0018] Figure 7 This is a block diagram illustrating the configuration of a storage device according to some example embodiments of the concept of the present invention.

[0019] Figure 8 and Figure 9 This is an operation timing diagram used to describe the operation of a storage device according to some example embodiments of the present invention.

[0020] Figure 10 The diagram illustrates the structure of a storage cell array and the stored data according to some example embodiments of the inventive concept.

[0021] Figure 11 This is a block diagram illustrating the configuration of processing units according to some exemplary embodiments of the present invention.

[0022] Figure 12 The format of monitoring data output from the processing unit is shown in some example embodiments of the present invention.

[0023] Figure 13 This is a block diagram illustrating the configuration of a storage module according to some example embodiments of the concept of the present invention. Detailed Implementation

[0024] In the following description, a storage module and a storage system having the storage module will be described with reference to the accompanying drawings, based on some exemplary embodiments of the concept of the present invention.

[0025] Figure 1 This is a block diagram illustrating the configuration of a storage system according to some exemplary embodiments of the present invention. The storage system 1000 may include a control unit 100 and at least one storage module 200. A monitoring device 300 may be connected externally to the storage system 1000.

[0026] exist Figure 1In this configuration, the control unit 100 may be, for example, a central processing unit (CPU) or a graphics processing unit (GPU). The control unit 100 may send a clock signal CK and a first plurality of bits of command / address CA to at least one storage module 200. The control unit 100 may also send and / or receive a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n from at least one storage module 200. Here, n may be a natural number greater than or equal to 1. In some embodiments, the second plurality of bits of data DQ11 to DQ1n may include first channel data DQ11 to DQ1n and second channel data DQ21 to DQ2n. The first channel data DQ11 to DQ1n may include a first predetermined number of bits of first data and a second predetermined number of bits of first error correction code (ECC), and the second channel data DQ21 to DQ2n may include a first predetermined number of bits of second data and a second predetermined number of bits of second ECC. As an example, the first channel data DQ11 to DQ1n may include 32 bits of first data and 8 bits of first ECC, and the second channel data DQ21 to DQ2n may include 32 bits of second data and 8 bits of second ECC. As another example, the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n may include 64 bits of data and 8 bits of ECC. In some embodiments, the number of bits in the first channel data DQ11 to DQ1n may not be equal to the number of bits in the second channel data DQ21 to DQ2n.

[0027] At least one storage module 200 can receive and store a first plurality of bits of command / address CA applied through one or more command / address terminals CAP, and a clock signal CK applied through one or more clock terminals CKP. When the command included in the first plurality of bits of command / address CA is a write command, at least one storage module 200 can receive and store a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n applied through a second plurality of data terminals DQ1P and DQ2P. When the command included in the first plurality of bits of command / address CA is a read command, at least one storage module 200 can transmit the stored second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n through the second plurality of data terminals DQ1P and DQ2P. In addition, at least one storage module 200 can send at least a portion of a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n applied through the second plurality of data terminals DQ1P and DQ2P and / or at least a portion of a first plurality of bits of command / address CA applied through one or more command / address terminals CAP as monitoring data mdata applied to the monitoring device 300 through the monitoring terminal COMP.

[0028] Figure 2This is a block diagram illustrating the configuration of a control unit according to some exemplary embodiments of the present invention. The control unit 100 may include a processor 100-2, a command and address generator 100-4, a clock signal generator 100-6, and a data input and output unit 100-8. The following will describe... Figure 2 The function of each box shown.

[0029] Processor 100-2 can execute a program according to the external command ECOM, generate command COM and address ADD, and send and receive (e.g., send and / or receive) data DATA. For example, processor 100-2 can communicate with various input devices (not shown) (e.g., keyboard, mouse, touch sensor, or voice, fingerprint, or motion recognition sensor, etc.) to receive the external command ECOM. Processor 100-2 can execute a program according to the external command ECOM to generate command COM, address ADD, and data DATA, and receive and process the data DATA to output to various output devices (not shown) (e.g., display unit or sound output unit, etc.). In addition, processor 100-2 can also generate a clock signal control signal ckcon.

[0030] Command and address generator 100-4 can receive command COM and address ADD from processor 100-2 in response to internal clock signal ck, to generate a first plurality of bits of command / address CA. For example, command and address generator 100-4 can generate the first plurality of bits of command / address CA in response to internal clock signal ck according to the Double Data Rate (DDR) protocol. According to the DDR protocol, the first plurality of bits of command / address CA can be generated in response to the rising and falling edges of internal clock signal ck.

[0031] The clock signal generator 100-6 can generate an internal clock signal ck and a clock signal CK in response to the clock signal control signal ckcon received from the processor 100-2.

[0032] Data input and output unit 100-8 can, in response to an internal clock signal ck, receive data DATA from processor 100-2 to generate a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n, or receive the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n to generate DATA to be sent to processor 100-2. For example, data input and output unit 100-8 can generate the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n in response to an internal clock signal ck according to a DDR protocol. For example, in response to the rising and falling edges of the internal clock signal ck, the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n can be input or output sequentially in numbers (e.g., 4, 8, 16, etc.) corresponding to a predetermined burst length.

[0033] Figure 3 The configuration of a storage module according to some example embodiments of the present invention is shown. The storage module 200 may include a buffer 10, 2n semiconductor storage devices M11 to M1n and M21 to M2n, a first plurality of command / address terminals CAP, a second plurality of data terminals DQ1P and DQ2P, a clock signal terminal CKP, and at least one monitoring terminal COMP.

[0034] Reference Figure 3The buffer 10 can receive and buffer a first plurality of bits of command / address CA, a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n, and a clock signal CK, respectively, sent from the control unit 100 via a first plurality of command / address terminals CAP, a second plurality of data terminals DQ1P and DQ2P, and a clock signal terminal CKP. Then, the buffer 10 can send module command / addresses caa and cab, module data dq11 to dq1n and dq21 to dq2n, and module clock signals cka and ckb to 2n semiconductor memory devices M11 to M1n and M21 to M2n. When the command storage module 200 sends data to the control unit 100, the buffer 10 can receive and buffer module data dq11 to dq1n and dq21 to dq2n output from 2n semiconductor memory devices M11 to M1n and M21 to M2n, so as to send a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n to the control unit 100 through the second plurality of data terminals DQ1P and DQ2P. The buffer 10 can send module command / address caa and module clock signal cka to the n semiconductor memory devices M11 to M1n in a common manner, and can send module command / address cab and module clock signal ckb to the n semiconductor memory devices M21 to M2n in a common manner. During a write operation, the buffer 10 can send module data dq11 to dq1n to the n semiconductor memory devices M11 to M1n respectively, and send module data dq21 to dq2n to the n semiconductor memory devices M21 to M2n respectively. Furthermore, during the read operation, the buffer 10 can receive and buffer module data dq11 to dq1n via the data terminal DQ1P to generate data DQ11 to DQ1n, and can receive and buffer module data dq21 to dq2n via the data terminal DQ2P to generate data DQ21 to DQ2n.

[0035] Furthermore, buffer 10 can receive and store at least a portion of a first plurality of bits of command / address CA and / or at least a portion of a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n, and can use the stored at least a portion of the first plurality of bits of command / address CA and / or the stored at least a portion of the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n as monitoring data mdata. During normal operation (e.g., write and read operations), the monitoring data mdata can be output to the monitoring terminal COMP. Figure 1The monitoring device 300 shown is described in some embodiments. In some embodiments, the buffer 10 can receive and store at least a portion of a first plurality of bits of command / address CA and / or at least a portion of a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n during normal operation, and in response to a request from the monitoring device 300, output the stored at least a portion of the first plurality of bits of command / address CA and / or the stored at least a portion of the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n as monitoring data mdata via the monitoring terminal COMP.

[0036] Figure 4 This is a block diagram illustrating the configuration of a buffer 10 according to some exemplary embodiments of the present invention. The buffer 10 may include a first interface unit 10-2, a second interface unit 10-4, and a storage and processing unit 10-10. The storage and processing unit 10-10 may include a storage device 10-6 and a processing unit 10-8.

[0037] exist Figure 4 In this configuration, the first interface unit 10-2 can receive and buffer a second plurality of data bits DQ11 to DQ1n and DQ21 to DQ2n, a first plurality of command / address bits CA, and a clock signal CK. Based on this, the first interface unit 10-2 can generate buffered write data bwdq11 to bwdq1n and bwdq21 to bwdq2n for the second plurality of bits, buffered command / address bits bca for the first plurality of bits, and buffered clock signal bck. Alternatively, or as an alternative, the buffer 10 receives and buffers a second plurality of read data bits brdq11 to brdq1n and brdq21 to brdq2n to generate the second plurality of data bits DQ11 to DQ1n and DQ21 to DQ2n. For example, the first interface unit 10-2 can convert the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n, which may be in analog form, the first plurality of bits of command / address CA, and the clock signal CK into the second plurality of bits of buffered write data bwdq11 to bwdq1n and bwdq21 to bwdq2n, the first plurality of bits of buffered write command / address bca, and the buffered clock signal bck, which may be in digital form. Alternatively, or as an alternative, the first interface unit 10-2 can convert the levels of the second plurality of bits of buffered read data brdq11 to brdq1n and brdq21 to brdq2n, which may be in digital form, to levels used for... Figure 1 The appropriate levels of the control unit 100 shown are used to generate a second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n. Therefore, in some embodiments, the first interface unit 10-2 can implement an analog-to-digital converter (ADC) and / or a digital-to-analog converter (DAC).

[0038] The second interface unit 10-4 can receive and buffer the write data bwdq11 to bwdq1n and bwdq21 to bwdq2n of the second plurality of buffers, the command / address bca of the first plurality of buffers, and the buffer clock signal bck. Based on this, it can generate module data dq11 to dq1n and dq21 to dq2n, module command / address caa and cab, and module clock signals cka and ckb. Alternatively, or as an alternative, the second interface unit 10-4 can receive and buffer the module data dq11 to dq1n and dq21 to dq2n to generate the read data brdq11 to brdq1n and brdq21 to brdq2n of the second plurality of buffers. For example, the second interface unit 10-4 can convert the write data bwdq11 to bwdq1n and bwdq21 to bwdq2n of the second plurality of bits of buffer, which may be in digital form, the command / address bca of the first plurality of bits, and the buffered clock signal bck to appropriate levels for 2n semiconductor memory devices M11 to M1n and M21 to M2n, to generate module data dq11 to dq1n and dq21 to dq2n, module command / address caa and cab, and module clock signals cka and ckb.

[0039] The storage and processing unit 10-10 can receive and store a third set of data idq corresponding to at least a portion of the write data bwdq11 to bwdq1n and bwdq21 to bwdq2n of the second set of bits, and / or a portion of the command / address bca of the first set of bits, so as to output the stored third set of data idq as monitoring data mdata.

[0040] Storage device 10-6 can store a third plurality of bits of data idq, and can output the stored third plurality of bits of data idq as a fourth plurality of bits of data tdq to processing unit 10-8. Storage device 10-6 can perform write operations to store the third plurality of bits of data idq and read operations to output the fourth plurality of bits of data tdq using a first-in-first-out (FIFO) method. Storage device 10-6 can be a dual-port memory including a first port and a second port that are independent of each other, and in some embodiments, it can be configured to perform write operations and read operations simultaneously via the first port and the second port. For example, storage device 10-6 can perform write operations to receive and write the third plurality of bits of data idq through the first port, and simultaneously perform read operations to read and output the fourth plurality of bits of data tdq through the second port. The first port can include a plurality of input terminals, and the second port can include a plurality of output terminals. The number of input terminals and / or output terminals provided can be related to the size of the first plurality of bits and / or the size of the second plurality of bits. For example, the number of input terminals of the first port and the number of output terminals of the second port can both be 72. The first plurality of bits can be 10 bits, the second plurality of bits can be 72 bits, the third plurality of bits can be 72 bits or less, and the number of bits of the fourth plurality of bits can be the same as or less than the number of bits of the third plurality of bits. For example, the third plurality of bits can be 72 bits and the fourth plurality of bits can be 8 bits. The storage device 10-6 can perform a write operation to store the data idq of the third plurality of bits, and when there is a read request from the processing unit 10-8, it performs a read operation to output the data tdq of the fourth plurality of bits.

[0041] Processing unit 10-8 can receive a fourth and a half bits of data tdq from storage device 10-6, and can send the fourth and a half bits of data tdq as monitoring data mdata. For example, processing unit 10-8 can receive the fourth and a half bits of data tdq, convert the received data into serial data, and serially output the monitoring data mdata.

[0042] Figure 5 This is a block diagram illustrating the configuration of a first interface unit 10-2 according to some exemplary embodiments of the present invention. The first interface unit 10-2 may include: data (DQ) input buffers 10-22 and 10-30, DQ output buffers 10-24 and 10-32, command / address (CA) input buffer 10-26, and clock signal input buffer 10-28. The following describes... Figure 5 The function of each box shown.

[0043] DQ input buffer 10-22 buffers data DQ11 to DQ1n to generate buffered write data bwdq11 to bwdq1n. DQ output buffer 10-24 buffers buffered read data brdq11 to brdq1n to generate data DQ11 to DQ1n. CA input buffer 10-26 buffers a first plurality of bits of command / address CA to generate a first plurality of bits of buffered command / address bca. CK input buffer 10-28 buffers the clock signal CK to generate a buffered clock signal bck. DQ input buffer 10-30 buffers data DQ21 to DQ2n to generate buffered write data bwdq21 to bwdq2n. DQ output buffer 10-32 buffers buffered read data brdq21 to brdq2n to generate data DQ21 to DQ2n.

[0044] In some embodiments, Figure 1 The control unit 100 shown can send signals that can be in digital form, but in some cases, the signal may be distorted, which may result in a signal in analog form. Figure 5 The DQ input buffers 10-22 and 10-30, CA input buffer 10-26, and CK input buffer 10-28 shown can buffer the second plurality of bits of data DQ11 to DQ1n and DQ21 to DQ2n, the first plurality of bits of command / address CA, and the clock signal CK received in analog form at the storage module 200, and can convert the received analog data into digital data. Furthermore, Figure 5 The DQ output buffers 10-24 and 10-32 shown can convert the read data brdq11 to brdq1n and brdq21 to brdq2n from the second plurality of bit buffers to levels used for... Figure 1 The appropriate level of the control unit 100 shown.

[0045] Figure 6 This is a block diagram illustrating the configuration of a second interface unit 10-4 according to some exemplary embodiments of the present invention. The second interface unit 10-4 may include module data (dq) output buffers 10-42 and 10-54, module command / address (caa, cab) output buffers 10-46 and 10-52, module clock signal (cka, ckb) output buffers 10-48 and 10-50, and dq input buffers 10-44 and 10-56. The following describes... Figure 6 The function of each box shown.

[0046] The DQ output buffer 10-42 buffers the buffered write data bwdq11 to bwdq1n to generate module data dq11 to dq1n. The DQ input buffer 10-44 buffers module data dq11 to dq1n to generate buffered read data brdq11 to brdq1n. The CAA output buffer 10-46 buffers the buffered command / address bca to generate module command / address caa. The CKA output buffer 10-48 buffers the buffered clock signal bck to generate module clock signal cka. The CKB output buffer 10-50 buffers the buffered clock signal bck to generate module clock signal ckb. The CAB output buffer 10-52 buffers the buffered command / address bca to generate module command / address cab. The DQ output buffer 10-54 buffers the buffered write data bwdq21 to bwdq2n to generate module data dq21 to dq2n. The dq input buffers 10-56 can buffer module data dq21 to dq2n to generate buffered read data brdq21 to brdq2n.

[0047] Figure 6 The DQ output buffers 10-42 and 10-54, CAA output buffer 10-46 and CAB output buffer 10-52, and CKA output buffer 10-48 and CKB output buffer 10-50 shown can convert the write data bwdq11 to bwdq1n and bwdq21 to bwdq2n of the second multiple-bit buffer, the command / address bca of the first multiple-bit buffer, and the level of the buffer clock signal bck to be used for... Figure 3 The appropriate levels of the 2n semiconductor memory devices M11 to M1n and M21 to M2n are shown to generate module data dq11 to dq1n and dq21 to dq2n, module command / address caa and cab, and module clock signals cka and ckb.

[0048] Figure 7 This is a block diagram illustrating the configuration of a storage device 10-6 according to some exemplary embodiments of the present invention. The storage device 10-6 may include a first address decoder 10-62, an input unit 10-64, a second address decoder 10-66, an output unit 10-68, a storage cell array 10-70, and a controller 10-72. Figure 7 The storage device 10-6 shown may be a dual-port memory, comprising a first port configured to receive a third plurality of bits of data idq and a second port configured to output a fourth plurality of bits of data tdq. The first port and the second port are... Figure 7 It is not explicitly shown, but the first port can be coupled to input unit 10-64, and the second port can be coupled to output unit 10-68. The following describes... Figure 7 The function of each box shown.

[0049] The first address decoder 10-62 can decode the first address add1 received from the controller 10-72, and based on this, it can generate a first selection signal sel1 and send the first selection signal sel1 to the memory cell array 10-70.

[0050] Input unit 10-64 can receive a third and a half bits of data idq in response to a write enable signal wen received from controller 10-72, and based on this, can generate a third and a half bits of write data wd to send to memory cell array 10-70.

[0051] The second address decoder 10-66 can decode the second address add2 received from the controller 10-72, and based on this, can generate a second selection signal sel2 and send the second selection signal sel2 to the memory cell array 10-70.

[0052] Output unit 10-68 can receive a fourth plurality of read data rd from memory cell array 10-70 in response to a read enable signal ren received from controller 10-72, and can generate a fourth plurality of data tdq based on this. The number of bits in the fourth plurality of bits can be the same as or less than the number of bits in the third plurality of bits.

[0053] The memory cell array 10-70 may include multiple dual-port memory cells and may store a third or more bits of write data wd in a selected memory cell in response to a first selection signal sel1. Alternatively, or as an alternative, the memory cell array 10-70 may output a fourth or more bits of read data rd from the selected memory cell in response to a second selection signal sel2.

[0054] Controller 10-72 can generate a write enable signal wen in response to a first read / write control signal RWC1, and can generate a read enable signal ren in response to a second read / write control signal RWC2. In some embodiments, controller 10-72 can fix the first read / write control signal RWC1 to a first state (e.g., power supply voltage (or ground voltage)) to activate the write enable signal wen, and fix the second read / write control signal RWC2 to a second state (e.g., ground voltage (or power supply voltage)) to activate the read enable signal ren. Furthermore, controller 10-72 can generate a first address add1 and a second address add2 in response to a buffered clock signal bck. In some embodiments, controller 10-72 can delay the first address add1 by a predetermined time to generate the second address add2. Therefore, storage device 10-6 can sequentially store a third plurality of bits of data idq and sequentially output a fourth plurality of bits of data tdq using a first-in, first-out (FIFO) method. When the first address `add1` and the second address `add2` are the same, the number of bits in the third and fourth plurality of positions can be the same. However, when the first address `add1` and the second address `add2` are different, the number of bits in the fourth plurality of positions is less than the number of bits in the third plurality of positions. For example, the number of bits in the third plurality of positions can be 72, and the number of bits in the fourth plurality of positions can be 8.

[0055] In some embodiments, the controller 10-72 can activate the write enable signal wen when the first read / write control signal RWC1 is fixed in a first state, and can activate the read enable signal ren when a second read / write control signal RWC2 with a second state is applied from the processing unit 10-8.

[0056] Figure 8 and Figure 9 This is an operation timing diagram used to describe the operation of a storage device according to some exemplary embodiments of the present invention. Figure 10 The illustration shows data stored in a storage area of ​​a memory cell array according to some example embodiments of the inventive concept. Figures 8 to 10 It is used to describe when passing Figure 1 The storage module 200 shown responds to the rising and falling edges of the buffered clock signal bck according to the DDR protocol. Figure 1 The diagram illustrates the operation of the storage device 10-6 when the control unit 100 sequentially receives data idq, including data D1 to data Dk, a third plurality of bits, and sequentially outputs data tdq, including data D1 to data Dk. Here, the number of bits in the fourth plurality of bits is the same as or less than the number of bits in the third plurality of bits.

[0057] The following is for reference. Figures 7 to 10 Describe the write operation of storage device 10-6.

[0058] When the first read / write control signal RWC1 is fixed to a first voltage (e.g., power supply voltage VDD) and the second read / write control signal RWC2 is fixed to a second voltage (e.g., ground voltage GND), the controller 10-72 can generate a write enable signal wen with a "high (H)" level and a read enable signal ren with a "high" level. That is, both the write enable signal wen and the read enable signal ren can be activated.

[0059] The controller 10-72 can generate a first address add1 in response to the rising and falling edges of the buffered clock signal bck, and the first address add1 increases or decreases sequentially from address a1 to address ak.

[0060] Input unit 10-64 can sequentially receive data idq, including data D1 to data Dk, in response to write enable signal wen, so as to sequentially generate write data wd, including data D1 to data Dk.

[0061] The first address decoder 10-66 can generate a first selection signal sel1 in response to a first address add1. The first address may include a first row address and a first column address, and one or more first word line selection signals wla1 to wlai may be generated based on the first row address, and one or more first column selection signals csla11 to cslakj may be generated based on the first column address. In some embodiments, j first column selection signals (csla11 to csla1j), ..., or (cslak1 to cslakj) may be generated, which may correspond to one of k groups of first column selection signals csla1 to cslak. Each of the j first column selection signals included in the corresponding group of the k groups of first column selection signals csla1 to cslak may be activated, for example, by ignoring or neglecting a predetermined number of high-order or low-order bits of the first column address. The first selection signal sel1 may include the generated first word line selection signals wla1 to wlai and the generated first column selection signals csla11 to cslakj.

[0062] As in Figure 10As most clearly seen in some embodiments, the memory cell array 10-70 may store a portion of a third plurality of bits of data D1 in a memory cell group MC11 (not shown) selected by the first word line select signal (e.g., signal wla1) in the first word line select signal group and the first column select signal group (e.g., signal group csla1, which may include signals csla11 to csla1j) in the first column select signal group. The third plurality of bits of data D1 may include j data D11 to D1j. Similarly, other portions of the third plurality of bits of data D2 to Dk may be sequentially stored in memory cell groups MC12 to MC1k selected by the first word line select signal (e.g., signal wla1) in the first word line select signal group and the subsequent signal groups (e.g., signal groups csla2 to cslak) in the first column select signal group. The third plurality of bits of data D2 to Dk may each include j data (D21 to D2j), ..., (Dk1 to Dkj).

[0063] The following is for reference. Figure 7 , Figure 8 and Figure 10 Describe the read operation of storage device 10-6.

[0064] Controller 10-72 can generate a second address add2 starting from a point in time where the time of generating the first address add1 is delayed by a predetermined time (e.g., offset by 90 degrees). This second address add2 can be incremented or decremented sequentially from address a1 to address ak. For example, ... Figure 8 As shown, the first address add1 can be increased from a1 to a2 on the falling edge of the buffered clock signal bck, and the second address add2 can be increased from a1 to a2 on the subsequent rising edge of the buffered clock signal bck (e.g., on the rising edge of the buffered clock signal where the first address add1 is increased from a2 to a3).

[0065] The second address decoder 10-66 can generate a second selection signal sel2 in response to the second address add2. The second address add2 can include a second row address and a second column address, and can generate one or more second word line selection signals wlb1 to wlbbi from the second row address, and can generate one or more second column selection signals cslb11 to cslbkj from the second column address. In some embodiments, j second column selection signals (cslb11 to cslb1j), ..., or (cslbk1 to cslbkj) can correspond to one of k groups of second column selection signals cslb1 to cslbk. Each of the j second column selection signals included in the corresponding group of the k groups of second column selection signals cslb1 to cslbk can be activated, for example, by ignoring or neglecting a predetermined number of high-order or low-order bits of the second column address. The second selection signal sel2 can include the generated second word line selection signals wlb1 to wlbbi and the generated second column selection signals cslb11 to cslbkj.

[0066] The memory cell array 10-70 can output a portion of a fourth plurality of bits of data D1 from the memory cells (not shown) of memory cell group MC11 selected by the first word line selection signal (e.g., signal wlb1) in the second word line selection signal group and the first column selection signal group in the second column selection signal group (e.g., signal group cslb1, which may include signals cslb11 to cslb1j). The fourth plurality of bits of data D1 may include j data D11 to D1j. Similarly, other portions of the fourth plurality of bits of data D2 to Dk stored in memory cell groups MC12 to MC1k selected by the first word line selection signal (e.g., signal wlb1) in the second word line selection signal group and the subsequent column selection signal groups in the second column selection signal group (e.g., signal groups cslb2 to cslbk) can be output sequentially. The fourth plurality of bits of data D2 to Dk may each include j data (D21 to D2j), ..., (Dk1 to Dkj).

[0067] The following is for reference. Figure 7 , Figure 9 and Figure 10 Another read operation of storage device 10-6 is described.

[0068] Controller 10-72 can generate a second address add2 starting from a predetermined time point (e.g., offset by 90 degrees) after the time point from which the first address add1 was generated. This second address add2 increases or decreases sequentially from address a11 to address akj. For example, as... Figure 8As shown, the first address add1 can be increased from a1 to a2 on the falling edge of the buffered clock signal bck, and the second address add2 can be increased from a11 to a12 on the subsequent rising edge of the buffered clock signal bck (e.g., on the rising edge of the buffered clock signal where the first address add1 increases from a2 to a3).

[0069] The second address decoder 10-66 can generate a second selection signal sel2 in response to the second address add2. The second address add2 can include a second row address and a second column address, and can generate one or more second word line selection signals wlb1 to wlbbi from the second row address, and one or more second column selection signals cslb11 to cslbkj from the second column address. In some embodiments, k second column selection signals cslb11 to cslbkj can be activated sequentially by considering (e.g., not ignoring or not ignoring) a predetermined number of high or low bits of the second column address. The second selection signal sel2 can include the generated second word line selection signals wla1 to wlbbi and the generated second column selection signals cslb11 to cslbkj.

[0070] The memory cell array 10-70 can output a portion of the data D11 included in the fourth plurality of bits of data D1 stored in the memory cells (not shown) of a subgroup (not shown) of the memory cell group MC11 selected by the first word line selection signal (e.g., signal wlb1) in the second word line selection signal group and the first column selection signal group (e.g., signal group cslb1 (cslb11 to cslbj)) in the second column selection signal group. The fourth plurality of bits of data D1 can include j data D11 to D1j. Similarly, other portions of the data D12 to D1j included in the fourth plurality of bits of data D1 stored in the memory cells (not shown) of a subgroup (not shown) of the memory cell group MC11 selected by the first word line selection signal (e.g., signal wlb1) in the second word line selection signal group and the subsequent column selection signal groups (e.g., signal groups cslb2 (cslb21 to cslb2j) to cslbk (cslbk1 to cslbkj)) in the second column selection signal group can be output sequentially. The data D21 to D2j, ..., Dk1 to Dkj included in the fourth plurality of bits of data D2 to Dk stored in the storage cells (not shown) of the subgroups (not shown) of the storage cell groups MC12 to MC1k can also be output sequentially.

[0071] That is, refer to Figures 7 to 10The storage device 10-6 can sequentially store the third or more bits of data idq using a first-in, first-out (FIFO) method, and can sequentially output the fourth or more bits of data tdq. The number of bits in the fourth or more bits can be the same as or less than the number of bits in the third or more bits.

[0072] In some embodiments, unlike those shown, the second read / write control signal RWC2 may not be fixed, and even when from Figure 3 When the processing unit 10-8 applies a signal with a second state or a second voltage (e.g., ground voltage level) to the controller 10-72, the storage device 10-6 can also perform as shown in the reference. Figures 7 to 10 The aforementioned read operation.

[0073] Figure 11 This is a block diagram illustrating some exemplary embodiments of a processing unit 10-8 according to the present invention. The processing unit 10-8 may include a register 10-82, a parallel-to-serial converter 10-84, a communication interface unit 10-86, and a control signal and clock signal generator 10-88. The following describes... Figure 11 The function of each box shown.

[0074] Input unit 10-82 can receive and store a fourth or more bits of data tdq to generate a fifth or more bits of data itdq.

[0075] The parallel-to-serial converter 10-84 can convert a fifth or more bits of data itdq into serial data in response to an internal clock signal ick, so as to sequentially generate a single bit of serial data sdq.

[0076] The communication interface unit 10-86 can receive data rdata to generate control data cdq, and can send serial data sdq as monitoring data mdata.

[0077] The control signal and clock signal generator 10-88 can set the state of the second read / write control signal RWC2 and the frequency of the internal clock signal ick via control data cdq, and can also generate the internal clock signal ick. For example, the control data cdq can be data used to set the baud rate, the number of data bits, the number of parity bits, the number of end bits, receiver access permission, transmitter access permission, etc. The frequency of the internal clock signal ick can be set via the baud rate, and the state of the second read / write control signal RWC2 can be set via transmitter access permission. Furthermore, the number of data bits can be set via the number of data bits. For example, the control signal and clock signal generator 10-88 can include a predetermined number of control registers (not shown) and a clock signal generator (not shown).

[0078] Figure 11 The processing unit 10-8 shown can generate monitoring data mdata using a serial communication method. As an example, processing unit 10-8 can be a Universal Synchronous / Asynchronous Receiver / Transmitter (USART).

[0079] Figure 12 The format of monitoring data output from the processing unit is shown in some example embodiments of the present invention. Figure 12 The format is shown when the number of data bits is set to 8, the number of stop bits is set to 1, and the number of parity bits is set to 1, so that nine 8-bit data bits tdq1 to tdq9 (i.e., a total of 72 bits of data) can be sent as monitoring data mdata. However, this disclosure is not limited thereto.

[0080] Reference Figure 12 It can sequentially send 1 bit of start data START (e.g., "0") and 8 bits of data tdq1 (including...) bit by bit. First, send a start bit (START), then send the 8-bit data tdq2 (d21 to d28) and a 1-bit parity bit PA1 for tdq2. Next, send the start bit (START), the 8-bit data tdq2 (d91 to d98), and the 1-bit parity bit PA2 for tdq2 sequentially. Finally, send the start bit (START), the 8-bit data tqd9 (d91 to d98), and the 1-bit parity bit PA9 for tdq9 sequentially. When the data transmission is complete, send a 1-bit stop bit (e.g., "1").

[0081] Figure 13 This is a block diagram illustrating the configuration of a storage module according to some exemplary embodiments of the concept proposed in this invention. Figure 3 The storage module 200 shown is different; the storage module 200' may include... Figure 4 The storage and processing unit 10-10 is shown outside the buffer 10'. Although not shown, Figure 13 The buffer 10' shown may include Figure 4 The first interface unit 10-2 and the second interface unit 10-4 shown are illustrated.

[0082] Figure 13 The function and operation of the storage module 200' shown can be referred to the above reference. Figures 1 to 12 The description is easy to understand.

[0083] In some embodiments, buffer 10 or buffer 10' and storage and processing unit 10-10 may, as described above, store at least a portion of the buffered write data and / or at least a portion of the buffered command / address and generate monitoring data mdata. In some embodiments, buffer 10 or buffer 10' and storage and processing unit 10-10 may also store the buffered clock signal and include the buffered clock signal in the monitoring data mdata.

[0084] Accordingly, the storage module can support a monitoring device that can more easily monitor data and / or commands / addresses by sending or forwarding data and / or commands / addresses sent from the control unit to the storage unit via monitoring terminals.

[0085] Although this disclosure has been specifically shown and described with reference to some exemplary embodiments, it will be apparent to those skilled in the art that various changes in form and detail may be made without departing from the inventive concept of this disclosure. Therefore, the above embodiments are to be interpreted in all respects as illustrative and not restrictive.

Claims

1. A storage module, comprising: The first plurality of terminals, the first plurality of terminals including a plurality of command / address terminals; The second plurality of terminals includes a plurality of data terminals; At least one monitoring terminal; A buffer configured to receive and buffer a second plurality of bits of data applied through the data terminal to generate buffered write data of the second plurality of bits, and configured to receive and buffer a first plurality of bits of command / address applied through the command / address terminal to generate buffered command / address of the first plurality of bits, wherein the buffer is further configured to buffer the buffered write data of the second plurality of bits and the buffered command / address of the first plurality of bits to generate module data and module command / address, wherein the buffer is further configured to store at least a portion of the buffered write data of the second plurality of bits, and wherein the buffer is further configured to transmit the stored at least a portion of the buffered write data of the second plurality of bits as monitoring data through the at least one monitoring terminal; and Multiple semiconductor memory devices are configured to receive and store module data in response to the module command / address. The buffer includes: A first interface unit is configured to buffer the data of the second plurality of bits and the command / address of the first plurality of bits to generate write data of the buffer of the second plurality of bits and the command / address of the buffer of the first plurality of bits. A second interface unit, configured to buffer write data of the second plurality of bits and commands / addresses of the first plurality of bits, to generate the module data and the module commands / addresses; and A storage and processing unit configured to store at least a portion of the write data of the second plurality of bits buffer and serially transmit the stored at least a portion of the write data of the second plurality of bits buffer as the monitoring data to the at least one monitoring terminal.

2. The storage module according to claim 1, wherein, The buffer is further configured to store at least a portion of the command / address of the first plurality of bits of the buffer, and wherein the buffer is further configured to transmit at least a portion of the stored command / address of the first plurality of bits of the buffer as the monitoring data via the at least one monitoring terminal.

3. The storage module according to claim 1, wherein, The first interface unit includes: A data input buffer, configured to buffer the second plurality of bits of data to generate buffered write data for the second plurality of bits; A command / address input buffer, configured to buffer the first plurality of bits of command / address to generate a buffered command / address of the first plurality of bits; and A clock signal input buffer, configured to buffer clock signals to generate a buffered clock signal.

4. The storage module according to claim 1, wherein, The first interface unit is also configured to buffer the clock signal to generate a buffered clock signal, and The storage and processing unit includes: A storage device configured to: in response to a clock signal of the buffer, store at least a portion of the write data of the second plurality of bits of the buffer, and output the stored at least a portion of the write data of the second plurality of bits of the buffer; and A processing unit configured to receive at least a portion of the write data of the second plurality of stored bits in a buffer, and convert the received data into serial data to generate the monitoring data.

5. The storage module according to claim 4, wherein, The storage device is a dual-port memory including a first port and a second port, wherein the dual-port memory is configured to use a first-in-first-out method to store at least a portion of the write data of the second plurality of bits buffered by the first port, and to output the at least a portion of the write data of the second plurality of bits buffered by the second port.

6. The storage module according to claim 4, wherein, The storage device is further configured to store at least a portion of the command / address of the first plurality of bit buffers and output the stored at least a portion of the command / address of the first plurality of bit buffers, and wherein the processing unit is configured to receive the stored at least a portion of the command / address of the first plurality of bit buffers and convert the received data into serial data.

7. A storage module, comprising: The first plurality of terminals, the first plurality of terminals including a plurality of command / address terminals; The second plurality of terminals includes a plurality of data terminals; At least one monitoring terminal; A buffer configured to receive and buffer data applied through the data terminal and commands / addresses applied through the command / address terminal, wherein the buffer is configured to generate buffered write data and buffered commands / addresses, and wherein the buffer is further configured to buffer the buffered write data and the buffered commands / addresses to generate module data and module commands / addresses. A storage and processing unit configured to store at least a portion of the write data of the buffer, and configured to transmit the stored at least a portion of the write data of the buffer as monitoring data via the at least one monitoring terminal; and Multiple semiconductor memory devices are configured to receive and store module data in response to the module command / address. The buffer includes: A first interface unit, configured to buffer the data and the command / address to generate buffered write data and buffered command / address; and The second interface unit is configured to buffer the write data of the buffer and the command / address of the buffer to generate the module data and the module command / address.

8. The storage module according to claim 7, wherein, The storage and processing unit is further configured to store at least a portion of the commands / addresses of the buffer, and is configured to send the stored at least a portion of the commands / addresses of the buffer to the at least one monitoring terminal.

9. The storage module according to claim 7, wherein, The first interface unit includes: A data input buffer, configured to buffer the data to generate the buffered write data; A command / address input buffer, configured to buffer the command / address to generate the buffered command / address; and A clock signal input buffer, configured to buffer clock signals to generate a buffered clock signal.

10. The storage module according to claim 7, wherein, The first interface unit is further configured to buffer clock signals to generate buffered clock signals, and wherein the storage and processing unit includes: A storage device configured to: in response to a clock signal of the buffer, store at least a portion of the write data of the buffer, and output the stored at least a portion of the write data of the buffer; and A processing unit configured to receive at least a portion of the write data of the stored buffer and convert the received data into serial data to generate the monitoring data.

11. The storage module according to claim 10, wherein, The storage device is a dual-port memory including a first port and a second port, and The dual-port memory is configured to use a first-in-first-out (FIFO) method to store at least a portion of the write data of the buffer through the first port and to output the at least a portion of the stored write data of the buffer through the second port.

12. The storage module according to claim 10, wherein, The processing unit is a universal synchronous / asynchronous transmitter / receiver.

13. A storage system, comprising: Control unit, the control unit includes: The processor is configured to execute programs to generate internal commands, internal addresses, and internal data. A clock signal generator, configured to generate a clock signal. A command / address generator, configured to: in response to the clock signal, receive the internal command and the internal address to generate a first plurality of bits of command / address, and Data input and output units, configured to receive the internal data to generate a second plurality of bits of data; and Storage module, the storage module comprising: The first plurality of terminals, comprising a plurality of command / address terminals. The second plurality of terminals, comprising a plurality of data terminals, At least one monitoring terminal, A buffer configured to receive and buffer second plurality of bits of data applied through the data terminal and first plurality of bits of command / address applied through the command / address terminal, to generate buffered write data of the second plurality of bits and buffered command / address of the first plurality of bits, the buffer further configured to buffer the buffered write data of the second plurality of bits and buffered command / address of the first plurality of bits to generate module data and module command / address. A storage and processing unit, configured to store at least a portion of the write data of the second plurality of bits buffer, and to transmit the at least a portion of the stored write data of the second plurality of bits buffer as monitoring data via the at least one monitoring terminal. Multiple semiconductor memory devices are configured to receive and store module data in response to the module command / address. The buffer includes: A first interface unit, configured to buffer the second plurality of bits of data and the first plurality of bits of command / address, to generate write data for the second plurality of bits of buffer and the command / address for the first plurality of bits of buffer; and The second interface unit is configured to buffer the write data of the second plurality of bits and the command / address of the first plurality of bits to generate the module data and the module command / address.

14. The storage system according to claim 13, wherein, The buffer is configured to also store at least a portion of the command / address of the first plurality of bits of the buffer, and to transmit the at least a portion of the stored command / address of the first plurality of bits of the buffer as the monitoring data via the at least one monitoring terminal.

15. The storage system according to claim 13, wherein, The buffer includes the storage and processing unit.

16. The storage system according to claim 13, wherein, The storage and processing unit is configured to store at least a portion of the write data of the second plurality of bits buffer, and to serially transmit the at least a portion of the stored write data of the second plurality of bits buffer as the monitoring data via the at least one monitoring terminal.

17. The storage system according to claim 16, wherein, The first interface unit is further configured to buffer the clock signal to generate a buffered clock signal, and wherein the storage and processing unit includes: A storage device configured to: in response to a clock signal of the buffer, store at least a portion of the write data of the second plurality of bits of the buffer, and output the stored at least a portion of the write data of the second plurality of bits of the buffer; and A processing unit configured to receive at least a portion of the write data of the second plurality of stored bits in a buffer, and convert the received data into serial data to generate the monitoring data.

18. The storage system according to claim 17, wherein, The storage device is a dual-port memory including a first port and a second port, wherein the dual-port memory uses a first-in-first-out method to store at least a portion of the write data of the second plurality of bits buffer through the first port and to output the at least a portion of the stored write data of the second plurality of bits buffer through the second port, and wherein the processing unit is a universal synchronous / asynchronous transmitter / receiver.

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