Light emitting display device and method of manufacturing the same

Abstract

The present application relates to a light emitting display device and a manufacturing method thereof. The present disclosure provides a light emitting display device and a manufacturing method thereof, the light emitting display device including: a first substrate and a second substrate; a first circuit layer disposed on one surface of the first substrate; a second circuit layer disposed on one surface of the second substrate facing the first substrate; a first pad layer disposed on one surface of the first circuit layer; a second pad layer disposed on one surface of the second circuit layer and electrically connected to the first pad layer; and a light emitting element layer disposed on the other surface of the second substrate not facing the first substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a light emitting display apparatus and a manufacturing method thereof. BACKGROUND

[0002] A light emitting display apparatus includes a light emitting element in which a light emitting layer is formed between an anode and a cathode, and is an apparatus that displays an image by causing the light emitting layer to emit light through an electric field between the two electrodes.

[0003] In order to cause the light emitting layer to emit light, a pixel circuit should be provided in a display area, and a driving circuit should be provided in a non-display area outside the display area, so as to apply various signals to the pixel circuit.

[0004] Since such a conventional light emitting display apparatus should include the pixel circuit and the driving circuit, there is a limitation in enlarging a light emitting area. SUMMARY

[0005] The present disclosure is designed to solve the above-described conventional problems, and the present disclosure relates to providing a light emitting display apparatus capable of enlarging a light emitting area and a manufacturing method thereof.

[0006] According to an aspect of the present disclosure, there is provided a light emitting display apparatus including a first substrate and a second substrate, a first circuit layer provided on one surface of the first substrate, a second circuit layer provided on one surface of the second substrate facing the first substrate, a first pad layer provided on one surface of the first circuit layer, a second pad layer provided on one surface of the second circuit layer and electrically connected to the first pad layer, and a light emitting element layer provided on the other surface of the second substrate not facing the first substrate.

[0007] According to another aspect of the present disclosure, there is provided a method of manufacturing a light emitting display apparatus, the method including forming a first circuit layer on one surface of a first substrate and forming a first pad layer on one surface of the first circuit layer, forming a second circuit layer on one surface of a second substrate and forming a second pad layer on one surface of the second circuit layer, aligning the first substrate with the second substrate such that the first pad layer and the second pad layer face each other, and then electrically connecting the first pad layer and the second pad layer, and forming a light emitting element layer on the other surface of the second substrate not facing the first substrate. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0009] Figure 1 is a schematic configuration diagram of a light emitting display apparatus according to an embodiment of the present disclosure;

[0010] Figure 2 is an equivalent circuit diagram of a pixel in a light emitting display device according to an embodiment of the present disclosure;

[0011] Figure 3 is a schematic cross-sectional view of a light emitting display device according to an embodiment of the present disclosure;

[0012] Figure 4 is a cross-sectional view of a light emitting display device according to another embodiment of the present disclosure;

[0013] Figure 5 is a cross-sectional view of a light emitting display device according to still another embodiment of the present disclosure;

[0014] Figures 6A to 6G is a cross-sectional view illustrating a manufacturing process of a light emitting display device according to an embodiment of the present disclosure; and

[0015] Figures 7A to 7F is a cross-sectional view illustrating a manufacturing process of a light emitting display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Advantages and features of the present disclosure and methods for achieving them will be apparent from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but will be implemented in various forms, and the embodiments of the present disclosure only make the disclosure of the present disclosure complete and are provided to fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure pertains, and the present disclosure is only limited by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are merely exemplary, and thus the present disclosure is not limited to the illustrated matters. Throughout the specification, like reference numerals refer to like components. Also, in the description of the present disclosure, when it is determined that a detailed description of the related art can unnecessarily obscure the gist of the present disclosure, a detailed description thereof will be omitted. When "include", "have" and "consist of" mentioned in the specification are used, other components can be added unless "only" is used. Unless otherwise specified, the case where a component is expressed in singular includes the case where a plurality of components is included.

[0018] In interpreting elements, although there is no other explicit description, the description is to be interpreted to include an error range.

[0019] In the case of describing a positional relationship, for example, when the positional relationship of two components is described as "on", "above", "below", "next to", or the like, other components can be located between the two components as long as "immediately" or "directly" is not used.

[0020] In the case of describing a temporal relationship, for example, when a temporal priority relationship is described using "after", "follow", "next", "before", or the like, a discontinuous case can also be included as long as "immediately" or "directly" is not used.

[0021] The terms "first", "second", and the like are used to describe various elements, but the elements are not limited by the terms. The terms are used only to distinguish one element from another element. Accordingly, the first element mentioned below can be the second element within the technical scope of the present disclosure.

[0022] Each feature of the various embodiments of the present disclosure can be partially or entirely coupled or combined with each other, various interlocking and driving are technically possible, and each embodiment can be independently executed with respect to each other or can be executed together in an association relationship.

[0023] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a schematic configuration diagram of a light emitting display apparatus according to an embodiment of the present disclosure.

[0025] As can be seen in Figure 1 , the light emitting display apparatus according to an embodiment of the present disclosure includes a pixel unit 10 and driving units 20, 30, 40.

[0026] The pixel unit 10 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels P disposed on a substrate. The plurality of gate lines GL and the plurality of data lines DL are arranged to cross each other to define a plurality of pixel regions, and the plurality of pixels P are disposed in the plurality of pixel regions.

[0027] Each of the plurality of pixels P displays an image according to a gate signal provided from an adjacent gate line GL and a data signal provided from an adjacent data line DL. Each of the plurality of pixels P can be defined as a region of a minimum unit of light emission and can be denoted as a sub-pixel. Accordingly, a combination of the plurality of pixels P adjacent to each other can form one unit pixel for displaying a color. For example, one unit pixel can be formed by a combination of three pixels P of red, green, and blue arranged adjacent to each other, but the present disclosure is not necessarily limited thereto.

[0028] Each of the plurality of pixels P includes a pixel circuit and a light emitting element connected to the pixel circuit, which will be described later with reference to Figure 2A description thereof will be given.

[0029] The drive units 20, 30, and 40 include a control circuit 20, a data drive circuit 30, and a gate drive circuit 40.

[0030] The control circuit 20 can generate pixel data for each pixel corresponding to each of the plurality of pixels P based on an image signal to supply the generated pixel data to the data drive circuit 30. Further, the control circuit 20 generates a data control signal based on a timing synchronization signal to supply the data control signal to the data drive circuit 30. Further, the control circuit 20 generates a gate control signal based on the timing synchronization signal to supply the gate control signal to the gate drive circuit 40.

[0031] The data drive circuit 30 is connected to a plurality of data lines DL provided in the pixel unit 10. The data drive circuit 30 receives the pixel data for each pixel and the data control signal supplied from the control circuit 20, and receives a plurality of reference gamma voltages supplied from a power supply circuit. The power supply circuit can be included in the drive units 20, 30, and 40 as a separate component. The data drive circuit 30 converts the pixel data for each pixel into a data signal for each pixel using the data control signal and the plurality of reference gamma voltages, and supplies the converted data signal for each pixel to the corresponding data line DL.

[0032] The gate drive circuit 40 is connected to a plurality of gate lines GL provided in the pixel unit 10. The gate drive circuit 40 generates a gate signal based on the gate control signal supplied from the control circuit 20 according to a predetermined sequence to supply the gate signal to the corresponding gate line GL.

[0033] Figure 2 is an equivalent circuit diagram of a pixel in a light emitting display device according to an embodiment of the disclosure.

[0034] As can be seen from Figure 2 A pixel of a light emitting display device according to an embodiment of the disclosure includes a pixel circuit PC and a light emitting element ED.

[0035] The pixel circuit PC is provided in a pixel region defined by the gate line GL and the data line DL, and is connected to the adjacent gate line GL, data line DL, and power supply line PL. The pixel circuit PC controls light emission of the light emitting element ED according to a data signal Vdata from the data line DL in response to a gate-on signal GS from the gate line GL, and can include at least two thin film transistors and at least one capacitor. The pixel circuit PC according to an embodiment includes a switching thin film transistor ST, a driving thin film transistor DT, and a capacitor Cst.

[0036] The switching thin-film transistor ST can include a gate electrode connected to the gate line GL, a source electrode or a drain electrode connected to the data line DL, and a drain electrode or a source electrode connected to the gate electrode of the driving thin-film transistor DT. The switching thin-film transistor ST is turned on according to a gate-on signal GS provided to the gate line GL, and provides a data signal Vdata provided to the data line DL to the gate electrode of the driving thin-film transistor DT.

[0037] The driving thin-film transistor DT includes a gate electrode connected to the drain electrode or the source electrode of the switching thin-film transistor ST, a drain electrode or a source electrode connected to the first driving power source VDD through the power supply line PL, and a source electrode or a drain electrode connected to the light emitting element ED. The driving thin-film transistor DT is turned on according to a gate-source voltage based on the data signal Vdata provided from the switching thin-film transistor ST to control a current provided to the light emitting element ED from the first driving power source VDD.

[0038] The capacitor Cst is connected between the gate electrode and the source electrode of the driving thin-film transistor DT or between the gate electrode and the drain electrode of the driving thin-film transistor DT to store a voltage corresponding to the data signal Vdata provided to the gate electrode of the driving thin-film transistor DT, and the driving thin-film transistor DT is turned on by the stored voltage. In this case, the capacitor Cst can maintain a state in which the driving thin-film transistor DT is turned on until a new data signal Vdata is provided via the switching thin-film transistor ST in the next frame.

[0039] The light emitting element ED is disposed in a light emitting region in the pixel region and emits light according to a current provided from the pixel circuit PC. The light emitting element ED includes a first electrode connected to the source electrode or the drain electrode of the driving thin-film transistor DT, a second electrode connected to the second driving power source VSS, and a light emitting layer disposed between the first electrode and the second electrode. Here, the light emitting layer can include at least one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer.

[0040] Figure 3 is a schematic cross-sectional view of a light emitting display apparatus according to an embodiment of the disclosure.

[0041] As can be seen from Figure 3 , the light emitting display apparatus according to an embodiment of the disclosure includes a first substrate 100, a first circuit layer 110, first pad layers 121, 122, and 123, a second substrate 200, a second circuit layer 210, second pad layers 221, 222, and 223, and a light emitting element layer 230.

[0042] The first substrate 100 constitutes a lower substrate of the light emitting display apparatus and can be made of a semiconductor substrate such as silicon.

[0043] The first circuit layer 110 is formed on one surface of the first substrate 100. Specifically, the first circuit layer 110 is formed on the upper surface of the first substrate 100 facing the second substrate 200. The above-described Figure 1 The driving units 20, 30, and 40 can be formed on the first circuit layer 110. Specifically, at least one of the control circuit 20, the data driving circuit 30, the gate driving circuit 40, and the power supply circuit can be formed on the first circuit layer 110. When the first substrate 100 is made of a semiconductor substrate such as silicon, a part of the circuits constituting the driving units 20, 30, and 40 can be formed inside the first substrate 100, and the remaining part of the circuits constituting the driving units 20, 30, and 40 can be formed in the first circuit layer 110. For example, the circuits constituting the driving units 20, 30, and 40 can be formed of various thin film transistors and various lines, and the various thin film transistors can be formed inside the first substrate 100, and the various lines can be formed on the first circuit layer 110.

[0044] The first pad layers 121, 122, and 123 are formed on one surface of the first circuit layer 110, specifically, on the upper surface of the first circuit layer 110 facing the second substrate 200. The first pad layers 121, 122, and 123 include the first pad 121 disposed in the first pixel P1, the first pad 122 disposed in the second pixel P2, and the first pad 123 disposed in the third pixel P3. The first pad layers 121, 122, and 123 can be connected to the data driving circuit 30 of the first circuit layer 110, can be connected to the gate driving circuit 40 of the first circuit layer 110, or can be connected to the power supply circuit of the first circuit layer 110.

[0045] The second substrate 200 constitutes an upper substrate of the light emitting display apparatus and can include an electrically conductive material. For example, the second substrate 200 can include a semiconductor material such as silicon. The second substrate 200 includes an electrically conductive material so that the second circuit layer 210 formed on one surface of the second substrate 200 and the light emitting element layer 230 formed on the other surface of the second substrate 200 can be electrically connected to each other.

[0046] The second circuit layer 210 is formed on one surface of the second substrate 200, specifically, on the lower surface of the second substrate 200 facing the first substrate 100. The above-described Figure 2 The pixel circuit PC described above can be formed in the second circuit layer 210 for each of the pixels P1, P2, and P3. That is, the gate line GL, the data line DL, the power supply line PL, the switching thin film transistor ST, the driving thin film transistor DT, and the capacitor Cst are formed in the second circuit layer 210.

[0047] When the second substrate 200 is made of a semiconductor substrate such as silicon, a part of the circuit constituting the pixel circuit PC can be formed inside the second substrate 200, and the remaining part of the circuit constituting the pixel circuit PC can be formed in the second circuit layer 210. For example, a part of the thin film transistors such as the switching thin film transistor ST and the drive thin film transistor DT is formed inside the second substrate 200, and the lines such as the gate line GL, the data line DL, and the power supply line PL can be formed in the second circuit layer 210 together with the remaining part of the thin film transistors.

[0048] The second pad layers 221, 222, and 223 are formed on one surface of the second circuit layer 210, specifically, on the lower surface of the second circuit layer 210 facing the first substrate 100. The second pad layers 221, 222, and 223 include the second pad 221 provided in the first pixel P1, the second pad 222 provided in the second pixel P2, and the second pad 223 provided in the third pixel P3. The second pad layers 221, 222, and 223 can be connected to the gate lines GL of the second circuit layer 210, can be connected to the data lines DL of the second circuit layer 210, and can be connected to the power supply lines PL of the second circuit layer 210.

[0049] The second pad layers 221, 222, and 223 are electrically connected to the first pad layers 121, 122, and 123, respectively. When the second pad layers 221, 222, and 223 are connected to the gate lines GL of the second circuit layer 210, the first pad layers 121, 122, and 123 are connected to the gate drive circuit 40 of the first circuit layer 110, and thus the gate signals generated from the gate drive circuit 40 of the first circuit layer 110 can be supplied to the gate lines GL of the second circuit layer 210 through the first pad layers 121, 122, and 123 and the second pad layers 221, 222, and 223. Further, when the second pad layers 221, 222, and 223 are connected to the data lines DL of the second circuit layer 210, the first pad layers 121, 122, and 123 are connected to the data drive circuit 30 of the first circuit layer 110, and thus the data signals generated from the data drive circuit 30 of the first circuit layer 110 can be supplied to the data lines DL of the second circuit layer 210 through the first pad layers 121, 122, and 123 and the second pad layers 221, 222, and 223. Further, when the second pad layers 221, 222, and 223 are connected to the power supply lines PL of the second circuit layer 210, the first pad layers 121, 122, and 123 are connected to the power supply circuit of the first circuit layer 110, and thus the power generated from the power supply circuit of the first circuit layer 110 can be supplied to the power supply lines PL of the second circuit layer 210 through the first pad layers 121, 122, and 123 and the second pad layers 221, 222, and 223.

[0050] The lower surfaces of the second pad layers 221, 222, and 223 can be in direct contact with the upper surfaces of the first pad layers 121, 122, and 123, respectively, but the present disclosure is not limited thereto. For example, an insulating layer can be additionally formed between the second pad layers 221, 222, and 223 and the first pad layers 121, 122, and 123, and the second pad layers 221, 222, and 223 and the first pad layers 121, 122, and 123 can be electrically connected by separate connection electrodes passing through the insulating layer.

[0051] The electrical connection between the second pad layers 221, 222, and 223 and the first pad layers 121, 122, and 123 is made for each of the pixels P1, P2, and P3. That is, the first pad 121 and the second pad 221 provided in the first pixel P1 are electrically connected to each other, the first pad 122 and the second pad 222 provided in the second pixel P2 are electrically connected to each other, and the first pad 123 and the second pad 223 provided in the third pixel P3 are electrically connected to each other.

[0052] The light emitting element layer 230 is formed on the other surface of the second substrate 200, specifically, on the upper surface of the second substrate 200 not facing the first substrate 100.

[0053] A part of the light emitting element ED described above Figure 2 may be formed in the light emitting element layer 230, and the remaining part of the light emitting element ED can be formed in the second substrate 200. Specifically, the first electrode of the light emitting element ED connected to the source electrode or the drain electrode of the driving thin film transistor DT is formed in the second substrate 200, and the light emitting layer and the second electrode can be formed in the light emitting element layer 230. In this case, the first electrode can be made of a semiconductor material.

[0054] As described above, according to the embodiment of the present disclosure, the first circuit layer 110 provided with the driving units 20, 30, and 40 is formed on one surface of the first substrate 100, the second circuit layer 210 provided with the pixel circuit PC is formed on one surface of the second substrate 200 facing the first substrate 100, and the light emitting element layer 230 is formed on the other surface of the second substrate 200 not facing the first substrate 100, so that the light emitting area of the light emitting element layer 230 can be enlarged.

[0055] Figure 4 is a cross-sectional view of a light emitting display device according to another embodiment of the present disclosure.

[0056] From Figure 4As can be seen, the light emitting display device according to another embodiment of the disclosure includes a first substrate 100, a first circuit layer 110, first pad layers 121, 122, and 123, a second substrate 200, a second circuit layer 210, second pad layers 221, 222, and 223, and a light emitting element layer 230.

[0057] Since the first substrate 100, the first circuit layer 110, and the first pad layers 121, 122, and 123 are the same as those described above Figure 3 with regard to the first substrate 100, the first circuit layer 110, and the first pad layers 121, 122, and 123, a repeated description will be omitted.

[0058] The second substrate 200 includes a semiconductor material such as silicon. Specifically, the second substrate 200 includes a base layer 201 made of a semiconductor material, a first doped layer 202 formed on one surface (specifically, a lower surface) of the base layer 201, and a second doped layer 203 formed on the other surface (specifically, an upper surface) of the base layer 201. For example, when the base layer 201 is made of a P-type semiconductor material, the first doped layer 202 and the second doped layer 203 can be made of a P+ type semiconductor material doped with a trivalent dopant having the same polarity as the base layer 201.

[0059] According to the embodiment of the disclosure, the first electrode E1 that can be used as an anode of the light emitting element ED can be formed of a combination of the base layer 201, the first doped layer 202, and the second doped layer 203. The work function of a highly doped semiconductor material such as P+ type silicon is greater than 5 eV. In contrast, the work function of indium tin oxide (ITO) that is used as a conventional anode of a light emitting element ED is about 4.7 eV, and the work function of Al is about 4.3 eV. Accordingly, according to the embodiment of the disclosure, it is possible to improve light emitting efficiency by using a semiconductor material having a high work function as the first electrode E1 of the light emitting element ED.

[0060] The first electrode E1 of the light emitting element ED formed of a combination of the base layer 201, the first doped layer 202, and the second doped layer 203 is individually provided for each of the pixels P1, P2, P3, and specifically, the first electrode E1 for each of the pixels P1, P2, P3 is spaced apart by a trench 205. That is, the trench 205 is provided in the second substrate 200, and an insulating material is provided in the trench 205, so that the first electrodes E1 of the light emitting elements ED for each of the pixels P1, P2, P3 are insulated from each other by the insulating material in the trench 205. In this case, the trench 205 can be formed in a structure in which the widths of the lower and upper portions are different from each other, and specifically, the width of the lower portion of the trench 205 can be formed to be greater than the width of the upper portion of the trench 205. Specifically, the width of the lower portion of the trench 205 can be the same as the distance of the second doped layer 203 from the source electrode S or the distance of the second doped layer 203 from the drain electrode D.

[0061] A thin film transistor (e.g., a drive thin film transistor DT) can be disposed in a boundary region between the plurality of pixels P1, P2, and P3. Specifically, a source electrode S and a drain electrode D of the drive thin film transistor DT can be formed between the first doped layer 202 in one of the pixels P1, P2, and P3 and the first doped layer 202 in another pixel adjacent thereto among the pixels P1, P2, and P3. Specifically, the source electrode S and the drain electrode D of the drive thin film transistor DT can be formed between one trench 205 and another trench 205 adjacent thereto in the boundary region between the plurality of pixels P1, P2, and P3. Throughout the present specification, the boundary region between the plurality of pixels P1, P2, and P3 refers to a region overlapping with a region in which the bank 231 in which the light emitting element layer 230 is formed.

[0062] The source electrode S and the drain electrode D can be made of an N-type semiconductor material doped with a pentavalent dopant having a polarity different from that of the base layer 201 in a partial region of the lower surface of the base layer 201. Accordingly, the second substrate 200 can include the source electrode S and the drain electrode D of the drive thin film transistor DT. In addition, another region on the lower surface of the base layer 201 corresponding to a region between the source electrode S and the drain electrode D can serve as a channel region of the drive thin film transistor DT.

[0063] The base layer 201 and the second doped layer 203 can be sequentially formed on the upper surface of the source electrode S and the drain electrode D. The source / drain electrode S / D and the base layer 201 and the second doped layer 203 sequentially formed thereon are spaced apart from the first electrode E1 of the light emitting element ED, and the trench 205 is interposed therebetween.

[0064] The second circuit layer 210 is formed on the lower surface of the second substrate 200 facing the first substrate 100.

[0065] The gate electrode G of the drive thin film transistor DT, the first connection line CL1 connecting the drive thin film transistor DT and the second pad layers 221, 222, and 223, and the second connection line CL2 connecting the drive thin film transistor DT and the first electrode E1 of the light emitting element ED are formed in the second circuit layer 210.

[0066] Specifically, the second circuit layer 210 can include a first insulating layer 211 formed on the lower surface of the second substrate 200, a gate electrode G formed on the lower surface of the first insulating layer 211, a second insulating layer 212 formed on the lower surface of the gate electrode G, a first connection line CL1 and a second connection line CL2 formed on the lower surface of the second insulating layer 212, and a third insulating layer 213 formed on the lower surface of the first connection line CL1 and the second connection line CL2.

[0067] The first insulating layer 211 can insulate the gate electrode G from the source electrode / drain electrode S / D, the second insulating layer 212 can insulate the gate electrode G from the first connection line CL1 / second connection line CL2, and the third insulating layer 213 can serve as a protective layer of the second circuit layer 210. Vias are formed in the first insulating layer 211, the second insulating layer 212, and the third insulating layer 213, respectively.

[0068] The drain electrode D of the drive thin film transistor DT can be electrically connected to the first connection line CL1 through a via provided in the first insulating layer 211 and the second insulating layer 212, and the first connection line CL1 can be electrically connected to the second pad layers 221, 222, and 223 through a via provided in the third insulating layer 213, so the drain electrode D of the drive thin film transistor DT can be electrically connected to the second pad layers 221, 222, and 223. In this case, the first connection line CL1 can serve as a power line PL.

[0069] Further, the source electrode S of the drive thin film transistor DT can be electrically connected to the second connection line CL2 through a via provided in the first insulating layer 211 and the second insulating layer 212, and the second connection line CL2 can be electrically connected to the first electrode E1 (specifically, the second doped layer 203) of the light emitting element ED through a via provided in the first insulating layer 211 and the second insulating layer 212, so the source electrode S of the drive thin film transistor DT can be electrically connected to the first electrode E1 of the light emitting element ED.

[0070] In some cases, the source electrode S of the drive thin film transistor DT can be electrically connected to the second pad layers 221, 222, and 223, and the drain electrode D of the drive thin film transistor DT can be electrically connected to the first electrode E1 of the light emitting element ED.

[0071] The second pad layers 221, 222, and 223 are formed on a lower surface of the second circuit layer 210 facing the first substrate 100. The second pad layers 221, 222, and 223 include a second pad 221 provided in the first pixel P1, a second pad 222 provided in the second pixel P2, and a second pad 223 provided in the third pixel P3, and each of the second pads 221, 222, and 223 can be electrically connected to the drain electrode D of the drive thin film transistor DT through the first connection line CL1 serving as a power line PL in the second circuit layer 210.

[0072] The second pad layers 221, 222, and 223 are electrically connected to the first pad layers 121, 122, and 123, respectively. In this case, the first pad layers 121, 122, and 123 are connected to the power supply circuit of the first circuit layer 110, and thus the power generated by the power supply circuit of the first circuit layer 110 can be supplied to the drain electrode D of the driving thin film transistor DT through the first pad layers 121, 122, and 123, the second pad layers 221, 222, and 223, the plurality of through-holes, and the first connection line CL1.

[0073] The light emitting element layer 230 is formed on the upper surface of the second substrate 200 not facing the first substrate 100.

[0074] The light emitting element layer 230 includes a bank 231, a light emitting layer 232, and a second electrode 233.

[0075] The bank 231 is formed on the upper surface of the second substrate 200, specifically, on the upper surface of the second doped layer 203 disposed in the boundary region between the pixels P1, P2, and P3. The bank 231 is formed in a mesh shape in a planar structure to define a light emitting region for each of the pixels P1, P2, and P3. Accordingly, the bank 231 is formed in the boundary region between the pixels P1, P2, and P3, and light emission can occur in a region where the bank 231 is not formed. The bank 231 can be formed of an inorganic insulating material or an organic insulating material. The bank 231 can be formed in a multi-layer structure, for example, in a two-layer structure consisting of a lower layer made of an inorganic insulating material and an upper layer made of an organic insulating material. The bank 231 can be formed to overlap the trench 205 so that the light emitting layer 232 does not come into contact with the trench 205.

[0076] The light emitting layer 232 is disposed on the first electrode E1 in the second substrate 200. Specifically, the light emitting layer 232 is formed on the upper surface of the second doped layer 203 in the pixels P1, P2, and P3. The light emitting layer 232 can include a red (R) light emitting layer, a green (G) light emitting layer, and a blue (B) light emitting layer patterned for each of the pixels P1, P2, and P3. However, the present disclosure is not necessarily limited thereto, and the light emitting layer 232 can be disposed to emit white light by including a plurality of layer stack structures emitting different colors of light. When the light emitting layer 232 includes a plurality of layer stack structures, the light emitting layer can not be patterned for each of the pixels P1, P2, and P3, but can be formed entirely on the upper surface of the second substrate 200, and in this case, a separate color filter can be disposed on the second electrode 233 for each of the pixels P1, P2, and P3.

[0077] The second electrode 233 is formed on the light emitting layer 232, specifically, without being patterned for each of the pixels P1, P2, and P3, but is formed entirely on the upper surface of the second substrate 200. The light emitting display device according to the embodiment of the disclosure is made in a so-called top emission method in which light emitted from the light emitting layer 232 is emitted upward, and the second electrode 233 can be made of a transparent electrode through which the light emitted from the light emitting layer 232 can be transmitted.

[0078] Figure 5 is a cross-sectional view of a light emitting display device according to still another embodiment of the disclosure. According to the light emitting display device according to the embodiment of the disclosure, Figure 5 The light emitting display device according to the embodiment of the disclosure is different from the light emitting display device according to the above-described Figure 4 The light emitting display device according to the embodiment of the disclosure is different from the light emitting display device according to the above-described

[0079] As can be seen in Figure 5 , the light emitting element layer 230 includes the bank 231, the light emitting layer 232, the second electrode 233, and the reflection layer 234.

[0080] The bank 231 includes the first bank layer 231a and the second bank layer 231b disposed on the first bank layer 231a. The thickness of the first bank layer 231a can be smaller than the thickness of the second bank layer 231b, and the width of the first bank layer 231a can be greater than the width of the second bank layer 231b. The first bank layer 231a can be made of an inorganic insulating material, and the second bank layer 231b can be made of an organic insulating material.

[0081] The reflection layer 234 can be formed between the first bank layer 231a and the second bank layer 231b. More specifically, the reflection layer 234 is formed on the edge region of the first bank layer 231a, and the second bank layer 231b is formed on a partial region of the reflection layer 234. As can be seen in the drawing shown by the arrow in Figure 5 , the reflection layer 234 can have a quadrangular frame structure in which a central region is empty, and a light emitting region is disposed in the central region. The region of the reflection layer 234 not covered by the second bank layer 231b is in contact with the light emitting layer 232. The reflection layer 234 can be made of a metal material such as silver (Ag) having excellent reflectivity, and thus light emitted from the light emitting layer 232 can be reflected by the reflection layer 234.

[0082] Since the light emitting display device according to another embodiment of the disclosure separately includes the reflection layer 234 below the light emitting layer 232 and the first electrode E1, a semiconductor material having a high work function can be used as a material of the first electrode E1, and a material having a high reflectivity can be used as a material of the reflection layer 234, so that the light emitting efficiency can be improved.

[0083] Generally, when a material having a high reflectance is used as a material of the first electrode E1 provided below the light-emitting layer 232, the light-emitting efficiency can be improved. However, it is preferable to substantially use a material having a high work function as the first electrode E1, and a material having a high work function among which a material having a high reflectance is not common. Therefore, in another embodiment of the present disclosure, a semiconductor material having a high work function is used as a material of the first electrode E1, and separately, a reflective layer 234 is formed of a material having a high reflectance, thereby maximizing the light-emitting efficiency.

[0084] The light-emitting layer 232 is in contact with each of the first electrode E1, the first bank layer 231a, the reflective layer 234, and the second bank layer 231b. Light is emitted from a portion of the light-emitting layer 232 in contact with the first electrode E1, and the emitted light is reflected by the reflective layer 234 and emitted upward.

[0085] The second electrode 233 is formed on the upper surfaces of the light-emitting layer 232 and the second bank layer 231b.

[0086] Figures 6A to 6G is a cross-sectional view illustrating a manufacturing process of a light-emitting display device according to an embodiment of the present disclosure, which involves a manufacturing process of the light-emitting display device according to the above-described Figure 5 embodiment of the light-emitting display device according to the above-described

[0087] First, as can be seen in Figure 6A , a first circuit layer 110 is formed on one surface of a first substrate 100, and first pad layers 121, 122, and 123 are formed on one surface of the first circuit layer 110. Also, a second circuit layer 210 is formed on one surface of a second substrate 200, and second pad layers 221, 222, and 223 are formed on one surface of the second circuit layer 210.

[0088] Specifically, a first doped layer 202 is formed by doping a dopant having the same polarity as the base layer 201 on one surface of the base layer 201 of the second substrate 200, and a source electrode S and a drain electrode D are formed by doping a dopant having a different polarity from the base layer 201 on one surface of the base layer 201. In this case, the first doped layer 202 is formed in the pixels P1, P2, and P3, and the source / drain electrodes S / D are formed in the boundary regions between the pixels P1, P2, and P3. In addition, a first trench 205a is formed between the source / drain electrodes S / D and the first doped layer 202, and the first trench 205a is filled with an insulating material.

[0089] Next, as can be seen in Figure 6BAs can be seen, by placing the second substrate 200 upside down on the first substrate 100, the first pad layers 121, 122 and 123 and the second pad layers 221, 222 and 223 are aligned so that they face each other, and then the first pad layers 121, 122 and 123 are electrically connected to the second pad layers 221, 222 and 223.

[0090] Next, if possible Figure 6C As can be seen, the thickness of the second substrate 200 (specifically, the thickness of the base layer 201) is reduced by grinding the other surface of the second substrate 200. Subsequently, a second doped layer 203 is formed by doping the other surface of the second substrate 200 (specifically, the other surface of the base layer 201) with a dopant having the same polarity as the base layer 201. When the thickness of the base layer 201 is too large, the resistance of the first electrode E1 of the light-emitting element may be too high; therefore, the thickness of the base layer 201 is reduced to lower the resistance of the first electrode E1.

[0091] Next, if possible Figure 6D As can be seen, a second trench 205b is formed in the region overlapping with the first trench 205a, and an insulating material is filled in the second trench 205b. Therefore, while separating each of pixels P1, P2, and P3 through the trench 205 formed by the first trench 205a and the second trench 205b, a first electrode E1 composed of a combination of a base layer 201, a first doped layer 202, and a second doped layer 203 is formed.

[0092] Next, if possible Figure 6E As can be seen, a first dam layer 231a is formed on another surface of the second substrate 200 (specifically, on the second doped layer 203 and the second trench 205b), a reflective layer 234 is patterned on the first dam layer 231a, and a second dam layer 231b is patterned on the reflective layer 234.

[0093] Next, if possible Figure 6F As can be seen, the first embankment 231a in the region of pixels P1, P2 and P3 is removed to expose the first electrode E1 underneath, which is composed of a base layer 201, a first doped layer 202 and a second doped layer 203.

[0094] Next, if possible Figure 6G As can be seen, a light-emitting layer 232 is formed on the first electrode E1 and the reflective layer 234, and a second electrode 233 is formed on the light-emitting layer 232.

[0095] Figures 7A to 7F This is a cross-sectional view illustrating the manufacturing process of a light-emitting display device according to another embodiment of the present disclosure, which relates to the above-described manufacturing process. Figure 5of another embodiment of the light-emitting display device according to the present disclosure. In the following, the same reference signs are assigned to the same configurations, and a repetitive description related to the structures and the like of the same configurations will be omitted.

[0096] First, as can be seen in Figure 7A the first substrate 100, and the first pad layers 121, 122, and 123 are formed on one surface of the first circuit layer 110. Further, the second circuit layer 210 is formed on one surface of the second substrate 200, and the second pad layers 221, 222, and 223 are formed on one surface of the second circuit layer 210.

[0097] Specifically, as in the above-described embodiment, the first doped layer 202 is formed by doping the same dopant as the base layer 201 on one surface of the base layer 201 of the second substrate 200, the source electrode S and the drain electrode D are formed by doping a dopant different in polarity from the base layer 201 on one surface of the base layer 201, the first trench 205a is formed between the source / drain electrode S / D and the first doped layer 202, and the insulating material is filled in the first trench 205a.

[0098] Further, the other surface of the base layer 201 is polished, and then the second doped layer 203 is formed by doping the same dopant as the base layer 201 on the entire other surface of the base layer 201.

[0099] As described above, according to Figures 7A to 7F the other embodiment of the present disclosure is different from the above-described embodiment according to Figures 6A to 6G the other embodiment of the present disclosure is different from the above-described embodiment according to

[0100] Next, as can be seen in Figure 7B the first pad layers 121, 122, and 123 and the second pad layers 221, 222, and 223 are aligned so as to face each other, and then the first pad layers 121, 122, and 123 are electrically connected with the second pad layers 221, 222, and 223.

[0101] Next, as can be seen in Figure 7CAs can be seen in FIG. 10A, the second trench 205b is formed in a region overlapping the first trench 205a, and the insulating material is filled in the second trench 205b. Thus, while being separated for each of the pixels P1, P2, and P3 by the trench 205 composed of the first trench 205a and the second trench 205b, the first electrode E1 composed of the combination of the base layer 201, the first doped layer 202, and the second doped layer 203 is formed. In some cases, the process of forming the second trench 205b and filling the insulating material can also be performed together with the process of forming the first doped layer 202. Figure 7C Figure 7A

[0102] Next, as can be seen in FIG. 10B, the first bank layer 231a is formed on the other surface of the second substrate 200 (specifically, on the second doped layer 203 and the second trench 205b), the reflective layer 234 is patterned on the first bank layer 231a, and the second bank layer 231b is patterned on the reflective layer 234. Figure 7D

[0103] Next, as can be seen in FIG. 10C, the first bank layer 231a in the regions of the pixels P1, P2, and P3 is removed to expose the first electrode E1 composed of the base layer 201, the first doped layer 202, and the second doped layer 203 thereunder. Figure 7E

[0104] Next, as can be seen in FIG. 10D, the light-emitting layer 232 is formed on the first electrode E1 and the reflective layer 234, and the second electrode 233 is formed on the light-emitting layer 232. Figure 7F

[0105] According to the embodiment of the present disclosure, the first circuit layer having the drive unit is formed on one surface of the first substrate, the second circuit layer having the pixel circuit is formed on the surface of the second substrate facing one surface of the first substrate, and the light-emitting element layer is formed on the other surface of the second substrate not facing the first substrate, thereby enabling the light-emitting area of the light-emitting element layer to be enlarged.

[0106] According to the embodiment of the present disclosure, since the first electrode of the light-emitting element can be formed by the combination of the base layer, the first doped layer, and the second doped layer constituting the second substrate, the first electrode can be formed of a semiconductor material having a high work function and a high concentration of doping, and thus the light-emitting efficiency can be improved.

[0107] According to another embodiment of the present disclosure, since the first electrode and the reflective layer are separately provided under the light-emitting layer, a semiconductor material having a high work function can be used as the material of the first electrode, and a material having a high reflectance can be used as the material of the reflective layer, and thus the light-emitting efficiency can be improved.

[0108] ​​​​​Embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, but the present disclosure is not necessarily limited to these embodiments and can be variously modified without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but the embodiments are intended to be described, and the scope of the technical spirit of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and are not restrictive. The scope of protection of the present disclosure should be interpreted by the claims, and all technical spirits within the equivalent scope of the claims should be interpreted as being included in the scope of the present disclosure.

[0109] Cross Reference to Related Applications

[0110] This application claims the benefit of Korean Patent Application No. 10-2020-0082810, filed July 6, 2020, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A light emitting display device comprising: a first substrate and a second substrate; a first circuit layer provided on one surface of the first substrate; a second circuit layer provided on one surface of the second substrate facing the first substrate; a first pad layer provided on one surface of the first circuit layer; a second pad layer provided on one surface of the second circuit layer and electrically connected to the first pad layer; and a light emitting element layer provided on the other surface of the second substrate not facing the first substrate, wherein the light emitting element layer is electrically connected to the second circuit layer through the second substrate. at least one circuit of a gate driver circuit, a data driver circuit, and a power supply circuit is provided in the first circuit layer, and 2. The light-emitting display device according to claim 1, wherein a gate line, a data line, a power supply line, a thin film transistor, and a capacitor are provided in the second circuit layer. the first pad layer is connected to the gate driver circuit of the first circuit layer and the second pad layer is connected to the gate line of the second circuit layer, or 3. The light-emitting display device according to claim 2, wherein the first pad layer is connected to the data driver circuit of the first circuit layer and the second pad layer is connected to the data line of the second circuit layer, or the first pad layer is connected to the power supply circuit of the first circuit layer and the second pad layer is connected to the power supply line of the second circuit layer. a first electrode of a light emitting element is provided inside the second substrate for each pixel, and a light emitting layer and a second electrode of the light emitting element are provided in the light emitting element layer.

4. The light-emitting display device according to claim 1, wherein the first electrode includes a base layer made of a semiconductor material, a first doped layer provided on one surface of the base layer, and a second doped layer provided on the other surface of the base layer, and 5. The light-emitting display device according to claim 4, wherein two adjacent first electrodes are spaced apart with a trench provided inside the second substrate therebetween. a source electrode and a drain electrode of a driving thin film transistor made of a semiconductor material are provided inside the second substrate.

6. The light-emitting display device according to claim 4, wherein one of the source electrode and the drain electrode is electrically connected to the second pad layer through a first connection line provided in the second circuit layer, and 7. The light-emitting display device according to claim 6, wherein the remaining one of the source electrode and the drain electrode is electrically connected to the first electrode through a second connection line provided in the second circuit layer. the second substrate further includes a base layer made of a semiconductor material on the source electrode and the drain electrode and a doped layer provided on the base layer, and 8. The light-emitting display device according to claim 6, wherein the base layer and the doped layer are spaced apart from the first electrode with a trench provided inside the second substrate therebetween. the light emitting element layer further includes a first bank layer, a second bank layer, and a reflective layer provided between the first bank layer and the second bank layer, and 9. The light-emitting display device according to claim 4, wherein the light emitting layer is provided in contact with the first electrode and the reflective layer. the reflective layer has a quadrangular frame structure with a central region empty, and the central region constitutes a light emitting region.

10. The light-emitting display device according to claim 9, wherein 11. A method of manufacturing a light emitting display device, the method comprising the steps of: ​ forming a first circuit layer on one surface of a first substrate and forming a first pad layer on one surface of the first circuit layer; forming a second circuit layer on one surface of a second substrate and forming a second pad layer on one surface of the second circuit layer; aligning the first substrate and the second substrate such that the first pad layer and the second pad layer face each other, and then electrically connecting the first pad layer and the second pad layer; and forming a light emitting element layer on the other surface of the second substrate which does not face the first substrate, wherein the light emitting element layer is electrically connected to the second circuit layer through the second substrate.

12. The method of claim 11, further comprising the step of: forming a first electrode of a light emitting element inside the second substrate, wherein the step of forming the light emitting element layer includes forming a light emitting layer on the first electrode and forming a second electrode on the light emitting layer.

13. The method of claim 12, wherein, The step of forming the first electrode includes forming a first doped layer on one surface of a base layer made of a semiconductor material, forming a second doped layer on the other surface of the base layer, and forming a trench in the second substrate.

14. The method of claim 13, wherein, The step of forming the first doped layer is performed before the step of electrically connecting the first pad layer and the second pad layer, and The step of forming the second doped layer is performed after the step of electrically connecting the first pad layer and the second pad layer.

15. The method of claim 13, wherein, The step of forming the first doped layer and the step of forming the second doped layer are performed before the step of electrically connecting the first pad layer and the second pad layer.

16. The method of claim 14, wherein, The step of forming the trench includes forming a first trench before electrically connecting the first pad layer and the second pad layer and forming a second trench after electrically connecting the first pad layer and the second pad layer.

17. The method of claim 15, wherein, The step of forming the trench includes forming a first trench before electrically connecting the first pad layer and the second pad layer and forming a second trench after electrically connecting the first pad layer and the second pad layer.

18. The method of claim 12, wherein, The step of forming the light emitting element layer further includes forming a first bank layer on the other surface of the second substrate, patterning a reflective layer on the first bank layer, patterning a second bank layer on the reflective layer, and removing a predetermined portion of the first bank layer so that the first electrode is exposed.

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