Flexible array substrate and display device

Abstract

The present disclosure provides a flexible array substrate and a display device, and belongs to the technical field of display. The flexible array substrate comprises at least one stretchable region; the stretchable region is divided into a pixel island region and a bridge region by a plurality of through holes, and the bridge region comprises a source-drain bridge region. The flexible array substrate comprises, in any one source-drain bridge region, a substrate, a plurality of first source-drain leads, a first insulating material layer, a plurality of second source-drain leads, a second insulating material layer and an encapsulation layer which are sequentially stacked; the number of the second source-drain leads is less than the number of the first source-drain leads; the second insulating material layer is provided with a plurality of isolation grooves, and the orthographic projection of the isolation grooves on the second source-drain metal layer isolates the second source-drain leads and the through holes. The flexible array substrate can improve the encapsulation effect of the stretchable region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a flexible array substrate and a display device. BACKGROUND

[0002] Flexible stretchable display panels are widely used in display devices with curved display surfaces. In a flexible stretchable display panel, a stretchable region can adopt a hole digging design to form an island-bridge region composed of a pixel island region and a bridge region. An isolation groove can be provided around the island-bridge region to avoid moisture from entering the pixel island region and the bridge region. However, the provision of the isolation groove increases the signal lead density of the bridge region and makes the signal leads closer to the isolation groove, so that moisture easily enters the signal leads from the isolation groove, resulting in reduced electrical performance of the bridge region.

[0003] The above information disclosed in the background section is only for the purpose of enhancing the understanding of the background of the present disclosure, and therefore it can include information that does not constitute the prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to provide a flexible array substrate and a display device to improve the packaging effect of a stretchable region.

[0005] To achieve the above-mentioned purposes, the present disclosure adopts the following technical solutions:

[0006] According to a first aspect of the present disclosure, a flexible array substrate is provided, comprising at least one stretchable region; the flexible array substrate is provided with a plurality of through holes in the stretchable region, and the plurality of through holes divide the stretchable region into a pixel island region for display and a bridge region for signal transmission; the bridge region comprises a source-drain bridge region, and the flexible array substrate comprises, in any one source-drain bridge region:

[0007] a substrate substrate;

[0008] a first source-drain metal layer disposed on one side of the substrate substrate and comprising a plurality of first source-drain leads;

[0009] a first insulating material layer disposed on a side of the first source-drain metal layer away from the substrate substrate;

[0010] a second source-drain metal layer disposed on a side of the first insulating material layer away from the substrate substrate; the second source-drain metal layer comprises a plurality of second source-drain leads, and the number of the second source-drain leads is less than the number of the first source-drain leads;

[0011] a second insulating material layer disposed on a side of the second source-drain metal layer away from the substrate;

[0012] a packaging layer disposed on a side of the second insulating material layer away from the substrate.

[0013] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, a minimum value of a distance between a projection of the second source-drain lead on the second insulating material layer and the isolation groove is not less than a pitch between two adjacent second source-drain leads.

[0014] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, a width of the isolation groove is not greater than 2 times the pitch between two adjacent second source-drain leads.

[0015] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, the width of the isolation groove is equal to 0.9-1.1 times the pitch between two adjacent second source-drain leads; and a number of the isolation grooves between the second source-drain lead and an adjacent through hole is multiple, and a pitch between two adjacent isolation grooves is equal to 0.9-1.1 times the pitch between two adjacent second source-drain leads.

[0016] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, the pitch between two adjacent second source-drain leads is not greater than 2 times a width of the second source-drain lead.

[0017] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, multiple second source-drain leads are arranged at equal intervals; and a minimum distance between two adjacent through holes and the second source-drain lead is equal.

[0018] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, a pitch between two adjacent first source-drain leads is not greater than a pitch between two adjacent second source-drain leads.

[0019] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, a minimum value of a distance between a projection of the first source-drain lead on the second insulating material layer and the isolation groove is not greater than a minimum value of a distance between a projection of the second source-drain lead on the second insulating material layer and the isolation groove.

[0020] In an exemplary embodiment of the present disclosure, in the source-drain bridging region, the projection of the first source-drain lead on the second insulating material layer at least partially overlaps the isolation groove.

[0021] In an example embodiment of the present disclosure, in the source-drain bridge region, a minimum value of a distance between a normal projection of the first source-drain lead on the second insulating material layer and the isolation groove is 1.5-2.7 microns; a minimum value of a distance between a normal projection of the second source-drain lead on the second insulating material layer and the isolation groove is 4.5-6.0 microns.

[0022] In an example embodiment of the present disclosure, the number of the first source-drain leads is greater than the number of the second source-drain leads by 1 or 2.

[0023] In an example embodiment of the present disclosure, a width of an end of the isolation groove away from the substrate is less than a width of an end of the isolation groove close to the substrate.

[0024] In an example embodiment of the present disclosure, in the source-drain bridge region, an extension direction of the first source-drain lead is parallel or perpendicular to an extension direction of the through hole; an extension direction of the second source-drain lead is parallel or perpendicular to the extension direction of the through hole.

[0025] In an example embodiment of the present disclosure, the pixel island region includes a plurality of sub-pixels, a size of any one of the sub-pixels along a row direction is a first size; in the source-drain bridge region, a pitch between two adjacent second source-drain leads is equal to a second size; the first size is greater than the second size.

[0026] In an example embodiment of the present disclosure, the through hole includes a first long hole extending along a row direction and a second long hole extending along a column direction; the source-drain bridge region is located between an end of the first long hole and a side of the second long hole.

[0027] In an example embodiment of the present disclosure, any one of the pixel island regions is located between two adjacent first long holes and between two adjacent second long holes; any one of the pixel island regions includes four pixels, and any one of the pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0028] In an example embodiment of the present disclosure, in any one of the pixel island regions, the four pixels form two pixel rows, and any one of the pixel rows includes two pixels arranged along the row direction.

[0029] In any one of the pixel rows, the pixel electrode of the blue sub-pixel and the pixel electrode of the red sub-pixel are arranged along the row direction and located on a side of the pixel electrode of the green sub-pixel away from the other pixel row.

[0030] In an example embodiment of the present disclosure, the flexible array substrate comprises a plurality of sub-pixels arranged in an array in any one of the pixel island regions, and any one of the sub-pixels comprises a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit; any one of the pixel driving circuits comprises a storage capacitor, a first thin film transistor to a seventh thin film transistor; wherein,

[0031] The first end of the first thin film transistor is used to load an initial signal, the second end of the first thin film transistor is electrically connected to the first electrode plate of the storage capacitor, and the control end of the first thin film transistor is used to load a reset signal;

[0032] The first end of the second thin film transistor is electrically connected to the second end of the third thin film transistor and the first end of the sixth thin film transistor, the second end of the second thin film transistor is electrically connected to the first electrode plate of the storage capacitor, and the control end of the second thin film transistor is used to load a scanning signal;

[0033] The first end of the third thin film transistor is electrically connected to the second end of the fourth thin film transistor and the second end of the fifth thin film transistor, and the control end of the third thin film transistor is electrically connected to the first electrode plate of the storage capacitor;

[0034] The first end of the fourth thin film transistor is used to load a data signal, and the control end of the fourth thin film transistor is used to load the scanning signal;

[0035] The first end of the fifth thin film transistor is used to load a power voltage, and the control end of the fifth thin film transistor is used to load an enable signal;

[0036] The second end of the sixth thin film transistor is used to be electrically connected to the pixel electrode, and the control end of the sixth thin film transistor is used to load the enable signal;

[0037] The first end of the seventh thin film transistor is used to load the initial signal, the second end of the seventh thin film transistor is used to be electrically connected to the pixel electrode, and the control end of the seventh thin film transistor is used to load the reset signal;

[0038] The second electrode plate of the storage capacitor is used to load the power voltage.

[0039] In an example embodiment of the present disclosure, any one of the pixel island regions comprises a first column of pixel driving circuits to a sixth column of pixel driving circuits arranged in a set direction in sequence, and any one column of pixel driving circuits comprises a plurality of pixel driving circuits arranged in a column direction; wherein the set direction is a direction parallel to the row direction;

[0040] In the source-drain bridge region, the number of the first source-drain leads is five; a first of the first source-drain leads in the set direction is used to load the data signal to the first column of pixel driving circuits; a second of the first source-drain leads in the set direction is used to load the data signal to the second column of pixel driving circuits; a fourth of the first source-drain leads in the set direction is used to load the data signal to the fifth column of pixel driving circuits.

[0041] In an exemplary embodiment of the present disclosure, in the source-drain bridge region, the number of the second source-drain leads is four; a first of the second source-drain leads in the set direction is used to load the power voltage to the first column of pixel driving circuits to the sixth column of pixel driving circuits; a second of the second source-drain leads in the set direction is used to load the data signal to the third column of pixel driving circuits; a third of the second source-drain leads in the set direction is used to load the data signal to the fourth column of pixel driving circuits; a fourth of the second source-drain leads in the set direction is used to load the data signal to the sixth column of pixel driving circuits.

[0042] According to a second aspect of the present disclosure, a display device is provided, comprising the flexible array substrate as described above.

[0043] The flexible array substrate and the display device provided by the present disclosure have two layers of source-drain metal layers in the source-drain bridge region, which can increase the width of each source-drain lead formed by the source-drain metal layers and the spacing between the source-drain leads, reduce the crosstalk between the source-drain leads and the impedance of the source-drain leads, improve the bendability of the source-drain leads and further improve the stretchability and electrical stability of the stretchable region. Furthermore, the number of the second source-drain leads is less than the number of the first source-drain leads, which can increase the spacing between the second source-drain leads and the isolation groove, reduce the risk of water vapor invading the second source-drain leads through the isolation groove, improve the reliability of the packaging of the stretchable region, and further improve the electrical stability of the stretchable region. BRIEF DESCRIPTION OF DRAWINGS

[0044] The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0045] Figure 1 is a structural schematic diagram of a stretchable region of an embodiment of the present disclosure.

[0046] Figure 2 is a structural schematic diagram of a flexible array substrate in a source-drain bridge region of an embodiment of the present disclosure.

[0047] Figure 3 is a structural schematic diagram of a flexible array substrate in a source-drain bridge region of an embodiment of the present disclosure.

[0048] Figure 4 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0049] Figure 5 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0050] Figure 6 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure; wherein, Figure 6 Only the relative positional relationship of the through hole, the first source-drain lead, the second source-drain lead, and the isolation groove is shown.

[0051] Figure 7 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0052] Figure 8 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0053] Figure 9 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0054] Figure 10 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0055] Figure 11 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0056] Figure 12 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0057] Figure 13 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0058] Figure 14 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0059] Figure 15 is a structural schematic diagram of a flexible array substrate in a source-drain bridge connection region according to an embodiment of the present disclosure.

[0060] Figure 16 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0061] Figure 17FIG. 1 is a schematic diagram of a structure of a semiconductor layer of a pixel driving circuit according to an embodiment of the present disclosure.

[0062] Figure 18 FIG. 2 is a schematic diagram of a structure of a first gate layer of a pixel driving circuit according to an embodiment of the present disclosure.

[0063] Figure 19 FIG. 3 is a schematic diagram of a structure of a second gate layer of a pixel driving circuit according to an embodiment of the present disclosure.

[0064] Figure 20 FIG. 4 is a schematic diagram of a structure of a first source-drain metal layer of a pixel driving circuit according to an embodiment of the present disclosure.

[0065] Figure 21 FIG. 5 is a schematic diagram of a structure of a second source-drain metal layer of a pixel driving circuit according to an embodiment of the present disclosure.

[0066] Figure 22 FIG. 6 is a schematic diagram of a structure of a semiconductor layer of a stretchable region according to an embodiment of the present disclosure.

[0067] Figure 23 FIG. 7 is a schematic diagram of a structure of a first gate layer of a stretchable region according to an embodiment of the present disclosure.

[0068] Figure 24 FIG. 8 is a schematic diagram of a structure of a second gate layer of a stretchable region according to an embodiment of the present disclosure.

[0069] Figure 25 FIG. 9 is a schematic diagram of a structure of a first source-drain metal layer of a stretchable region according to an embodiment of the present disclosure.

[0070] Figure 26 FIG. 10 is a schematic diagram of a structure of a second source-drain metal layer of a stretchable region according to an embodiment of the present disclosure.

[0071] Figure 27 FIG. 11 is a schematic diagram of a structure of a pixel electrode layer of a stretchable region according to an embodiment of the present disclosure.

[0072] The main element reference numerals in the drawings are explained as follows.

[0073] A, row direction; B, column direction; C, set direction; 010, through hole; 010a, opening area; 011, first long hole; 012, second long hole; 020, pixel island area; 021, pixel distribution area; 022, pixel wiring area; 030, bridge area; 031, source-drain bridge area; 032, gate bridge area; 040, source-drain lead; 041, power supply lead; 042, data lead; 050, support substrate; 0681, first electrode plate of storage capacitor; 0682, second electrode plate of storage capacitor; 100, substrate substrate; 200, first source-drain metal layer; 201, first source-drain lead; 211, first connection lead; 212, second connection lead; 213, third connection lead; 221, source-drain first via area; 222, source-drain second via area; 223, source-drain third via area; 224, source-drain fourth via area; 225, source-drain fifth via area; 226, source-drain sixth via area; 227, source-drain seventh via area; 228, source-drain eighth via area; 229, source-drain ninth via area; 231, first metal lead; 232, second metal lead; 233, third metal lead; 234, fourth metal lead; 235, fifth metal lead; 246, sixth metal lead; 247, seventh metal lead; 248, eighth metal lead; 249, ninth metal lead; 2410, tenth metal lead; 2411, eleventh metal lead; 2412, twelfth metal lead; 300, first insulating material layer; 301, first passivation layer; 302, first planarization layer; 400, second source-drain metal layer; 401, second source-drain lead; 411, column power supply lead; 412, row power supply lead; 413, transition pad; 4313, thirteenth metal lead; 4314, fourteenth metal lead; 4315, fifteenth metal lead; 4316, sixteenth metal lead; 500, second insulating material layer; 501, second planarization layer; 502, second passivation layer; 503, isolation groove; 600, encapsulation layer; 701, shielding layer; 702, third insulating material layer; 703, organic light-emitting layer; 704, common electrode layer; 7051, pixel electrode of red sub-pixel; 7052, pixel electrode of green sub-pixel; 7053, pixel electrode of blue sub-pixel; 810, semiconductor layer; 8111, first channel area; 8112, second channel area; 8113, third channel area; 8114, fourth channel area; 8115, fifth channel area; 8116, sixth channel area; 8117, seventh channel area; 8121, first conductive segment; 8122, second conductive segment; 8123, third conductive segment; 8124, fourth conductive segment; 8125, fifth conductive segment; 8126, sixth conductive segment; 8127, seventh conductive segment; 8131, semiconductor layer first via area; 8132, semiconductor layer second via area; 8133, semiconductor layer third via area; 8136, semiconductor layer sixth via area;8137, seventh via region of semiconductor layer; 8211, first gate lead; 8212, second gate lead; 8213, third gate lead; 8221, scan lead; 8222, enable lead; 8223, reset lead; 8231, first lead region; 8232, second lead region; 8234, fourth lead region; 8235, fifth lead region; 8236, sixth lead region; 8237, seventh lead region; 8245, fifth via region of gate layer; 8311, fourth gate lead; 8312, fifth gate lead; 8313, sixth gate lead; 8321, initialization lead; 8322, auxiliary electrode plate; 8334, fourth via region of gate layer; 8338, eighth via region of gate layer; 8339, ninth via region of gate layer. DETAILED DESCRIPTION

[0074] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments can be implemented in any number of ways. Rather, these embodiments are to be understood as illustrative of the various embodiments of the present disclosure. Accordingly, person skilled in the art will understand that numerous changes can be made from the details of the embodiments set forth below without departing from the scope and spirit of the present disclosure. Various embodiments can be implemented individually, collectively or in any combination thereof.

[0075] In the drawings, the thicknesses of regions and layers can be exaggerated for clarity. Like reference numerals in different drawings denote like elements, and so a detailed description thereof will be omitted.

[0076] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0077] The use of the terms "a" and "an" and "the" and "at least one" are intended to include both singular and plural referents unless the context clearly dictates otherwise. The use of the term "at least one" followed by a list of one or more items (for example, "at least one of A and B") is intended to include all of the individual items in the list (A or B) and any combination of the individual items in the list (A and B), for example.

[0078] The present disclosure provides a flexible array substrate including at least one stretchable region; as Figure 1As shown, the flexible array substrate is provided with a plurality of through holes 010 in the stretchable region, and the plurality of through holes 010 divide the stretchable region into a pixel island region 020 for display and a bridge region 030 for signal transmission; wherein the bridge region 030 includes a source-drain bridge region 031; Figure 2 and Figure 3 As shown, the flexible array substrate includes a base substrate 100, a first source-drain metal layer 200, a first insulating material layer 300, a second source-drain metal layer 400, a second insulating material layer 500, and an encapsulation layer 600 in any source-drain bridge area 031. The first source-drain metal layer 200 is provided on one side of the base substrate 100 and includes a plurality of first source-drain leads 201; the first insulating material layer 300 is provided on a side of the first source-drain metal layer 200 away from the base substrate 100; the second source-drain metal layer 400 is provided on a side of the first insulating material layer 300 away from the base substrate 100; the second source-drain metal layer 400 includes a plurality of second source-drain leads 401, and the number of the second source-drain leads 401 is less than the number of the first source-drain leads 201; the second insulating material layer 500 is provided on a side of the second source-drain metal layer 400 away from the base substrate 100; see Figure 6 and Figure 12 The second insulating material layer 500 is provided with a plurality of isolation trenches 503 ( Figure 2 and Figure 3 The isolation groove 503 is filled with the encapsulation layer 600), and the orthographic projection of the isolation groove 503 on the second source-drain metal layer 400 isolates the second source-drain lead 401 and the through hole 010; the encapsulation layer 600 is provided on the side of the second insulating material layer 500 away from the base substrate 100.

[0079] The flexible array substrate provided by the present disclosure has two source-drain metal layers in the source-drain bridge region 031. This can increase the width of each source-drain lead 040 formed by the source-drain metal layers and the spacing between the source-drain leads 040, reduce crosstalk between the source-drain leads 040, and reduce the impedance of the source-drain leads 040, thereby improving the bendability of the source-drain leads 040 and thereby improving the stretchability and electrical stability of the stretchable region. Furthermore, the number of second source-drain leads 401 is less than the number of first source-drain leads 201, which can increase the spacing between the second source-drain leads 401 and the isolation trench 503, reducing the risk of moisture intruding into the second source-drain leads 401 through the isolation trench 503, improving the reliability of the packaging in the stretchable region, and further improving the electrical stability of the stretchable region.

[0080] In the present disclosure, the width of a certain structure in the source-drain bridge connection region 031 refers to the size of the orthogonal projection of the structure on the substrate 100 in the plane of the substrate 100 and perpendicular to the extension direction of the source-drain lead 040. For example, the width of the source-drain lead refers to the size of the orthogonal projection of the source-drain lead 040 of the source-drain bridge connection region 031 on the substrate 100 in the plane of the substrate 100 and perpendicular to the extension direction of the source-drain lead 040. For another example, the width of the isolation groove 503 refers to the size of the orthogonal projection of the isolation groove 503 of the source-drain bridge connection region 031 on the substrate 100 in the plane of the substrate 100 and perpendicular to the extension direction of the source-drain lead 040.

[0081] The structure, principle and effect of the flexible array substrate provided by the present disclosure will be further explained and described below in combination with the drawings.

[0082] The flexible array substrate provided by the present disclosure has at least one stretchable region, which can adapt to a curved surface by stretching deformation and still realize display function after stretching. The stretchable region can be located in a local region such as the edge or corner of the flexible array substrate, or can cover the entire display area of the flexible array substrate, which is not specially limited by the present disclosure. For example, in an embodiment of the present disclosure, the flexible array substrate can have four stretchable regions, and the four stretchable regions are located at the four top corners of the flexible array substrate; in this way, the flexible array substrate can be applied to a four-curved-surface display screen. For another example, in another embodiment of the present disclosure, the stretchable region of the flexible array substrate covers at least the display area of the flexible array substrate, i.e., the display area of the flexible array substrate is all the stretchable region; in this way, the flexible array substrate can be used to prepare a head-mounted display helmet.

[0083] In the stretchable region, as shown in Figure 1 The flexible array substrate can be provided with a plurality of through holes 010 to improve the stretching performance of the stretchable region. The through holes 010 can divide the stretchable region into island-bridge regions connected to each other, which include pixel island regions 020 for display and bridge connection regions 030 for signal transmission, and the adjacent pixel island regions 020 are connected through the bridge connection regions 030. The shape and arrangement of the through holes 010 can be selected and determined according to requirements, which can be I-shaped holes, long strip holes or other shaped through holes 010. The flexible array substrate is also provided with an isolation groove 503, which is arranged around each through hole 010 to block the channel for water and oxygen to invade from the through hole 010 to the island-bridge region, thereby protecting the pixel island region 020 and the bridge connection region 030.

[0084] Alternatively, the through hole 010 can be a long strip hole. Referring to Figure 1The through holes 010 can include first long strip holes 011 extending along the row direction A and second long strip holes 012 extending along the column direction B; wherein one second long strip hole 012 is arranged between any two adjacent first long strip holes 011 in the same row, and the two adjacent first long strip holes 011 in the same row are staggered; one first long strip hole 011 is arranged between any two adjacent second long strip holes 012 in the same column, and the two adjacent second long strip holes 012 in the same column are staggered. In this way, each pixel island region 020 is surrounded by two first long strip holes 011 and two second long strip holes 012, one first long strip hole 011 is used to divide two adjacent pixel island regions 020 in the column direction, and one second long strip hole 012 is used to divide two adjacent pixel island regions 020 in the row direction. The bridge connection region 030 includes a gate bridge connection region 032 and a source-drain bridge connection region 031, wherein the gate bridge connection region 032 is located between the side of the first long strip hole 011 and the end of the second long strip hole 012, and is used to connect two adjacent pixel island regions 020 in the same row; the source-drain bridge connection region 031 is located between the end of the first long strip hole 011 and the side of the second long strip hole 012, and is used to connect two adjacent pixel island regions 020 in the same column.

[0085] Further, the pixel island region 020 can include a pixel distribution region 021 and two pixel wiring regions 022 on both sides of the pixel distribution region 021. The pixel distribution region 021 can be provided with one or more pixels, and each pixel can include one or more sub-pixels. Optionally, each sub-pixel can be a self-luminous light-emitting element, for example, can have an OLED (Organic Light-Emitting Diode), a Micro LED (Micro Light-Emitting Diode), etc. Optionally, each pixel can include sub-pixels of multiple different colors, so as to realize color display through color mixing of sub-pixels of different colors. For example, in an embodiment of the present disclosure, one pixel island region 020 can include four pixels, each pixel including a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In other words, any one pixel island region 020 is located between two adjacent first long strip holes 011 and between two adjacent second long strip holes 012; any one pixel island region 020 includes four pixels, and any one pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0086] Optionally, the size of any one sub-pixel along the row direction A is a first size; in the source-drain bridge connection region 031, the distance between the two adjacent second source-drain leads 401 is equal to a second size; the first size is greater than the second size.

[0087] As Figure 1As shown, the pixel wiring area 022 is located at the side of the pixel distribution area 021 close to the first long hole 011, and is connected with the source-drain bridge connection area 031 and the gate bridge connection area 032. In other words, in the pixel island area 020, along the column direction B, the pixel wiring area 022, the pixel distribution area 021 and the pixel wiring area 022 are sequentially arranged. In this way, the pixel distribution area 021 can converge each source-drain lead 040 to the source-drain bridge connection area 031 through the pixel wiring area 022, and the pixel distribution area 021 can converge each gate lead to the gate bridge connection area 032 through the pixel wiring area 022.

[0088] Optionally, the gate bridge connection area 032 can be provided with a gate lead, so as to provide one or more of a scanning signal, an enabling signal, a reset signal, an initialization signal and other gate signals for the pixel island area 020. Of course, the gate lead of the gate bridge connection area 032 can also be used to provide one or more of a scanning signal, an enabling signal, a reset signal, an initialization signal and other gate signals for the pixels in other areas of the flexible array substrate.

[0089] The source-drain bridge connection area 031 can be provided with a source-drain lead 040, which includes a first source-drain lead 201 located in the first source-drain metal layer 200 and a second source-drain lead 401 located in the second source-drain metal layer 400. The source-drain lead 040 is used to provide a data signal, a power voltage, or to transmit a sensing signal of the pixel island area 020. Of course, if sub-pixels are also provided outside the stretchable area of the flexible array substrate, in some cases, the source-drain lead 040 of the source-drain bridge connection area 031 can also provide a data signal, a power voltage, or transmit a sensing signal of the pixels in other areas of the flexible array substrate.

[0090] Preferably, in the source-drain bridge connection area 031, the extension direction of the first source-drain lead 201 is parallel or perpendicular to the extension direction of the through hole 010; the extension direction of the second source-drain lead 401 is parallel or perpendicular to the extension direction of the through hole 010. Further, in the source-drain bridge connection area 031, the extension direction of the first source-drain lead 201 and the second source-drain lead 401 is parallel to the extension direction of the second long hole 012. That is, in the source-drain bridge connection area 031, the extension direction of the first source-drain lead 201 and the second source-drain lead 401 is the column direction B.

[0091] Optionally, in the pixel wiring area 022, the extension direction of the first source-drain lead 201 and the second source-drain lead 401 is parallel or perpendicular to the extension direction of the through hole 010. In other words, for any one of the first source-drain lead 201 or the second source-drain lead 401, in the pixel wiring area 022, it can extend along the row direction A, or extend along the column direction B, or partially extend along the row direction A and the remaining part extend along the column direction B.

[0092] In one embodiment of the present disclosure, the flexible array substrate is further provided with pixels outside the stretchable area, the source-drain leads 040 of a first portion of these pixels do not pass through the stretchable area, the source-drain leads 040 of a second portion of these pixels can share the source-drain leads 040 with the pixels in the pixel island area 020, and the source-drain leads 040 of a third portion of these pixels can pass through the source-drain bridge area 031 of the stretchable area and are not used to drive the pixels in the pixel island area 020.

[0093] like Figure 1 As shown, in the source-drain bridge region 031, the source-drain lead 040 includes a power lead 041 for applying a power supply voltage and a data lead 042 for applying a data signal. Figure 1 Only one power lead 041 and one data lead 042 are shown as examples. Figure 1 It is only used to illustrate the existence of the power lead 041 and the data lead 042 , rather than to illustrate the number of the power lead 041 and the number of the data lead 042 .

[0094] Optionally, only one power lead 041 may be provided in a source-drain bridge region 031. This power lead 041 can provide a power supply voltage to each sub-pixel in the pixel island region 020 through bridging or other means. This can reduce the number of source-drain leads 040 in the source-drain bridge region 031, thereby facilitating an increase in the spacing and width of the source-drain leads 040, thereby improving the bendability of the source-drain leads 040 and, consequently, the stretchability and electrical stability of the stretchable region. Furthermore, since the number of source-drain leads 040 is reduced, the source-drain leads 040 can be further away from the through-hole 010 and the isolation trench 503, thereby improving the reliability of the packaging in the stretchable region. In particular, the reduction in the number of source-drain leads 040 in the source-drain bridge area 031 facilitates reducing the width of the source-drain bridge area 031 and reducing the area ratio of the source-drain bridge area 031, thereby increasing the size and area ratio of the pixel island area 020, and thereby increasing the pixel density or luminous area of ​​the flexible array substrate in the stretchable area, thereby improving the display effect.

[0095] Optionally, the width of the power lead 041 is greater than the width of the data lead 042 to reduce the voltage drop of the power lead 041. Preferably, the width of the power lead 041 is 1.5 to 3 times the width of the data lead 042.

[0096] In one embodiment of the present disclosure, in one source-drain bridge region 031 , there is one power lead 041 , and the power lead 041 is a second source-drain lead 401 .

[0097] Exemplarily, in an embodiment of the present disclosure, the pixel island region 020 includes 4 pixels, each of which includes 3 independently light-emitting sub-pixels, i.e., a red sub-pixel, a green sub-pixel and a blue sub-pixel. In the source-drain bridge region 031, 9 source-drain leads 040 can be provided, including 5 first source-drain leads 201 and 4 second source-drain leads 401. One of the second source-drain leads 401 is used as a power supply lead 041 for loading a power supply voltage to each sub-pixel of the pixel island region 020; 6 of the source-drain leads 040 are used as data leads 042 for loading a data signal to each sub-pixel of the pixel island region 020; and 2 of the source-drain leads 040 are used as data leads 042 for providing a data signal to the sub-pixels outside the stretchable region, and are not used for providing a data signal to the sub-pixels of the pixel island region 020. Compared with the scheme of providing all the source-drain leads 040 in the same source-drain metal layer, the embodiment can reduce the total wiring width of the source-drain leads 040 by 43%, and can ensure the packaging effect of each source-drain lead 040.

[0098] Optionally, in the source-drain bridge region 031, the minimum distance between the orthogonal projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation groove 503 is not less than the interval between the adjacent two second source-drain leads 401. In this way, a sufficient distance between the second source-drain lead 401 and the isolation groove 503 can be ensured, so that the moisture is difficult to invade the second source-drain lead 401 through the isolation groove 503, thereby avoiding the electrical performance of the second source-drain lead 401 from being degraded.

[0099] Preferably, in the source-drain bridge region 031, the minimum distance between the orthogonal projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation groove 503 is equal to 1.5-2.0 times the interval between the adjacent two second source-drain leads 401. For example, in an embodiment of the present disclosure, in the source-drain bridge region 031, the interval between the adjacent two second source-drain leads 401 is equal to 3 microns, and the minimum distance between the orthogonal projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation groove 503 is equal to 4.5-6.0 microns.

[0100] Optionally, the width of the isolation groove 503 is not greater than 2 times the interval between the adjacent two second source-drain leads 401. In this way, the width of the isolation groove 503 can be prevented from being too large to compress the distance between the second source-drain lead 401 and the isolation groove 503, so that a sufficient distance between the second source-drain lead 401 and the isolation groove 503 can be ensured, so that the moisture is difficult to invade the second source-drain lead 401 through the isolation groove 503. Furthermore, by reducing the width of the isolation groove 503, more isolation grooves 503 can be provided to further improve the packaging stability of the source-drain bridge region 031.

[0101] Optionally, in the source-drain bridge connection region 031, the number of isolation grooves 503 between the second source-drain lead 401 and an adjacent through-hole 010 is multiple, and the distance between adjacent two isolation grooves 503 is not greater than 2 times the distance between adjacent two second source-drain leads 401. In this way, when multiple isolation grooves 503 are arranged on one side of the source-drain bridge connection region 031, the distance between the second source-drain lead 401 and the isolation groove 503 can be prevented from being compressed due to the too large distance between the isolation grooves 503, so that the second source-drain lead 401 and the isolation groove 503 have a large enough distance, and the water vapor is difficult to enter the second source-drain lead 401 through the isolation groove 503. Moreover, by reducing the distance between the isolation grooves 503, more isolation grooves 503 can be arranged to further improve the packaging stability of the source-drain bridge connection region 031.

[0102] Preferably, in the source-drain bridge connection region 031, the width of the isolation groove 503 is 0.9-1.1 times the distance between adjacent two second source-drain leads 401; and the number of isolation grooves 503 between the second source-drain lead 401 and an adjacent through-hole 010 is multiple, and the distance between adjacent two isolation grooves 503 is 0.9-1.1 times the distance between adjacent two second source-drain leads 401. In this way, the width of the isolation groove 503 and the distance between the isolation grooves 503 can be further compressed, so that more isolation grooves 503 can be arranged in the source-drain bridge connection region 031, and the distance between the isolation groove 503 and the second source-drain lead 401 is larger, further improving the packaging stability of the source-drain bridge connection region 031 and the electrical performance stability of the source-drain lead 040. For example, in an embodiment of the present disclosure, in the source-drain bridge connection region 031, the distance between adjacent two second source-drain leads 401 is equal to 3 microns, the width of the isolation groove 503 is equal to 2.7-3.3 microns, and the distance between adjacent two isolation grooves 503 on the same side of the source-drain bridge connection region 031 is equal to 2.7-3.3 microns.

[0103] Optionally, in the source-drain bridge connection region 031, the distance between adjacent two second source-drain leads 401 is not greater than 2 times the minimum value of the width of the second source-drain lead 401. In this way, the distance between the second source-drain lead 401 and the isolation groove 503 can be prevented from being compressed due to the too large distance between the second source-drain leads 401, so that the second source-drain lead 401 and the isolation groove 503 have a large enough distance, and the water vapor is difficult to enter the second source-drain lead 401 through the isolation groove 503. Moreover, by reducing the distance between the second source-drain leads 401, more isolation grooves 503 can be arranged to further improve the packaging stability of the source-drain bridge connection region 031.

[0104] Preferably, in the source-drain bridge region 031, the spacing between two adjacent second source-drain leads 401 is equal to 0.9 to 1.1 times the minimum width of the second source-drain leads 401. For example, in one embodiment of the present disclosure, the minimum width of the second source-drain leads 401 is 3 microns, and the spacing between two adjacent second source-drain leads 401 is 2.7 to 3.3 microns.

[0105] Of course, in another embodiment of the present disclosure, the spacing between two adjacent second source-drain leads 401 in the source-drain bridge region 031 can also be determined based on, for example, the alignment accuracy of the exposure machine during the flexible array substrate fabrication process. Under the condition that the crosstalk between the two adjacent second source-drain leads 401 is controllable, the spacing between two adjacent second source-drain leads 401 in the source-drain bridge region 031 can be reduced within the range permitted by the fabrication process. For example, in one embodiment of the present disclosure, based on the alignment and exposure accuracy of the exposure machine, the spacing between the second source-drain leads 401 in the source-drain bridge region 031 can be 2 to 4 microns. Preferably, the spacing between the second source-drain leads 401 in the source-drain bridge region 031 can be 3 microns.

[0106] Alternatively, as Figures 2-5 As shown, in the source-drain bridge region 031, multiple second source-drain leads 401 are arranged at equal intervals; the minimum distance between two adjacent through-holes 010 in the source-drain bridge region 031 is equal to the minimum distance between the second source-drain leads 401 in the source-drain bridge region 031. Thus, in the source-drain bridge region 031, the second source-drain leads 401 of the second source-drain metal layer 400 are arranged centrally and symmetrically, ensuring sufficient space for the isolation trenches 503 on both sides of the source-drain bridge region 031 adjacent to the through-holes 010. This further ensures a sufficient distance between each second source-drain lead 401 and the isolation trenches 503, making it difficult for moisture to penetrate the second source-drain leads 401 through the isolation trenches 503.

[0107] Optionally, in the source-drain bridge region 031, the spacing between two adjacent first source-drain leads 201 is no greater than the spacing between two adjacent second source-drain leads 401. This prevents the width of the source-drain bridge region 031 from increasing due to excessive spacing between the first source-drain leads 201, thereby increasing the area ratio of the pixel island region 020 and improving the pixel density or light-emitting area of ​​the stretchable region.

[0108] Preferably, in the source-drain bridge region 031, the spacing between two adjacent first source-drain leads 201 is 0.9 to 1.0 times the spacing between two adjacent second source-drain leads 401. For example, in one embodiment of the present disclosure, in the source-drain bridge region 031, the spacing between two adjacent second source-drain leads 401 is 3 microns, and the spacing between two adjacent first source-drain leads 201 is 2.7 to 3.0 microns.

[0109] Alternatively, as Figure 6 As shown, in the source-drain bridge region 031, the minimum distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 is no greater than the minimum distance between the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation trench 503. Because the isolation trench 503 is formed in the second insulating material layer 500, the first source-drain lead 201 is completely covered by the first insulating material layer 300, making it difficult for moisture to penetrate the first source-drain lead 201 through the isolation trench 503. Therefore, reducing the distance between the first source-drain lead 201 and the isolation trench 503 does not degrade the electrical performance stability of the first source-drain lead 201. Furthermore, reducing the distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 can also reduce the width of the source-drain bridge region 031, thereby increasing the area ratio of the pixel island region 020 and improving the pixel density in the stretchable region.

[0110] In one embodiment of the present disclosure, Figure 6 As shown, in the source-drain bridge region 031, the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 completely does not overlap with the isolation trench 503. In this embodiment, in the source-drain bridge region 031, the orthographic projection of the isolation trench 503 on the first source-drain metal layer 200 is located between the first source-drain lead 201 and the through-hole 010, ensuring a sufficient distance between the first source-drain lead 201 and the through-hole 010. For example, in the source-drain bridge region 031, the minimum distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 is 1.5 to 2.7 microns; the minimum distance between the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation trench 503 is 4.5 to 6.0 microns.

[0111] Preferably, in the source-drain bridge region 031, the minimum distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 is 2.1 microns; and the minimum distance between the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation trench 503 is 5.2 microns. Thus, compared to the minimum distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503, the minimum distance between the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation trench 503 is increased by 148%. This keeps the second source-drain lead 401 away from the isolation trench 503, improving the packaging of the second source-drain lead 401.

[0112] In an embodiment of the present disclosure, the orthogonal projection of the first source-drain lead 201 on the second source-drain metal layer 400 is spaced apart from each of the second source-drain leads 401 and does not overlap with each other. In this way, the parasitic capacitance between the source-drain leads 040 can be reduced, and the crosstalk between the source-drain leads 040 can be reduced.

[0113] In another embodiment of the present disclosure, the orthogonal projection of the first source-drain lead 201 on the second insulating material layer 500 at least partially overlaps with the isolation groove 503. In this embodiment, part of the first source-drain lead 201, for example, the outermost first source-drain lead 201, can be located below the isolation groove 503. In this way, the minimum distance between the orthogonal projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation groove 503 is 0 microns; this can further reduce the width of the source-drain bridge connection area 031, thereby facilitating further increasing the area ratio of the pixel island area 020 and improving the pixel density or light-emitting area of the stretchable area.

[0114] Optionally, the number of the first source-drain leads 201 is 1 or 2 more than the number of the second source-drain leads 401. In this way, the number of the first source-drain leads 201 is prevented from greatly exceeding the number of the second source-drain leads 401, which can cause the source-drain bridge connection area 031 to be too wide. In an embodiment of the present disclosure, the number of the source-drain leads 040 is even, and the number of the first source-drain leads 201 is 2 more than the number of the second source-drain leads 401. In another embodiment of the present disclosure, the number of the source-drain leads 040 is odd, and the number of the first source-drain leads 201 is 1 more than the number of the second source-drain leads 401.

[0115] Optionally, the width of the isolation groove 503 away from one end of the substrate 100 is less than the width of the isolation groove 503 close to one end of the substrate 100. In this way, for a flexible array substrate in which the light-emitting element is an organic electroluminescent diode, when the organic light-emitting layer 703 and the common electrode layer 704 of the flexible array substrate are formed by evaporation, the organic light-emitting layer 703 and the common electrode layer 704 are discontinuous at the side wall of the isolation groove 503. In this way, the invasion of water and oxygen along the interface between the organic light-emitting layer 703 and the second insulating layer into the source-drain bridge connection area 031 and the pixel island area 020 can be avoided, the water and oxygen invasion channel is blocked, and the stability of the encapsulation of the source-drain bridge connection area 031 and the pixel island area 020 is ensured.

[0116] In an embodiment of the present disclosure, as shown in Figure 2 and Figure 3 the isolation groove 503 can penetrate through the second insulating material layer 500, so that the isolation groove 503 can more effectively block the water and oxygen invasion route and improve the encapsulation effect of the second source-drain lead 401.

[0117] In another embodiment of the present disclosure, as shown in Figure 4 and Figure 5 The isolation groove 503 does not penetrate the second insulating material layer 500, i.e. the size of the isolation groove 503 in the direction perpendicular to the substrate 100 is smaller than the size of the second insulating material layer 500 in the direction perpendicular to the substrate 100. In this way, the first insulating material layer 300 and part of the second insulating material layer 500 are arranged between the first source-drain lead 201 and the isolation groove 503, which can improve the protection effect of the first source-drain lead 201 and avoid the intrusion of water vapor into the first source-drain lead 201.

[0118] Optionally, the substrate 100 is a flexible substrate 100 to ensure the stretchable performance of the flexible array substrate. The material of the substrate 100 can be a flexible material, for example, polyimide. The substrate 100 can also be a composite of multiple layers of materials. For example, in an embodiment of the present disclosure, the substrate 100 can include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer which are sequentially stacked.

[0119] Optionally, the first source-drain metal layer 200 can include a layer of conductive material or a plurality of layers of conductive material which are stacked. For example, in an embodiment of the present disclosure, the first source-drain metal layer 200 can include a titanium layer, an aluminum layer and a titanium layer which are sequentially stacked.

[0120] Optionally, as shown in Figures 2-5 The flexible array substrate can further include a shielding layer 701 and a third insulating material layer 702. The shielding layer 701 is arranged between the first source-drain metal layer 200 and the substrate 100 in the source-drain bridge connection area 031 to shield light to avoid external light from shining on the source-drain lead 040. The third insulating material layer 702 is arranged between the shielding layer 701 and the first source-drain metal layer 200 to isolate the first source-drain metal layer 200 and the shielding layer 701. In an embodiment of the present disclosure, the material of the third insulating material layer 702 can be silicon oxide, silicon nitride, silicon oxynitride or other inorganic insulating materials.

[0121] Optionally, as shown in Figures 2-5As shown, the first insulating material layer 300 can include a first passivation layer 301 and a first planarization layer 302. The first passivation layer 301 covers the surface of the first source-drain metal layer 200 away from the substrate 100, so as to protect the first source-drain metal layer 200. In an embodiment of the present disclosure, the material of the first passivation layer 301 can be silicon oxide, silicon nitride, silicon oxynitride or other dense inorganic insulating material. The first planarization layer 302 is located on the side of the first passivation layer 301 away from the substrate 100, and is used to provide a planarization surface for the second source-drain metal layer 400. Further, the first planarization layer 302 can be an organic insulating material, so as to balance the stress distribution of the first source-drain metal layer 200 and the second source-drain metal layer 400 while providing a planarization surface, and improve the deformation ability of the source-drain bridge connection region 031. In an embodiment of the present disclosure, the material of the first planarization layer 302 can include polyimide.

[0122] Optionally, the second source-drain metal layer 400 is arranged on the side of the first planarization layer 302 away from the substrate 100, and can include a layer of conductive material, or can include a plurality of layers of conductive material stacked together. For example, in an embodiment of the present disclosure, the second source-drain metal layer 400 can include a titanium layer, an aluminum layer and a titanium layer stacked in sequence. It can be understood that the materials of the first source-drain metal layer and the second source-drain metal layer 400 can be the same or different, and the present disclosure does not limit this.

[0123] Optionally, as shown in FIG. 3B, the second source-drain metal layer 400 can include a second passivation layer 401 and a second planarization layer 402. The second passivation layer 401 covers the surface of the second source-drain metal layer 400 away from the substrate 100, so as to protect the second source-drain metal layer 400. In an embodiment of the present disclosure, the material of the second passivation layer 401 can be silicon oxide, silicon nitride, silicon oxynitride or other dense inorganic insulating material. The second planarization layer 402 is located on the side of the second passivation layer 401 away from the substrate 100, and is used to provide a planarization surface for the third source-drain metal layer 500. Further, the second planarization layer 402 can be an organic insulating material, so as to balance the stress distribution of the second source-drain metal layer 400 and the third source-drain metal layer 500 while providing a planarization surface, and improve the deformation ability of the source-drain bridge connection region 031. In an embodiment of the present disclosure, the material of the second planarization layer 402 can include polyimide. Figures 2-5As shown, the second insulating material layer 500 can include a second planarization layer 501 and a second passivation layer 502 which are stacked. The second planarization layer 501 covers the side of the second source-drain metal layer 400 away from the substrate 100, and can be made of an organic material, such as polyimide. In an embodiment of the present disclosure, the second planarization layer 501 can also extend to other regions of the flexible array substrate, such as the pixel island region 020 of the flexible array substrate, and provide a planarization surface for the pixel electrode in the pixel island region 020. In another embodiment of the present disclosure, the second planarization layer 501 can also extend to other regions of the flexible array substrate, such as the pixel island region 020 of the flexible array substrate, and be patterned as a pixel definition layer in the pixel island region 020. Of course, the second planarization layer 501 can also be a stack of multiple organic layers. For example, in another embodiment of the present disclosure, the second planarization layer 501 includes a first organic insulating layer and a second organic insulating layer which are stacked in sequence on the side of the second source-drain metal layer 400 away from the substrate 100. The first organic insulating layer and the second organic insulating layer can extend to other regions of the flexible array substrate, such as the pixel island region 020 of the flexible array substrate. The first organic insulating layer can provide a planarization surface for the pixel electrode in the pixel island region 020, and the second organic insulating layer can be patterned as a pixel definition layer in the pixel island region 020.

[0124] The second passivation layer 502 is disposed on the side of the second planarization layer 501 away from the substrate 100, and can be made of silicon nitride, silicon oxynitride, silicon oxide, or other inorganic insulating materials. In an embodiment of the present disclosure, the second passivation layer 502 is used as a mask layer to achieve the patterning of the second planarization layer 501.

[0125] For example, the second insulating material layer 500 can be prepared by sequentially forming a second planarization material layer and a second passivation material layer on the side of the second source-drain metal layer 400 away from the substrate 100, patterning the second passivation material layer to expose the second planarization material layer, and etching the second planarization material layer with the second passivation layer 502 as a mask to form a groove in the second planarization material layer. In this way, the second insulating material layer 500 can include the second planarization layer 501 and the second passivation layer 502 which are stacked, and the groove of the second planarization layer 501 and the opening of the second passivation layer 502 together form the isolation groove 503 of the second insulating material layer 500.

[0126] Furthermore, a wet etching process can be used to etch the second planarization material layer so that the width of the groove on the second planarization layer 501 is greater than the width of the opening of the second passivation layer 502, thereby making the width of the end of the isolation groove 503 away from the base substrate 100 smaller than the width of the end of the isolation groove 503 close to the base substrate 100, or making the second passivation layer 502 not supported by the second planarization layer 501 near the opening.

[0127] Optionally, before forming the second passivation layer 502, a complete and non-hollowed-out initial base substrate can be used to prepare a flexible array substrate; during the process of forming the isolation groove 503, or after forming the isolation groove 503, a through hole 010 of the flexible array substrate can be prepared, so that the initial flexible array substrate is also patterned to form the base substrate 100 of the flexible array substrate.

[0128] Optionally, the light-emitting element of the flexible array substrate can be an organic light-emitting diode. To facilitate the fabrication of the organic light-emitting diode, an open mask can be used to evaporate all or part of the organic light-emitting layer material and the common electrode layer material to form the organic light-emitting layer 703 and the common electrode layer 704. During the evaporation process, the organic light-emitting layer material and the common electrode layer material are discontinuous at the sidewalls of the isolation trench 503, thereby preventing the formation of a continuous channel for water and oxygen intrusion.

[0129] In other words, in some embodiments, Figure 3 and Figure 5 As shown, in the source-drain bridge region 031, the flexible array substrate may further include an organic light-emitting layer 703 and a common electrode layer 704 stacked on a side of the second insulating material layer 500 away from the base substrate 100, and the organic light-emitting layer 703 and the common electrode layer 704 are discontinuous at the isolation trench 503. The encapsulation layer 600 may be provided on a surface of the common electrode layer 704 away from the base substrate 100.

[0130] Optionally, the encapsulation layer 600 may be a thin film encapsulation layer 600 , which may include alternating inorganic material layers and organic material layers.

[0131] Exemplarily, the method for preparing the flexible array substrate may include the following steps:

[0132] Step S110, as Figure 7 As shown, a flexible base substrate 100 is provided on a support substrate 050; a first source-drain metal layer 200 is formed on a side of the base substrate 100 away from the support substrate 050. The first source-drain metal layer 200 includes a plurality of first source-drain leads 201 in the source-drain bridge region 031. Optionally, the support substrate 050 may be a glass substrate.

[0133] Step S120, asFigure 8 As shown, a first insulating material layer 300 is formed on the side of the first source-drain metal layer 200 away from the substrate 100, and the first insulating material layer 300 covers each of the first source-drain leads 201 on the source-drain bridge connection region 031;

[0134] In step S130, as shown in FIG. 4, a second source-drain metal layer 400 is formed on the side of the first insulating material layer 300 away from the substrate 100; and on the source-drain bridge connection region 031, the second source-drain metal layer 400 includes a plurality of second source-drain leads 401, and the number of the second source-drain leads 401 is less than the number of the first source-drain leads 201. Figure 9

[0135] In step S140, as shown in FIG. 5, a second planarization layer 501 and a second passivation layer 502 are sequentially formed on the side of the second source-drain metal layer 400 away from the substrate 100, thereby forming a second insulating material layer 500 covering each of the second source-drain leads 401 on the source-drain bridge connection region 031. Figure 10 Figure 11

[0136] In step S150, as shown in FIG. 6, the second insulating material layer 500 is subjected to a patterning process to form at least two isolation grooves 503; on the source-drain bridge connection region 031, the projection of the isolation grooves 503 on the second source-drain metal layer 400 isolates the second source-drain leads 401 and the opening region 010a on both sides of the source-drain bridge connection region 031. Figure 12

[0137] Optionally, when the isolation grooves 503 are formed, the opening region 010a can also be opened to form a through hole 010 in the opening region 010a.

[0138] In step S160, as shown in FIG. 7, an encapsulation layer 600 is formed on the side of the second insulating material layer 500 away from the substrate 100. Figure 13 In step S170, the support substrate 050 is peeled off.

[0139] In some embodiments, as shown in FIG. 8, after the isolation grooves 503 are formed, an organic light-emitting layer 703 and a common electrode layer 704 can also be formed; the organic light-emitting layer 703 and the common electrode layer 704 are discontinuous at the isolation grooves 503.

[0140] As shown in FIG. 9, after the organic light-emitting layer 703 and the common electrode layer 704 are formed, an encapsulation layer 600 can also be formed on the side of the common electrode layer 704 away from the substrate 100. Figure 14 Figure 15

[0141] ​​​​​​Next, a structure of the pixel island region 020 is exemplarily introduced to exemplarily show a connection manner of the source-drain bridge connection region 031 and the pixel island region 020, so as to more clearly explain and illustrate the structure of the source-drain bridge connection region 031.

[0142] In the example of the pixel island region, the pixel island region 020 includes four pixels, each of which includes three sub-pixels, such as a red sub-pixel, a green sub-pixel and a blue sub-pixel, each of which includes a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit.

[0143] The four pixels form two pixel rows, and each of the pixel rows includes two pixels arranged along a row direction A. Figure 27 As shown, in each of the pixel rows, the pixel electrodes 7053 of the blue sub-pixels and the pixel electrodes 7051 of the red sub-pixels are arranged along the row direction A and are located on a side of the pixel electrodes 7052 of the green sub-pixels away from the other pixel row. In this way, the two pixel rows form four pixel electrode rows, and each of the two middle pixel electrode rows includes two pixel electrodes 7052 of the green sub-pixels arranged along the row direction A; and each of the two side pixel electrode rows includes two pixel electrodes 7053 of the blue sub-pixels and two pixel electrodes 7051 of the red sub-pixels arranged along the row direction A.

[0144] The four pixels also form two pixel columns, and each of the pixel columns includes two pixels arranged along a column direction B. In each of the pixel columns, the pixel electrodes 7053 of the two blue sub-pixels are arranged along the column direction, the pixel electrodes 7051 of the two red sub-pixels are arranged along the column direction, and the pixel electrodes 7052 of the two green sub-pixels are arranged along the column direction. In each of the pixel columns, the pixel electrodes 7051 of the red sub-pixels are located on a side of the pixel electrodes 7053 of the blue sub-pixels along a set direction C, and the set direction C is a direction parallel to the row direction A.

[0145] Correspondingly, pixel island 020 is provided with twelve pixel driving circuits connected one-to-one to the twelve pixel electrodes. These pixel driving circuits are arranged in two rows, namely, a first row of pixel driving circuits near source-drain bridge connection area 031 and a second row of pixel driving circuits farther away from source-drain bridge connection area 031. These pixel driving circuits are also arranged in six columns, including a first column of pixel driving circuits, a second column of pixel driving circuits, a third column of pixel driving circuits, a fourth column of pixel driving circuits, a fifth column of pixel driving circuits, and a sixth column of pixel driving circuits arranged sequentially along a set direction C. The pixel driving circuits in the first and fourth columns of pixel driving circuits are connected to pixel electrodes 7053 of blue sub-pixels, the pixel driving circuits in the second and fifth columns of pixel driving circuits are connected to pixel electrodes 7052 of green sub-pixels, and the pixel driving circuits in the third and sixth columns of pixel driving circuits are connected to pixel electrodes 7051 of red sub-pixels.

[0146] In this example, if Figure 16 As shown, any pixel driving circuit can be a 7T1C (7 thin film transistors, 1 storage capacitor Cst) architecture. Among them, the third thin film transistor T3 serves as a driving transistor, a first end of which is electrically connected to the second end of the fifth thin film transistor T5, a second end of which is electrically connected to the first end of the sixth thin film transistor T6, and a control end of which is electrically connected to the first electrode plate of the storage capacitor Cst. The first end of the first thin film transistor T1 is used to load the initial signal (V init ), the second end is electrically connected to the first electrode plate of the storage capacitor Cst, and the control end is used to load the reset signal (Reset). The first end of the second thin film transistor T2 is electrically connected to the second end of the third thin film transistor T3, the second end is electrically connected to the first electrode plate of the storage capacitor Cst, and the control end is used to load the scan signal. The first end of the fourth thin film transistor T4 is used to load the data signal (V data ), the second end is electrically connected to the first end of the third thin film transistor T3, and the control end is used to load the scanning signal (Gate). The first end of the fifth thin film transistor T5 is used to load the power supply voltage (V DD ), the second end is electrically connected to the first end of the third thin film transistor T3, and the control end is used to load the enable signal (EM, Emission). The first end of the sixth thin film transistor T6 is electrically connected to the second end of the third thin film transistor T3, the second end is used to be electrically connected to the pixel electrode, and the control end is used to load the enable signal (EM, Emission). The first end of the seventh thin film transistor T7 is used to load the initial signal (V init ), the second end is used to be electrically connected to the pixel electrode, and the control end is used to load the reset signal. The first electrode plate of the storage capacitor Cst is electrically connected to the control end of the third thin film transistor T3, and the second electrode plate is used to load the power supply voltage (V DD ).

[0147] In this example, the flexible array substrate may include a base substrate, a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain metal layer, a first insulating material layer, a second source-drain metal layer, a second planarization layer, a pixel electrode layer, an organic light-emitting layer, a common electrode layer, and an encapsulation layer, which are stacked in sequence.

[0148] The material of the semiconductor layer can be polysilicon, which can change the conductivity at different positions through processes such as doping, thereby forming multiple channel regions and conductive segments. Figure 17 and Figure 22 As shown, in any pixel driving circuit, the semiconductor layer 810 may be formed with a first channel region 8111 serving as a channel region of the first thin film transistor T1, a second channel region 8112 serving as a channel region of the second thin film transistor T2, a third channel region 8113 serving as a channel region of the third thin film transistor T3, a fourth channel region 8114 serving as a channel region of the fourth thin film transistor T4, a fifth channel region 8115 serving as a channel region of the fifth thin film transistor T5, a sixth channel region 8116 serving as a channel region of the sixth thin film transistor T6, and a seventh channel region 8117 serving as a channel region of the seventh thin film transistor T7, as well as a first conductive segment 8121, a second conductive segment 8122, a third conductive segment 8123, a fourth conductive segment 8124, a fifth conductive segment 8125, a sixth conductive segment 8126, and a seventh conductive segment 8127. The first conductive segment 8121 is connected to the first end of the fourth channel region 8114 and is provided with a first semiconductor layer via region 8131. The second conductive segment 8122 is connected to the second end of the fourth channel region 8114, the first end of the fifth channel region 8115, and the first end of the third channel region 8113. The third conductive segment 8123 is connected to the second end of the fifth channel region 8115 and is provided with a sixth semiconductor layer via region 8136. The fourth conductive segment 8124 is connected to the second end of the third channel region 8113, the first end of the sixth channel region 8116, and the second end of the second channel region 8112. The fifth conductive segment 8125 is connected to the second end of the sixth channel region 8116, the second end of the seventh channel region 8117 of the next pixel driving circuit, and the second end of the second channel region 8112, and is provided with a seventh via region 8137 of the semiconductor layer; the sixth conductive segment 8126 is connected to the first end of the second channel region 8112 and the second end of the first channel region 8111, and is provided with a third via region 8133 of the semiconductor layer; the seventh conductive segment 8127 is connected to the first end of the first channel region 8111 and the first end of the seventh channel region 8117, and is provided with a second via region 8132 of the semiconductor layer.

[0149] like Figure 18 and Figure 23As shown, the first gate layer may include a first gate lead 8211, a second gate lead 8212, a third gate lead 8213, and a first gate structure including a pixel driving circuit. The first gate lead 8211, the second gate lead 8212, and the third gate lead 8213 pass through the gate bridge area 032 and extend to the pixel wiring area.

[0150] like Figure 18 As shown, the first gate structure of the pixel driving circuit includes a scan lead 8221, an enable lead 8222, a reset lead 8223, and a first electrode plate 0681 of the storage capacitor. The reset lead 8223 segment includes a first lead region 8231 and a seventh lead region 8237. The orthographic projection of the first lead region 8231 on the semiconductor layer 810 overlaps with the first channel region 8111, serving as the gate of the first thin-film transistor T1. The orthographic projection of the seventh lead region 8237 on the semiconductor layer 810 overlaps with the seventh channel region 8117, serving as the gate of the seventh thin-film transistor T7. The scan lead 8221 segment includes a second lead region 8232 and a fourth lead region 8234. The orthographic projection of the second lead region 8232 on the semiconductor layer 810 overlaps with the second channel region 8112, serving as the gate of the second thin-film transistor T2. The orthographic projection of the fourth lead region 8234 on the semiconductor layer 810 overlaps with the fourth channel region 8114, serving as the gate of the fourth thin-film transistor T4. The enable lead 8222 segment includes a fifth lead region 8235 and a sixth lead region 8236. The orthographic projection of the fifth lead region 8235 on the semiconductor layer 810 overlaps with the fifth channel region 8115, serving as the gate of the fifth thin-film transistor T5. The orthographic projection of the sixth lead region 8236 on the semiconductor layer 810 overlaps with the sixth channel region 8116, serving as the gate of the sixth thin-film transistor T6. The orthographic projection of the first electrode plate 0681 of the storage capacitor on the semiconductor layer 810 completely covers the third channel region 8113, allowing the first electrode plate 0681 of the storage capacitor to also serve as the gate of the third thin-film transistor T3. The first electrode plate 0681 of the storage capacitor is also provided with a fifth gate layer via region 8245.

[0151] like Figure 19 and Figure 24As shown, the second gate layer can include a fourth gate lead line 8311, a fifth gate lead line 8312, a sixth gate lead line 8313, and a second gate structure of the pixel driving circuit. Among them, the fourth gate lead line 8311, the fifth gate lead line 8312, and the sixth gate lead line 8313 pass through the gate bridge connection 032 area and extend to the pixel wiring area. The second gate structure of the pixel driving circuit includes an initialization lead line 8321, an auxiliary electrode plate 8322, and a second electrode plate 0682 of the storage capacitor. The second electrode plate 0682 of the storage capacitor coincides with the orthographic projection part of the first electrode plate 0681 of the storage capacitor on the substrate substrate, and the orthographic projection of the gate layer fifth via hole area 8245 on the substrate substrate is located outside the orthographic projection of the second electrode plate 0682 of the storage capacitor on the substrate substrate; the second electrode plate 0682 of the storage capacitor is provided with a gate layer fourth via hole area 8334. The third gate lead line 8213 is provided with a gate layer eighth via hole area 8338. The auxiliary electrode plate 8322 is used to cover part of the sixth conductive segment 8126 and part of the first conductive segment 8121, and is provided with a gate layer ninth via hole area 8339. Among them, the sixth gate lead line 8313 in the pixel wiring area is connected with the initialization lead line 8321 of the pixel driving circuit close to the pixel wiring area.

[0152] As shown in Figure 20 and Figure 25 , the first source-drain metal layer includes a plurality of source-drain lead lines and a first source-drain conductive structure of the pixel driving circuit.

[0153] As shown in Figure 20As shown, the first source-drain conductive structure of the pixel driving circuit includes a data lead structure 0421, a power lead structure 0411, a first connection lead 211, a second connection lead 212, and a third connection lead 213. The power lead structure 0411 is arranged on one side of the data lead structure 0421 in the set direction C, and the first connection lead 211, the second connection lead 212, and the third connection lead 213 are arranged on one side of the power lead structure 0411 in the set direction C. The data lead structure 0421 is provided with a source-drain first via area 221, which is connected with the semiconductor layer first via area 8131 to form a first metallization via. The power lead structure 0411 is provided with a source-drain fourth via area 224, a source-drain sixth via area 226, and a source-drain ninth via area 229; the source-drain fourth via area 224 is connected with the gate layer fourth via area 8334 to form a fourth metallization via, the source-drain sixth via area 226 is connected with the semiconductor layer sixth via area 8136 to form a sixth metallization via, and the source-drain ninth via area 229 is connected with the gate layer ninth via area 8339 to form a ninth metallization via. The first connection lead 211 is provided with a source-drain eighth via area 228 and a source-drain second via area 222; the source-drain eighth via area 228 is connected with the gate layer eighth via area 8338 to form an eighth metallization via, and the source-drain second via area 222 is connected with the semiconductor layer second via area 8132 to form a second metallization via; the second connection lead 212 is provided with a source-drain third via area 223 and a source-drain fifth via area 225; the source-drain third via area 223 is connected with the semiconductor layer third via area 8133 to form a third metallization via, and the source-drain fifth via area 225 is connected with the gate layer fifth via area 8245 to form a fifth metallization via; the third connection lead 213 is provided with a source-drain seventh via area 227, which is connected with the semiconductor layer seventh via area 8137 to form a seventh metallization via.

[0154] The source-drain lead located in the first source-drain metal layer includes the first source-drain lead 201 of the array substrate and a plurality of wiring leads located in the pixel island area 020. The first source-drain lead 201 includes the first metal lead 231, the second metal lead 232, the third metal lead 233, the fourth metal lead 234, and the fifth metal lead 235 arranged in the set direction C in sequence in the source-drain bridge area 031; the first metal lead 231, the second metal lead 232, the third metal lead 233, and the fourth metal lead 234 extend to the pixel wiring area 021; the fifth metal lead 235 passes through the pixel island area from the side of the first column of pixel driving circuits away from the sixth column of pixel driving circuits. The wiring leads include the sixth metal lead 246 to the twelfth metal lead 2412 located between two columns of pixels; the third metal lead 233 and the twelfth metal lead 2412 are connected.

[0155] The first metal lead wire 231 is connected with the data lead wire structure 0421 of the first column of pixel driving circuits, the second metal lead wire 232 is connected with the data lead wire structure 0421 of the second column of pixel driving circuits, and the fourth metal lead wire 234 is connected with the data lead wire structure 0421 of the fifth column of pixel driving circuits. The sixth metal lead wire 246 is connected with the enable lead wire 8222 of the second row of pixel driving circuits through a via, and is connected with the first gate lead wire 8211 through a via. The seventh metal lead wire 247 is connected with the scan lead wire 8221 of the second row of pixel driving circuits through a via, and is connected with the fourth gate lead wire 8311 through a via. The eighth metal lead wire 248 is connected with the enable lead wire 8222 of the first row of pixel driving circuits through a via, and is connected with the second gate lead wire 8212 through a via. The ninth metal lead wire 249 is connected with the scan lead wire 8221 of the first row of pixel driving circuits through a via, and is connected with the reset lead wire 8223 of the second row of pixel driving circuits through a via, and is connected with the fifth gate lead wire 8312 through a via. The tenth metal lead wire 2410 is connected with the reset lead wire 8223 of the first row of pixel driving circuits through a via, and is connected with the third gate lead wire 8213 through a via. The eleventh metal lead wire 2411 is connected with the initialization lead wire 8321 of the first row of pixel driving circuits through a via, and is connected with the initialization lead wire 8321 of the second row of pixel driving circuits through a via.

[0156] As shown in Figure 21 and Figure 26 , the second source-drain metal layer includes a plurality of source-drain lead wires and a second source-drain conductive structure of the pixel driving circuit.

[0157] The second source-drain conductive structure of the pixel driving circuit includes a column-direction power supply lead wire 411, a row-direction power supply lead wire 412, and a transfer pad 413, wherein the column-direction power supply lead wire 411 and the row-direction power supply lead wire 412 are connected with each other and are electrically connected with the power supply lead wire structure 0411 of the pixel driving circuit through a via. The transfer pad 413 is connected with the third connection lead wire 213 of the pixel driving circuit through a via.

[0158] The source-drain lead lines located at the second source-drain metal layer include a second source-drain lead line 401, which includes a thirteenth metal lead line 4313, a fourteenth metal lead line 4314, a fifteenth metal lead line 4315, and a sixteenth metal lead line 4316 arranged in the set direction C in sequence in the source-drain bridge connection area 031. The thirteenth metal lead line 4313 extends to the pixel wiring area 022 and is connected with the column-direction power supply lead line 411 of the pixel driving circuit. The fourteenth metal lead line 4314 extends to the pixel wiring area 022 and is connected with the data lead line structure 0421 of the third column of pixel driving circuits through a via. The fifteenth metal lead line 4315 extends to the pixel wiring area 020 and is connected with the data lead line structure 0421 of the fourth column of pixel driving circuits through a via. The sixteenth metal lead line 4316 extends to the pixel wiring area 022 and is connected with the data lead line structure 0421 of the sixth column of pixel driving circuits through a via.

[0159] In this way, the first metal lead line 231 is used to load the data signal (V data ) to the data lead line structure 0421 of the first column of pixel driving circuits; the second metal lead line 232 is used to load the data signal (V data ) to the data lead line structure 0421 of the second column of pixel driving circuits; the fourth metal lead line 234 is used to load the data signal (V data ) to the data lead line structure 0421 of the fifth column of pixel driving circuits; the thirteenth metal lead line 4313 is used to load the power voltage to the power supply lead line structure 0411 of each column of pixel driving circuits; the fourteenth metal lead line 4314 is used to load the data signal (V data ) to the data lead line structure 0421 of the third column of pixel driving circuits; the fifteenth metal lead line 4315 is used to load the data signal (V data ) to the data lead line structure 0421 of the fourth column of pixel driving circuits; and the sixteenth metal lead line 4316 is used to load the data signal (V data ) to the data lead line structure 0421 of the sixth column of pixel driving circuits.

[0160] The pixel electrode layer is provided with twelve pixel electrodes, each of which is arranged in correspondence with the transfer pad 413 of each pixel driving circuit and is electrically connected with the corresponding transfer pad 413 through a via.

[0161] The display device can be a head-mounted display, a four-curved-surface mobile phone, or other types of display devices. Since the display device has any one of the flexible array substrates described in the flexible array substrate embodiments, it has the same beneficial effects, and the disclosure will not be repeated here.

[0162] It should be appreciated that the present disclosure is not limited to the details of construction and arrangement of parts set forth in the specification. The present disclosure is capable of other embodiments and of being practiced or being carried out in various ways. Variations and modifications of the foregoing are within the scope of the present disclosure. It should be understood that the present disclosure fully encompasses all combinations of two or more individual features set forth herein and / or in the appended claims. All these different combinations are considered to be within the scope of the present disclosure. The embodiments of the present disclosure as described are to be used as illustrative examples only and are not intended to limit the scope of the present disclosure in any way.

Claims

1. A flexible array substrate, characterized in that: The flexible array substrate includes at least one stretchable region; the flexible array substrate is provided with a plurality of through holes in the stretchable region, and the plurality of through holes divide the stretchable region into a pixel island region for display and a bridge region for signal transmission; the bridge region includes a source-drain bridge region, and the flexible array substrate includes: substrate; A first source-drain metal layer is provided on one side of the base substrate and includes a plurality of first source-drain leads; A first insulating material layer is provided on a side of the first source / drain metal layer away from the base substrate; a second source-drain metal layer, disposed on a side of the first insulating material layer away from the base substrate; the second source-drain metal layer comprises a plurality of second source-drain leads, and the number of the second source-drain leads is less than the number of the first source-drain leads; a second insulating material layer, provided on a side of the second source-drain metal layer away from the base substrate; the second insulating material layer is provided with a plurality of isolation trenches, the orthographic projections of the isolation trenches on the second source-drain metal layer isolating the second source-drain leads from the through-holes; an encapsulation layer, provided on a side of the second insulating material layer away from the base substrate; In the source-drain bridge region, a minimum value of a distance between an orthographic projection of the second source-drain lead on the second insulating material layer and the isolation trench is not less than a spacing between two adjacent second source-drain leads.

2. The flexible array substrate according to claim 1, wherein: In the source-drain bridge region, the width of the isolation trench is no greater than twice the distance between two adjacent second source-drain leads.

3. The flexible array substrate according to claim 1, wherein: In the source-drain bridge area, the width of the isolation groove is equal to 0.9 to 1.1 times the spacing between two adjacent second source-drain leads; between the second source-drain lead and an adjacent through-hole, there are multiple isolation grooves, and the spacing between two adjacent isolation grooves is equal to 0.9 to 1.1 times the spacing between two adjacent second source-drain leads.

4. The flexible array substrate according to claim 1, wherein: In the source-drain bridge region, a distance between two adjacent second source-drain leads is no more than twice the width of the second source-drain leads.

5. The flexible array substrate according to claim 1, wherein: In the source-drain bridge area, a plurality of the second source-drain leads are arranged at equal intervals; and the minimum distance between two adjacent through holes in the source-drain bridge area and the second source-drain leads is equal.

6. The flexible array substrate according to claim 1, wherein: In the source-drain bridge region, a distance between two adjacent first source-drain leads is no greater than a distance between two adjacent second source-drain leads.

7. The flexible array substrate according to claim 1, wherein: In the source-drain bridge area, the minimum value of the distance between the orthographic projection of the first source-drain lead on the second insulating material layer and the isolation trench is not greater than the minimum value of the distance between the orthographic projection of the second source-drain lead on the second insulating material layer and the isolation trench.

8. The flexible array substrate according to claim 1, wherein: In the source-drain bridge region, an orthographic projection of the first source-drain lead on the second insulating material layer at least partially overlaps with the isolation trench.

9. The flexible array substrate according to claim 1, wherein: In the source-drain bridge area, the minimum distance between the orthographic projection of the first source-drain lead on the second insulating material layer and the isolation trench is 1.5 to 2.7 microns; the minimum distance between the orthographic projection of the second source-drain lead on the second insulating material layer and the isolation trench is 4.5 to 6.0 microns.

10. The flexible array substrate according to claim 1, wherein: The number of the first source-drain wirings is greater than the number of the second source-drain wirings by 1 or 2.

11. The flexible array substrate according to claim 1, wherein: The width of the isolation trench at one end away from the base substrate is smaller than the width of the isolation trench at one end close to the base substrate.

12. The flexible array substrate according to any one of claims 1 to 11, wherein: In the source-drain bridge region, an extension direction of the first source-drain lead is parallel to or perpendicular to an extension direction of the through hole; and an extension direction of the second source-drain lead is parallel to or perpendicular to an extension direction of the through hole.

13. The flexible array substrate according to any one of claims 1 to 11, characterized in that: The pixel island region includes a plurality of sub-pixels, and the size of any sub-pixel along the row direction is a first size; in the source-drain bridge region, the spacing between two adjacent second source-drain leads is equal to the second size; The first size is greater than the second size.

14. The flexible array substrate according to any one of claims 1 to 11, characterized in that: The through holes include a first long hole extending in a row direction and a second long hole extending in a column direction; the source-drain bridge region is located between an end of the first long hole and a side of the second long hole.

15. The flexible array substrate according to claim 14, wherein: Any one of the pixel islands is located between two adjacent first long strip holes and between two adjacent second long strip holes; any one of the pixel islands includes four pixels, and any one of the pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

16. The flexible array substrate according to claim 15, wherein: In any one of the pixel islands, four pixels form two pixel rows, and any one of the pixel rows includes two pixels arranged along the row direction; In any one of the pixel rows, the pixel electrode of the blue sub-pixel and the pixel electrode of the red sub-pixel are arranged along the row direction and are located on a side of the pixel electrode of the green sub-pixel away from the other pixel row.

17. The flexible array substrate according to any one of claims 1 to 11, characterized in that: The flexible array substrate includes a plurality of sub-pixels arranged in an array in any one of the pixel island areas, and any one of the sub-pixels includes a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit; Any one of the pixel driving circuits includes a storage capacitor, a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor; wherein, The first end of the first thin film transistor is used to load an initial signal, the second end of the first thin film transistor is electrically connected to the first electrode plate of the storage capacitor, and the control end of the first thin film transistor is used to load a reset signal; a first end of the second thin film transistor electrically connected to the second end of the third thin film transistor and the first end of the sixth thin film transistor, a second end of the second thin film transistor electrically connected to the first electrode plate of the storage capacitor, and a control end of the second thin film transistor for loading a scan signal; The first end of the third thin film transistor is electrically connected to the second end of the fourth thin film transistor and the second end of the fifth thin film transistor, and the control end of the third thin film transistor is electrically connected to the first electrode plate of the storage capacitor; The first terminal of the fourth thin film transistor is used to load the data signal, and the control terminal of the fourth thin film transistor is used to load the scan signal; The first terminal of the fifth thin film transistor is used to load a power supply voltage, and the control terminal of the fifth thin film transistor is used to load an enable signal; The second end of the sixth thin film transistor is used to be electrically connected to the pixel electrode, and the control end of the sixth thin film transistor is used to load the enable signal; The first terminal of the seventh thin film transistor is used to load the initial signal, the second terminal of the seventh thin film transistor is used to be electrically connected to the pixel electrode, and the control terminal of the seventh thin film transistor is used to load the reset signal; The second electrode plate of the storage capacitor is used to load the power supply voltage.

18. The flexible array substrate according to claim 17, wherein: Any one of the pixel islands includes a first column of pixel driving circuits, a second column of pixel driving circuits, a third column of pixel driving circuits, a fourth column of pixel driving circuits, a fifth column of pixel driving circuits, and a sixth column of pixel driving circuits sequentially arranged along a set direction, and any one column of pixel driving circuits includes a plurality of the pixel driving circuits arranged along the column direction; wherein the set direction is a direction parallel to the row direction; In the source-drain bridge area, the number of the first source-drain leads is five; the first first source-drain lead along the set direction is used to load the data signal to the first column pixel driving circuit; the second first source-drain lead along the set direction is used to load the data signal to the second column pixel driving circuit; and the fourth first source-drain lead along the set direction is used to load the data signal to the fifth column pixel driving circuit.

19. The flexible array substrate according to claim 18, wherein: In the source-drain bridge area, the number of the second source-drain leads is four; the first second source-drain lead along the set direction is used to load the power supply voltage to the first column pixel driving circuit to the sixth column pixel driving circuit; the second second source-drain lead along the set direction is used to load the data signal to the third column pixel driving circuit; the third second source-drain lead along the set direction is used to load the data signal to the fourth column pixel driving circuit; and the fourth second source-drain lead along the set direction is used to load the data signal to the sixth column pixel driving circuit.

20. A display device, characterized in that: The flexible array substrate comprises the flexible array substrate according to any one of claims 1 to 19.

Images