A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. By enabling the driving pixel circuit in the second display area to drive the second light-emitting device in the second display area to emit light, the second display area can achieve a light-emitting display effect. Moreover, by using the virtual pixel circuit in the peripheral area to drive the first light-emitting device in the first display area to emit light, the first display area can achieve a light-emitting display effect, and further the entire display area can achieve a light-emitting display effect. Since the first light-emitting device is provided in the first display area without providing a pixel circuit and a metal trace, not only can the first display area achieve a display function, but also the first display area has no pixel circuit and metal trace, so that the light transmittance of the first display area is high.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the rapid development of display technologies, the screen-to-body ratio of display products has gradually increased. However, in display products, such as mobile phones, components such as front cameras and sensors need to be provided, which is not conducive to the design of full-screen displays. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to achieve full-screen design and increase the screen-to-body ratio.

[0004] A display panel provided by an embodiment of the present invention includes:

[0005] A substrate, including a display area and a peripheral area surrounding the display area; wherein, the display area includes a first display area and a second display area;

[0006] A plurality of pixel circuits, including a plurality of virtual pixel circuits and a plurality of driving pixel circuits; wherein, the plurality of virtual pixel circuits are located in the peripheral area, and the plurality of driving pixel circuits are located in the second display area;

[0007] A plurality of light-emitting devices, located on a side of the plurality of pixel circuits away from the substrate, and the plurality of light-emitting device layers include a plurality of first light-emitting devices and a plurality of second light-emitting devices; wherein, the plurality of first light-emitting devices are located in the first display area, and the plurality of second light-emitting devices are located in the second display area;

[0008] Wherein, at least one of the virtual pixel circuits is electrically connected to at least one of the first light-emitting devices, and at least one of the driving pixel circuits is electrically connected to at least one of the second light-emitting devices.

[0009] In some examples, the plurality of first light-emitting devices are arranged in an array in the first display area, and the plurality of second light-emitting devices are arranged in an array in the second display area; wherein, one row of the first light-emitting devices and one row of the second light-emitting devices are in the same row; and / or, one column of the first light-emitting devices and one column of the second light-emitting devices are in the same column.

[0010] In some examples, the peripheral area includes a first peripheral sub-area and a second peripheral sub-area that are oppositely arranged, and a third peripheral sub-area and a fourth peripheral sub-area that are oppositely arranged;

[0011] The first peripheral sub-region, the first display region, and the second peripheral sub-region are arranged along a first direction, and the third peripheral sub-region, the first display region, and the fourth peripheral sub-region are arranged along a second direction; wherein, the first direction is different from the second direction;

[0012] The multiple virtual pixel circuits are located in at least one of the first peripheral sub-region, the second peripheral sub-region, the third peripheral sub-region, and the fourth peripheral sub-region, and the virtual pixel circuits are electrically connected to the first light-emitting device through at least one connecting trace.

[0013] In some examples, the distance between the first peripheral sub-region and the first display region is less than the distance between the second peripheral sub-region and the first display region, and the multiple virtual pixel circuits are arranged in the first peripheral sub-region.

[0014] In some examples, the first peripheral sub-region includes a plurality of first virtual regions arranged along the second direction; wherein, each of the first virtual regions includes a plurality of virtual pixel circuits arranged in an array;

[0015] The multiple first light-emitting devices are divided into multiple first row groups; each of the first row groups includes at least two adjacent rows of the first light-emitting devices;

[0016] One of the first row groups corresponds to one of the first virtual regions, and one of the first light-emitting devices in the first row group is electrically connected to one of the virtual pixel circuits in the corresponding first virtual region through the connecting trace.

[0017] In some examples, the first row group includes a first sub-row group and a second sub-row group; wherein, the first display region has a first center line along the first direction, and the first light-emitting devices in the first sub-row group and the second sub-row group are symmetrically arranged along the first center line;

[0018] The first virtual region includes a first sub-virtual region and a second sub-virtual region; wherein, the first sub-virtual region and the second sub-virtual region are symmetrically arranged along the first center line, and the first sub-row group and the first sub-virtual region are located on the same side of the first center line;

[0019] The first light-emitting device in the first sub-row group is electrically connected to the virtual pixel circuit in the first sub-virtual region through the connecting trace;

[0020] The first light-emitting device in the second sub-row group is electrically connected to the virtual pixel circuit in the second sub-virtual region through the connecting trace.

[0021] In some examples, in the same first row group, the connecting traces corresponding to the first sub-row group and the second sub-row group are symmetrically arranged along the first center line.

[0022] In some examples, the second display area further includes a plurality of driving gate lines and a plurality of driving data lines; wherein, one row of the driving pixel circuits is electrically connected to one of the driving gate lines, and one column of the driving pixel circuits is electrically connected to one of the driving data lines;

[0023] The first sub-virtual area further includes: a plurality of first sub-virtual gate lines and a plurality of first sub-virtual data lines; wherein, in the first sub-virtual area, one row of the virtual pixel circuits is electrically connected to one of the first sub-virtual gate lines, and one column of the virtual pixel circuits is electrically connected to one of the first sub-virtual data lines;

[0024] The second sub-virtual area further includes: a plurality of second sub-virtual gate lines and a plurality of second sub-virtual data lines; wherein, in the second sub-virtual area, one row of the virtual pixel circuits is electrically connected to one of the second sub-virtual gate lines, and one column of the virtual pixel circuits is electrically connected to one of the second sub-virtual data lines;

[0025] For the first light-emitting device and the second light-emitting device in the same row, the driving signals transmitted by the first sub-virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, the second sub-virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, and the driving gate line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are the same;

[0026] For the first light-emitting device and the second light-emitting device in the same column, the first sub-virtual data line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, the second sub-virtual data line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, and the driving data line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are electrically connected.

[0027] In some examples, the peripheral area further includes: a gate driving circuit electrically connected to the plurality of driving gate lines; wherein, the gate driving circuit is configured to input driving signals to the plurality of driving gate lines, and for the first light-emitting device and the second light-emitting device in the same row, the first sub-virtual gate line, the second sub-virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, and the driving gate line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are electrically connected; or,

[0028] The peripheral region further includes: a gate driving circuit electrically connected to the plurality of driving gate lines, a first virtual gate driving circuit electrically connected to the plurality of first sub-virtual gate lines, and a second virtual gate driving circuit electrically connected to the plurality of second sub-virtual gate lines; wherein, the gate driving circuit is configured to input a driving signal to the plurality of driving gate lines, the first virtual gate driving circuit is configured to input a driving signal to the plurality of first sub-gate lines, and the second virtual gate driving circuit is configured to input a driving signal to the plurality of second sub-gate lines.

[0029] In some examples, some of the plurality of virtual pixel circuits are located in the third peripheral sub-region, and the remaining parts of the plurality of virtual pixel circuits are located in the fourth peripheral sub-region.

[0030] In some examples, the second display region further includes a plurality of driving gate lines and a plurality of driving data lines; wherein, one row of the driving pixel circuits is electrically connected to one of the driving gate lines, and one column of the driving pixel circuits is electrically connected to one of the driving data lines;

[0031] The third peripheral sub-region further includes: a plurality of second virtual gate lines and a plurality of second virtual data lines; wherein, in the third peripheral sub-region, one row of the virtual pixel circuits is electrically connected to one of the second virtual gate lines, and one column of the virtual pixel circuits is electrically connected to one of the second virtual data lines;

[0032] The fourth peripheral sub-region further includes: a plurality of third virtual gate lines and a plurality of third virtual data lines; wherein, in the fourth peripheral sub-region, one row of the virtual pixel circuits is electrically connected to one of the third virtual gate lines, and one column of the virtual pixel circuits is electrically connected to one of the third virtual data lines;

[0033] For the first light-emitting device and the second light-emitting device in the same row, the driving signals transmitted by the second virtual gate line and the third virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device and the driving gate line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are the same;

[0034] For the first light-emitting device and the second light-emitting device in the same column, the second virtual data line and the third virtual data line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device and the driving data line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are electrically connected.

[0035] In some examples, the peripheral area further includes: a gate driving circuit electrically connected to the plurality of driving gate lines; wherein, the gate driving circuit is configured to input a driving signal to the plurality of driving gate lines, and for the first light-emitting device and the second light-emitting device in the same row, the second virtual gate line and the third virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device and the driving gate line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are the same; or,

[0036] The peripheral area further includes: a gate driving circuit electrically connected to the plurality of driving gate lines, a second virtual gate driving circuit electrically connected to the plurality of second virtual gate lines, and a third virtual gate driving circuit electrically connected to the plurality of third virtual gate lines; wherein, the gate driving circuit is configured to input a driving signal to the plurality of driving gate lines, the second virtual gate driving circuit is configured to input a driving signal to the plurality of second virtual gate lines, and the third virtual gate driving circuit is configured to input a driving signal to the plurality of third virtual gate lines.

[0037] An embodiment of the present invention further provides a display device, including the above display panel.

[0038] The beneficial effects of the present invention are as follows:

[0039] The display panel and the display device provided by the embodiment of the present invention enable the driving pixel circuit in the second display area to drive the second light-emitting device in the second display area to emit light, so that the second display area can achieve a light-emitting display effect. And, the virtual pixel circuit in the peripheral area is used to drive the first light-emitting device in the first display area to emit light, so that the first display area can achieve a light-emitting display effect, and further the entire display area can achieve a light-emitting display effect. Since the first light-emitting device is provided in the first display area without providing a pixel circuit and a metal trace, not only can the first display area achieve a display function, but also the first display area has no pixel circuit and metal trace, so that the light transmittance of the first display area is high. In this way, when the display panel is applied to a display device, components such as a front camera, a sensor, and a receiver can be provided below the first display area of the display panel to achieve a full-screen design and improve the screen-to-body ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1a are schematic structural diagrams of some display panels in the embodiments of the present invention;

[0041] Figure 1b are schematic structural diagrams of some other display panels in the embodiments of the present invention;

[0042] Figure 1c are schematic structural diagrams of some further display panels in the embodiments of the present invention;

[0043] Figure 2 Schematic diagram of a partial cross-sectional structure of some display panels in an embodiment of the present invention;

[0044] Figure 3a Schematic diagram of the structure of some other display panels in an embodiment of the present invention;

[0045] Figure 3b Schematic diagram of the structure of some other display panels in an embodiment of the present invention;

[0046] Figure 4 Schematic diagram of the structure of some other display panels in an embodiment of the present invention;

[0047] Figure 5 Schematic diagram of the structure of some other display panels in an embodiment of the present invention. Detailed implementation manners

[0048] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. And, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The "first", "second" and similar terms used in the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0050] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present invention. And, the same or similar reference numerals throughout denote the same or similar elements or elements having the same or similar functions.

[0051] Organic Light Emitting Diode (OLED) display panel has the advantages of low energy consumption and self-luminescence, and is one of the hot spots in the field of flat panel display panel research. Since OLED is current-driven, a stable current is required to control its light emission. Generally, OLED display panels use pixel circuits to generate driving current to drive OLED to emit light. In specific implementation, the pixel circuit generally has transistors and capacitors, so that the driving current can be generated by the combination of transistors and capacitors to drive OLED to emit light.

[0052] In order to improve the uniformity of the characteristics of the transistors in the pixel circuit, a virtual pixel circuit 121 may be provided in the peripheral area BB surrounding the display area AA, so that the pixel circuit in the display area AA and the virtual pixel circuit 121 in the peripheral area BB may be prepared simultaneously, thereby improving the uniformity of the transistors in the display area AA.

[0053] In view of this, an embodiment of the present invention provides a display panel, which drives the first light-emitting device 111 in the first display area aa1 to emit light by reusing the virtual pixel circuit 121 in the peripheral area BB, so that the first display area aa1 can achieve a light-emitting display effect. In this way, not only can the entire display area AA achieve a light-emitting display effect, but also the light transmittance in the first display area aa1 can be improved.

[0054] In a specific implementation, an embodiment of the present invention provides a display panel, such as Figure 1a and Figure 1b As shown, it may include:

[0055] The base substrate 100 includes a display area AA and a peripheral area BB surrounding the display area AA; wherein the display area AA includes a first display area aa1 and a second display area aa2;

[0056] A plurality of pixel circuits, including a plurality of virtual pixel circuits 121 and a plurality of driving pixel circuits 122; wherein the plurality of virtual pixel circuits 121 are located in the peripheral area BB, and the plurality of driving pixel circuits 122 are located in the second display area aa2;

[0057] A plurality of light-emitting devices are located on a side of the plurality of pixel circuits away from the base substrate 100, and the plurality of light-emitting device layers include a plurality of first light-emitting devices 111 and a plurality of second light-emitting devices 112; wherein the plurality of first light-emitting devices 111 are located in the first display area aa1, and the plurality of second light-emitting devices 112 are located in the second display area aa2;

[0058] Among them, at least one virtual pixel circuit 121 is electrically connected to at least one first light-emitting device 111 , and at least one driving pixel circuit 122 is electrically connected to at least one second light-emitting device 112 .

[0059] In the display panel provided by the embodiment of the present invention, by driving the second light-emitting device 112 in the second display area aa2 with the driving pixel circuit 122 in the second display area aa2, the second display area aa2 can achieve a light-emitting display effect. Moreover, by driving the first light-emitting device 111 in the first display area aa1 with the virtual pixel circuit 121 in the peripheral area BB, the first display area aa1 can achieve a light-emitting display effect, and further the entire display area AA can achieve a light-emitting display effect. Since the first light-emitting device 111 is provided in the first display area aa1 without providing a pixel circuit and metal traces (such as a driving gate line 131 and a driving data line 161), not only can the first display area aa1 achieve a display function, but also the first display area aa1 has no pixel circuit and metal traces, so that the light transmittance of the first display area aa1 is high. In this way, when the display panel is applied to a display device, components such as a front camera, a sensor, and a receiver can be provided below the first display area aa1 of the display panel to achieve a full-screen design and increase the screen-to-body ratio.

[0060] Exemplarily, the virtual pixel circuit 121 for driving the first light-emitting device 111 to emit light in the embodiment of the present invention can be a virtual pixel circuit provided in the peripheral area BB to improve the uniformity of the characteristics of the transistors of the pixel circuits in the display area. In this way, this part of the virtual pixel circuit 121 in the peripheral area BB can be reused to drive the first light-emitting device 111 in the first display area aa1 to emit light, so that the first display area aa1 can achieve a light-emitting display effect. Moreover, no additional virtual pixel circuit needs to be provided, so that the width of the peripheral area BB can be ensured to be small.

[0061] In specific implementation, in the embodiment of the present invention, the display panel may include: a plurality of pixel units arranged in an array in the first display area aa1 and the second display area aa2. Each pixel unit includes a plurality of sub-pixels. Exemplarily, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0062] In specific implementation, in the embodiment of the present invention, the pixel distribution density in the first display area aa1 may be less than the pixel distribution density in the second display area aa2. This can further improve the light transmittance of the first display area aa1.

[0063] In specific implementation, in the embodiments of the present invention, a plurality of first light-emitting devices 111 are arranged in an array in the first display area aa1, and a plurality of second light-emitting devices 112 are arranged in an array in the second display area aa2. For example, in the first display area aa1, one sub-pixel may include one first light-emitting device 111. In the second display area aa2, one sub-pixel may include one driving pixel circuit 122 and one second light-emitting device 112, and the driving pixel circuit 122 and the second light-emitting device 112 in the same sub-pixel are electrically connected to each other. Among them, a row of first light-emitting devices 111 and a row of second light-emitting devices 112 may be located in the same row. Or a column of first light-emitting devices 111 and a column of second light-emitting devices 112 may be located in the same column. In this way, the first light-emitting devices 111 in the first display area aa1 and the second light-emitting devices 112 in the second display area aa2 can be evenly arranged.

[0064] In specific implementation, in the embodiments of the present invention, the first light-emitting device 111 and the second light-emitting device 112 may respectively include: an anode, a light-emitting layer, and a cathode arranged in a stack. Among them, the virtual pixel circuit 121 is electrically connected to the anode of the first light-emitting device 111, and the driving pixel circuit 122 is electrically connected to the anode of the second light-emitting device 112. Exemplarily, the first light-emitting device 111 and the second light-emitting device 112 may include at least one of: an OLED, a quantum dot light emitting diode (QLED), a Micro LED, and a Mini LED. Further, the anode and the cathode of the first light-emitting device 111 may both be transparent conductive materials, such as indium tin oxide (ITO) materials, indium zinc oxide (IZO) materials, carbon nanotubes, or graphene, etc. The anode of the second light-emitting device 112 may both be reflective conductive materials, such as metal materials, such as gold, silver, aluminum, etc. The cathode of the second light-emitting device 112 may both be transparent conductive materials, such as indium tin oxide (ITO) materials, indium zinc oxide (IZO) materials, carbon nanotubes, or graphene, etc., which is not limited herein.

[0065] In specific implementation, the virtual pixel circuit 121 and the driving pixel circuit 122 may respectively include a plurality of transistors and capacitors. Exemplarily, in the embodiments of the present invention, as Figure 2As shown, taking one transistor in the virtual pixel circuit 121 as an example and taking one transistor in the driving pixel circuit 122 as an example, the display panel may include a transistor array layer 010 located on the substrate 100, a first planarization layer 011 located on the side of the transistor array layer 010 away from the substrate 100, the layer where the connection trace 210 is located on the side of the first planarization layer 011 away from the substrate 100, a second planarization layer 012 located on the side of the layer where the connection trace 210 is located away from the substrate 100, a third planarization layer 013 located on the side of the second planarization layer 012 away from the substrate 100, the layer where the anode 310 is located on the side of the third planarization layer 013 away from the substrate 100, a pixel defining layer 014 located on the side of the anode 310 - located layer away from the substrate 100, a light - emitting layer 320 located on the side of the pixel defining layer 014 away from the substrate 100, and a cathode 330 located on the side of the light - emitting layer 320 away from the substrate 100. Among them, the transistor array layer 010 includes an active layer for forming a transistor, a gate insulating layer, a gate, an interlayer dielectric layer, a capacitive electrode layer, an interlayer insulating layer, and the layer where the source and drain are located. And, in the second display area aa2, the drain of the transistor in the driving pixel circuit 122 is directly electrically connected to the anode 310 of the second light - emitting device 112 through a second via 016 penetrating the first planarization layer 011, the second planarization layer 012, and the third planarization layer 013. The virtual pixel circuit 121 in the peripheral area BB can be electrically connected to the first light - emitting device 111 in the first display area aa1 through at least one connection trace 210. For example, one end of the connection trace 210 is electrically connected to the drain of the transistor in the virtual pixel circuit 121 through a first via 015 penetrating the first planarization layer 011, and the other end of the connection trace 210 is electrically connected to the anode 310 of the first light - emitting device 111 through a via penetrating the second planarization layer 012 and the third planarization layer 013.

[0066] In specific implementation, in the embodiments of the present invention, as Figure 1a shown, one virtual pixel circuit 121 can be electrically connected to one first light - emitting device 111 through one connection trace 210. Further, the material of the connection trace 210 can be a transparent conductive material, such as indium tin oxide (ITO) material, indium zinc oxide (IZO) material, carbon nanotubes, or graphene, etc., which is not limited herein.

[0067] In specific implementation, in the embodiments of the present invention, as Figure 1a and Figure 1bAs shown, the connecting traces 210 are arranged at intervals, which can avoid short - circuit of the connecting traces 210 and affect the display. Further, there is a gap between the orthographic projection of the connecting trace 210 on the substrate 100 and the orthographic projection of the second via 016 on the substrate 100, which can avoid the electrical connection between the connecting trace 210 and the second light - emitting device 112 and affect the display effect.

[0068] In specific implementation, in the embodiment of the present invention, as Figure 1a and Figure 1b shown, the peripheral area BB includes a relatively - arranged first peripheral sub - area bb1 and second peripheral sub - area bb2, and a relatively - arranged third peripheral sub - area bb3 and fourth peripheral sub - area bb4. And, the first peripheral sub - area bb1, the first display area aa1, and the second peripheral sub - area bb2 are arranged along the first direction F1, and the third peripheral sub - area bb3, the first display area aa1, and the fourth peripheral sub - area bb4 are arranged along the second direction F2; wherein, the first direction F1 is different from the second direction F2. And, a plurality of virtual pixel circuits 121 are located in at least one of the first peripheral sub - area bb1, the second peripheral sub - area bb2, the third peripheral sub - area bb3, and the fourth peripheral sub - area bb4. Exemplarily, the peripheral area BB has four sides, two of which are relatively arranged, and the other two are relatively arranged. A plurality of virtual pixel circuits 121 are located in at least one of these four sides. Exemplarily, the first direction F1 may be the row direction of the sub - pixels, and the second direction F2 may be the column direction of the sub - pixels. Or, the first direction F1 may be the column direction of the sub - pixels, and the second direction F2 may be the row direction of the sub - pixels, which is not limited herein.

[0069] In specific implementation, in the embodiment of the present invention, as Figure 1a and Figure 1b shown, the distance between the first peripheral sub - area bb1 and the first display area aa1 is less than the distance between the second peripheral sub - area bb2 and the first display area aa1. Exemplarily, the minimum distance between the edge of the first peripheral sub - area bb1 and the center of the first display area aa1 is less than the minimum distance between the edge of the second peripheral sub - area bb2 and the center of the first display area aa1. Exemplarily, the second display area aa2 surrounds the first display area aa1. The first display area aa1 is close to the edge of the first peripheral sub - area bb1. Further, a plurality of virtual pixel circuits 121 are arranged in an array in the first peripheral sub - area bb1. This can reduce the length of the connecting traces 210 between the plurality of virtual pixel circuits 121 and the first light - emitting device 111, thereby reducing the problem of large resistance caused by the long connecting traces 210.

[0070] In specific implementation, in the embodiment of the present invention, as Figure 1a and Figure 1bAs shown, the second display area aa2 may further include a plurality of driving gate lines 131 and a plurality of driving data lines 161; among them, one row of driving pixel circuits 122 is electrically connected to one driving gate line 131, and one column of driving pixel circuits 122 is electrically connected to one driving data line 161. In this way, a driving signal can be provided to the driving pixel circuit 122 through the driving gate line 131, and a data display signal can be provided to the driving pixel circuit 122 through the driving data line 161, so that the driving pixel circuit 122 can control the second light-emitting device 112 to emit light.

[0071] In a specific implementation, in the embodiment of the present invention, as Figure 3a With Figure 3b shown, the first peripheral sub-region bb1 may include a plurality of first virtual regions XN-k arranged along the second direction F2 (1≤k≤K, k and K are integers, and K = 2 is taken as an example in the figure); among them, each first virtual region XN-k may include a plurality of virtual pixel circuits arranged in an array. Exemplarily, the number of virtual pixel circuits included in each first virtual region XN-k may be the same. Of course, it is also possible to make the number of virtual pixel circuits included in some first virtual regions XN-k the same, and the rest different, which is not limited herein.

[0072] In a specific implementation, in the embodiment of the present invention, as Figure 3a With Figure 3b shown, a plurality of first light-emitting devices can be divided into a plurality of first row groups HZ-k; each first row group HZ-k may include at least two adjacent rows of first light-emitting devices. Exemplarily, the number of first row groups may be the same as the number of first virtual regions. Then, one first row group can correspond to one first virtual region, and one first light-emitting device in the first row group is electrically connected to one virtual pixel circuit in the corresponding first virtual region through a connection trace. For example, as Figure 3a With Figure 3b shown, each first row group HZ-k may include two adjacent rows of first light-emitting devices. Alternatively, each first row group HZ-k may also include three adjacent rows of first light-emitting devices. Alternatively, each first row group HZ-k may also include four adjacent rows of first light-emitting devices. Of course, in actual applications, the number of rows of first light-emitting devices included in each first row group HZ-k can be determined according to the requirements of the actual application environment, which is not limited herein.

[0073] In a specific implementation, in the embodiment of the present invention, as Figure 3a With Figure 3bAs shown, the first row group HZ-k may include a first sub-row group HZ1-k and a second sub-row group HZ2-k; wherein, the first display area aa1 may have a first center line L0 along the first direction F1. Among them, the first display area aa1 may be arranged approximately symmetrically with respect to the first center line L0. And, the first virtual area XN-k may include a first sub-virtual area XN1-k and a second sub-virtual area XN2-k; wherein, the first sub-virtual area XN1-k and the second sub-virtual area XN2-k are arranged symmetrically along the first center line L0.

[0074] Exemplarily, as Figure 3a With Figure 3b shown, the first light-emitting devices 111 in the first sub-row group HZ1-k and the second sub-row group HZ2-k in the same first row group HZ-k may be arranged symmetrically along the first center line L0. It is also possible to arrange the first sub-virtual area XN1-k and the second sub-virtual area XN2-k in the same first virtual area XN-k symmetrically along the first center line L0. Further, the first sub-row group HZ1-k and the first sub-virtual area XN1-k are located on the same side of the first center line L0, that is, the first sub-row group HZ1-k and the first sub-virtual area XN1-k are located on one side of the first center line L0, and the second sub-row group HZ2-k and the second sub-virtual area XN2-k are located on the other side of the first center line L0. And, the first light-emitting device 111 in the first sub-row group HZ1-k is electrically connected to the virtual pixel circuit 121 in the first sub-virtual area XN1-k through the connection trace 210. And, the first light-emitting device 111 in the second sub-row group HZ2-k is electrically connected to the virtual pixel circuit 121 in the second sub-virtual area XN2-k through the connection trace 210.

[0075] In a specific implementation, in the embodiment of the present invention, as Figure 3a With Figure 3b shown, in the same first row group HZ-k, the connection traces 210 corresponding to the first sub-row group HZ1-k and the second sub-row group HZ2-k may be arranged symmetrically along the first center line L0. This can improve the symmetry of the display panel and reduce the patterning process of the connection traces.

[0076] In a specific implementation, in the embodiment of the present invention, as Figure 3a With Figure 3bAs shown, the first sub-virtual region XN1-k may further include: a plurality of first sub-virtual gate lines 021 and a plurality of first sub-virtual data lines 031; wherein, in the first sub-virtual region XN1-k, one row of virtual pixel circuits 121 is electrically connected to one first sub-virtual gate line 021, and one column of virtual pixel circuits 121 is electrically connected to one first sub-virtual data line 031. Among them, for the first light-emitting devices 111 and the second light-emitting devices 112 in the same row, the driving signals transmitted by the first sub-virtual gate line 021 to which the virtual pixel circuit 121 corresponding to the first light-emitting device 111 is electrically connected and the driving gate line 131 to which the driving pixel circuit 122 corresponding to the second light-emitting device 112 is electrically connected are the same. In this way, the first light-emitting devices 111 and the second light-emitting devices 112 in the same row can be lit simultaneously. And, for the first light-emitting devices 111 and the second light-emitting devices 112 in the same column, the first sub-virtual data line 031 to which the virtual pixel circuit 121 corresponding to the first light-emitting device 111 is electrically connected and the driving data line 161 to which the driving pixel circuit 122 corresponding to the second light-emitting device 112 is electrically connected are electrically connected.

[0077] In a specific implementation, in the embodiment of the present invention, as Figure 3a with Figure 3b shown, the second sub-virtual region may further include: a plurality of second sub-virtual gate lines 022 and a plurality of second sub-virtual data lines 032; wherein, in the second sub-virtual region XN2-k, one row of virtual pixel circuits 121 is electrically connected to one second sub-virtual gate line 022, and one column of virtual pixel circuits 121 is electrically connected to one second sub-virtual data line 032. Among them, for the first light-emitting devices 111 and the second light-emitting devices 112 in the same row, the driving signals transmitted by the second sub-virtual gate line 022 to which the virtual pixel circuit 121 corresponding to the first light-emitting device 111 is electrically connected and the driving gate line 131 to which the driving pixel circuit 122 corresponding to the second light-emitting device 112 is electrically connected are the same. In this way, the first light-emitting devices 111 and the second light-emitting devices 112 in the same row can be lit simultaneously. And, for the first light-emitting devices 111 and the second light-emitting devices 112 in the same column, the second sub-virtual data line 032 to which the virtual pixel circuit 121 corresponding to the first light-emitting device 111 is electrically connected and the driving data line 161 to which the driving pixel circuit 122 corresponding to the second light-emitting device 112 is electrically connected are electrically connected.

[0078] In a specific implementation, in the embodiment of the present invention, as Figure 3bAs shown, the peripheral region BB may further include: a gate driving circuit 150 electrically connected to a plurality of driving gate lines 131; wherein, the gate driving circuit 150 is configured to input driving signals to the plurality of driving gate lines 131, and for the first light-emitting device 111 and the second light-emitting device 112 in the same row, the first sub-virtual gate line 021 and the second sub-virtual gate line 022 electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 and the driving gate line 131 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112 are electrically connected. In this way, the driving gate, the first sub-virtual gate line 021, and the second sub-virtual gate line 022 can share the gate driving circuit 150.

[0079] Alternatively, in a specific implementation, the peripheral region further includes: a gate driving circuit electrically connected to a plurality of driving gate lines, a first virtual gate driving circuit electrically connected to a plurality of first sub-virtual gate lines, and a second virtual gate driving circuit electrically connected to a plurality of second sub-virtual gate lines; wherein, the gate driving circuit is configured to input driving signals to the plurality of driving gate lines, the first virtual gate driving circuit is configured to input driving signals to the plurality of first sub-gate lines, and the second virtual gate driving circuit is configured to input driving signals to the plurality of second sub-gate lines. In this way, the first sub-gate line, the second sub-pixel, and the driving gate line can be independently controlled respectively.

[0080] Alternatively, in a specific implementation, in the embodiment of the present invention, as Figure 1a shown in Figure 1b As shown, the first peripheral sub-region bb1 further includes a plurality of first virtual gate lines 132 and a plurality of first virtual data lines 162; wherein, one virtual pixel circuit 121 in one row is electrically connected to one first virtual gate line 132, and one virtual pixel circuit 121 in one column is electrically connected to one first virtual data line 162. In this way, driving signals can be provided to the virtual pixel circuit 121 through the first virtual gate line 132, and data display signals can be provided to the virtual pixel circuit 121 through the first virtual data line 162, so that the virtual pixel circuit 121 can control the first light-emitting device 111 to emit light.

[0081] In a specific implementation, in the embodiment of the present invention, as Figure 1b shown, for the first light-emitting device 111 and the second light-emitting device 112 in the same column, the first virtual data line 162 electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 and the driving data line 161 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112 are electrically connected.

[0082] In a specific implementation, in the embodiment of the present invention, as Figure 1a shown in Figure 1bAs shown, for the first light-emitting device 111 and the second light-emitting device 112 in the same row, the driving signals transmitted by the first virtual gate line 132 electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 and the driving gate line 131 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112 are the same. In this way, the first light-emitting device 111 and the second light-emitting device 112 in the same row can be lit simultaneously.

[0083] In specific implementation, in the embodiment of the present invention, as Figure 1a With Figure 1b shown, the peripheral area BB may further include: a gate driving circuit 150 electrically connected to a plurality of driving gate lines 131; wherein, the gate driving circuit 150 is configured to input driving signals to the plurality of driving gate lines 131, and for the first light-emitting device 111 and the second light-emitting device 112 in the same row, the first virtual gate line 132 electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 and the driving gate line 131 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112 are electrically connected. In this way, the driving gate and the first virtual gate line 132 can share the gate driving circuit 150.

[0084] Exemplarily, the display panel may adopt bilateral driving to reduce the delay of the driving signal. For example, a gate driving circuit 150 is provided in the third peripheral sub-area bb3 of the peripheral area BB. Another gate driving circuit 150 is provided in the fourth peripheral sub-area bb4 of the peripheral area BB. That is, two gate driving circuits 150 are provided. Of course, the display panel may also adopt unilateral driving. For example, a gate driving circuit 150 is provided in the third peripheral sub-area bb3 of the peripheral area BB. Or, a gate driving circuit 150 is provided in the fourth peripheral sub-area bb4 of the peripheral area BB.

[0085] The embodiment of the present invention further provides some display panels, and the schematic structural diagram is as Figure 1c shown, which is a deformation of the implementation manner in the above embodiment. Only the differences between this embodiment and the above embodiment will be described below, and the same parts will not be elaborated here.

[0086] In specific implementation, in the embodiment of the present invention, as Figure 1c shown, the peripheral area BB may further include: a gate driving circuit 150 electrically connected to a plurality of driving gate lines 131; wherein, the gate driving circuit 150 is configured to input driving signals to the plurality of driving gate lines 131. In this way, the gate driving circuit 150 can input driving signals to the driving gate.

[0087] Exemplarily, the display panel may adopt bilateral driving to reduce the delay of the driving signal. For example, a gate driving circuit 150 is provided in the third peripheral sub-region bb3 of the peripheral region BB. Another gate driving circuit 150 is provided in the fourth peripheral sub-region bb4 of the peripheral region BB. That is, two gate driving circuits 150 are provided. Of course, the display panel may also adopt unilateral driving. For example, a gate driving circuit 150 is provided in the third peripheral sub-region bb3 of the peripheral region BB. Or, a gate driving circuit 150 is provided in the fourth peripheral sub-region bb4 of the peripheral region BB.

[0088] In specific implementation, in the embodiments of the present invention, as Figure 1c shown, the peripheral region BB may further include: a first virtual gate driving circuit 221 electrically connected to a plurality of first virtual gate lines 132; wherein, the first virtual gate driving circuit 221 is configured to input driving signals to the plurality of first virtual gate lines 132. This can enable the driving gate and the first virtual gate lines 132 to be independently controlled respectively.

[0089] Exemplarily, the display panel may adopt bilateral driving to reduce the delay of the driving signal. For example, a first virtual gate driving circuit 221 is provided in the third peripheral sub-region bb3 of the peripheral region BB. Another first virtual gate driving circuit 221 is provided in the fourth peripheral sub-region bb4 of the peripheral region BB. That is, two first virtual gate driving circuits 221 are provided. Of course, the display panel may also adopt unilateral driving. For example, a first virtual gate driving circuit 221 is provided in the third peripheral sub-region bb3 of the peripheral region BB. Or, a first virtual gate driving circuit 221 is provided in the fourth peripheral sub-region bb4 of the peripheral region BB.

[0090] The embodiments of the present invention further provide some display panels, and the schematic structural diagram is as Figure 4 shown, which is a modification of the implementation manner in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0091] In specific implementation, in the embodiments of the present invention, as Figure 4 shown, some of the plurality of virtual pixel circuits 121 are located in the third peripheral sub-region bb3, and the rest of the plurality of virtual pixel circuits 121 are located in the fourth peripheral sub-region bb4. This can disperse the virtual pixel circuits 121 and reduce the width of the peripheral region BB.

[0092] Further, the number of virtual pixel circuits 121 in the third peripheral sub-region bb3 and the fourth peripheral sub-region bb4 can be made the same. In this way, the occupied areas of the virtual pixel circuits 121 in the third peripheral sub-region bb3 and the fourth peripheral sub-region bb4 can be made as identical as possible. Alternatively, in practical applications, the number of virtual pixel circuits 121 in the third peripheral sub-region bb3 and the fourth peripheral sub-region bb4 does not necessarily have to be exactly the same, and the difference in the number of virtual pixel circuits 121 in the third peripheral sub-region bb3 and the fourth peripheral sub-region bb4 can also be 1 to 10. In this way, the difference in the number of virtual pixel circuits 121 in the third peripheral sub-region bb3 and the fourth peripheral sub-region bb4 can be made relatively small. Consequently, the difference in the occupied areas of the virtual pixel circuits 121 in the third peripheral sub-region bb3 and the fourth peripheral sub-region bb4 can also be made relatively small.

[0093] In specific implementation, in the embodiments of the present invention, as Figure 4 shown, the third peripheral sub-region bb3 further includes: a plurality of second virtual gate lines (not shown in the figure) and a plurality of second virtual data lines (not shown in the figure); wherein, in the third peripheral sub-region bb3, one row of virtual pixel circuits 121 is electrically connected to one second virtual gate line, and one column of virtual pixel circuits 121 is electrically connected to one second virtual data line. In this way, a driving signal can be provided to the virtual pixel circuits 121 in the third peripheral sub-region bb3 through the second virtual gate lines, and a data display signal can be provided to the virtual pixel circuits 121 in the third peripheral sub-region bb3 through the second virtual data lines, so that the virtual pixel circuits 121 in the third peripheral sub-region bb3 can control the first light-emitting device 111 to emit light.

[0094] In specific implementation, in the embodiments of the present invention, as Figure 4 shown, the fourth peripheral sub-region bb4 further includes: a plurality of third virtual gate lines (not shown in the figure) and a plurality of third virtual data lines (not shown in the figure); wherein, in the fourth peripheral sub-region bb4, one row of virtual pixel circuits 121 is electrically connected to one third virtual gate line, and one column of virtual pixel circuits 121 is electrically connected to one third virtual data line. In this way, a driving signal can be provided to the virtual pixel circuits 121 in the fourth peripheral sub-region bb4 through the third virtual gate lines, and a data display signal can be provided to the virtual pixel circuits 121 in the fourth peripheral sub-region bb4 through the third virtual data lines, so that the virtual pixel circuits 121 in the fourth peripheral sub-region bb4 can control the first light-emitting device 111 to emit light.

[0095] In specific implementation, in the embodiments of the present invention, as Figure 4As shown, for the first light-emitting device 111 and the second light-emitting device 112 in the same column, the second virtual data line and the third virtual data line electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 are electrically connected to the driving data line 161 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112.

[0096] In a specific implementation, in the embodiments of the present invention, as Figure 4 shown, for the first light-emitting device 111 and the second light-emitting device 112 in the same row, the driving signals transmitted by the second virtual gate line and the third virtual gate line electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 and the driving gate line 131 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112 are the same. In this way, the first light-emitting device 111 and the second light-emitting device 112 in the same row can be lit simultaneously.

[0097] In a specific implementation, in the embodiments of the present invention, as Figure 4 shown, the peripheral area BB may further include: a gate driving circuit 150 electrically connected to a plurality of driving gate lines 131; wherein, the gate driving circuit 150 is configured to input driving signals to the plurality of driving gate lines 131, and for the first light-emitting device 111 and the second light-emitting device 112 in the same row, the second virtual gate line and the third virtual gate line electrically connected to the virtual pixel circuit 121 corresponding to the first light-emitting device 111 and the driving gate line 131 electrically connected to the driving pixel circuit 122 corresponding to the second light-emitting device 112 are the same one. In this way, the driving gate, the second virtual gate line, and the third virtual gate line can share the gate driving circuit 150.

[0098] Exemplarily, the display panel may adopt bilateral driving to reduce the delay of the driving signal. For example, a gate driving circuit 150 is provided in the third peripheral sub-area bb3 of the peripheral area BB. Another gate driving circuit 150 is provided in the fourth peripheral sub-area bb4 of the peripheral area BB. That is, two gate driving circuits 150 are provided. Of course, the display panel may also adopt unilateral driving. For example, a gate driving circuit 150 is provided in the third peripheral sub-area bb3 of the peripheral area BB. Or, a gate driving circuit 150 is provided in the fourth peripheral sub-area bb4 of the peripheral area BB.

[0099] Exemplarily, as Figure 4 shown, in the third peripheral sub-area bb3, the area where the virtual pixel circuit 121 is located and the area where the gate driving circuit 150 is located are arranged along the first direction F1. That is to say, the projections of the area where the virtual pixel circuit 121 is located and the area where the gate driving circuit 150 is located in the first direction F1 do not overlap. Further, the projection of the area where the virtual pixel circuit 121 is located in the third peripheral sub-area bb3 and the first display area aa1 in the first direction F1 overlaps.

[0100] Exemplarily, as Figure 4 shown, in the fourth peripheral sub-region bb4, the region where the virtual pixel circuit 121 is located and the region where the gate driving circuit 150 is located are arranged along the first direction F1. That is to say, the positive projections of the region where the virtual pixel circuit 121 is located and the region where the gate driving circuit 150 is located in the first direction F1 do not overlap either. Further, the positive projections of the region where the virtual pixel circuit 121 is located in the fourth peripheral sub-region bb4 and the first display region aa1 overlap in the first direction F1.

[0101] The embodiments of the present invention further provide some display panels, and the schematic structural diagram is as Figure 5 shown, which is a deformation of the implementation manner in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0102] In specific implementation, in the embodiments of the present invention, as Figure 5 shown, the peripheral region BB may further include: a gate driving circuit 150 electrically connected to a plurality of driving gate lines 131; wherein, the gate driving circuit 150 is configured to input driving signals to the plurality of driving gate lines 131. In this way, the gate driving circuit 150 can input driving signals to the driving gates.

[0103] Exemplarily, the display panel may adopt bilateral driving to reduce the delay of driving signals. For example, a gate driving circuit 150 is provided in the third peripheral sub-region bb3 of the peripheral region BB. Another gate driving circuit 150 is provided in the fourth peripheral sub-region bb4 of the peripheral region BB. That is, two gate driving circuits 150 are provided. Of course, the display panel may also adopt unilateral driving. For example, a gate driving circuit 150 is provided in the third peripheral sub-region bb3 of the peripheral region BB. Or, a gate driving circuit 150 is provided in the fourth peripheral sub-region bb4 of the peripheral region BB.

[0104] In specific implementation, in the embodiments of the present invention, as Figure 5 shown, the peripheral region BB may further include: a second virtual gate driving circuit 222 electrically connected to a plurality of second virtual gate lines 133 and a third virtual gate driving circuit 223 electrically connected to a plurality of third virtual gate lines 134; wherein, the second virtual gate driving circuit 222 is configured to input driving signals to the plurality of second virtual gate lines 133, and the third virtual gate driving circuit 223 is configured to input driving signals to the plurality of third virtual gate lines 134. In this way, the driving gates, the second virtual gate lines 133, and the third virtual gate lines 134 can be independently controlled respectively.

[0105] Exemplarily, as Figure 5As shown, in the third peripheral sub-region bb3, the region where the virtual pixel circuit 121 is located and the region where the gate driving circuit 150 is located are arranged along the first direction F1, and the region where the second virtual gate driving circuit 222 is located and the region where the gate driving circuit 150 is located are arranged along the first direction F1. That is to say, the orthographic projection of the region where the virtual pixel circuit 121 is located and the region where the gate driving circuit 150 is located in the first direction F1 do not overlap, and the orthographic projection of the region where the second virtual gate driving circuit 222 is located and the region where the gate driving circuit 150 is located in the first direction F1 do not overlap. Further, the orthographic projections of the region where the virtual pixel circuit 121 is located, the region where the second virtual gate driving circuit 222 is located, and the first display region aa1 in the third peripheral sub-region bb3 in the first direction F1 overlap. This can reduce the interference of the second virtual gate driving circuit 222 on the signal transmitted on the connection trace 210.

[0106] Exemplarily, as Figure 5 shown, in the fourth peripheral sub-region bb4, the region where the virtual pixel circuit 121 is located and the region where the gate driving circuit 150 is located are arranged along the first direction F1, and the region where the third virtual gate driving circuit 223 is located and the region where the gate driving circuit 150 is located are arranged along the first direction F1. That is to say, the orthographic projection of the region where the virtual pixel circuit 121 is located and the region where the gate driving circuit 150 is located in the first direction F1 do not overlap, and the orthographic projection of the region where the third virtual gate driving circuit 223 is located and the region where the gate driving circuit 150 is located in the first direction F1 do not overlap. Further, the orthographic projections of the region where the virtual pixel circuit 121 is located, the region where the third virtual gate driving circuit 223 is located, and the first display region aa1 in the fourth peripheral sub-region bb4 in the first direction F1 overlap. This can reduce the interference of the third virtual gate driving circuit 223 on the signal transmitted on the connection trace 210.

[0107] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above-mentioned display panel provided by the embodiment of the present invention. The principle of the display device to solve the problem is similar to that of the foregoing display panel. Therefore, the implementation of the display device can refer to the implementation of the foregoing display panel, and the repeated parts will not be elaborated here.

[0108] In specific implementation, in the embodiment of the present invention, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated here, nor should it be regarded as a limitation to the present invention.

[0109] The display panel and the display device provided by the embodiments of the present invention enable the driving pixel circuit in the second display area to drive the second light-emitting device in the second display area to emit light, so that the second display area can achieve a light-emitting display effect. Moreover, by multiplexing the virtual pixel circuit in the peripheral area to drive the first light-emitting device in the first display area to emit light, the first display area can achieve a light-emitting display effect, and further the entire display area can achieve a light-emitting display effect. Since the first light-emitting device is provided in the first display area without providing a pixel circuit and a metal trace, not only can the first display area achieve a display function, but also the first display area has no pixel circuit and metal trace, so that the light transmittance of the first display area is high. Thus, when the display panel is applied to a display device, components such as a front camera, a sensor, and a receiver can be provided below the first display area of the display panel to achieve a full-screen design and improve the screen-to-body ratio.

[0110] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A display panel, characterized in that, Comprising: A substrate, including a display area and a peripheral area surrounding the display area; wherein, the display area includes a first display area and a second display area, the peripheral area includes a first peripheral sub-area and a second peripheral sub-area arranged oppositely, and the first peripheral sub-area includes a plurality of first virtual areas; A plurality of pixel circuits, including a plurality of virtual pixel circuits and a plurality of driving pixel circuits; wherein, the plurality of virtual pixel circuits are located in the peripheral area, and the plurality of driving pixel circuits are located in the second display area; A plurality of light-emitting devices, located on a side of the plurality of pixel circuits away from the substrate; and the plurality of light-emitting device layers include a plurality of first light-emitting devices and a plurality of second light-emitting devices; wherein, the plurality of first light-emitting devices are located in the first display area, and the plurality of second light-emitting devices are located in the second display area; Wherein, at least one of the virtual pixel circuits is electrically connected to at least one of the first light-emitting devices, at least one of the driving pixel circuits is electrically connected to at least one of the second light-emitting devices, each of the first virtual areas includes a plurality of virtual pixel circuits arranged in an array, the plurality of first light-emitting devices are divided into a plurality of first row groups, each of the first row groups includes at least two adjacent rows of the first light-emitting devices, one of the first row groups corresponds to one of the first virtual areas, and one of the first light-emitting devices in the first row group is electrically connected to one of the virtual pixel circuits in the corresponding first virtual area through a connection trace.

2. The display panel according to claim 1, wherein The plurality of first light-emitting devices are arranged in an array in the first display area, and the plurality of second light-emitting devices are arranged in an array in the second display area; wherein, one row of the first light-emitting devices and one row of the second light-emitting devices are in the same row; and / or, one column of the first light-emitting devices and one column of the second light-emitting devices are in the same column.

3. The display panel according to claim 2, wherein The peripheral area further includes a third peripheral sub-area and a fourth peripheral sub-area arranged oppositely; The first peripheral sub-area, the first display area, and the second peripheral sub-area are arranged along a first direction, and the third peripheral sub-area, the first display area, and the fourth peripheral sub-area are arranged along a second direction; wherein, the first direction is different from the second direction; The plurality of virtual pixel circuits are located in at least one of the first peripheral sub-area, the second peripheral sub-area, the third peripheral sub-area, and the fourth peripheral sub-area.

4. The display panel according to claim 3, wherein The distance between the first peripheral sub-area and the first display area is less than the distance between the second peripheral sub-area and the first display area, and the plurality of virtual pixel circuits are arranged in the first peripheral sub-area.

5. The display panel according to claim 3, wherein The first row group includes a first sub-row group and a second sub-row group; wherein, the first display area has a first center line along the first direction, and the first light-emitting devices in the first sub-row group and the second sub-row group are symmetrically arranged along the first center line; The first virtual area includes a first sub-virtual area and a second sub-virtual area; wherein, the first sub-virtual area and the second sub-virtual area are symmetrically arranged along the first center line, and the first sub-row group and the first sub-virtual area are on the same side of the first center line; The first light-emitting device in the first sub-row group is electrically connected to the virtual pixel circuit in the first sub-virtual area through the connection trace; The first light-emitting device in the second sub-row group is electrically connected to the virtual pixel circuit in the second sub-virtual area through the connection trace.

6. The display panel according to claim 5, wherein In the same first row group, the connection traces corresponding to the first sub-row group and the second sub-row group are symmetrically arranged along the first center line.

7. The display panel according to claim 5, wherein The second display area further includes a plurality of driving gate lines and a plurality of driving data lines; wherein, one row of the driving pixel circuits is electrically connected to one of the driving gate lines, and one column of the driving pixel circuits is electrically connected to one of the driving data lines; The first sub-virtual area further includes: a plurality of first sub-virtual gate lines and a plurality of first sub-virtual data lines; wherein, in the first sub-virtual area, one row of the virtual pixel circuits is electrically connected to one of the first sub-virtual gate lines, and one column of the virtual pixel circuits is electrically connected to one of the first sub-virtual data lines; The second sub-virtual area further includes: a plurality of second sub-virtual gate lines and a plurality of second sub-virtual data lines; wherein, in the second sub-virtual area, one row of the virtual pixel circuits is electrically connected to one of the second sub-virtual gate lines, and one column of the virtual pixel circuits is electrically connected to one of the second sub-virtual data lines; For the first light-emitting device and the second light-emitting device in the same row, the driving signals transmitted by the first sub-virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, the second sub-virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, and the driving gate line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are the same; For the first light-emitting device and the second light-emitting device in the same column, the first sub-virtual data line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, the second sub-virtual data line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, and the driving data line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are electrically connected.

8. The display panel according to claim 7, wherein The peripheral area further includes: a gate driving circuit electrically connected to the plurality of driving gate lines; wherein, the gate driving circuit is configured to input a driving signal to the plurality of driving gate lines, and for the first light-emitting device and the second light-emitting device in the same row, the first sub-virtual gate line, the second sub-virtual gate line electrically connected to the virtual pixel circuit corresponding to the first light-emitting device, and the driving gate line electrically connected to the driving pixel circuit corresponding to the second light-emitting device are electrically connected; or, The peripheral area further includes: a gate driving circuit electrically connected to the plurality of driving gate lines, a first virtual gate driving circuit electrically connected to the plurality of first sub-virtual gate lines, and a second virtual gate driving circuit electrically connected to the plurality of second sub-virtual gate lines; wherein, the gate driving circuit is configured to input a driving signal to the plurality of driving gate lines, the first virtual gate driving circuit is configured to input a driving signal to the plurality of first sub-virtual gate lines, and the second virtual gate driving circuit is configured to input a driving signal to the plurality of second sub-virtual gate lines.

9. A display device, characterized in that, A display panel including the display panel according to any one of claims 1-8.

Images