An LZ77 decoding circuit and its working method

Abstract

An LZ77 decoding circuit, in the pair data flow direction, includes: an input / output control circuit, an input buffer, an input preprocessing circuit, an address mapping circuit, a RAM input / output control circuit, RAM, an output preprocessing circuit, and an output buffer. The RAM and the output buffer together constitute a lookup window. The RAM input / output control circuit searches for the data needed for the pair in the RAM of the lookup window. In the literal data flow direction, the LZ77 decoding circuit includes: an input buffer, an input preprocessing circuit, and an output buffer. Data in the output buffer updates the RAM. This invention effectively improves the LZ77 decoding speed through an improved lookup window structure and separate preprocessing of input and output data.

Description

Technical Field

[0001] This invention discloses an LZ77 decoding circuit and its working method, belonging to the technical field of data decoding. Background Technology

[0002] LZ77 is a dictionary-based algorithm that uses the encoded information as a dictionary. If a character to be encoded has appeared before, it is replaced with the character's position and length, thus achieving compression. Almost all commonly used compression tools, such as ARJ, PKZip, WinZip, LHArc, RAR, GZip, and many hardware-built-in compression algorithms, utilize the LZ77 algorithm.

[0003] Data compressed by LZ77 has two forms: literal and pair(length, distance). Literal is the uncompressed character, while pair is a two-dimensional tuple containing two pieces of information, length and distance, representing a string sequence of variable length. When decompressing data, literal does not require special processing, while pair needs to be recovered through a search window. Therefore, the processing speed of the pair determines the decoding speed of the entire circuit.

[0004] Chinese patent document CN109716659A describes a high-performance single-stream LZ77 compression technology. This technology involves a computing device that updates an index data structure based on the input data stream. The input data stream is divided into multiple blocks. Each block has a predetermined length, e.g., 136 bytes, and overlaps with previous blocks by a predetermined amount, e.g., 8 bytes. The computing device processes multiple blocks in parallel using the index data to generate multiple token streams. Tokens include text tokens and reference tokens, where the reference token refers to an earlier matching data in the input data stream. This document effectively improves the decoding efficiency of the LZ77 algorithm, a core component of existing Gzip decompression algorithms. However, this document does not provide the corresponding address mapping circuit functional module and output preprocessing circuit functional module. Therefore, it is difficult to intuitively control the processing speed of the circuit for pairs during data recovery. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention discloses an LZ77 decoding circuit.

[0006] The present invention also discloses the working method of the above-described decoding circuit.

[0007] This invention improves the decoding speed of LZ77 by improving the lookup window structure and preprocessing the input and output data separately.

[0008] The detailed technical solution of this invention is as follows:

[0009] An LZ77 decoding circuit is characterized in that the data to be decompressed is data that can be recovered to contain literals and pairs. Since LZ77 compression is usually used in conjunction with other compression algorithms for multi-level compression, the data to be decompressed must be recoverable to literals or pairs for LZ77 decoding to function effectively with the decoding circuit described herein. Figure 10 , 11 Taking GZIP decompression as an example, the data to be decompressed is first decompressed by the Huffman decoding circuit, and then LZ77 decompression is performed.

[0010] According to the pair data flow direction, the LZ77 decoding circuit includes:

[0011] The system includes an input / output control circuit, an input buffer, an input preprocessing circuit, an address mapping circuit, a RAM input / output control circuit, RAM, an output preprocessing circuit, and an output buffer. The RAM and the output buffer together constitute a lookup window. The RAM input / output control circuit searches for the data needed for the pair in the RAM of the lookup window.

[0012] According to the literal data stream direction, the LZ77 decoding circuit includes:

[0013] The system includes an input buffer, an input preprocessing circuit, and an output buffer. The literal data in the data to be decompressed represents the portion that has not been compressed by the LZ77. The literal data is directly placed into the output buffer through the input preprocessing circuit.

[0014] The data in the output buffer updates the RAM. All decompressed data and literal data directly placed in the output buffer are first stored in the output buffer. Simultaneously, the output buffer counts the data; when the data volume reaches a certain threshold, the corresponding data is written to the RAM of the lookup window via the RAM input / output control circuit for storage, thereby updating the RAM. Figure 1 As shown;

[0015] The input / output control circuit is used to control the input of the data to be decompressed and the output of the decompressed data.

[0016] The input buffer is used to buffer data input through the input / output control circuit. The input buffer needs to limit the lower limit of its size, but it is not a fixed value. Instead, it is related to max(literal_length, pair_length), which is the maximum value between the length of the literal bit and the length of the pair bit (distance + length). In other words, the input buffer should be able to hold at least the longest literal or pair bit.

[0017] The input preprocessing circuit is used to preprocess the data to be decompressed into literal data and / or pair data. In this technical field, in specific compression algorithms, literal and pair are distinguished by a certain "marker". Taking the application of LZ77 in the GZIP compression algorithm as an example, literal is represented by 0-255, while length (the first component of the pair) is represented by 257-285 plus extension bits. During decompression, literal and length can be distinguished by the range of data. Length and distance appear in pairs, and the data after length is distance.

[0018] The address mapping circuit is used to parse the pair data. If all or part of the required data for the pair data is located in RAM (when all the required data exists in the output buffer, length data is directly copied from the output buffer): the distance in the pair data is mapped to an address that RAM can recognize (ram_rd_st_addr). The number of times data needs to be read from RAM is calculated based on the length in the pair data (ram_rd_cnt). Based on the number of data in the output buffer (out_buf_cnt) and the address currently pointed to by RAM (ram_cur_addr), the location, number of reads, and length information of the data to be found are determined.

[0019] The output preprocessing circuit reads data from RAM based on the data's location, number of reads, and length information, and then trims and splices the data to finally form the decompressed data.

[0020] The output buffer is used to cache the decompressed data;

[0021] The RAM input / output control circuit is used to control the writing and reading of data in the RAM;

[0022] The lookup window includes RAM and an output cache, wherein the output cache updates the RAM.

[0023] According to a preferred embodiment of the present invention, the lookup window includes a dual-port RAM and an output buffer. In the minimum architecture of the lookup window, the size of the dual-port RAM is consistent with the size of the "dictionary" used when performing LZ77 compression. For example, in the GZIP algorithm, a 32KByte "dictionary" is used during LZ77 compression, and the RAM size should be consistent with the "dictionary" size. The size of the output buffer itself is greater than or equal to the data width corresponding to each address of the RAM. The data width corresponding to each address of the RAM is nByte. For example, if a 32KByte RAM uses a 4K*8Byte format, then n=8, and the size of the output buffer should be greater than or equal to 8Byte. During decompression, the output buffer counts the decompressed data. Whenever the count value is greater than or equal to 8Byte, this 8Byte of data is written to the RAM through the RAM input / output control module, and simultaneously output through the input / output control module. After this, this data is discarded by the output buffer through a shift operation, and the count value is decremented by 8 accordingly. This technical feature avoids the waste of clock resources caused by frequent RAM reads and writes, and can read multiple bytes of data in one clock cycle when decompressing pairs, making full use of RAM and output buffer circuits, thereby improving decoding speed.

[0024] The working method of the above-mentioned decoding circuit is characterized by including:

[0025] 1) The decoding circuit reads a piece of data to be decompressed and places it into the input buffer;

[0026] 2) Preprocess the data to be decompressed into literal data and / or pair data, and send the literal data into the output buffer and the pair data into the address mapping circuit;

[0027] 3) Map the distance in the pair data to an address that the lookup window can recognize (ram_rd_st_addr), calculate the number of times the data needs to be read from the lookup window based on the length in the pair data (ram_rd_cnt), and determine the location, number of reads, and length information of the data to be searched based on the number of data in the output buffer (out_buf_cnt) and the address currently pointed to by the RAM (ram_cur_addr).

[0028] 4) Read the data back from the search window according to the location, number of reads, and length information of the data to be searched;

[0029] 5) Perform output preprocessing on the read-back data: trim and splice the data to obtain the decompressed data;

[0030] 6) Repeat steps 1)-5) until all data to be decompressed is decompressed.

[0031] According to a preferred embodiment of the present invention, the working method further includes:

[0032] The literal data and the decompressed data are sent to the output buffer, the data is counted, and when the data volume reaches a preset threshold, the output buffer writes the corresponding data into RAM for storage, and at the same time updates the RAM;

[0033] During decompression, the position of a single matched string can fall into one of the following three categories:

[0034] It exists only in RAM;

[0035] Or it may only exist in the output buffer;

[0036] It may exist in both RAM and output buffer simultaneously.

[0037] According to a preferred embodiment of the present invention, the literal data and the decompressed data are sent to the output buffer, and when all the data to be decompressed is processed at one time, the data in the output buffer is output.

[0038] According to a preferred embodiment of the present invention, updating the RAM is a rolling update, comprising:

[0039] When writing data from the output buffer to RAM, each data item is written sequentially, either from low address to high address or from high address to low address. Taking a 4K*8Byte RAM as an example, when writing from high address to low address, a 12-bit `ram_cur_addr` represents the address where the next data item will be written. At the start of decompression, `ram_cur_addr` should point to the highest address 4095. After each 8-byte data item is written, the address is decremented by 1. When `ram_cur_addr` reaches 0, due to the binary counting characteristics, `ram_cur_addr` is decremented back to 4095, thus achieving a rolling update of the RAM. Similarly, writing can start from the low address 0, but after each data write, `ram_cur_addr` should be incremented by 1, also achieving the effect of a rolling update of the RAM.

[0040] According to a preferred embodiment of the present invention, step 5) output preprocessing includes:

[0041] Trim the data, removing redundant data;

[0042] The data is concatenated, and the cropped data is reassembled with the subsequent data into an aligned format.

[0043] Because the strings represented by pair data are of variable length—for example, in the GZIP algorithm, the length ranges from 3 to 258 bytes—and each time the data is read back from the lookup window through RAM, it is the entire data at that address, so redundant data needs to be trimmed. Figure 9 If the matched data for a pair consists of only 4 bytes (c, d, e, f), but a read operation on RAM reads all bytes (a, b, c, d, e, f, g, h) from that address, then the data excluding the valid c, d, e, and f needs to be truncated. The truncated data is then appended to the high-order bits of the output buffer. Since the output buffer already contains 3 bytes (x, y, z), the appended output buffer will contain x, y, z, c, d, e, and f. This allows for RAM updates and data output, completing the decompression operation for a single pair of data.

[0044] According to a preferred embodiment of the present invention, the mapping rule of the address mapping circuit in step 2) includes:

[0045] 1) The address mapping circuit determines the magnitude of the distance in the pair data:

[0046] 1-1) If distance is less than or equal to out_buf_cnt, then copy length data directly from the output buffer;

[0047] 1-2) If distance is greater than out_buf_cnt, copy data from RAM and check the length:

[0048] 1-2-1) If length <= distance – out_buf_cnt, then the data to be searched exists only in RAM, and the starting address (ram_rd_st_addr) = ram_cur_addr - [(distance – out_buf_cnt) / number of bytes corresponding to each address in RAM] 向上取整， Read count (rd_cnt):

[0049] If length <= [(distance - out_buf_cnt) / number of bytes per RAM address] 取余， Perform only one RAM read operation, rd_cnt = 1;

[0050] If length > [(distance - out_buf_cnt) / number of bytes per RAM address] 取余,rd_cnt = [[length - [(distance - out_buf_cnt) / number of bytes per RAM address]] 取余 [Number of bytes per RAM address] 向上取整；

[0051] The reading process is as follows: starting from the starting address, the RAM is read. After each read, ram_rd_st_addr is decremented by 1, and then the new ram_rd_st_addr is read again, until rd_cnt reads are completed. The data read in the first and last read operations of the RAM may be redundant.

[0052] 1-2-2) If length > distance - out_buf_cnt, then search for distance - out_buf_cnt data in RAM, and obtain the remaining length - distance - out_buf_cnt data from the output buffer.

[0053] The above are the address mapping rules. In addition, the data read from RAM needs to be trimmed and spliced ​​by the output preprocessing circuit before it can finally enter the output buffer.

[0054] The technical advantages of this invention are:

[0055] 1. This invention can be widely applied to the LZ77 decoding part in various decompression algorithms. This invention only requires designing the corresponding input preprocessing circuit according to the "marking" form of literals and pairs in different algorithms. At the same time, different sizes of RAM are selected according to the size of the "dictionary" used during compression. Other circuit parts can be universal, which is convenient for porting and increases the reusability of the circuit.

[0056] 2. The composition and update method of the lookup window described in this invention: The lookup window is composed of RAM and output buffer. Only when the data in the output buffer reaches a certain threshold is a write operation performed on the RAM. This operation method avoids the waste of clock resources caused by frequent reading and writing of RAM. Moreover, when decompressing pair data, multiple bytes of data can be read in one clock cycle, making full use of RAM and output buffer circuits and improving decoding speed.

[0057] 3. This invention proposes a mapping rule for the address mapping circuit that matches the lookup window structure and an output preprocessing circuit, which can quickly obtain the decompressed data. Attached Figure Description

[0058] Figure 1 This is the LZ77 decoding circuit structure described in this invention;

[0059] Figure 2 This invention relates to a data decompression flowchart;

[0060] Figure 3 This is the input preprocessing circuit of the present invention;

[0061] Figure 4 This is a schematic diagram of a single RAM write operation according to the present invention;

[0062] Figure 5 This is a schematic diagram of RAM rolling update according to the present invention;

[0063] Figure 6 This is a schematic diagram of the search window described in this invention;

[0064] Figure 7-1 This is a schematic diagram of the pair matching data of the present invention existing only in RAM;

[0065] Figure 7-2 This is a schematic diagram illustrating the case where the data matched by the pair in this invention only exists in the output buffer;

[0066] Figure 7-3 This is a schematic diagram of the pair matching data of the present invention existing simultaneously in RAM and output buffer;

[0067] Figure 8 This is a schematic diagram of the address mapping circuit of the present invention;

[0068] Figure 9 This is a schematic diagram illustrating the cropping and splicing of read-back data according to the present invention;

[0069] Figure 10 This is a schematic diagram illustrating the application scenario of the LZ77 decoding circuit in the GZIP decoding of this invention;

[0070] Figure 11 This is a flowchart illustrating the application scenario of the LZ77 decoding circuit in the GZIP decoding of this invention. Detailed Implementation

[0071] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0072] Example 1

[0073] like Figure 1 , 2 As shown in Figure 3,

[0074] An LZ77 decoding circuit, wherein the data to be decompressed is data that can be recovered to contain literals and pairs;

[0075] According to the pair data flow direction, the LZ77 decoding circuit includes:

[0076] The system includes an input / output control circuit, an input buffer, an input preprocessing circuit, an address mapping circuit, a RAM input / output control circuit, RAM, an output preprocessing circuit, and an output buffer. The RAM and the output buffer together constitute a lookup window. The RAM input / output control circuit searches for the data needed for the pair in the RAM of the lookup window.

[0077] According to the literal data stream direction, the LZ77 decoding circuit includes:

[0078] The system includes an input buffer, an input preprocessing circuit, and an output buffer; the data in the output buffer updates the RAM.

[0079] The input / output control circuit is used to control the input of the data to be decompressed and the output of the decompressed data.

[0080] The input buffer is used to buffer data input through the input / output control circuit;

[0081] The input preprocessing circuit is used to preprocess the data to be decompressed into literal data and / or pair data;

[0082] The address mapping circuit is used to parse the pair data, map the distance in the pair data to an address that RAM can recognize (ram_rd_st_addr), calculate the number of times data needs to be read from RAM based on the length in the pair data (ram_rd_cnt), and determine the location, number of reads, and length information of the data to be searched based on the number of data in the output buffer (out_buf_cnt) and the address currently pointed to by RAM (ram_cur_addr).

[0083] The output preprocessing circuit reads data from RAM based on the data's location, number of reads, and length information, and then trims and splices the data to finally form the decompressed data.

[0084] The output buffer is used to cache the decompressed data;

[0085] The RAM input / output control circuit is used to control the writing and reading of data in the RAM;

[0086] The lookup window includes: RAM and an output cache, wherein the output cache updates the RAM, such as... Figure 6 As shown.

[0087] Example 2

[0088] like Figure 5As shown in Example 1, an LZ77 decoding circuit includes a lookup window comprising a dual-port RAM and an output buffer. In the minimum architecture of the lookup window, the size of the dual-port RAM is consistent with the size of the "dictionary" used for LZ77 compression. For example, in the GZIP algorithm, a 32KByte "dictionary" is used for LZ77 compression, and the RAM size should match the "dictionary" size. The size of the output buffer itself is greater than or equal to the data width corresponding to each address of the RAM. The data width corresponding to each address of the RAM is nByte. For example, a 32KByte RAM uses a 4K*8Byte format, where n=8. Therefore, the size of the output buffer should be greater than or equal to 8Byte. During decompression, the output buffer counts the decompressed data. Whenever the count value is greater than or equal to 8Byte, this 8Byte of data is written to the RAM through the lookup window input / output control module, and simultaneously output through the input / output control module. After this, the data is discarded by the output buffer through a shift operation, and the count value is decremented by 8. This technical feature avoids the waste of clock resources caused by frequent RAM reads and writes, and can read multiple bytes of data in one clock cycle when decompressing pairs, making full use of RAM and output buffer circuits, thereby improving decoding speed.

[0089] Example 3

[0090] The working method of the decoding circuit as described in Examples 1 and 2 includes:

[0091] 1) The decoding circuit reads a piece of data to be decompressed and places it into the input buffer;

[0092] 2) Preprocess the data to be decompressed into literal data and / or pair data, and send the literal data into the output buffer and the pair data into the address mapping circuit;

[0093] 3) Map the distance in the pair data to an address recognizable by the lookup window (ram_rd_st_addr). Calculate the number of times data needs to be read from the lookup window based on the length in the pair data (ram_rd_cnt). Determine the location, number of reads, and length information of the data to be searched based on the number of data items in the output buffer (out_buf_cnt) and the current address pointed to by the RAM (ram_cur_addr). Figure 8 As shown;

[0094] 4) Read the data back from the search window according to the location, number of reads, and length information of the data to be searched;

[0095] 5) Perform output preprocessing on the read-back data: trim and splice the data to obtain the decompressed data;

[0096] 6) Repeat steps 1)-5) until all data to be decompressed is decompressed.

[0097] Example 4

[0098] The working method of the decoding circuit as described in Example 3 further includes:

[0099] The literal data and the decompressed data are sent to the output buffer, the data is counted, and when the data volume reaches a preset threshold, the output buffer writes the corresponding data into RAM for storage, and at the same time updates the RAM;

[0100] During decompression, the position of a single matched string can fall into one of the following three categories:

[0101] It exists only in RAM;

[0102] Or it may only exist in the output buffer;

[0103] It may exist simultaneously in RAM and the output buffer. For example... Figure 7-1 , 7-2 As shown in Figure 7-3.

[0104] The literal data and the decompressed data are sent to the output buffer. When all the data to be decompressed is processed, the data in the output buffer is output.

[0105] Updating RAM is a rolling update, such as... Figure 4 , 5 As shown, it includes:

[0106] When writing data from the output buffer to RAM, each data item is written sequentially, either from low address to high address or from high address to low address. Taking a 4K*8Byte RAM as an example, when writing from high address to low address, a 12-bit `ram_cur_addr` represents the address where the next data item will be written. At the start of decompression, `ram_cur_addr` should point to the highest address 4095. After each 8-byte data item is written, the address is decremented by 1. When `ram_cur_addr` reaches 0, due to the binary counting characteristics, `ram_cur_addr` is decremented back to 4095, thus achieving a rolling update of the RAM. Similarly, writing can start from the low address 0, but after each data write, `ram_cur_addr` should be incremented by 1, also achieving the effect of a rolling update of the RAM.

[0107] Step 5) output preprocessing includes:

[0108] Trim the data, removing redundant data;

[0109] The data is concatenated, and the cropped data is reassembled with the subsequent data into an aligned format.

[0110] Because the strings represented by pair data are of variable length—for example, in the GZIP algorithm, the length ranges from 3 to 258 bytes—and the data read back from the lookup window through RAM each time is the entire data at that address, redundant data needs to be trimmed. Figure 9 If the matched data for a pair consists of only 4 bytes (c, d, e, f), but a read operation on RAM reads all bytes (a, b, c, d, e, f, g, h) from that address, then the data excluding the valid c, d, e, and f needs to be truncated. The truncated data is then appended to the high-order bits of the output buffer. Since the output buffer already contains 3 bytes (x, y, z), the appended output buffer will contain x, y, z, c, d, e, and f. This allows for RAM updates and data output, completing the decompression operation for a single pair of data.

[0111] Example 5

[0112] The mapping rules of the address mapping circuit in step 2) according to Embodiment 3 include:

[0113] 1) The address mapping circuit determines the magnitude of the distance in the pair data:

[0114] 1-1) If distance is less than or equal to out_buf_cnt, then copy length data directly from the output buffer;

[0115] 1-2) If distance is greater than out_buf_cnt, copy data from RAM and check the length:

[0116] 1-2-1) If length <= distance – out_buf_cnt, then the data to be searched exists only in RAM, and the starting address (ram_rd_st_addr) = ram_cur_addr - [(distance – out_buf_cnt) / number of bytes corresponding to each address in RAM] 向上取整， Read count (rd_cnt):

[0117] If length <= [(distance - out_buf_cnt) / number of bytes per RAM address] 取余， Perform only one RAM read operation, rd_cnt = 1;

[0118] If length > [(distance - out_buf_cnt) / number of bytes per RAM address] 取余, rd_cnt = [[length - [(distance - out_buf_cnt) / number of bytes per RAM address]] 取余 [Number of bytes per RAM address] 向上取整；

[0119] The reading process is as follows: starting from the starting address, the RAM is read. After each read, ram_rd_st_addr is decremented by 1, and then the new ram_rd_st_addr is read again, until rd_cnt reads are completed. The data read in the first and last read operations of the RAM may be redundant.

[0120] 1-2-2) If length > distance - out_buf_cnt, then search for distance - out_buf_cnt data in RAM, and obtain the remaining length - distance - out_buf_cnt data from the output buffer.

[0121] The above are the address mapping rules. In addition, the data read from RAM needs to be trimmed and spliced ​​by the output preprocessing circuit before it can finally enter the output buffer.

[0122] The address mapping circuit and mapping rules proposed in this invention enable the length and distance in the original pair data to be adapted to the lookup window structure described in this invention. At the same time, the output preprocessing circuit trims and splices the redundant information brought by this lookup window structure, thereby quickly obtaining the string matched by the pair.

[0123] If the RAM data width is 1 byte, then processing a pair of data of length `length` requires at least `length` clock cycles. Even with a pipelined circuit, each read operation consumes at least one clock cycle, limiting the decoding speed to less than 1 byte / cycle. This invention appropriately increases the data width corresponding to each address in the RAM to improve the decoding speed limit, and proposes a corresponding RAM update method to further improve decoding speed. For example, if the RAM size is 32KByte (4K*8Byte), since the data width of each address is 8 bytes, if the RAM is updated every time one byte is decompressed, a read operation must be performed before writing to that address. For example, if eight literals are continuously decompressed, such as the sequence "abcdefgh", the RAM update process would proceed in the following order: write a → read a → write a → read a → write a → read a → write abc → read abc → write abc → read abc → write abcd → read abcd → write abcde… → read abcdefg → write abcdefgh. Completing this operation requires 15 clock cycles, which is time-consuming.

[0124] The "dual-port RAM + output buffer" structure proposed in this invention, if the decompressed data is first placed into the output buffer and counted (out_buf_cnt), and the output buffer size is 8 bytes, then the RAM update operation is performed only when the data buffer has reached 8 bytes. See [link to documentation]. Figure 5 The output buffer state changes in the following order: a→ab→abc→abcd→abcde→abcdef→abcdefg→abcdefgh→write to abcdefgh. Figure 4 It only takes 9 clock cycles, which greatly improves decoding efficiency.

[0125] Simultaneously, the decompressed data is output, and the output buffer is cleared. From the above explanation, we can see that the lookup window contains two parts: one part is the data already written to RAM, and the other part is the data not yet written to RAM. The data in the output buffer is the data not yet written to RAM, due to the set threshold.

Claims

1. An LZ77 decoding circuit, characterized in that, The data to be decompressed is data that can be recovered to contain literals and pairs; According to the pair data flow direction, the LZ77 decoding circuit includes: The system includes an input / output control circuit, an input buffer, an input preprocessing circuit, an address mapping circuit, a RAM input / output control circuit, RAM, an output preprocessing circuit, and an output buffer. The RAM and the output buffer together constitute a lookup window. The RAM input / output control circuit searches for the data needed for the pair in the RAM of the lookup window. According to the literal data stream direction, the LZ77 decoding circuit includes: Input buffer, input preprocessing circuitry, and output buffer; The data in the output buffer is used to update the RAM; The input / output control circuit is used to control the input of the data to be decompressed and the output of the decompressed data. The input buffer is used to buffer data input through the input / output control circuit; The input preprocessing circuit is used to preprocess the data to be decompressed into literal data and / or pair data; The address mapping circuit is used to parse the pair data: mapping the distance in the pair data to a RAM-recognizable address ram_rd_st_addr, calculating the number of times the data needs to be read from RAM ram_rd_cnt based on the length in the pair data, and determining the location, number of reads, and length information of the data to be searched based on the number of data in the output buffer out_buf_cnt and the address currently pointed to by RAM ram_cur_addr. The output preprocessing circuit reads data from RAM based on the data's location, number of reads, and length information, and then trims and splices the data read from RAM to finally form the decompressed data. The output buffer is used to buffer the decompressed data. Specifically, it counts the decompressed data. When the count value is greater than or equal to the data width nByte corresponding to each address in RAM, the nByte data is written into RAM through the lookup window input / output control module. At the same time, this data is output through the input / output control module. After that, this data will be discarded by the output buffer in a shifted manner, and the count value will be decremented by n accordingly. The RAM input / output control circuit is used to control the writing and reading of data in the RAM; The lookup window includes RAM and an output cache. The output cache performs rolling updates on the RAM. The rolling update means that when writing data from the output cache to RAM, each piece of data is written sequentially in the direction of either low address to high address or high address to low address.

2. The LZ77 decoding circuit according to claim 1, characterized in that, The lookup window includes a dual-port RAM and an output buffer; in the minimum architecture of the lookup window, the size of the dual-port RAM is the same as the size of the "dictionary" when using LZ77 compression; the size of the output buffer itself is greater than or equal to the data width corresponding to each address of the RAM.

3. The operating method of the decoding circuit as described in claim 1 or 2, characterized in that, include: 1) The decoding circuit reads a piece of data to be decompressed and places it into the input buffer; 2) Preprocess the data to be decompressed into literal data and / or pair data, and send the literal data into the output buffer and the pair data into the address mapping circuit; 3) Map the distance in the pair data to an address that the lookup window can recognize, ram_rd_st_addr. Calculate the number of times the data needs to be read from the lookup window, ram_rd_cnt, based on the length in the pair data. Determine the location, number of reads, and length information of the data to be searched based on the number of data in the output buffer, out_buf_cnt, and the address currently pointed to by RAM, ram_cur_addr. 4) Read the data back from the search window according to the location, number of reads, and length information of the data to be searched; 5) Perform output preprocessing on the read-back data: trim and splice the data to obtain the decompressed data; 6) Repeat steps 1)-5) until all data to be decompressed is decompressed.

4. The operating method of the decoding circuit as described in claim 3, characterized in that, The working method also includes: The literal data and the decompressed data are sent to the output buffer, the data is counted, and when the data volume reaches a preset threshold, the output buffer writes the corresponding data into RAM for storage, and at the same time updates the RAM; During decompression, the position of a single matched string can fall into one of the following three categories: It exists only in RAM; Or it may only exist in the output buffer; It may exist in both RAM and output buffer simultaneously.

5. The operating method of the decoding circuit as described in claim 3, characterized in that, The literal data and the decompressed data are sent to the output buffer. When all the data to be decompressed is processed, the data in the output buffer is output.

6. The operating method of the decoding circuit as described in claim 4 or 5, characterized in that, Updating RAM is a rolling update, which includes: When writing data from the output buffer to RAM, each piece of data is written sequentially, either from low address to high address or from high address to low address.

7. The operating method of the decoding circuit as described in claim 3, characterized in that, Step 5) output preprocessing includes: Trim the data, removing redundant data; The data is concatenated, and the cropped data is reassembled with the subsequent data into an aligned format.

8. The operating method of the decoding circuit as described in claim 3, characterized in that, The mapping rules for the address mapping circuit in step 2) include: 1) The address mapping circuit determines the magnitude of the distance in the pair data: 1-1) If distance is less than or equal to out_buf_cnt, then copy length data directly from the output buffer; 1-2) If distance is greater than out_buf_cnt, copy data from RAM and check the length: 1-2-1) If length <= distance – out_buf_cnt, then the data to be searched only exists in RAM. Starting address ram_rd_st_addr = ram_cur_addr - [(distance - out_buf_cnt) / number of bytes per RAM address] 向上取整， Read count rd_cnt: If length <= [(distance - out_buf_cnt) / number of bytes per RAM address] 取余， Perform only one RAM read operation, rd_cnt=1; If length > [(distance - out_buf_cnt) / number of bytes per RAM address] 取余 rd_cnt = [[length - [(distance-out_buf_cnt) / number of bytes per RAM address]] 取余 [Number of bytes per RAM address] 向上取整 ; The reading process is as follows: starting from the starting address, the RAM is read. Each time it is read, ram_rd_st_addr is decremented by 1, and then the new ram_rd_st_addr is read again, until rd_cnt times are read. 1-2-2) If length > distance – out_buf_cnt, then search for distance – out_buf_cnt data in RAM, and obtain the remaining length - distance - out_buf_cnt data from the output buffer.

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