Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a preparation method thereof and a display device, which can solve the carrier crosstalk problem between different sub-pixels in the display substrate, effectively improve the gray scale definition of the display substrate, and improve the display effect. The display substrate comprises a substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel comprising at least one light emitting device, each light emitting device comprising a first electrode layer, a light emitting layer, an organic functional layer and a second electrode layer arranged in a containing portion of a pixel defining layer; an interlayer insulating layer is arranged between the pixel defining layer and the substrate. The display substrate further comprises a first inner recess portion penetrating through part of the thickness of the pixel defining layer and the interlayer insulating layer; and the organic functional layer forms a first opening at the position corresponding to the first inner recess portion.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic Light Emitting Diode (OLED) display panels possess numerous advantages, including self-emissiveness, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, wide viewing angle, wide operating temperature range, and the ability to display large areas of full color. They are widely recognized in the industry as the display panel with the greatest development potential. OLED display panels are self-emissive display panels. Their light-emitting devices typically include pixel electrodes used as anodes, a common electrode used as cathodes, and an organic functional layer disposed between the pixel electrodes and the common electrode. When current flows through them, these organic functional layers emit light.

[0003] However, the applicant discovered in practice that current OLED devices generally suffer from crosstalk between different sub-pixels. That is, charge carriers can enter adjacent sub-pixels through the electron transport layer or hole transport layer in the organic functional layer, causing adjacent sub-pixels to emit light, resulting in a reduction in the grayscale clarity of the display device and affecting the display effect of the device. Summary of the Invention

[0004] The purpose of this disclosure is to adopt the following technical solution.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate including a substrate, comprising a plurality of sub-pixels disposed on the substrate, each sub-pixel including at least a light-emitting device; the light-emitting device includes a first electrode layer, a second electrode layer disposed on the substrate, and a light-emitting layer and an organic functional layer located between the first electrode layer and the second electrode layer; the organic functional layer of each light-emitting device is an integrally formed structure; the display substrate further includes: an interlayer insulating layer located on the side of the first electrode layer near the substrate, and a pixel defining layer located on the side of the first electrode layer near the light-emitting layer; the pixel defining layer has a plurality of receiving portions formed therein, and the orthographic projection of one of the first electrode layers on the substrate at least partially overlaps with the orthographic projection of one of the receiving portions on the substrate;

[0006] A first recess is formed between any two adjacent sub-pixels, extending through a portion of the thickness of the pixel defining layer and the interlayer insulating layer; the organic functional layer forms a first opening at a position corresponding to the first recess.

[0007] Wherein, the length of the first opening between any two adjacent sub-pixels is not less than a first length, where the first length is the maximum width of the adjacent sub-pixels in the extension direction of the first opening.

[0008] Wherein, the lengths of each of the first openings are equal, and the length of the first opening is not less than the second length, the second length being the largest of the widths of each of the sub-pixels in the extension direction of the first opening.

[0009] Among them, a plurality of second recesses are formed between any adjacent sub-pixels, penetrating the thickness of the pixel defining layer and the interlayer insulating layer;

[0010] The orthographic projection of the second recess on the substrate corresponds to the apex corner of the orthographic projection of the receiving portion of the pixel defining layer on the substrate; the organic functional layer forms a second opening at the corresponding position of the second recess.

[0011] The second electrode layer of each of the light-emitting devices is an integrally formed structure, and a second opening is formed at the corresponding position of the second electrode layer and the organic functional layer in the second recess.

[0012] There are multiple first recesses between adjacent sub-pixels, and each first recess extends in the same direction.

[0013] The organic functional layer includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0014] The second electrode layer of each of the light-emitting devices is an integrally formed structure, and a first opening is formed at the corresponding position of the second electrode layer and the organic functional layer in the first recess.

[0015] The display panel further includes a limiting portion located on both sides of the first recess and disposed in the same layer as the first electrode layer, wherein the material of the limiting portion is the same as the material of the first electrode layer.

[0016] Each sub-pixel further includes a pixel driving circuit, the pixel driving circuit including a thin-film transistor, and the display substrate further includes a buffer layer located between the active layer of the thin-film transistor and the substrate; a gate insulating layer located between the gate layer and the active layer of the thin-film transistor; a first insulating layer located between the gate layer and the source and drain layers of the thin-film transistor; a planarization layer located between the source and drain layers of the thin-film transistor and the first electrode layer; the drain of the thin-film transistor is electrically connected to the first electrode layer through a via penetrating the planarization layer.

[0017] The interlayer insulating layer includes the buffer layer, the gate insulating layer, the first insulating layer, and the planarization layer; the first recess penetrates at least one of the buffer layer, the first insulating layer, and the planarization layer.

[0018] The first concave portion penetrates a portion of the thickness of the planarization layer.

[0019] The depth range of the first concave portion is:

[0020] Secondly, embodiments of this disclosure also provide a method for fabricating a display substrate, including forming a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including at least a light-emitting device; the process of forming the light-emitting device includes sequentially forming a first electrode layer, a second electrode layer, and a light-emitting layer and an organic functional layer located between the first electrode layer and the second electrode layer on the substrate; the organic functional layer of each light-emitting device is an integrally formed structure; the method further includes: forming an interlayer insulating layer on the side of the first electrode layer near the substrate; forming a pixel defining layer on the side of the first electrode layer near the light-emitting layer; a plurality of receiving portions are formed in the pixel defining layer, and the orthographic projection of one of the first electrode layers on the substrate at least partially overlaps with the orthographic projection of one of the receiving portions on the substrate;

[0021] A first recess is formed between any adjacent sub-pixels, penetrating a portion of the thickness of the pixel defining layer and the interlayer insulating layer; the organic functional layer forms a first opening at a corresponding position of the first recess.

[0022] The method further includes: forming two first recesses with the same extending direction between any adjacent sub-pixels and penetrating a portion of the thickness of the pixel defining layer and the interlayer insulating layer; the organic functional layer forming the first opening at a corresponding position of the first recesses.

[0023] The method further includes: forming a plurality of second recesses that penetrate the thickness of the pixel defining layer and the interlayer insulating layer between any adjacent sub-pixels;

[0024] The orthographic projection of the second recess on the substrate corresponds to the apex corner of the orthographic projection of the receiving portion of the pixel defining layer on the substrate; the organic functional layer forms a second opening at the corresponding position of the second recess.

[0025] Thirdly, embodiments of this disclosure provide a display device having any of the display substrates described above. Attached Figure Description

[0026] Figure 1 This is a plan view of a display substrate according to an embodiment of the present disclosure;

[0027] Figure 2 This is a schematic diagram of the circuit structure of a display substrate according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic diagram of the structure of a display substrate in the prior art;

[0029] Figure 4 This is a structural example diagram of a display substrate according to an embodiment of the present disclosure;

[0030] Figure 5 This is a plan view of a first opening in an embodiment of the present disclosure.

[0031] Figure 6 This is a plan view of another first opening in an embodiment of this disclosure;

[0032] Figure 7 This is a plan view of yet another first opening in an embodiment of this disclosure;

[0033] Figure 8 This is a plan view of a first opening and a second opening in an embodiment of this disclosure;

[0034] Figure 9 This is a flowchart illustrating a method for fabricating a display substrate according to an embodiment of the present disclosure;

[0035] Figure 10 This is a flowchart illustrating another method for preparing a display substrate according to an embodiment of the present disclosure;

[0036] Figure 11 This is a flowchart illustrating another method for preparing a display substrate according to an embodiment of the present disclosure. Detailed Implementation

[0037] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] The following description, in conjunction with the accompanying drawings, details the display panel and its manufacturing method, as well as the specific implementation methods of the display panel provided in this disclosure.

[0040] Figure 1 This is a planar schematic diagram of a display substrate according to an embodiment of the present disclosure; as shown... Figure 1 As shown, the display substrate includes a substrate 1 and a plurality of sub-pixels formed on the substrate 1. The sub-pixels are divided into four types: red sub-pixel R, blue sub-pixel B, first green sub-pixel G1, and second green sub-pixel G2, and their arrangement is as follows: Figure 1 As shown, each sub-pixel contains a pixel driving circuit and a light-emitting device. The pixel driving circuit may include a 7T1C (i.e., seven transistors and one capacitor) structure, such as including a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first reset transistor, a second reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor. Figure 2 This is a schematic diagram of the circuit structure of a display substrate according to an embodiment of the present disclosure; see reference. Figure 2The source 304 of the data writing transistor T4 is electrically connected to the source 304 of the driving transistor T3. The drain 302 of the data writing transistor T4 is configured to be electrically connected to the data line Vd to receive the data signal. The gate 304 of the data writing transistor T4 is configured to be electrically connected to the first scan signal line Ga1 to receive the scan signal. The first plate CC1 of the storage capacitor Cst is electrically connected to the first power supply voltage terminal VDD. The second plate CC2 of the storage capacitor Cst is electrically connected to the gate 304 of the driving transistor T3. The source 304 of the threshold compensation transistor T2 is electrically connected to the drain 304 of the driving transistor T3. The drain 302 of the threshold compensation transistor T2 is electrically connected to the gate 304 of the driving transistor T3. The gate 304 of the threshold compensation transistor T2 is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal. The source 304 of the first reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal. The drain 302 of the first reset transistor T1 is electrically connected to the gate 304 of the driving transistor T3. The gate 304 of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Rst1. The first reset transistor T7 receives a first sub-reset control signal; the source 304 of the second reset transistor T7 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the drain 302 of the second reset transistor T7 is electrically connected to the first electrode layer 5 of the light-emitting device, and the gate 304 of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second sub-reset control signal; the source 304 of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage terminal VDD, and the drain 302 of the first light-emitting control transistor T5 is connected to the source of the driving transistor T3. The gate 304 of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the source 304 of the second light-emitting control transistor T6 is electrically connected to the drain 302 of the driving transistor T3, the drain 302 of the second light-emitting control transistor T6 is electrically connected to the first electrode layer 5 of the light-emitting device, and the gate 304 of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal; the second electrode layer 7 of the light-emitting device is electrically connected to the second power supply voltage terminal VSS.

[0041] Figure 3 This is a schematic diagram of the structure of a display substrate in the prior art; such as Figure 3As shown, the display substrate includes a substrate 1 and multiple light-emitting devices formed on the substrate 1. Each light-emitting device includes a first electrode layer 5, a second electrode layer 7 disposed on the substrate 1, and a light-emitting layer 6 and an organic functional layer 8 located between the first electrode layer 5 and the second electrode layer 7. The organic functional layer 8 includes a hole transport layer 801 between the light-emitting layer 6 and the first electrode layer 5 and an electron transport layer 802 between the light-emitting layer 6 and the second electrode layer 7. The organic functional layer 8 of each light-emitting device is a monolithic structure. Therefore, this display substrate generally suffers from crosstalk problems between different sub-pixels. That is, charge carriers can enter adjacent sub-pixels through the current transport layer or the hole transport layer 801 in the organic functional layer 8, causing adjacent sub-pixels to emit light, resulting in a reduction in the grayscale clarity of the display substrate and greatly affecting the display effect.

[0042] In a first aspect, embodiments of this disclosure provide a display substrate, Figure 4 This is a structural example diagram of a display substrate according to an embodiment of this disclosure; as shown below. Figure 4 As shown, the display substrate includes a substrate 1 and a plurality of sub-pixels disposed on the substrate 1. Each sub-pixel includes at least one light-emitting device. The light-emitting device includes a first electrode layer 5 and a second electrode layer 7 disposed on the substrate 1, and a light-emitting layer 6 and an organic functional layer 8 located between the first electrode layer 5 and the second electrode layer 7. The organic functional layer 8 of each light-emitting device is an integrally formed structure. The display substrate also includes an interlayer insulating layer 2 located on the side of the first electrode layer 5 near the substrate 1, and a pixel defining layer 4 located on the side of the first electrode layer 5 near the light-emitting layer 6. A plurality of spacers 9 are disposed on the side of the pixel defining layer away from the substrate. A plurality of receiving portions are formed in the pixel defining layer 4, and the orthographic projection of a first electrode layer 5 on the substrate 1 at least partially overlaps with the orthographic projection of a receiving portion on the substrate 1. A first recess 11 is formed between any adjacent sub-pixels, penetrating a portion of the thickness of the pixel defining layer 4 and the interlayer insulating layer 2. The organic functional layer 8 forms a first opening 12 at a corresponding position in the first recess 11. Because there is a first recess 11 between adjacent sub-pixels that penetrates part of the thickness of the pixel limiting layer 4 and the interlayer insulating layer 2, the organic functional layer 8 material above the first recess 11 is deposited at the bottom of the first recess 11, so that the pixel limiting layer 4 between adjacent sub-pixels forms a first opening 12 above the corresponding position of the first recess 11. Since the charge carriers cannot pass through the first opening 12, the crosstalk path between adjacent sub-pixels is cut off, avoiding the problem of adjacent sub-pixels emitting light due to crosstalk, improving the grayscale clarity of the display substrate, and improving the display effect.

[0043] In some examples, Figure 5 This is a plan view of a first opening in an embodiment of this disclosure, such as... Figure 5As shown, the length of the first opening 12 between any adjacent sub-pixels is not less than the first length, which is the maximum width of the adjacent sub-pixels in the extension direction of the first opening 12. That is, the length of the first opening 12 between adjacent sub-pixels is not less than the maximum width of the sub-pixel with the largest area among the adjacent sub-pixels in the extension direction of the first opening 12. This arrangement ensures that the first opening 12 can fully block the carrier transmission channel between adjacent sub-pixels, avoid the problem of carrier crosstalk causing adjacent sub-pixels to emit light, improve the grayscale clarity of the display substrate, and improve the display effect.

[0044] In some examples, Figure 6 This is a plan view of another first opening in an embodiment of this disclosure, as shown below. Figure 6 As shown, the lengths of all first openings 12 are equal, and the length of each first opening 12 is not less than the second length, which is the largest width among all sub-pixels in the extension direction of the first opening 12. That is, the length of the first opening 12 is not less than the width of the sub-pixel with the largest area in the display substrate in the extension direction of the first opening 12. This arrangement unifies the lengths of all first openings 12 to the same value, allowing each corresponding first recess 11 to be manufactured according to the same parameters during the manufacturing process, reducing the difficulty of the process, and ensuring that the first opening 12 can effectively block the passage of charge carriers between adjacent sub-pixels.

[0045] In some examples, there are multiple first recesses 11 between adjacent sub-pixels, and all first recesses 11 extend in the same direction, for example, Figure 7 This is a plan view of another first opening 12 in an embodiment of the present disclosure, as shown below. Figure 7 As shown, two first receiving portions with the same extension direction and length are respectively provided between the red sub-pixel R and the adjacent first green sub-pixel G1 and second green sub-pixel G2. Similarly, two first receiving portions with the same extension direction and length are respectively provided between the blue sub-pixel B and the adjacent first green sub-pixel G1 and second green sub-pixel G2. The first receiving portions penetrate a portion of the thickness of the pixel limiting layer 4 and the interlayer insulating layer 2. Compared with the scheme of providing a first recess 11 between adjacent sub-pixels, this double recess structure has a better blocking effect on charge carriers and a more significant improvement in display effect.

[0046] In some examples, in addition to the first recess 11, a plurality of second recesses are formed between any adjacent sub-pixels, extending through a portion of the thickness of the pixel limiting layer 4 and the interlayer insulating layer 2; the orthographic projection of a second recess on the substrate 1 corresponds to the apex angle of the orthographic projection of the receiving portion of the pixel limiting layer 4 on the substrate 1; the organic functional layer 8 forms a second opening 13 at the corresponding position of the second recess.

[0047] For example, Figure 8 This is a plan view of a first opening and a second opening in an embodiment of this disclosure, as shown below. Figure 8 As shown, two first receiving portions with the same extension direction and length are respectively provided between the red sub-pixel R and the adjacent first green sub-pixel G1 and second green sub-pixel G2; two first receiving portions with the same extension direction and length are respectively provided between the blue sub-pixel B and the adjacent first green sub-pixel G1 and second green sub-pixel G2; the first receiving portions penetrate a portion of the thickness of the pixel limiting layer 4 and the interlayer insulating layer 2, and the organic functional layer 8 forms a first opening 12 at the corresponding position of the first receiving portion. Two second recesses are respectively provided at the two opposite corners of the red sub-pixel R and the blue sub-pixel B; two second recesses are respectively provided at the two opposite corners of the first green sub-pixel G1 and the second green sub-pixel G2, the second recesses penetrating a portion of the thickness of the pixel limiting layer 4 and the interlayer insulating layer 2, and the organic functional layer 8 forms a second opening 13 at the corresponding position of the second receiving portion. This configuration not only blocks carrier diffusion at the relative edge positions of adjacent sub-pixels, but also effectively blocks carrier diffusion at the relative apex positions of adjacent sub-pixels, thereby reducing carrier crosstalk between adjacent sub-pixels and improving the display effect of the display substrate.

[0048] In some examples, the second electrode layer 7 of each light-emitting device is an integrally formed structure, and a first opening 12 is formed at the position corresponding to the organic functional layer 8 in the first recess 11.

[0049] In some examples, the second electrode layer 7 of each light-emitting device is an integrally formed structure, and a second opening 13 is formed at the corresponding position of the second electrode layer 7 and the organic functional layer 8 in the second recess.

[0050] The above configuration not only blocks the organic functional layer 8 between adjacent sub-pixels, but also blocks the second electrode layer 7 between adjacent sub-pixels, thereby avoiding crosstalk of charge carriers to adjacent sub-pixels through the second electrode layer 7.

[0051] In some examples, the organic functional layer 8 includes at least one of a hole transport layer 801, a hole injection layer, an electron transport layer 802, and an electron injection layer. By providing an organic functional layer 8 containing the above-mentioned films, the luminous efficiency of the light-emitting layer 6 and the stability of the light-emitting layer 6 can be improved.

[0052] In some examples, such as Figure 4As shown, the display substrate also includes limiting portions 10 located on both sides of the first recess 11 and disposed in the same layer as the first electrode layer 5. The material of the limiting portions 10 is the same as that of the first electrode layer 5. Since the first receiving portion and the second receiving portion are formed by etching the pixel limiting layer 4 and the interlayer insulating layer 2 with dry etching gas, and since the aforementioned dry etching gas cannot etch the first electrode layer 5, the position and width of the first recess 11 can be defined by the limiting portions 10 disposed in the same material as the first electrode layer 5.

[0053] In some examples, such as Figure 4 As shown, each sub-pixel also includes a pixel driving circuit, which includes a thin-film transistor 3. The display substrate also includes a buffer layer 201 located between the active layer 301 of the thin-film transistor 3 and the substrate 1; a gate insulating layer 202 located between the layer containing the gate 304 of the thin-film transistor 3 and the layer containing the active layer 301; a first insulating layer 203 located between the layer containing the gate 304 of the thin-film transistor 3 and the layers containing the source 304 and drain 302 of the thin-film transistor 3; a planarization layer 204 located between the layers containing the source 304 and drain 302 of the thin-film transistor 3 and the first electrode layer 5; the drain 302 of the thin-film transistor 3 is electrically connected to the first electrode layer 5 through a via penetrating the planarization layer 204.

[0054] The interlayer insulating layer 2 includes a buffer layer 201, a gate insulating layer 202, a first insulating layer 203, and a planarization layer 204; the first recess 11 penetrates at least one of the buffer layer 201, the first insulating layer 203, and the planarization layer 204. This arrangement of the display substrate makes the thickness of each layer in the display substrate uniform, improves the overall stability, and increases the reliability of the light-emitting device.

[0055] In some examples, the first recess 11 extends through a portion of the thickness of the planarization layer 204. Therefore, the organic functional layer 8 material above the first recess 11 is deposited at the bottom of the first recess 11 to form the first opening 12, thereby blocking the carrier transport channel between adjacent sub-pixels, solving the carrier crosstalk problem between adjacent sub-pixels, and improving the display effect of the display substrate.

[0056] In some examples, the depth range of the first recess 11 is... The first recess 11 within this depth range not only allows the upper organic functional layer 8 to be deposited to form the first opening 12, but also ensures that the first recess 11 will not be too deep and damage other structures in the display substrate.

[0057] In some examples, such as Figure 1As shown, the display substrate contains multiple sub-pixels, including a red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2, and a blue sub-pixel B. In the display panel, the multiple first green sub-pixels G1 and the multiple second green sub-pixels G2 are arranged alternately along a first direction to form a first pixel row; the multiple red sub-pixels R and the multiple blue sub-pixels B are arranged alternately along the first direction to form a second pixel row; the multiple first pixel rows and the multiple second pixel rows are arranged alternately along a second direction. Furthermore, in the second direction, the multiple first green sub-pixels G1 and the multiple second green sub-pixels G2 are arranged alternately to form a first pixel column, and the multiple red sub-pixels R and the multiple blue sub-pixels B are arranged alternately to form a second pixel column. The multiple first pixel columns and the multiple second pixel rows are arranged alternately along the first direction. This pixel arrangement gives the display substrate significant advantages in color performance, viewing angle, and brightness compared to other pixel arrangements, and allows for a larger number of sub-pixels to be arranged in the same area, resulting in higher resolution.

[0058] In a second aspect, embodiments of this disclosure provide a method for fabricating a display substrate, which is used to fabricate any of the aforementioned display substrates. The method includes: forming a substrate 1 and a plurality of sub-pixels disposed on the substrate 1, each sub-pixel including at least a light-emitting device; the process of forming the light-emitting device includes sequentially forming a first electrode layer 5, a second electrode layer 7, and a light-emitting layer 6 and an organic functional layer 8 located between the first electrode layer 5 and the second electrode layer 7 on the substrate 1; the organic functional layer 8 of each light-emitting device is an integrally formed structure; characterized in that the method further includes: forming an interlayer insulating layer 2 on the side of the first electrode layer 5 near the substrate 1; forming a pixel defining layer 4 on the side of the first electrode layer 5 near the light-emitting layer 6; forming a plurality of accommodating portions in the pixel defining layer 4, wherein the orthographic projection of one first electrode layer 5 on the substrate 1 at least partially overlaps with the orthographic projection of one accommodating portion on the substrate 1; forming a first recess 11 penetrating a portion of the thickness of the pixel defining layer 4 and the interlayer insulating layer 2 between any adjacent sub-pixels; and forming a first opening 12 at a corresponding position in the first recess 11 in the organic functional layer 8.

[0059] Since charge carriers cannot pass through the first opening 12, the crosstalk path between adjacent sub-pixels is cut off, effectively avoiding the problem of adjacent sub-pixels emitting light due to crosstalk, improving the grayscale clarity of the display substrate, and improving the display effect.

[0060] Specifically, Figure 9 This is a flowchart illustrating a method for fabricating a display substrate according to an embodiment of the present disclosure; as shown... Figure 9 As shown, to form Figure 5 Taking the display substrate shown as an example, the preparation method of the display substrate specifically includes the following steps.

[0061] S101: Forming a substrate 1, an interlayer insulating layer 2 on the substrate 1, and multiple pixel driving circuits.

[0062] In some examples, the specific steps in step S101 may include: forming a substrate 1; forming a buffer layer 201 on the substrate 1; forming a plurality of pixel driving circuits on the side of the buffer layer 201 away from the substrate 1, each pixel driving circuit including a thin-film transistor 3; forming a gate insulating layer 202 between the layer containing the gate 304 of the thin-film transistor 3 and the layer containing the active layer 301 of the thin-film transistor 3; forming a first insulating layer 203 between the layer containing the gate 304 of the thin-film transistor 3 and the layers containing the source 304 and drain 302 of the thin-film transistor 3; and forming a planarization layer 204 on the side of the layers containing the source 304 and drain 302 of the thin-film transistor 3 away from the substrate 1. The buffer layer 201, the gate insulating layer 202, the first insulating layer 203, and the planarization layer 204 constitute the interlayer insulating layer 2. The display substrate prepared by the above method has uniform thickness of each film layer and good stability of the pixel driving circuit.

[0063] S102: A first electrode layer 5 and a plurality of limiting portions 10 are formed on the side of the interlayer insulating layer 2 away from the substrate 1.

[0064] In some examples, the specific steps in step S102 may include: forming a first electrode layer 5 and a plurality of defining portions 10 on the side of the interlayer insulating layer 2 facing away from the substrate 1. The first electrode layer 5 is connected to the drain 302 of the thin-film transistor 3 through a via penetrating the planarization layer 204. The first electrode layer 5 has a plurality of disconnected regions, and a defining portion 10 is formed in any disconnected region, with only one defining portion 10 formed in each disconnected region. The material of the defining portion 10 is the same as the material of the first electrode layer 5. Since the dry etching gas used to form the first recess 11 cannot etch the material of the first electrode layer 5, the defining portion 10 can define the formation position and width of the first recess 11.

[0065] S103: A pixel defining layer 4 and a first recess 11 are formed on the side of the first electrode layer 5 away from the substrate 1.

[0066] In some examples, the specific steps in step S103 may include: forming a pixel defining layer 4 on the side of the first electrode layer 5 facing away from the substrate 1, wherein a plurality of accommodating portions are formed in the pixel defining layer 4, and the orthographic projection of one accommodating portion on the substrate 1 at least partially overlaps with the orthographic projection of one of the first electrode layers 5 on the substrate 1. A first recess 11 is etched at a corresponding position of the defining portion 10, the first recess 11 penetrating a portion of the thickness of the pixel defining layer 4 and the interlayer insulating layer 2. Since the first recess 11 is a groove structure, the organic functional layer 8 material subsequently formed above the first recess 11 will be deposited into the groove, thereby cutting off the carrier passage path between different sub-pixels in the display substrate, reducing carrier crosstalk between different sub-pixels, and improving the display effect of the display panel.

[0067] S104: A light-emitting layer 6 and an organic functional layer 8 are formed at the corresponding positions in each receiving part.

[0068] In some examples, the specific steps in step S104 may include: forming a light-emitting layer 6 and an organic functional layer 8 at corresponding positions in each accommodating portion. Each organic functional layer 8 is an integral structure, and the organic functional layer 8 includes a hole transport layer 801 between the light-emitting layer 6 and the first electrode layer 5 and an electron transport layer 802 on the side of the light-emitting layer 6 facing away from the substrate 1. The organic functional layer 8 deposits a first opening 12 at the corresponding position of the first accommodating portion. Since charge carriers cannot pass through the gap formed by the first opening 12, the charge carrier transport channel between adjacent sub-pixels is blocked, effectively reducing the charge carrier crosstalk problem between different sub-pixels and improving the display effect of the display panel.

[0069] S105: A second electrode layer 7 is formed on the side of the organic functional layer 8 away from the substrate 1.

[0070] In some examples, the specific steps in step S105 may include: forming a second electrode layer 7 on the side of the organic functional layer 8 away from the substrate 1, the second electrode layer 7 being deposited at the corresponding position of the first recess 11, and forming a first opening 12 with the organic functional layer 8 at this location, so the first opening 12 also blocks the second electrode layer 7 between adjacent sub-pixels, thereby avoiding crosstalk of charge carriers to adjacent sub-pixels through the second electrode layer 7.

[0071] Specifically, Figure 10 This is a flowchart of another method for preparing a display substrate according to an embodiment of this disclosure; as shown Figure 10 As shown, to form Figure 7 Taking the display substrate shown as an example, the preparation method of the display substrate specifically includes the following steps.

[0072] S201: Forming a substrate 1, an interlayer insulating layer 2 on the substrate 1, and multiple pixel driving circuits.

[0073] In some examples, the specific steps in step S201 may include: forming a substrate 1; forming a buffer layer 201 on the substrate 1; forming a plurality of pixel driving circuits on the side of the buffer layer 201 away from the substrate 1, each pixel driving circuit including a thin-film transistor 3; forming a gate insulating layer 202 between the layer containing the gate 304 of the thin-film transistor 3 and the layer containing the active layer 301 of the thin-film transistor 3; forming a first insulating layer 203 between the layer containing the gate 304 of the thin-film transistor 3 and the layers containing the source 304 and drain 302 of the thin-film transistor 3; and forming a planarization layer 204 on the side of the layers containing the source 304 and drain 302 of the thin-film transistor 3 away from the substrate 1. The buffer layer 201, the gate insulating layer 202, the first insulating layer 203, and the planarization layer 204 constitute the interlayer insulating layer 2. The display substrate prepared by the above method has uniform thickness of each film layer and good stability of the pixel driving circuit.

[0074] S202: A first electrode layer 5 and a plurality of limiting portions 10 are formed on the side of the interlayer insulating layer 2 away from the substrate 1.

[0075] In some examples, the specific steps in step S202 may include: forming a first electrode layer 5 and a plurality of defining portions 10 on the side of the interlayer insulating layer 2 facing away from the substrate 1. The first electrode layer 5 is connected to the drain 302 of the thin-film transistor 3 through a via penetrating the planarization layer 204. The first electrode layer 5 has a plurality of disconnected regions, and defining portions 10 are formed in any disconnected region, with two defining portions 10 formed in one disconnected region. The material of the defining portions 10 is the same as the material of the first electrode layer 5. Since the dry etching gas used to form the first recess 11 cannot etch the material of the first electrode layer 5, the defining portions 10 can define the formation position and width of the first recess 11.

[0076] S203: A pixel defining layer 4 and a first recess 11 are formed on the side of the first electrode layer 5 away from the substrate 1.

[0077] In some examples, the specific steps in step S203 may include: forming a pixel defining layer 4 on the side of the first electrode layer 5 facing away from the substrate 1, wherein a plurality of accommodating portions are formed in the pixel defining layer 4, and the orthographic projection of one accommodating portion on the substrate 1 at least partially overlaps with the orthographic projection of one of the first electrode layers 5 on the substrate 1. A first recess 11 is etched at a corresponding position of the defining portion 10, and the first recess 11 penetrates a portion of the thickness of the pixel defining layer 4 and the interlayer insulating layer 2. This fabrication method allows two spaced-apart first recesses 11 with the same extending direction to be formed between adjacent sub-pixels of the display substrate. Subsequently, the organic functional layer 8 material formed above the first recess 11 is deposited into the recess, thereby cutting off the carrier passage path between different sub-pixels in the display substrate, reducing carrier crosstalk between different sub-pixels, and improving the display effect of the display panel.

[0078] S204: A light-emitting layer 6 and an organic functional layer 8 are formed at corresponding positions in each accommodating part.

[0079] In some examples, the specific steps in step S204 may include: forming a light-emitting layer 6 and an organic functional layer 8 at the corresponding position of each accommodating portion. Each organic functional layer 8 is an integral structure, and the organic functional layer 8 includes a hole transport layer 801 between the light-emitting layer 6 and the first electrode layer 5 and an electron transport layer 802 on the side of the light-emitting layer 6 facing away from the substrate 1. The organic functional layer 8 is deposited at the corresponding position of the first accommodating portion to form a first opening 12. This fabrication method forms two first openings 12 between adjacent sub-pixels in the display substrate. Since charge carriers cannot pass through the gaps formed by the first openings 12, the charge carrier transport channels between adjacent sub-pixels are blocked, effectively reducing the problem of charge carrier crosstalk between different sub-pixels and improving the display effect of the display panel.

[0080] S205: A second electrode layer 7 is formed on the side of the organic functional layer 8 away from the substrate 1.

[0081] In some examples, the specific steps in step S205 may include: forming a second electrode layer 7 on the side of the organic functional layer 8 away from the substrate 1, the second electrode layer 7 being deposited at the corresponding position of the first recess 11, and forming a first opening 12 with the organic functional layer 8 at this location, so that the first opening 12 also blocks the second electrode layer 7 between adjacent sub-pixels, thereby avoiding crosstalk of charge carriers to adjacent sub-pixels through the second electrode layer 7.

[0082] Specifically, Figure 11 This is a flowchart illustrating another method for fabricating a display substrate according to an embodiment of the present disclosure; as follows: Figure 11 As shown, to form Figure 8 Taking the display substrate shown as an example, the preparation method of the display substrate specifically includes the following steps.

[0083] S301: Forming a substrate 1, an interlayer insulating layer 2 on the substrate 1, and multiple pixel driving circuits.

[0084] In some examples, the specific steps in step S301 may include: forming a substrate 1; forming a buffer layer 201 on the substrate 1; forming a plurality of pixel driving circuits on the side of the buffer layer 201 away from the substrate 1, each pixel driving circuit including a thin-film transistor 3; forming a gate insulating layer 202 between the layer containing the gate 304 of the thin-film transistor 3 and the layer containing the active layer 301 of the thin-film transistor 3; forming a first insulating layer 203 between the layer containing the gate 304 of the thin-film transistor 3 and the layers containing the source 304 and drain 302 of the thin-film transistor 3; and forming a planarization layer 204 on the side of the layers containing the source 304 and drain 302 of the thin-film transistor 3 away from the substrate 1. The buffer layer 201, the gate insulating layer 202, the first insulating layer 203, and the planarization layer 204 constitute the interlayer insulating layer 2. The display substrate prepared by the above method has uniform thickness of each film layer and good stability of the pixel driving circuit.

[0085] S302: A first electrode layer 5 and a plurality of limiting portions 10 are formed on the side of the interlayer insulating layer 2 away from the substrate 1.

[0086] In some examples, the specific steps in step S302 may include: forming a first electrode layer 5 and a plurality of defining portions 10 on the side of the interlayer insulating layer 2 facing away from the substrate 1. The first electrode layer 5 is connected to the drain 302 of the thin-film transistor 3 through a via penetrating the planarization layer 204. The first electrode layer 5 has a plurality of disconnected regions, and defining portions 10 are formed in any disconnected region, with two defining portions 10 formed in one disconnected region. The material of the defining portions 10 is the same as the material of the first electrode layer 5. Since the dry etching gas used to form the first recess 11 cannot etch the material of the first electrode layer 5, the defining portions 10 can define the formation position and width of the first recess 11.

[0087] S303: A pixel defining layer 4, a first recess 11, and a second recess are formed on the side of the first electrode layer 5 away from the substrate 1.

[0088] In some examples, the specific steps in step S303 may include: forming a pixel defining layer 4 on the side of the first electrode layer 5 facing away from the substrate 1, wherein a plurality of accommodating portions are formed in the pixel defining layer 4, and the orthographic projection of one accommodating portion on the substrate 1 at least partially overlaps with the orthographic projection of one of the first electrode layers 5 on the substrate 1. Etching is performed at the corresponding positions of the defining portions 10 to form a first recess 11 or a second recess, both of which penetrate a portion of the thickness of the pixel defining layer 4 and the interlayer insulating layer 2. This fabrication method not only enables the formation of two spaced first recesses 11 with the same extension direction between adjacent sub-pixels of the display substrate, but also enables the formation of a second recess at the corresponding position of the top corner of the sub-pixel. This allows the organic functional layer 8 material formed above the first recesses 11 and the second recesses to be deposited into the recesses, which not only blocks carrier diffusion at the opposite edge positions of adjacent sub-pixels, but also effectively blocks carrier diffusion at the opposite top corner positions of adjacent sub-pixels, effectively reducing carrier crosstalk between adjacent sub-pixels and improving the display effect of the display substrate.

[0089] S304: A light-emitting layer 6 and an organic functional layer 8 are formed at corresponding positions in each receiving part.

[0090] In some examples, the specific steps in step S304 may include: forming a light-emitting layer 6 and an organic functional layer 8 at corresponding positions in each accommodating portion. Each organic functional layer 8 is an integral structure, and the organic functional layer 8 includes a hole transport layer 801 between the light-emitting layer 6 and the first electrode layer 5 and an electron transport layer 802 on the side of the light-emitting layer 6 facing away from the substrate 1. The organic functional layer 8 deposits to form a first opening 12 at the corresponding position in the first accommodating portion and a second opening 13 at the corresponding position in the second accommodating portion. This fabrication method forms two first openings 12 between adjacent sub-pixels in the display substrate, and a second opening 13 at the corresponding position of the apex of the sub-pixel. Since charge carriers cannot pass through the gap formed by the first opening 12 and the second opening 13, the charge carrier transport channel between adjacent sub-pixels is blocked, effectively reducing the charge carrier crosstalk problem between different sub-pixels and improving the display effect of the display panel.

[0091] S305: A second electrode layer 7 is formed on the side of the organic functional layer 8 away from the substrate 1.

[0092] In some examples, the specific steps in step S305 may include: forming a second electrode layer 7 on the side of the organic functional layer 8 away from the substrate 1, the second electrode layer 7 being deposited at the corresponding positions of the first recess 11 and the second recess, forming a first opening 12 and a second opening 13 with the organic functional layer 8 at this location, so the first opening 12 and the second opening 13 also block the second electrode layer 7 between adjacent sub-pixels, thereby avoiding crosstalk of charge carriers to adjacent sub-pixels through the second electrode layer 7.

[0093] Thirdly, this disclosure provides a display device that includes any of the aforementioned display substrates. Therefore, the display device of this embodiment has higher grayscale clarity and better display effect compared to traditional display devices. This display device can be any product or component with display function, such as electronic paper, QLED panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0094] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a substrate, a plurality of sub-pixels disposed on the substrate, each sub-pixel including at least one light-emitting device; the light-emitting device comprising a first electrode layer and a second electrode layer disposed on the substrate, and a light-emitting layer and an organic functional layer located between the first electrode layer and the second electrode layer; the organic functional layer of each light-emitting device is an integrally formed structure; characterized in that, The display substrate further includes: an interlayer insulating layer located on the side of the first electrode layer near the substrate, and a pixel defining layer located on the side of the first electrode layer near the light-emitting layer; the pixel defining layer has a plurality of receiving portions formed therein, and the orthographic projection of one of the first electrode layers on the substrate at least partially overlaps with the orthographic projection of one of the receiving portions on the substrate. A first recess is formed between any two adjacent sub-pixels, penetrating at least a portion of the thickness of the pixel defining layer and the interlayer insulating layer; the organic functional layer forms a first opening at a position corresponding to the first recess; Wherein, the orthographic projection of the first recess on the substrate does not overlap with the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the first recess on the substrate surrounds a portion of the orthographic projection of the sub-pixel on the substrate; the diameter of the first recess gradually increases along the direction away from the substrate; the sidewall of the first recess has a smooth surface.

2. The display substrate according to claim 1, characterized in that, The length of the first opening between any two adjacent sub-pixels is not less than a first length, where the first length is the maximum width of the adjacent sub-pixels in the extension direction of the first opening.

3. The display substrate according to claim 2, characterized in that, Each of the first openings has an equal length, and the length of the first opening is not less than the second length, which is the largest of the widths of each of the sub-pixels in the extension direction of the first opening.

4. The display substrate according to claim 1, characterized in that, A plurality of second recesses, extending through a portion of the thickness of the pixel defining layer and the interlayer insulating layer, are also formed between any adjacent sub-pixels; The orthographic projection of the second recess on the substrate corresponds to the apex corner of the orthographic projection of the receiving portion of the pixel defining layer on the substrate; the organic functional layer forms a second opening at the corresponding position of the second recess.

5. The display substrate according to claim 4, characterized in that, The second electrode layer of each of the light-emitting devices is an integrally formed structure, and a second opening is formed at the corresponding position of the second inner recess of the second electrode layer and the organic functional layer.

6. The display substrate according to claim 1, characterized in that, The number of first recesses between adjacent sub-pixels is multiple, and the extension direction of each first recess is the same.

7. The display substrate according to claim 1, characterized in that, The organic functional layer includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

8. The display substrate according to claim 1, characterized in that, The second electrode layer of each of the light-emitting devices is an integrally formed structure, and a first opening is formed at the corresponding position of the second electrode layer and the organic functional layer in the first recess.

9. The display substrate according to claim 1, characterized in that, The display substrate further includes a limiting portion located on both sides of the first recess and disposed in the same layer as the first electrode layer, wherein the material of the limiting portion is the same as the material of the first electrode layer.

10. The display substrate according to claim 1, characterized in that, Each of the sub-pixels also includes a pixel driving circuit, the pixel driving circuit including a thin film transistor, and the display substrate also includes a buffer layer located between the active layer of the thin film transistor and the substrate. A gate insulating layer located between the gate layer and the active layer of the thin film transistor, and a first insulating layer located between the gate layer and the source and drain layers of the thin film transistor; A planarization layer is located between the source and drain layers of the thin-film transistor and the first electrode layer; the drain of the thin-film transistor is electrically connected to the first electrode layer through a via penetrating the planarization layer; The interlayer insulating layer includes the buffer layer, the gate insulating layer, the first insulating layer, and the planarization layer; the first recess penetrates at least one of the buffer layer, the first insulating layer, and the planarization layer.

11. The display substrate according to claim 10, characterized in that, The first recess penetrates a portion of the thickness of the planarization layer.

12. The display substrate according to claim 11, characterized in that, The depth of the first concave portion ranges from 1200 Å to 2000 Å.

13. The display substrate according to claim 12, characterized in that, The plurality of sub-pixels include red sub-pixels, first green sub-pixels, second green sub-pixels, and blue sub-pixels. In the display substrate, the plurality of first green sub-pixels and the plurality of second green sub-pixels are arranged alternately in a first direction to form a first pixel row; the plurality of red sub-pixels and the plurality of blue sub-pixels are arranged alternately in a first direction to form a second pixel row; the plurality of first pixel rows and the plurality of second pixel rows are arranged alternately in a second direction, and in the second direction, the plurality of first green sub-pixels and the plurality of second green sub-pixels are arranged alternately in a first pixel column, the plurality of red sub-pixels and the plurality of blue sub-pixels are arranged alternately in a second pixel column, and the plurality of first pixel columns and the plurality of second pixel rows are arranged alternately in a first direction.

14. A method for fabricating a display substrate, comprising forming a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including at least a light-emitting device; the process of forming the light-emitting device includes sequentially forming a first electrode layer, a second electrode layer, and a light-emitting layer and an organic functional layer located between the first electrode layer and the second electrode layer on the substrate; the organic functional layer of each light-emitting device is an integrally formed structure; characterized in that, The method further includes: forming an interlayer insulating layer on the side of the first electrode layer near the substrate; forming a pixel defining layer on the side of the first electrode layer near the light-emitting layer; wherein a plurality of receiving portions are formed in the pixel defining layer, and the orthographic projection of one of the first electrode layers on the substrate at least partially overlaps with the orthographic projection of one of the receiving portions on the substrate; A first recess is formed between any adjacent sub-pixels, penetrating a portion of the thickness of the pixel defining layer and the interlayer insulating layer; the organic functional layer forms a first opening at a corresponding position of the first recess. Wherein, the orthographic projection of the first recess on the substrate does not overlap with the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the first recess on the substrate surrounds a portion of the orthographic projection of the sub-pixel on the substrate; the diameter of the first recess gradually increases along the direction away from the substrate; the sidewall of the first recess has a smooth surface.

15. The preparation method according to claim 14, characterized in that, The method further includes: forming two first recesses with the same extending direction between any adjacent sub-pixels and penetrating a portion of the thickness of the pixel defining layer and the interlayer insulating layer; the organic functional layer forming the first opening at a corresponding position of the first recesses.

16. The preparation method according to claim 15, characterized in that, The method further includes: forming a plurality of second recesses that penetrate the thickness of the pixel defining layer and the interlayer insulating layer between any adjacent sub-pixels; The orthographic projection of the second recess on the substrate corresponds to the apex corner of the orthographic projection of the receiving portion of the pixel defining layer on the substrate; the organic functional layer forms a second opening at the corresponding position of the second recess.

17. A display device, characterized in that, The display substrate includes any one of claims 1-13.

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