Array substrate, display panel and display device

Abstract

The embodiment of the present application provides an array substrate, a display panel and a display device, wherein the array substrate has a display area and a non-display area located on the periphery of the display area, and the array substrate comprises: a substrate; a data module, which is arranged on the substrate and located in the non-display area, and the data module comprises a plurality of data fan-out lines; a clock module, which is located in the non-display area and is stacked with the data module along the thickness direction of the array substrate, and the clock module comprises a plurality of clock signal lines; the orthographic projection of the data module on the substrate and the orthographic projection of the clock module on the substrate at least partially overlap. The data module and the clock module are stacked along the thickness direction, and the orthographic projection of the data module on the substrate and the orthographic projection of the clock module on the substrate at least partially overlap, which can reduce the size of the non-display area occupied by the data module and the clock module, thereby reducing the size of the frame, and can solve the problem of a wide frame in the display panel.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is an active light-emitting device. Compared with the traditional liquid crystal display (LCD) display method, OLED display technology does not require a backlight and has the characteristic of self-luminescence. OLED uses a thinner organic material film layer and a glass substrate. When an electric current passes through, the organic material will emit light. Therefore, OLED display panels can significantly save electricity, can be made lighter and thinner, can withstand a wider range of temperature changes than LCD display panels, and have a larger viewing angle. OLED display panels are expected to become the next generation of flat-panel display technology after LCD, and are one of the most popular technologies in flat-panel display technology.

[0003] Each sub-pixel in an OLED display panel needs to be driven. Usually, an OLED display panel includes scan lines and data lines. The scan lines input signals to the sub-pixels in the same row, and the data lines input data signals to the sub-pixels in the same column. When the sub-pixel receives signals input by both the scan lines and the data lines, the sub-pixel can emit light. Since each row has a corresponding scan line and each column has a corresponding data line, this results in a large number of signal lines in the OLED display panel, making it difficult to achieve a narrow frame. Summary of the invention

[0004] Embodiments of the present application provide an array substrate, a display panel, and a display device, which are intended to solve the problem of a wide frame in a display panel.

[0005] An embodiment of the first aspect of the present application provides an array substrate, the array substrate having a display area and a non-display area located on the periphery of the display area, the array substrate comprising: a substrate; a data module, arranged on the substrate and located in the non-display area, the data module comprising a plurality of data fan-out lines; a clock module, located in the non-display area and stacked with the data module along the thickness direction of the array substrate, the clock module comprising a plurality of clock signal lines; an orthographic projection of the data module on the substrate and an orthographic projection of the clock module on the substrate at least partially overlap.

[0006] According to an implementation of the first aspect of the present application, the orthographic projection of the clock module on the substrate is located within the orthographic projection of the data module on the substrate.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the array substrate includes two or more conductive layers arranged on a substrate and stacked along a thickness direction of the array substrate, and a plurality of data fan-out lines are arranged in the two or more conductive layers.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, multiple data fan-out lines are located in two or more adjacent conductive layers, multiple clock signal lines are located in the same conductive layer, and the conductive layer where the multiple clock signal lines are located is located on the side of the conductive layer where the multiple data fan-out lines are located facing or away from the substrate.

[0009] According to any of the aforementioned implementations of the first aspect of the present application, it also includes data lines located in the display area, the data lines and the data fan-out lines are connected one-to-one, and the data fan-out lines connecting two adjacent data lines are located in different conductive layers.

[0010] According to any of the aforementioned implementations of the first aspect of the present application, the data line is extended and formed along a first direction, and the data module and the clock module are located on one side of the display area in the first direction.

[0011] According to any of the aforementioned implementations of the first aspect of the present application, it further includes a scanning line extending along a second direction, the second direction intersecting the first direction;

[0012] There are two data modules and two clock modules, and the two data modules and the two clock modules are respectively arranged at two sides of the non-display area in the second direction.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the display area includes a first sub-display area and a second sub-display area distributed along a second direction, the data lines in the first sub-display area are connected to a data module located on a side of the first sub-display area away from the second sub-display area, the scan lines in the first sub-display area are connected to a clock module located on a side of the first sub-display area away from the second sub-display area, the data lines in the second sub-display area are connected to the data module located on a side of the second sub-display area away from the first sub-display area, and the scan lines in the second sub-display area are connected to the clock module located on a side of the second sub-display area away from the first sub-display area.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, the areas of the first sub-display area and the second sub-display area are equal.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, the two or more conductive layers include: a first conductive layer, including shielding lines located in the display area and part of the data fan-out lines located in the non-display area.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, the two or more conductive layers further include a second conductive layer located on a side of the first conductive layer away from the substrate, and the plurality of data fan-out lines are respectively arranged in the first conductive layer and the second conductive layer.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the two or more conductive layers further include a third conductive layer located on the side of the second conductive layer away from the substrate, and multiple data fan-out lines are respectively arranged in the first conductive layer, the second conductive layer and the third conductive layer.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the two or more conductive layers further include a fourth conductive layer located on a side of the third conductive layer facing away from the substrate, and the plurality of clock signal lines are located in the fourth conductive layer.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, there is a first gap between adjacent data fan-out lines, and the orthographic projection of at least part of the clock signal line on the substrate and the orthographic projection of the first gap on the substrate at least partially overlap.

[0020] According to any of the aforementioned implementations of the first aspect of the present application, there is a second gap between two adjacent clock signal lines, and the width of the second gap is greater than the width of the first gap.

[0021] An embodiment of the second aspect of the present application further provides a display panel, comprising an array substrate of any of the above-mentioned embodiments of the first aspect.

[0022] The embodiment of the third aspect of the present application further provides a display device, comprising the display panel of the embodiment of the second aspect mentioned above.

[0023] In the array substrate provided in the embodiment of the present application, the array substrate includes a substrate and a data module and a clock module arranged on the substrate. The data module and the clock module are both located in the non-display area. The data module includes a plurality of data fan-out lines to transmit data drive signals to the display area through the data fan-out lines. The clock module includes a plurality of clock signal lines to transmit clock drive signals to the display area through the clock signal lines. The data module and the clock module are stacked in the thickness direction, and the orthographic projection of the data module on the substrate and the orthographic projection of the clock module on the substrate at least partially overlap, which can reduce the size of the non-display area occupied by the data module and the clock module, thereby reducing the size of the frame, and can solve the problem of a wide frame in the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0025] Figure 1 It is a structural schematic diagram of an array substrate provided by an embodiment of the first aspect of the present application;

[0026] Figure 2 yes Figure 1 A schematic diagram of the local enlarged structure at position I in the middle;

[0027] Figure 3 yes Figure 1 Sectional view at AA in the middle;

[0028] Figure 4 is a structural schematic diagram of an array substrate provided by another embodiment of the first aspect of the present application;

[0029] Figure 5 is a structural schematic diagram of an array substrate provided by another embodiment of the present application;

[0030] Figure 6 In another embodiment of the first aspect of the present application Figure 1 Sectional view at AA in the middle;

[0031] Figure 7 In another embodiment of the first aspect of the present application Figure 1 Cross-sectional view at AA in the middle.

[0032] Description of reference numerals:

[0033] 10. Array substrate;

[0034] 100, substrate;

[0035] 200, data module; 210, data fan-out line;

[0036] 300, clock module; 310, clock signal line;

[0037] 400, conductive layer; 410, first conductive layer; 420, second conductive layer; 430, third conductive layer; 440, fourth conductive layer;

[0038] 500, data line;

[0039] 600, scan lines;

[0040] 700, driving circuit; 710, thin film transistor; 711, semiconductor layer;

[0041] 800, shift register;

[0042] 900, occlusion line;

[0043] AA, display area; AA1, first sub-display area; AA2, second sub-display area; NA, non-display area; Y, first direction; X, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0044] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0045] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0046] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0047] In order to better understand this application, Figures 1 to 7 The array substrate, display panel and display device of the embodiments of the present application are described in detail.

[0048] Please also read Figures 1 to 3 , Figure 1 It is a structural schematic diagram of an array substrate 10 provided in an embodiment of the first aspect of the present application. Figure 2 yes Figure 1 Schematic diagram of the local enlarged structure at point I in the middle. Figure 3 yes Figure 1 Cross-sectional view at AA in the middle.

[0049] like Figures 1 to 3As shown, the array substrate 10 has a display area AA and a non-display area NA located on the periphery of the display area AA, and the array substrate 10 includes: a substrate 100; a data module 200, which is arranged on the substrate 100 and located in the non-display area NA, and the data module 200 includes a plurality of data fan-out lines 210; a clock module 300, which is located in the non-display area NA and is stacked with the data module 200 along the thickness direction Z of the array substrate 10, and the clock module 300 includes a plurality of clock signal lines 310; the orthographic projection of the data module 200 on the substrate 100 and the orthographic projection of the clock module 300 on the substrate 100 at least partially overlap.

[0050] Figure 1 and Figure 2 The data module 200 and the clock module 300 are framed by dotted lines, and the dotted lines do not constitute a limitation on the structure of the array substrate 10 in the embodiment of the present application. Figure 1 and Figure 2 Some of the data fan-out lines 210 are not used because they are located at the bottom layer. Figure 1 and Figure 2 FIG. 4 schematically shows the relative position relationship between some of the data fan-out lines 210 and the clock signal lines 310 , which does not mean that the data fan-out lines 210 and the clock signal lines 310 are located in the same layer.

[0051] In the array substrate 10 provided in the embodiment of the present application, the array substrate 10 includes a substrate 100 and a data module 200 and a clock module 300 disposed on the substrate 100. The data module 200 and the clock module 300 are both located in the non-display area NA. The data module 200 includes a plurality of data fan-out lines 210 to transmit data drive signals to the display area AA through the data fan-out lines 210. The clock module 300 includes a plurality of clock signal lines 310 to transmit clock drive signals to the display area AA through the clock signal lines 310. The data module 200 and the clock module 300 are stacked along the thickness direction Z, and the orthographic projection of the data module 200 on the substrate 100 and the orthographic projection of the clock module 300 on the substrate 100 at least partially overlap, which can reduce the size of the non-display area NA occupied by the data module 200 and the clock module 300, thereby reducing the frame size, and can solve the problem of a wide frame in the display panel.

[0052] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 , the orthographic projection of the clock module 300 on the substrate 100 is located within the orthographic projection of the data module 200 on the substrate 100. Figure 1 and Figure 2 The dashed box where the clock module 300 is located is located within the dashed box where the data module 200 is located.

[0053] Usually, the number of clock signal lines 310 is less than the number of data fan-out lines 210, so the size of the data module 200 is larger than the size of the clock module 300. In these optional embodiments, the orthographic projection of the clock module 300 on the substrate 100 is set within the orthographic projection of the data module 200 on the substrate 100, which can further reduce the space occupied by the clock module 300 and the data module 200 and reduce the frame size.

[0054] In the embodiment of the present application, the data module 200 refers to a module including a data fan-out line 210, and specifically refers to a layer structure of a region where the data fan-out line 210 is located and the data fan-out line 210. For example, please continue to refer to Figure 2 The data module 200 may further include a first gap d1 between two adjacent data fan-out lines 210 , and the data module 200 may further include a conductive layer 400 where the data fan-out lines 210 are located and an insulating layer between two adjacent layers of data fan-out lines 210 .

[0055] In the embodiment of the present application, the clock module 300 refers to a module including a clock signal line 310, and specifically refers to a layer structure of a region where the clock signal line 310 is located and the clock signal line 310. For example, please continue to refer to Figure 2 The clock module 300 may further include a second gap d2 located between two adjacent clock signal lines 310 .

[0056] In some optional embodiments, the width of the second gap d2 is greater than the width of the first gap d1. The width of the second gap d2 refers to the distance between two adjacent clock signal lines 310, and the width of the first gap d1 refers to the distance between two adjacent data fan-out lines 210. When the width of the second gap d2 is greater than the width of the first gap d1, the distance between two adjacent clock signal lines 310 is larger. On the one hand, the parasitic capacitance formed between the two adjacent clock signal lines 310 can be improved, and the stability of signal transmission on the clock signal line 310 is improved.

[0057] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 , at least a portion of the orthographic projection of the clock signal line 310 on the substrate 100 and the orthographic projection of the first gap d1 on the substrate 100 at least partially overlap. This can reduce the stacking area of ​​the data fan-out line 210 and the clock signal line 310, reduce the parasitic capacitance generated thereby, and improve the stability of signal transmission.

[0058] Optionally, the orthographic projection of the clock signal line 310 on the substrate 100 is located within the orthographic projection of the first gap d1 on the substrate 100, that is, the clock signal line 310 and the data fan-out line 210 are completely misaligned, which can further reduce the stacking area of ​​the data fan-out line 210 and the clock signal line 310, and reduce the parasitic capacitance generated thereby, thereby improving the stability of signal transmission.

[0059] In some optional embodiments, please continue to refer to Figure 3 The array substrate 10 includes two or more conductive layers 400 disposed on the substrate 100 and stacked along the thickness direction Z of the array substrate 10 , and a plurality of data fan-out lines 210 are disposed in the two or more conductive layers 400 .

[0060] In these optional embodiments, disposing multiple data fan-out lines 210 in more than two conductive layers 400 can reduce the number of data fan-out lines 210 in the same conductive layer 400, thereby reducing the space occupied by the data fan-out lines 210 in the conductive layer 400 and further reducing the frame size.

[0061] Optional, please continue to Figure 3 , multiple data fan-out lines 210 are located in more than two adjacent conductive layers 400, multiple clock signal lines 310 are located in the same conductive layer 400, and the conductive layer 400 where the multiple clock signal lines 310 are located is located on the side of the conductive layer 400 where the multiple data fan-out lines 210 are located facing or away from the substrate 100.

[0062] In these optional embodiments, the two or more conductive layers 400 where the data fan-out lines 210 are located are adjacent to each other, and the clock signal line 310 is located on one side of the conductive layer 400 where the data fan-out lines 210 are located. The two or more conductive layers 400 where the data fan-out lines 210 are located are adjacent to each other, which can reduce the crossing of the data fan-out lines 210 and the clock signal lines 310, and can shorten the length of the data fan-out lines 210, thereby simplifying the wiring of the array substrate 10.

[0063] In some optional embodiments, please continue to refer to Figures 1 to 3 The array substrate 10 further includes data lines 500 located in the display area AA. The data lines 500 and the data fan-out lines 210 are connected in a one-to-one correspondence, and the data fan-out lines 210 connected to two adjacent data lines 500 are located in different conductive layers 400. Figure 1 and Figure 2 In the figure, since some data fan-out lines 210 are located at the bottom layer, the connection relationship between all data lines 500 and the data fan-out lines 210 is not shown.

[0064] In these optional embodiments, the data fan-out lines 210 connecting two adjacent data lines 500 are located in different conductive layers 400 , which can reduce the distance between the data line 500 and the data fan-out line 210 connected thereto, thereby reducing the wiring distance and simplifying the wiring of the array substrate 10 .

[0065] Optional, please continue to Figure 1 , the column substrate further includes a plurality of driving circuits 700 arranged in rows and columns, each driving circuit 700 is used to drive each sub-pixel to display. The driving circuits 700 in the same column are used to connect the same data line 500. For example, the column direction is the first direction Y, and the row direction is the second direction X. Then the data line 500 is extended along the first direction Y. Optionally, the array substrate 10 further includes a scanning line 600 extending along the second direction X, and the same scanning line 600 is used to connect the plurality of driving circuits 700 in the same row.

[0066] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 , the data module 200 and the clock module 300 are located at one side of the display area AA in the first direction Y. The distance between the data module 200 and the data line 500 can be reduced, and the end of the data line 500 extending along the first direction Y is directly connected to the data fan-out line 210 in the data module 200, so that the data line 500 does not need to go around to the side of the display area AA in the second direction X and then connect to the data fan-out line 210, which can simplify the wiring structure of the array substrate 10.

[0067] See also Figure 4 , Figure 4 It is a structural schematic diagram of an array substrate 10 provided in another embodiment of the first aspect of the present application.

[0068] In some optional embodiments, such as Figure 4 As shown, there are two data modules 200 and two clock modules 300 , and the two data modules 200 and the two clock modules 300 are respectively arranged on both sides of the non-display area NA in the second direction X.

[0069] In these optional embodiments, first, the two data modules 200 and the clock module 300 are arranged on both sides of the non-display area NA in the second direction X, and a gap can be formed between the two clock modules 300 and the data module 200, and other wires such as voltage signal lines can be arranged in the gap. In addition, there are two clock modules 300, and the two clock modules 300 can transmit signals to the scan line 600 from both sides of the display area AA in the second direction X to achieve bilateral driving.

[0070] In some optional embodiments, please continue to refer to Figure 4The display area AA includes a first sub-display area AA1 and a second sub-display area AA2 distributed along a second direction X, a data line 500 in the first sub-display area AA1 is connected to a data module 200 located on a side of the first sub-display area AA1 away from the second sub-display area AA2, a scan line 600 in the first sub-display area AA1 is connected to a clock module 300 located on a side of the first sub-display area AA1 away from the second sub-display area AA2, a data line 500 in the second sub-display area AA2 is connected to the data module 200 located on a side of the second sub-display area AA2 away from the first sub-display area AA1, and a scan line 600 in the second sub-display area AA2 is connected to the clock module 300 located on a side of the second sub-display area AA2 away from the first sub-display area AA1.

[0071] That is, the data line 500 in the first sub-display area AA1 is connected to Figure 4 The data module 200 on the left side of the viewing direction is shown, and the scan line 600 in the first sub-display area AA1 is connected to Figure 4 The clock module 300 is shown on the left side of the viewing direction. The data line 500 in the second sub-display area AA2 is connected to Figure 4 The data module 200 on the right side of the viewing direction is shown, and the scan line 600 in the second sub-display area AA2 is connected to Figure 4 The clock module 300 is shown on the right side of the view direction. The distance between the data line 500 and the data fan-out line 210 connected thereto can be further reduced, thereby shortening the wiring distance. The distance between the clock module 300 and the scan line 600 can also be reduced. Figure 4 The dot-dash line is used to indicate the boundary between the first sub-display area AA1 and the second sub-display area AA2 , and the dot-dash line does not constitute a structural limitation on the array substrate 10 of the embodiment of the present application.

[0072] Optional, please continue to Figure 4 , the areas of the first sub-display area AA1 and the second sub-display area AA2 are equal. Then the number of driving circuits 700 and the number of data lines 500 arranged in the first sub-display area AA1 and the second sub-pixel area are equal, so that the wiring of the array substrate 10 can be symmetrically arranged, simplifying the wiring of the array substrate 10.

[0073] Optional, please continue to Figure 4 , two scan lines 600 are arranged in the same row, one of which is located in the first sub-display area AA1 and is used to transmit signals to the driving circuit 700 in the first sub-display area AA1, and the other scan line 600 is located in the second sub-display area AA2 and is used to transmit signals to the driving circuit 700 in the second sub-display area AA2. Such an arrangement can shorten the extension path of the same scan line 600 and speed up signal transmission.

[0074] See also Figure 5 , Figure 5 1 is a schematic structural diagram of an array substrate 10 provided in yet another embodiment of the present application.

[0075] In some optional embodiments, such as Figure 5 As shown, the array substrate 10 also includes a shift register 800, which is arranged on at least one side of the display area AA in the second direction X, the scan line 600 is connected to one end of the shift register 800, and the clock signal line 310 is connected to the other end of the shift register 800, and the clock signal line 310 transmits a signal to the scan line 600 through the shift register 800.

[0076] Optional, please continue to Figure 5 There are multiple shift registers 800, and the multiple shift registers 800 are arranged on both sides of the display area AA in the second direction X. One or more shift registers 800 located on the same side of the display area AA are connected to multiple clock signal lines 310 of the same clock module 300.

[0077] See also Figure 1 and Figure 6 , Figure 6 In another embodiment of the first aspect of the present application Figure 1 Cross-sectional view at AA in the middle.

[0078] In some optional embodiments, such as Figure 6 As shown, the two or more conductive layers 400 include: a first conductive layer 410, including a shielding line 900 located in the display area AA and a portion of the data fan-out line 210 located in the non-display area NA. In these embodiments, both the shielding line 900 and the data fan-out line 210 are disposed in the first conductive layer 410, and the thickness of the array substrate 10 will not be increased.

[0079] In some optional embodiments, please continue to refer to Figure 6 The driving circuit 700 includes a thin film transistor 710, and the thin film transistor 710 includes a semiconductor layer 711. The shielding line 900 is located on the side of the semiconductor layer 711 facing the substrate 100. The shielding line 900 is used to shield the light incident from the substrate 100 to the semiconductor layer 711, thereby improving the service life of the thin film transistor 710.

[0080] In some optional embodiments, please continue to refer to Figure 6 The more than two conductive layers 400 also include a second conductive layer 420 located on the side of the first conductive layer 410 away from the substrate 100, and the multiple data fan-out lines 210 are respectively arranged in the first conductive layer 410 and the second conductive layer 420, which can reduce the space size occupied by the multiple data fan-out lines 210 and reduce the size of the non-display area NA.

[0081] Optional, please continue to Figure 6 The clock module 300 is located on the side of the second conductive layer 420 away from the substrate 100 , so that the first conductive layer 410 and the second conductive layer 420 used to set the data fan-out line 210 can be arranged adjacent to each other, simplifying the wiring of the array substrate 10 .

[0082] See also Figure 7 , Figure 7 In another embodiment of the first aspect of the present application Figure 1 Cross-sectional view at AA in the middle.

[0083] In some optional embodiments, such as Figure 7 As shown, the two or more conductive layers 400 further include a third conductive layer 430 located on the side of the second conductive layer 420 away from the substrate 100, and the plurality of data fan-out lines 210 are respectively arranged in the first conductive layer 410, the second conductive layer 420 and the third conductive layer 430. The space occupied by the plurality of data fan-out lines 210 can be further reduced, and the size of the non-display area NA can be reduced.

[0084] Please continue reading Figure 7 When the array substrate 10 includes a third conductive layer 430, the clock module 300 is located on the side of the third conductive layer 430 away from the substrate 100, so that the first conductive layer 410, the second conductive layer 420 and the third conductive layer 430 used to set the data fan-out line 210 can be arranged adjacent to each other, simplifying the wiring of the array substrate 10.

[0085] Please continue reading Figure 7 The more than two conductive layers 400 further include a fourth conductive layer 440 located on a side of the third conductive layer 430 facing away from the substrate, and the plurality of clock signal lines 310 are located in the fourth conductive layer 440 .

[0086] In these optional embodiments, the data fan-out line 210 is located in the adjacent first conductive layer 410, the second conductive layer 420 and the third conductive layer 430, which can simplify the wiring complexity. The clock signal line 310 is located at 440 farthest from the substrate 100, and the clock signal line 310 and the data fan-out line 210 are located in different conductive layers 400, which can reduce the size of the non-display area NA and realize a narrow frame design.

[0087] Optionally, the non-display area NA further includes a pad (not shown in the figure), which is located on the side of the data module 200 and the clock module 300 away from the display area AA, and includes a data pad and a clock pad, and the data pad is used to connect the data fan-out line 210, so that the data fan-out line 210 can be electrically connected to the outside through the data pad. The clock pad is used to connect the clock signal line 310, so that the clock signal line 310 can be electrically connected to the outside through the clock pad.

[0088] The embodiment of the second aspect of the present application further provides a display panel, comprising the array substrate 10 of any of the above-mentioned embodiments of the first aspect. Since the display panel of the embodiment of the present application comprises the above-mentioned array substrate 10, the display panel of the embodiment of the present application has the beneficial effects of the above-mentioned array substrate 10, which will not be described in detail here.

[0089] The third aspect of the present application also provides a display device, including the above-mentioned display panel. The display device in the embodiment of the present invention includes but is not limited to a mobile phone, a personal digital assistant (PDA), a tablet computer, an e-book, a television, a door access control system, a smart fixed telephone, a console, and other devices with display functions.

[0090] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: The array substrate has a display area and a non-display area located around the display area, and the array substrate includes: substrate; A data module, disposed on the substrate and located in the non-display area, the data module comprising a plurality of data fan-out lines; A clock module, located in the non-display area and stacked with the data module along the thickness direction of the array substrate, the clock module comprising a plurality of clock signal lines; The orthographic projection of the clock module on the substrate is located within the orthographic projection of the data module on the substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate comprises two or more conductive layers which are arranged on the substrate and stacked along the thickness direction of the array substrate, and the plurality of data fan-out lines are arranged in the two or more conductive layers.

3. The array substrate according to claim 2, characterized in that: The multiple data fan-out lines are located in two or more adjacent conductive layers, the multiple clock signal lines are located in the same conductive layer, and the conductive layer where the multiple clock signal lines are located is located on the side of the conductive layer where the multiple data fan-out lines are located facing or away from the substrate.

4. The array substrate according to claim 2, characterized in that: It also includes data lines located in the display area, the data lines and the data fan-out lines are connected in a one-to-one correspondence, and the data fan-out lines connecting two adjacent data lines are located in different conductive layers.

5. The array substrate according to claim 4, characterized in that: The data line is extended and formed along a first direction, and the data module and the clock module are located at one side of the display area in the first direction.

6. The array substrate according to claim 5, characterized in that: It also includes a scanning line extending along a second direction, wherein the second direction intersects the first direction; There are two data modules and two clock modules, and the two data modules and the two clock modules are respectively arranged at two sides of the non-display area in the second direction.

7. The array substrate according to claim 6, characterized in that: The display area includes a first sub-display area and a second sub-display area distributed along the second direction, the data lines in the first sub-display area are connected to the data module located on a side of the first sub-display area away from the second sub-display area, the scan lines in the first sub-display area are connected to the clock module located on a side of the first sub-display area away from the second sub-display area, the data lines in the second sub-display area are connected to the data module located on a side of the second sub-display area away from the first sub-display area, and the scan lines in the second sub-display area are connected to the clock module located on a side of the second sub-display area away from the first sub-display area.

8. The array substrate according to claim 7, characterized in that: The first sub-display area and the second sub-display area are equal in area.

9. The array substrate according to claim 2, characterized in that: The two or more conductive layers include: a first conductive layer, including shielding lines located in the display area and a portion of the data fan-out lines located in the non-display area.

10. The array substrate according to claim 9, characterized in that: The two or more conductive layers further include a second conductive layer located on a side of the first conductive layer away from the substrate, and the plurality of data fan-out lines are respectively arranged in the first conductive layer and the second conductive layer.

11. The array substrate according to claim 10, characterized in that: The two or more conductive layers further include a third conductive layer located on a side of the second conductive layer away from the substrate, and the plurality of data fan-out lines are respectively arranged in the first conductive layer, the second conductive layer and the third conductive layer.

12. The array substrate according to claim 11, characterized in that: The two or more conductive layers further include a fourth conductive layer located on a side of the third conductive layer away from the substrate, and the plurality of clock signal lines are located in the fourth conductive layer.

13. The array substrate according to claim 1, characterized in that: There is a first gap between adjacent data fan-out lines, and at least a portion of the orthographic projection of the clock signal line on the substrate and the orthographic projection of the first gap on the substrate at least partially overlap.

14. The array substrate according to claim 13, characterized in that: There is a second gap between two adjacent clock signal lines, and the width of the second gap is greater than the width of the first gap.

15. A display panel, characterized in that: Comprising the array substrate according to any one of claims 1 to 14.

16. A display device, characterized in that: Includes the display panel as claimed in claim 15.

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