Method for manufacturing NMOS transistor

Abstract

The present invention provides a method for manufacturing an NMOS transistor, comprising: providing a substrate formed with a shallow trench isolation structure and a P-type well region, on which a gate structure and a first sidewall are formed; implanting germanium ions into the P-type well regions on both sides of the first sidewall to form silicon-germanium regions; forming a buffer layer; forming a stress layer; performing an annealing process to generate stress memory in the channel region; removing the stress layer and the buffer layer and forming a second sidewall. By forming a buffer layer, a stress layer and performing an annealing process (the above three steps are the SMT process) to generate stress memory in the channel region before forming the second sidewall, the present application can reduce the distance between the stress layer and the channel region, enabling the channel region to generate more stress memory, enhancing the stress boosting effect of the SMT process on the NMOS transistor, accelerating the carrier mobility of the NMOS transistor, and thus improving the speed of the NMOS device.

Description

Technical Field

[0001] The present application relates to the technical field of CMOS devices, and particularly relates to a method for manufacturing an NMOS transistor. Background Art

[0002] As the feature size of the CMOS integrated circuit process technology continues to shrink, the short-channel effect is continuously strengthened. Currently, by increasing the doping concentration of the device channel and reducing the gate oxide layer thickness, the depletion layer between the source / drain and the substrate can be reduced and the gate control ability can be improved, thereby improving the short-channel effect. However, a highly doped channel will increase Coulomb scattering, and improving the gate control ability will form a strong electric field resulting in enhanced interface scattering, thereby causing a decrease in carrier mobility and ultimately reducing the speed of the device. Therefore, many current studies propose using strained silicon technology to improve the carrier mobility of the device, compensate for the Coulomb scattering caused by high doping and the interface scattering caused by the strong electric field, thereby increasing the speed of the device.

[0003] Currently, there are two types of strained silicon technologies for NMOS devices. The first one is: the source / drain embedded SiC strain process, but this process has certain difficulties. Firstly, the selectivity of the SiC strain material epitaxial growth process is relatively poor. While growing on the bottom wall of the source / drain groove, it will also grow on non-single crystal regions such as oxides, such as on the side walls of the source / drain groove and the shallow trench isolation structure (STI); in addition, the thermal stability of the SiC strain material during high-temperature thermal annealing is relatively poor. When the temperature is greater than 900 °C, some C atoms in the SiC strain material will leave the substitutional lattice and the stress is lost. The second one is: the stress memory technology (SMT) process. Currently, although the SiGe process and the SMT process for improving the speed of PMOS devices are relatively mature, the effect on improving the speed of NMOS devices is not very good. Therefore, a new method for manufacturing an NMOS transistor is needed to optimize and improve the existing SMT process. Summary of the Invention

[0004] The present application provides a method for manufacturing an NMOS transistor, which can solve the problem that the existing SMT process cannot improve the speed of NMOS devices.

[0005] On the one hand, an embodiment of the present application provides a method for manufacturing an NMOS transistor, including:

[0006] Providing a substrate, in which a plurality of shallow trench isolation structures and P-type well regions located between the shallow trench isolation structures are formed, and a gate structure and a first sidewall located on the side of the gate structure are formed on the substrate;

[0007] Using the first sidewall as a mask, implanting germanium ions into the P-type well regions on both sides of the first sidewall to form silicon-germanium regions;

[0008] A buffer layer is formed, and the buffer layer covers the gate structure, the first sidewall, the silicon germanium region, and the shallow trench isolation structure;

[0009] A stress layer is formed, and the stress layer covers the buffer layer;

[0010] An annealing process is performed to generate stress memory in the silicon germanium region and a partial P-type well region;

[0011] The stress layer and the buffer layer are removed; and,

[0012] A second sidewall is formed, and the second sidewall is located on the side of the first sidewall.

[0013] Optionally, in the method for manufacturing the NMOS transistor, after the second sidewall is formed, the method for manufacturing the NMOS transistor further includes:

[0014] A protective layer is formed, and the protective layer covers the silicon germanium region and the shallow trench isolation structure on the side of the second sidewall.

[0015] Optionally, in the method for manufacturing the NMOS transistor, after the protective layer is formed, the method for manufacturing the NMOS transistor further includes:

[0016] Using the second sidewall as a mask, N-type conductive ions are implanted into the silicon germanium region under the protective layer to form a shallow doped drain structure.

[0017] Optionally, in the method for manufacturing the NMOS transistor, during the process of implanting germanium ions into the P-type well regions on both sides of the first sidewall to form a silicon germanium region, the dose of germanium ions is 1E15 atoms / cm 3 ~1E16 atoms / cm 3 and the implantation energy is 25 KeV to 45 KeV.

[0018] Optionally, in the method for manufacturing the NMOS transistor, the annealing process is a spike annealing process, the process temperature is 800 °C to 1200 °C, and the operation time is 60 s to 5400 s.

[0019] Optionally, in the method for manufacturing the NMOS transistor, the material of the stress layer is silicon nitride.

[0020] Optionally, in the method for manufacturing the NMOS transistor, the thickness of the stress layer is 30 nm to 70 nm.

[0021] Optionally, in the method for manufacturing the NMOS transistor, the material of the buffer layer is silicon oxide.

[0022] Optionally, in the method for manufacturing the NMOS transistor, the thickness of the buffer layer is 10 nm to 25 nm.

[0023] Optionally, in the method for manufacturing the NMOS transistor, a wet cleaning process is used to remove the stress layer and the buffer layer.

[0024] The technical solution of the present application has at least the following advantages:

[0025] In the present application, before forming the buffer layer, a germanium ion implantation process is performed on the P-type well regions on both sides of the first sidewall to obtain silicon-germanium regions, which can amorphize the surface of part of the P-type well regions and cause lattice dislocation, thereby increasing the tensile stress on the surface of the NMOS channel region (mainly including the P-type well regions and the silicon-germanium regions).

[0026] Furthermore, in the present application, before forming the second sidewall, a buffer layer is formed, a stress layer is formed, and an annealing process (the above three steps are the SMT process) is performed to generate stress memory in the channel region, which can reduce the distance between the stress layer and the channel region, cause more stress memory in the channel region, enhance the stress enhancement effect of the SMT process on the NMOS transistor, accelerate the carrier mobility of the NMOS transistor, and thus improve the speed of the NMOS device.

[0027] In addition, in the present application, after forming the second sidewall, a protective layer is formed, which can effectively retain the stress memory in the channel region, further enhance the stress enhancement effect of the NMOS transistor, and thus improve the speed of the NMOS device. Description of the Drawings

[0028] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 is a flowchart of the method for manufacturing the NMOS transistor according to an embodiment of the present invention;

[0030] Figures 2 - 8 is a schematic diagram of the semiconductor structure in each process step of manufacturing the NMOS transistor according to an embodiment of the present invention;

[0031] Among them, the reference numerals are explained as follows:

[0032] 100 - Substrate, 101 - P - type well region, 102 - Silicon - germanium region, 110 - Shallow trench isolation structure, 120 - Gate structure, 130 - First sidewall, 140 - Buffer layer, 150 - Stress layer, 170 - Protective layer. Detailed implementation manners

[0033] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0034] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0035] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0036] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0037] An embodiment of the present application provides a method for manufacturing an NMOS transistor. Please refer to Figure 1 , Figure 1 which is a flowchart of the method for manufacturing an NMOS transistor according to an embodiment of the present invention. The method for manufacturing an NMOS transistor includes:

[0038] S10: Provide a substrate, in which a plurality of shallow trench isolation structures and a P - type well region located between the shallow trench isolation structures are formed, and a gate structure and a first sidewall located on the side of the gate structure are formed on the substrate;

[0039] S20: Using the first sidewall as a mask, implant germanium ions into the P-type well regions on both sides of the first sidewall to form silicon-germanium regions;

[0040] S30: Form a buffer layer that covers the gate structure, the first sidewall, the silicon-germanium regions, and the shallow trench isolation structure;

[0041] S40: Form a stress layer that covers the buffer layer;

[0042] S50: Perform an annealing process to generate stress memory in the silicon-germanium regions and part of the P-type well regions;

[0043] S60: Remove the stress layer and the buffer layer;

[0044] S70: Form a second sidewall on the side of the first sidewall.

[0045] Specifically, please refer to Figures 2 - 8 , Figures 2 - 8 which is a schematic diagram of the semiconductor structure in each process step of manufacturing an NMOS transistor according to an embodiment of the present invention.

[0046] First, as Figure 2 shown, provide a substrate 100 in which a plurality of shallow trench isolation structures 110 and P-type well regions 101 located between the shallow trench isolation structures 110 are formed. A gate structure 120 and a first sidewall 130 located on the side of the gate structure 120 are formed on the substrate 100. Specifically, the substrate 100 can be one of single-crystalline silicon, polycrystalline silicon, and amorphous silicon. The substrate 100 can also be gallium arsenide, silicon-gallium compound, etc. The substrate 100 can also have a silicon-on-insulator or silicon-on-epitaxial layer structure; the substrate 100 can also be other semiconductor materials, which will not be listed one by one here. The gate structure 120 can include a gate oxide layer and a polysilicon gate, etc. In this embodiment, the specific structure (layers) of the gate structure 120 are not limited and can be a common gate structure 120 in existing NMOS device technologies. The material of the first sidewall 130 can be silicon nitride. In this embodiment, a silicon nitride film layer covering the surface of the gate structure 120 and the substrate 100 can be formed first, and then the silicon nitride film layer on the top of the gate structure 120 and the surface of the substrate 100 is removed by lithography and etching processes, and the silicon nitride film layer on the side of the gate structure 120 is retained to obtain the first sidewall 130.

[0047] Then, as Figure 3As shown, using the first sidewall 130 as a mask, germanium ions are implanted into the P-type well regions 101 on both sides of the first sidewall 130 to form silicon-germanium regions 102. Specifically, in the germanium ion implantation process, the dose of germanium ions can be 1E15 atoms / cm 3 ~1E16 atoms / cm 3 , the implantation energy can be 25 KeV to 45 KeV, and the angle can be 10° to 30°. In this embodiment, no specific process parameters of the germanium ion implantation process are limited, and the process parameters can be determined according to the specific process conditions. By performing the germanium ion implantation process on the P-type well regions 101 in the substrate 100 on both sides of the first sidewall 130 before forming the buffer layer 140, the surface of part of the P-type well regions 101 can be amorphized and the crystal lattice can be misaligned, thereby increasing the tensile stress on the surface of the NMOS device channel region (mainly including the silicon-germanium regions 102 and the P-type well regions 101), and thus increasing the carrier mobility of the NMOS device.

[0048] Next, as Figure 4 shown, a buffer layer 140 is formed, and the buffer layer 140 covers the gate structure 120, the first sidewall 130, the silicon-germanium region 101, and the shallow trench isolation structure 110. Specifically, in this embodiment, a common process such as chemical vapor deposition (CVD) can be used to form the buffer layer 140, and the material of the buffer layer 140 can be silicon oxide. The thickness of the buffer layer 140 is 10 nm to 25 nm.

[0049] Furthermore, as Figure 5 shown, a stress layer 150 is formed, and the stress layer 150 covers the buffer layer 140. Specifically, in this embodiment, a common process such as chemical vapor deposition (CVD) can be used to form the stress layer 150, and the material of the stress layer 150 can be silicon nitride. The thickness of the stress layer 150 is 30 nm to 70 nm.

[0050] Even further, an annealing process is performed on the semiconductor structure formed by the above process steps to generate stress memory in the silicon-germanium regions 102 and part of the P-type well regions 101 (the channel region of the NMOS transistor). Specifically, the annealing process can be a spike annealing process, the process temperature is 800 °C to 1200 °C, and the operation time is 60 s to 5400 s. Through the annealing process, the stress is memorized, so that the stress remains in the channel region after the stress layer 150 and the buffer layer 140 are removed subsequently.

[0051] Next, as Figure 6As shown, the stress layer 150 and the buffer layer 140 are removed. Specifically, in this embodiment, a wet cleaning process can be used to remove the stress layer 150 and the buffer layer 140. Phosphoric acid can be selected as a reagent for wet cleaning. The stress layer 150 and the buffer layer 140 are removed at one time through the wet cleaning process, thereby eliminating surface defects of the gate structure 120 and the first sidewall 130 without any impurities remaining, thereby improving device reliability.

[0052] Finally, if Figure 7 As shown, a second sidewall 160 is formed, and the second sidewall 160 is located on the side of the first sidewall 130. Specifically, the material of the second sidewall 160 may include silicon oxide and silicon nitride stacked in sequence. In this embodiment, silicon oxide and silicon nitride covering the gate structure 120, the first sidewall 130 and the surface of the substrate 100 may be formed first, and then the silicon oxide and silicon nitride on the top of the gate structure 120 and the surface of the substrate 100 may be removed by photolithography and etching processes, and the stacked silicon oxide and silicon nitride on the side of the gate structure 120 (on the first sidewall 130) may be retained to obtain the second sidewall 160.

[0053] In this embodiment, before forming the second sidewall 160, a buffer layer 140 is formed, a stress layer 150 is formed, and an annealing process is performed (the above three steps are SMT processes) to generate stress memory in the channel region, and the distance between the stress layer 150 and the channel region (the silicon germanium region 102 and the P-type well region 101) can be reduced, so that the channel region generates more stress memory, enhances the stress enhancement effect of the SMT process on the NMOS transistor, accelerates the carrier mobility of the NMOS transistor, and thus improves the speed of the NMOS device.

[0054] Better, such as Figure 8 As shown, after forming the second sidewall 160, the method for preparing the NMOS transistor may further include: forming a protective layer 170, the protective layer 170 covers the silicon germanium region 102 and the shallow trench isolation structure 110 in the substrate 100 on the side of the second sidewall 160. Specifically, the protective layer 170 may be a silicon layer or a self-aligned silicide layer, and the protective layer 170 may be formed by a chemical vapor deposition process or a physical vapor deposition (PVD) process. The thickness of the protective layer 170 may be 20nm to 100nm. The present application forms the protective layer 170 on the silicon germanium region 102 and the shallow trench isolation structure 110 after forming the second sidewall 160, so as to effectively retain the stress memory of the channel region, thereby further enhancing the stress lifting effect of the NMOS transistor, thereby further improving the speed of the NMOS device.

[0055] Preferably, after forming the protective layer 170, the method for manufacturing the NMOS transistor of this embodiment further includes: using the second sidewall 160 as a mask, injecting N-type conductive ions into the silicon germanium region 102 under the protective layer 170 to form a lightly doped drain structure (not shown).

[0056] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. The obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing an NMOS transistor, characterized in that, Including: Providing a substrate, in which a plurality of shallow trench isolation structures and P-type well regions located between the shallow trench isolation structures are formed, a gate structure is formed on the substrate, and a first sidewall is located on the side of the gate structure; Using the first sidewall as a mask, implanting germanium ions into the P-type well regions on both sides of the first sidewall to form silicon-germanium regions; Forming a buffer layer, the buffer layer covering the gate structure, the first sidewall, the silicon-germanium regions and the shallow trench isolation structures; Forming a stress layer, the stress layer covering the buffer layer; Performing an annealing process to generate stress memory in the silicon-germanium regions and part of the P-type well regions; Removing the stress layer and the buffer layer; Forming a second sidewall, the second sidewall being located on the side of the first sidewall; and, Forming a protective layer, the protective layer covering the silicon-germanium regions and the shallow trench isolation structures on the side of the second sidewall.

2. The manufacturing method of the NMOS transistor according to claim 1, characterized in that, After forming the protective layer, the method for manufacturing the NMOS transistor further includes: Using the second sidewall as a mask, implanting N-type conductive ions into the silicon-germanium regions under the protective layer to form a shallow doped drain structure.

3. The manufacturing method of the NMOS transistor according to claim 1, characterized in that, During the process of implanting germanium ions into the P-type well regions on both sides of the first sidewall to form silicon-germanium regions, the dose of germanium ions is 1E15 atoms / cm 3 ~1E16 atoms / cm 3 , and the implantation energy is 25 keV to 45 keV.

4. The manufacturing method of the NMOS transistor according to claim 1, characterized in that, The annealing process is a spike annealing process, the process temperature is 800°C to 1200°C, and the operation time is 60s to 5400s.

5. The manufacturing method of the NMOS transistor according to claim 1, characterized in that, The material of the stress layer is silicon nitride.

6. The manufacturing method of the NMOS transistor according to claim 1, wherein, The thickness of the stress layer is 30nm to 70nm.

7. The manufacturing method of the NMOS transistor according to claim 1, characterized in that, The material of the buffer layer is silicon oxide.

8. The manufacturing method of the NMOS transistor according to claim 1, characterized in that, The thickness of the buffer layer is 10nm to 25nm.

9. The manufacturing method of the NMOS transistor according to claim 1, wherein, Removing the stress layer and the buffer layer by using a wet cleaning process.

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