Fusible structures and methods of making the same

Abstract

A fusible structure includes a metal wire having different portions with different thicknesses. Thinner portions of the metal wire are designed to change destructively at lower voltages, while thicker portions of the metal wire are designed to change destructively at higher voltages. Additionally, one or more dummy structures are positioned proximate to the thinner portions of the metal wire. In some embodiments, the dummy structures are positioned close enough to prevent metal sputtering when the metal wire changes destructively. Embodiments of the present application also provide a method of manufacturing a fusible structure.

Description

Technical Field

[0001] Embodiments of this application relate to fusible structures and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of devices to solve problems in many different fields. Some of these devices, such as fusible structures, are configured for multiple uses, including data storage. As fusible structures become smaller and more complex, the performance of these devices has become a major concern for the industry. Summary of the Invention

[0003] In some embodiments, a fusible structure includes: a metal wire extending along a first direction; and a first pseudo-structure configured to be close to the metal wire relative to a second direction perpendicular to the first direction; and wherein: relative to the first direction, the metal wire includes a first portion, a second portion, and a third portion, the second portion being located between the first portion and the third portion; relative to the third direction perpendicular to the first and second directions, the first portion has a first thickness, the second portion has a second thickness, the first thickness being greater than the second thickness; and the first pseudo-structure is close to the second portion of the metal wire.

[0004] In some embodiments, a fusible structure includes: a metal wire extending along a first direction; a first pseudo-structure configured to be spaced a first distance from the metal wire relative to a second direction perpendicular to the first direction; and wherein: relative to the first direction, the metal wire includes a first portion, a second portion, and a third portion, the second portion being located between the first portion and the third portion; and relative to a third direction perpendicular to the first and second directions, the first portion is thinner than the second portion.

[0005] In some embodiments, a method of manufacturing a fusible structure includes: forming a metal wire extending along a first direction, the forming of the metal wire including: configuring a mask such that the metal wire has a first portion located between a second portion and a third portion; using an optical proximity correction technique and the mask such that the first portion is thinner than each of the second and third portions; and forming a first pseudo-structure proximate to the metal wire and aligned with the first portion relative to the first direction. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A These are component diagrams of a fusible structure according to some embodiments;

[0008] Figure 1B This is a component diagram showing a cross-sectional view of a metal wire 102 taken along the centerline of a metal wire in a first direction according to some embodiments;

[0009] Figure 2 These are component diagrams of a fusible structure according to some embodiments;

[0010] Figure 3A These are component diagrams of a fusible structure according to some embodiments;

[0011] Figure 3B This is a component diagram showing a cross-sectional view of a metal wire taken along the centerline of a first direction according to some embodiments;

[0012] Figure 4A These are component diagrams of a fusible structure according to some embodiments;

[0013] Figure 4B This is a component diagram showing a cross-sectional view of a metal wire taken along the centerline of a first direction according to some embodiments;

[0014] Figure 5 These are component diagrams of a fusible structure according to some embodiments;

[0015] Figure 6 This is a flowchart of a method for generating a layout diagram according to some embodiments;

[0016] Figure 7 This is a flowchart of a method for forming a metal wire according to some embodiments;

[0017] Figure 8A and Figure 8B Correspondingly, there are component diagrams and cross-sectional views according to some embodiments;

[0018] Figure 9A and Figure 9B Correspondingly, there are component diagrams and cross-sectional views according to some embodiments;

[0019] Figure 10 This is a block diagram of an electronic design automation (EDA) system according to some embodiments;

[0020] Figure 11 This is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to some embodiments. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0022] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0023] The embodiments include fusible structures and corresponding manufacturing methods. In some embodiments, the fusible structure includes a metal wire having different thicknesses in different portions. Compared to previously known techniques, the thinner portions of the metal wire are designed to be destructively altered at lower voltages, while the thicker portions are designed to be destructively altered at higher voltages. Additionally, one or more dummy structures are positioned close to the thinner portions of the metal wire. In some embodiments, when the metal wire is destructively altered, the dummy structures are placed close enough to prevent metal sputtering.

[0024] Figure 1A This is a top view of a fusible structure 100 according to some embodiments.

[0025] In some embodiments, the fusible structure 100 serves as an eFuse. The fusible structure 100 includes a metal wire 102, which in some embodiments is a narrow strip (also referred to as a “wire”) of a conductive material (metal, polysilicon, etc.). To program the fusible structure 100, a programming current is applied to the metal wire 102, which destructively alters (i.e., melts) the metal wire 102, thereby increasing the resistance of the fusible structure 100. In some embodiments, programming the fusible structure 100 is referred to as burning the fusible structure 100. In some embodiments, the fusible structure 100 serves as a one-time programmable memory (OTP). In some embodiments, to determine the bit state stored by the fusible structure 100, a sensing current can be transmitted through the metal wire 102. A sensing amplifier (not shown) electrically connected to the metal wire 102 compares the current on the metal wire 102 with a reference current. The sensing current is lower in magnitude than the programming current, so it does not destructively alter the metal wire 102. The programming current is higher in magnitude than the sensing current. Therefore, the programming voltage corresponding to the programming current is higher in magnitude than the sensing voltage corresponding to the sensing current.

[0026] The programming voltage is configured to generate a sufficient programming current to destructively alter metal line 102, causing a destructive change to metal line 102. This destructive change disconnects metal line 102, creating an electrical discontinuity (or open circuit) within it. When metal line 102 is destructively altered and disconnected, it is configured to a high-resistance state. Prior to this destructive change, as... Figure 1A As shown, metal wire 102 is in a low-resistance state. This will be explained in further detail below. Figure 1A The construction of the fusible structure 100 shown facilitates the use of a lower programming voltage, and therefore a lower programming current, to disruptively alter the metal line 102, causing (again) the metal line 102 to be in a high-resistance state. In other words, the programming voltage is extended to a lower voltage, thereby reducing the likelihood that the metal line 102 will not disconnect. Increasing the range of programming voltages to include lower voltages is beneficial, for example, because the voltages used in modern semiconductor devices are decreasing.

[0027] In some embodiments, the high-resistance state or low-resistance state of the fuse structure 100 is used to represent bit values, and thus the data is stored in a non-volatile manner. A sense amplifier (not shown) in the memory circuitry (not shown) is configured to generate a read current whose magnitude is insufficient to change the metal line 102, and the corresponding resistance state (high-resistance state or low-resistance state) of the corresponding fusible structure 100 is determined by the sense amplifier (not shown). In a write operation (also referred to as a “programming operation”), a source line driver (not shown) is configured to provide a write voltage (also referred to as a “programming voltage”) to the metal line 102 to destructively alter the metal line 102. Other types of functionality besides serving as non-volatile memory are also within the scope of various embodiments.

[0028] A fusible structure 100 is disposed within a semiconductor structure 104. The semiconductor structure 104 includes a semiconductor substrate 106 and one or more metal layers 108 formed on or below the semiconductor substrate 106. In this embodiment, all components of the fusible structure 100 are formed in one metal layer 108. In other embodiments, one or more components of the fusible structure 100 are formed in one metal layer, while another one or more components of the fusible structure 100 are formed in another metal layer.

[0029] Metal wire 102 has along parallel to Figure 1A The metal wire 102 has a major axis extending along a first direction perpendicular to the X-axis. The metal wire 102 has a minor axis extending along a second direction perpendicular to the X-axis. In this embodiment, the minor axis is parallel to the Y-axis. The metal wire 102 includes a first portion 110, a second portion 112, and a third portion 114. The first portion 110 is located between the second portion 112 and the third portion 114 relative to the X-axis. The minor axis is parallel to each of the X-axis and Y-axis (e.g., parallel to the Z-axis). Figure 1AIn a third direction (not shown), the second portion 112 and the third portion 114 have approximately a first thickness, while the first portion 110 has approximately a second thickness. The first portion 110 is located between the second portion 112 and the third portion 114 relative to the X-axis (i.e., parallel to the X-axis). The second thickness is less than the first thickness. Relative to the X-axis, the first portion 110 has a length (L_110) divided by boundary lines fp1 and fp2; in some embodiments, the length of the first portion 110 is approximately L_110 ≈ 0.12 μm. Relative to the X-axis, the second portion 112 has a length (L_112) divided by boundary lines sp1 and fp1; in some embodiments, the length of the second portion 112 is approximately L_112 ≈ 0.666 μm. Relative to the X-axis, the third portion 114 has a length (L_114) divided by boundary lines fp2 and sp2; in some embodiments, the length of the third portion 114 is L_114 ≈ 0.666 μm. In some embodiments, L_112≈L_114. In some embodiments, L_110≈0.18*L_112. In some embodiments, L_112≈L_114. In some embodiments, L_110≈0.18*L_114. In some embodiments, the length between the boundary line tv1 and fp1 is L_tv1_fp1≈0.14μm. In some embodiments, the length between the boundary line tv2 and fp2 is L_tv2_fp2≈0.14μm. In some embodiments, L_tv1_fp1≈L_tv2_fp2. In some embodiments, L_110≈0.86*L_tv1_fp1. In some embodiments, L_110≈0.86*L_tv2_fp2. Because the first portion 110 is thinner than the second portion 112 and the third portion 114, it disconnects at a lower current amplitude and therefore a lower voltage amplitude compared to each of the second portion 112 and the third portion 114. The thinner first portion 110 and its disconnection at a lower current amplitude and therefore a lower voltage amplitude advantageously increase the lower limit of the voltage range used for programming voltage.

[0030] The fusible structure 100 includes pseudo-structures 116 and 118. Pseudo-structures 116 and 118 are located on opposite sides of the metal line 102 relative to the X-axis. Pseudo-structures 116 and 118 are aligned with each other relative to the X-axis. Pseudo-structure 116 is separated from the metal line 102 by a distance D1 relative to the Y-axis. Pseudo-structure 118 is separated from the metal line 102 by a distance D2 relative to the Y-axis. In this embodiment, distances D1 and D2 are equal. In other embodiments, distances D1 and D2 are different.

[0031] Dummy structures 116 and 118 are designed to prevent damage to the first portion 110 of the metal line 102 from affecting nearby non-dummy structures or devices. In some cases, programming / burning / destroying the first portion 110 can cause sputtering, which can damage nearby non-dummy structures and / or devices. Dummy structures 116 and 118 are positioned to absorb material sputtered from the first portion 110, which reduces (if not prevented) damage to nearby structures and / or devices.

[0032] Reducing the distances D1 and D2 helps to make the first thickness of the first portion 110 thinner than the rest of the metal wire 102 (i.e., the second portion 112 and the third portion 114). In some embodiments, the distances D1 and D2 are equal. In some embodiments, D1 = D2 = 22 nanometers. In some embodiments, D1 = D2 = 32 nanometers. In some embodiments, D1 = D2 = 42 nanometers. In some embodiments, D1 = D2 = 60 nanometers. In some embodiments, D1 = D2 = 90 nanometers. In some embodiments, D1 = D2 = 120 nanometers.

[0033] Pseudo-structures 116 and 118 can have any shape. In 1A, pseudo-structures 116 and 118 are rectangular and have the same proportions. The major axis of pseudo-structure 116 and the major axis of pseudo-structure 118 are each set along the X-axis to define a length a. The minor axis of pseudo-structure 116 and the minor axis of pseudo-structure 118 are each set along the Y-axis to define a width b. In some embodiments, the ratio of length a to width b is between approximately 0.01 and 100. In some embodiments, the ratio of length a to distance D1 is between approximately 0.01 and 100. The ratio of length a to distance D2 is between approximately 0.01 and 100.

[0034] like Figure 1A As shown, the fusible structure 100 also includes conductive pads 120, 122, 124, and 126. In some embodiments, the conductive pads 120, 122, 124, and 126 are connected to the metal line 102 via conductors and vias in other conductive layers and via layers (not shown). In this way, programming voltage and sensing voltage are applied to the metal line 102. The leftmost edge of the conductive pad 120 and the leftmost edge of the conductive pad 122 are aligned with the first end of the metal line 102. The first end of the metal line 102 and the leftmost edges of the conductive pads 120 and 122 are separated by a boundary line sp1. The conductive pads 120 and 122 each have a major axis extending along the X-axis to the boundary line tv1. The rightmost edge of the conductive pad 124 and the rightmost edge of the conductive pad 126 are aligned with the second end of the metal line 102. The second end of the metal line 102 and the rightmost edges of the conductive pads 124 and 126 are separated by a boundary line sp2. Conductive pads 124 and 126 each have a long axis extending along the X-axis to the dividing line tv2.

[0035] Relative to the X-axis, the length L of the metal line 102 is defined between the rightmost edges of the conductive pads 120 and 122 (divided by boundary line tv1) and the leftmost edges of the conductive pads 124 and 126 (divided by boundary line tv2). Therefore, in Figure 1A In this context, length L is the length of metal wire 102 from boundary line tv1 to boundary line tv2. In some embodiments, L≈0.4μm.

[0036] Metal wire 102 defines a minor axis along the Y-axis, which provides the width w of metal wire 102. In some embodiments, the ratio of distance D1 to length L is between approximately 0.01 and 100. In some embodiments, the ratio of length a to distance D2 is between approximately 0.01 and 100. In some embodiments, the ratio of length L to width w is between approximately 4 and 100. In some embodiments, the above ratios provide sufficient spacing so that metal wire 102 is relatively thin in the first portion 110.

[0037] exist Figure 1A In the diagram, pseudo-structures 116 and 118 are aligned with the first portion 110 relative to the X-axis. However, relative to the X-axis, the first portion 110 extends slightly through pseudo-structures 116 and 118, extending to both the left and right sides of pseudo-structures 116 and 118. Therefore, in Figure 1A In this context, a distance relationship exists where the distance fp1-fp2 is greater than the length a. In some embodiments, optical proximity correction (OPC) is used to facilitate this distance relationship.

[0038] Figure 1B This is a component diagram showing a cross-sectional view of the metal wire 102 taken along the X-axis and the centerline IB of the metal wire 102 according to some embodiments.

[0039] The thickness of the metal line 102 relative to the Z-axis is shown in Figure 1B The Y-axis is not shown in the middle. Figure 1B In the middle, because the Y-axis enters and leaves the page. For example... Figure 1BAs shown, the metal line 102 has a first portion 110 located relative to the X-axis between a second portion 112 and a third portion 114. In this embodiment, the second portion 112 and the third portion 114 have a thickness t2, while the first portion 110 has a thickness t1, where t2 > t1. Therefore, the second portion 112 and the third portion 114 are thicker than the first portion 110. Accordingly, since the first portion 110 is thinner than the second portion 112 and the third portion 114, it is destructively altered at a lower programming voltage compared to the second portion 112 and the third portion 114. More specifically, the first portion 110 has less material than the second portion 112 and the third portion 114 and is therefore more susceptible to damage from resistive heating. In one embodiment, the first portion 110 is destructively altered by an applied programming voltage of 1.53 volts.

[0040] Pseudostructure 116 (see Figure 1A ) and pseudostructure 118 (see Figure 1A The first part 110 is placed near the first part 110. Because the first part 110 is designed to be destructively altered, and because the pseudostructures 116 and 118 prevent metal sputtering, the first part 110 is thinner than the second part 112 and the third part 114. Figure 1A As shown, each of pseudo-structures 116 and 118 is located at the center of the first part 110. However, the length 'a' of each of pseudo-structures 116 and 118 is shorter than the length of the first part 110.

[0041] Figure 2 This is a top view of a fusible structure 200 according to some embodiments.

[0042] Fusible structure 200 is similar to Figure 1A The discussion of fusible structure 200 focuses on the differences between fusible structure 200 and fusible structure 100. Similar components include similar markings.

[0043] The dimensions of pseudostructures 216 and 218 are similar. Figure 1AThe dimensions of pseudo-structures 116 and 118 are specified. Additionally, pseudo-structures 216 and 218 are positioned relative to the X and Y axes in a similar manner to pseudo-structures 116 and 118. However, in this embodiment, pseudo-structures 216 and 218 reside in a different metal layer than metal lines 112 and contact pads 120, 122, 124, 126. In this embodiment, pseudo-structures 216 and 218 are located in the second metal layer of metal layer 108 of semiconductor structure 104, while metal lines 110 and contact pads 120, 122, 124, 126 are located in the first metal layer of metal layer 108, which is located below the second metal layer.

[0044] In some embodiments, the memory circuitry further includes a programming device. In some embodiments, multiple fuse elements are connected to a respective programming device. Therefore, multiple fuse elements share the same programming device, which significantly reduces the area occupied by the memory circuitry compared to other methods. In some embodiments, the programming device includes at least one transistor sized to provide a programming voltage (and thus a programming current) to the fusible structure 100 during a write operation. In some embodiments, the programming device is a source line driver, or part of a source line driver.

[0045] Figure 3A This is a top view of a fusible structure 300 according to some embodiments.

[0046] Fusible structure 300 is similar to Figure 1A The discussion of fusible structure 300 focuses on the differences between fusible structure 300 and fusible structure 100. Similar components include similar markings.

[0047] In this embodiment, the fusible structure 300 includes a metal wire 302 and pseudo-structures 316, 318, 320, and 322. The metal wire 302 includes a first portion 310, a second portion 311, a third portion 312, a fourth portion 314, and a fifth portion 315. Relative to the X-axis, the first portion 310 is located between the third portion 312 and the fifth portion 315. The first portion 310 is demarcated by boundary lines tv1 and m1. Relative to the X-axis, the second portion 311 is located between the fifth portion 315 and the fourth portion 314. The second portion 311 is demarcated by boundary lines m2 and tv2. Relative to the X-axis, the third portion 312 is demarcated by boundary lines sp1 and tv1. Boundary line sp1 demarcates the left end of the metal wire 302 relative to the X-axis. Relative to the X-axis, the fourth portion 314 is demarcated by boundary lines tv2 and sp2. Boundary line sp2 demarcates the right end of the metal wire 302 relative to the X-axis. Relative to the X-axis, the fifth part 315 lies between the first part 310 and the second part 311. The fifth part 315 is divided by the dividing lines m1 and m2.

[0048] As explained in further detail below (see below) Figure 3B The first portion 310 and the second portion 311 are thinner than the third portion 312, the fourth portion 314, and the fifth portion 315. More specifically, the first portion 310 has less material than the third portion 312, the fourth portion 314, and the fifth portion 315, and is therefore more susceptible to damage from resistance heating. Thus, the first portion 310 and the second portion 311 are destructively altered at a lower programming voltage compared to the third portion 312, the fourth portion 314, and the fifth portion 315. By destructively altering the first portion 310 and / or the second portion 311, the fusible structure 300 changes from a low-resistance state to a high-resistance state.

[0049] The fusible structure 300 includes pseudostructures 316, 318, 320, and 322. Pseudostructures 316 and 320 are located on one side of the metal line 302 relative to the X-axis, while pseudostructures 318 and 322 are located on the opposite side of the metal line 302 relative to the X-axis. Pseudostructures 316 and 318 are aligned with the first portion 310 relative to the X-axis. Pseudostructures 316 and 318 are positioned close enough to the first portion 310 to allow the first portion 310 to be thinner than the third portion 312 and the fifth portion 315. Figure 3A As shown, a length relationship exists, wherein the lengths of pseudo-structures 316 and 318 are each shorter than the length of the first portion 310 relative to the X-axis. In some embodiments, this length relationship is facilitated by optical proximity correction (OPC).

[0050] Pseudo-structures 318 and 322 are aligned with the second portion 311 relative to the X-axis. Pseudo-structures 318 and 322 are placed close enough to the second portion 311 to allow the second portion 311 to be thinner than the fifth portion 315 and the fourth portion 314. More specifically, compared to the third portion 312, the fourth portion 314, and the fifth portion 315, the second portion 311 has less material and is therefore more susceptible to damage from resistance heating. Figure 3A As shown, a length relationship exists, wherein the lengths of pseudo-structures 316 and 318 are each shorter than the length of the first portion 310 relative to the X-axis. In some embodiments, this length relationship is facilitated by OPC.

[0051] Pseudo-structure 316 is separated from pseudo-structure 320 relative to the X-axis, and pseudo-structure 318 is separated from pseudo-structure 322 relative to the X-axis. As a result, the fifth portion 315 is located between the first portion 310 and the second portion 311, wherein the fifth portion 315 is thicker than the first portion 310 and the second portion 311.

[0052] Figure 3B This is a component diagram showing a cross-sectional view of the metal wire 302 taken along the X-axis at the centerline IIIB of the metal wire 302.

[0053] The thickness of the metal line 302 relative to the Z-axis is shown in Figure 3B The Y-axis is not shown in the middle. Figure 3B In the middle, because the Y-axis enters and leaves the page. For example... Figure 3B As shown, metal line 302 has a first portion 310 located between a third portion 312 and a fifth portion 315 relative to the X-axis. Metal line 302 also has a second portion 311 located between a fifth portion 315 and a fourth portion 314 relative to the X-axis. In this embodiment, the third portion 312, the fourth portion 314, and the fifth portion 315 have a thickness t2, while the first portion 310 and the second portion 311 have a thickness t1, where t2 > t1. Therefore, the third portion 312, the fourth portion 314, and the fifth portion 315 are thicker than the first portion 310 and the second portion 311. Therefore, compared to the third portion 312, the fourth portion 314, and the fifth portion 315, the first portion 310 and the second portion 311 are destructively altered at a lower programming voltage. In one embodiment, the first portion 310 and the second portion 311 are destructively altered by an applied programming voltage of 1.53 volts.

[0054] Figure 4A This is a top view of a fusible structure 400 according to some embodiments.

[0055] Fusible structure 400 is similar to Figure 1A The discussion of fusible structure 400 focuses on the differences between fusible structure 400 and fusible structure 100. Similar components include similar markings.

[0056] Metal wire 402 includes a first portion 410, a second portion 412, and a third portion 414. The second portion 412 and the third portion 414 have approximately a first thickness relative to the Z-axis, while the first portion 410 has approximately a second thickness. The first portion 410 is located between the second portion 412 and the third portion 414 relative to the X-axis (i.e., parallel to the X-axis). The second thickness is less than the first thickness. The first portion 410 is demarcated by boundary lines fp1′ and fp2′. The second portion 412 is demarcated by boundary lines sp1 and fp1′. The third portion 414 is demarcated by boundary lines fp2′ and sp2. Because the first portion 410 is thinner than the second portion 412 and the third portion 414, the first portion 410 breaks at a lower current amplitude and therefore at a lower voltage amplitude.

[0057] and Figure 1A Compared to the first part 110 shown, Figure 4AThe first portion 410 is longer relative to the X-axis because the fusible structure 400 includes pseudo-structures 416, 418, and 420. Pseudo-structures 416 and 420 are located on one side of the metal line 402, while pseudo-structure 418 is located on the opposite side of the metal line 402 relative to the X-axis. Pseudo-structure 418 is aligned with the first portion 410 relative to the X-axis and is partially located between and partially overlaps with pseudo-structures 416 and 420 relative to the X-axis. Pseudo-structures 416 and 420 are partially aligned with the first portion 410 relative to the X-axis. However, pseudo-structure 416 extends to the left across the boundary line fp1', and pseudo-structure 420 extends to the right across the boundary line fp2'. Therefore, pseudo-structures 416 and 420 allow the first portion 410 to be longer than the first portion 410. Figure 1A The first part 110, but does not extend to the entire length of the leftmost edge of pseudostructure 416 and the rightmost edge of pseudostructure 420, because fusible structure 400 is asymmetrical with respect to pseudostructures 416, 418, and 420.

[0058] Figure 4B This is an assembly diagram showing a cross-sectional view of the metal wire 402 taken along the X-axis at the centerline IVB of the metal wire 402 according to some embodiments.

[0059] The thickness of metal line 402 relative to the Z-axis is shown in Figure 4B The Y-axis is not shown in the middle. Figure 4B In the middle, because the Y-axis enters and leaves the page. For example... Figure 4B As shown, metal line 402 has a first portion 410 located relative to the X-axis between a second portion 412 and a third portion 414. In this embodiment, the second portion 412 and the third portion 414 have a thickness t2, while the first portion 410 has a thickness t1, where t2 > t1. Therefore, the second portion 412 and the third portion 414 are thicker than the first portion 410. Consequently, compared to the second portion 412 and the third portion 414, the first portion 410 is destructively altered at a lower programming voltage. In one embodiment, the first portion 410 is destructively altered by an applied programming voltage of 1.53 volts.

[0060] Figure 5 This is a top view of a fusible structure 500 according to some embodiments.

[0061] Fusible structure 500 is similar to Figure 1A The discussion of fusible structure 500 focuses on the differences between fusible structure 500 and fusible structure 100. Similar components include similar markings.

[0062] The fusible structure 500 is similar to the fusible structure 100, except that the fusible structure 500 does not include the pseudo-structure 116. It is worth noting that different embodiments of the fusible structure, such as fusible structures 100, 200, 300, 400, and 500, include different numbers of pseudo-structures to provide different numbers of portions of different thicknesses, whether asymmetrical or symmetrical.

[0063] Figure 6 This is a flowchart of a method 600 for generating a layout diagram according to some embodiments.

[0064] According to some embodiments, method 600 may, for example, use EDA system 2 (discussed below). Figure 10 ) and integrated circuit (IC) manufacturing system 1100 (discussed below) Figure 11 This is achieved through [method 600]. Regarding method 600, examples of layout diagrams include those with corresponding [features / methods]. Figure 1A , Figure 2 , Figure 3A , Figure 4A , Figure 5 , Figure 8A ,and Figure 9A The diagram shows the layout of the shapes of fusible structures 100, 200, 300, 400, 500, 800 and 900.

[0065] exist Figure 6 In method 600, boxes 602-604 are included. At box 602, a layout diagram is generated, which, among other things, includes the corresponding... Figure 1A , Figure 2 , Figure 3A , Figure 4A , Figure 5 , Figure 8A ,and Figure 9A The shapes of the fusible structures 100, 200, 300, 400, 500, 800, and 900 are indicated in the diagram. The flow proceeds from box 602 to box 604.

[0066] At box 604, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures are performed; or (b) one or more semiconductor masks are fabricated; or (C) one or more components of a semiconductor device layer are fabricated. See below. Figure 11 The following discussion concerns the IC manufacturing system 1100.

[0067] Figure 7 This is a flowchart 700 of a method for forming a metal wire extending along the X-axis according to some embodiments.

[0068] Examples of metal lines formed by flowchart 700 include those corresponding to Figure 1A , Figure 3A ,and Figure 4AMetal wires 102, 302, and 402. In some embodiments, the method includes, during block 602, actions to manufacture, such as in the corresponding Figure 1A , Figure 2 , Figure 3A , Figure 4A , Figure 5 , Figure 8A ,and Figure 9A The procedure for fusible structures 100, 200, 300, 400, 500, 800, and 900 is described. The method includes blocks 702-706.

[0069] At box 702, the mask is configured such that the metal line has a first portion, which is located between the second and third portions. An example of the metal line is shown below. Figure 1A , Figure 3A ,and Figure 4A The metal lines are 102, 302, and 402. An example of the mask is shown below. Figure 8B and Figure 9B The discussion will proceed from box 702 to box 704.

[0070] At frame 704, optical proximity correction (OPC) technology is used in conjunction with a mask to make the first portion thinner than each of the second and third portions. Examples of the first portion include... Figure 1B , Figure 3B ,and Figure 4B The first part 110, the first part 310, the second part 311, and the first part 410 are in the diagram. The flow proceeds from box 704 to box 706.

[0071] At frame 706, the first pseudo-structure is formed close to the metal line and aligned with the first portion relative to the X-axis. Examples of pseudo-structures include... Figure 1A and Figure 5 The pseudo-structures 116 and 118 in the text Figure 2 The pseudostructures 216 and 218 in the text Figure 3A The pseudostructures 316, 318, 320, and 322 in the text are... Figure 4A The pseudostructures 416, 418, and 420 are in the model.

[0072] Figure 8A and Figure 8B Correspondingly, there are component diagrams and cross-sectional views according to some embodiments.

[0073] Figure 8A It is a top view, and Figure 8BThis is a cross-sectional view along the centerline VIIIB of metal line 810. The corresponding mask 802 has a segment 804 located above portion 806. Portion 806 is demarcated by dividing lines C1 and C2. OPC technology is used with mask 802 to make portion 806 thinner than each of portion 818 and third portion 820.

[0074] Figure 9A and Figure 9B Correspondingly, there are component diagrams and cross-sectional views according to some embodiments.

[0075] Figure 9A It is a top view, and Figure 9B This is a cross-sectional view along the centerline IXB of metal line 910. The corresponding mask 902 has a segment 904 located below portion 906. Portion 906 is demarcated by dividing lines C1 and C2. OPC technology is used in conjunction with mask 902 to make portion 906 thinner than each of portion 918 and third portion 920.

[0076] Figure 10 This is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0077] In some embodiments, the EDA system 1000 includes an APR system. According to one or more embodiments, the methods described herein for designing layout diagrams can be implemented, for example, using the EDA system 1000 according to some embodiments.

[0078] In some embodiments, the EDA system 1000 is a general-purpose computing device that includes a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. The storage medium 1004 is encoded, among other things, with computer program code 1006 (i.e., a set of executable instructions), i.e., storing the computer program code 1006. Execution of the instructions 1006 of the hardware processor 1002 represents (at least partially) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (the processes and / or methods mentioned below).

[0079] Processor 1002 is electrically connected to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically connected to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014 to enable processor 1002 and computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable storage medium 1004, thereby enabling system 1000 to be used to implement some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0080] In one or more embodiments, the computer-readable storage medium 1004 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes read-only optical disc memory (CD-ROM), read / write optical disc (CD-R / W), and / or digital video optical disc (DVD).

[0081] In one or more embodiments, storage medium 1004 stores computer program code 1006 configured such that system 1000 (where such execution represents (at least partially) EDA tools) can be used to implement part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1004 also stores information that facilitates the implementation of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1004 stores a standard cell library 1007 including such standard cells disclosed herein. In one or more embodiments, storage medium 1004 stores one or more layout figures 1009 corresponding to one or more layouts disclosed herein.

[0082] EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is connected to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0083] EDA system 1000 also includes a network interface 1012 connected to processor 1002. Network interface 1012 allows system 1000 to communicate with network 1014, to which one or more other computer systems can be connected. Network interface 1012 includes a wireless network interface such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods may be implemented in two or more systems 1000.

[0084] System 1000 is configured to receive information via I / O interface 1010. The information received via I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1002. The information is transmitted to processor 1002 via bus 1008. EDA system 1000 is configured to receive UI-related information via I / O interface 1010. This information is stored as a user interface (UI) 1042 on computer-readable medium 1004.

[0085] In some embodiments, one or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, one or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, one or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, one or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 1000. In some embodiments, layout diagrams including standard cells use materials such as those obtained from CADENCE DESIGN SYSTEMS, Inc. Use tools or other suitable layout generation tools to generate it.

[0086] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in memory or memory cells, such as one or more of an optical disc such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as ROM, RAM, a memory card, etc.

[0087] Figure 11This is a block diagram of an integrated circuit (IC) manufacturing system 1100 and its associated IC manufacturing process according to some embodiments.

[0088] Manufacturing system 1100 is configured to manufacture in the corresponding Figures 1A-1B , Figure 2 , Figures 3A-3B , Figures 4A-4B , Figure 5 , Figure 8A , Figure 8B , Figure 9A ,and Figure 9B The disclosed fusible structures are 100, 200, 300, 400, 500, 800, and 900.

[0089] In some embodiments, based on a layout diagram, for example, manufacturing system 1100 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0090] exist Figure 11 In this IC manufacturing system 1100, entities such as design room 1120, mask room 1130, and IC manufacturer / fab 1150 interact with each other in connection with the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1160. The entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1120, mask room 1130, and IC fab 1150 are owned by a single, larger company. In some embodiments, two or more of design room 1120, mask room 1130, and IC fab 1150 coexist in a shared facility and use shared resources.

[0091] Design studio (or design team) 1120 generates IC design layout 1122. IC design layout 1122 includes various geometric patterns designed for IC device 1160. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers, constituting various components of the IC device 1160 to be manufactured. Various layers combine to form various IC features. For example, a portion of IC design layout 1122 includes various IC features formed in a semiconductor substrate (e.g., a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, and various material layers disposed on the semiconductor substrate. Design studio 1120 implements appropriate design procedures to form IC design layout 1122. Design procedures include one or more of logic design, physical design, or place-and-route operations. IC design layout 1122 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1122 may be expressed in GDSII or DFII file format.

[0092] Mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. Mask chamber 1130 uses an IC design layout 1122 to fabricate one or more masks 1145 for fabricating various layers of an IC device 1160 according to the IC design layout 1122. Mask chamber 1130 performs mask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file (“RDF”). Mask data preparation 1132 provides the RDF to mask fabrication 1144. Mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 1145 or a semiconductor wafer 1153. The design layout 1122 is controlled by mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1150. Figure 11 In this diagram, mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0093] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1122. In some embodiments, mask data preparation 1132 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary patterning, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0094] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1122, which has already been processed in the OPC, and which includes certain geometric and / or connectivity constraints to ensure sufficient margin to address issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1144, which can undo portions of the modifications implemented by the OPC to satisfy the mask creation rules.

[0095] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC), which simulates the process performed by IC fab 1150 to manufacture IC device 1160. The LPC simulates this process based on IC design layout 1122 to create a simulated manufactured device, such as IC device 1160. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated manufactured device has been created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0096] It should be understood that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOPs) to modify the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0097] Following mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a set of masks 1145 can be fabricated based on a modified IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to pattern the mask (photomask or photomask plate) 1145 based on the modified IC design layout 1122. The mask 1145 can be formed using various techniques. In some embodiments, the mask 1145 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque areas and transmits through the transparent areas. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1145 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1145, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The masks generated by mask fabrication 1144 are used in a variety of processes. For example, such masks can be used in ion implantation processes to form various doped regions in semiconductor wafer 1153; such masks can be used in etching processes to form various etched regions in semiconductor wafer 1153; and / or such masks can be used in other suitable processes.

[0098] IC Fab 1150 is an IC manufacturing enterprise that includes one or more manufacturing sites for manufacturing various IC products. In some embodiments, IC Fab 1150 is a semiconductor foundry. For example, there may be one manufacturing site for front-end manufacturing (front-end manufacturing, or FEOL) of multiple IC products, a second manufacturing site for providing back-end manufacturing (back-end manufacturing, or BEOL) for the interconnection and packaging of IC products, and a third manufacturing site for providing other services for the foundry operations.

[0099] IC fab 1150 includes manufacturing tool 1152 configured to perform various manufacturing operations on semiconductor wafer 1153 to manufacture IC device 1160 according to (some) masks (e.g., mask 1145). In various embodiments, manufacturing tool 1152 includes one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of implementing one or more suitable manufacturing processes as discussed herein.

[0100] IC fab 1150 uses masks 1145 manufactured by mask chamber 1130 to fabricate IC device 1160. Therefore, IC fab 1150 uses IC design layout 1122 at least indirectly to fabricate IC device 1160. In some embodiments, semiconductor wafer 1153 is fabricated by IC fab 1150 using masks 1145 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0101] Regarding integrated circuit (IC) manufacturing systems (e.g.) Figure 11Details of the system 1100 and related IC manufacturing processes can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016 (A method for transforming a first IC pattern, wherein the first IC pattern comprises a shape not one of a plurality of user-defined shapes, the method comprising the steps of: using a computer to derive a second IC pattern approximating the first IC pattern, wherein the second IC pattern comprises a shape as one of a plurality of user-defined shapes; calculating a pattern proximity error between the first IC pattern and the second IC pattern; and, if the pattern proximity error is greater than a user-defined threshold, performing the steps of: dividing the first IC pattern into a plurality of subpatterns; and recursively transforming each of the plurality of subpatterns). A), U.S. Pre-Publication No. 20150278429, published October 1, 2015 (A method comprising: receiving a design layout of an IC having principal features; performing process correction on the principal features to generate a modified principal feature; using a computer to generate a simulated profile of the modified principal feature having a plurality of points; generating a plurality of auxiliary data, wherein each auxiliary data includes at least one process performance factor associated with one of the points; storing the simulated profile and auxiliary data in a tangible computer-readable medium for use in other IC processing stages, including a mask inspection process or a wafer inspection process; forming a mask using the design layout having the modified principal feature; and using The method involves simulating contours and multiple auxiliary data to inspect a mask, wherein at least one process performance factor includes a mask error enhancement factor (MEEF), and wherein the inspection of the mask includes: identifying a point associated with a MEEF data higher than another MEEF data; identifying a point associated with a higher MEEF data compared to the other point; and inspecting the mask feature corresponding to one of the points more thoroughly than another feature of the mask corresponding to said other point. This is similar to U.S. Prelicensed Publication No. 20140040838, published February 6, 2014 (A method of manufacturing a mask, comprising: receiving an IC design layout; performing a target feature periphery (TFS) inspection operation to identify features in the IC design layout). The method includes: determining the target feature surrounding location (TFSL); inserting a phase line (PB) on the TFSL; performing optical proximity correction (OPC) on the IC design layout having the PB to form a modified IC design layout; and fabricating a mask based on the modified IC design layout. This is in contrast to U.S. Patent No. 7,260,442, issued August 21, 2007, which describes a mask manufacturing method comprising: providing material data and mask data; determining first process parameters based on the material data and the mask data; performing a first mask process to process a first mask based on the first process parameters; collecting first process data corresponding to the first mask process; and determining feedback correction data based on the material data, the mask data, and the first process data.The entire contents of each item found in the following are incorporated herein by reference: (The first process parameter is corrected based on feedback correction data to obtain the second process parameter; and a second mask process is performed based on the second process parameter to process the second mask.)

[0102] In some embodiments, a fusible structure includes: a metal wire extending along a first direction; and a first dummy structure configured to be close to the metal wire relative to a second direction perpendicular to the first direction; wherein: relative to the first direction, the metal wire includes a first portion, a second portion, and a third portion, the second portion being located between the first portion and the third portion; relative to a third direction perpendicular to the first and second directions, the first portion has a first thickness, the second portion has a second thickness, the first thickness being greater than the second thickness; and the first dummy structure is close to the second portion of the metal wire. In some embodiments, the second portion of the metal wire and the first dummy structure have substantially the same width. In some embodiments, the size of the gap between the first dummy structure and the metal wire is proportional to the second thickness of the metal wire. In some embodiments, the metal wire is electrically connected to a conductor. In some embodiments, the first dummy structure is substantially aligned with the second portion of the metal wire relative to the first direction. In some embodiments, the fusible structure further includes: a second dummy structure; wherein: the second dummy structure is close to the metal wire relative to the second direction; the second dummy structure is substantially aligned with the second portion relative to the first direction; and the second dummy structure and the first dummy structure are located on opposite sides of the metal wire relative to the first direction. In some embodiments, the fusible structure further includes: a third pseudo-structure and a fourth pseudo-structure; and wherein: relative to a first direction, the metal wire includes a fourth portion and a fifth portion; the third portion and the fifth portion each have approximately a first thickness relative to a third direction; the fourth portion is located between the third portion and the fifth portion; the fourth portion has approximately a second thickness relative to a third direction; the third pseudo-structure and the fourth pseudo-structure are close to the metal wire relative to a second direction; the third pseudo-structure and the fourth pseudo-structure are substantially aligned with the second portion relative to a first direction; and the third pseudo-structure and the fourth pseudo-structure are located on opposite sides of the metal wire relative to a first direction. In some embodiments, the fusible structure further includes: a second pseudo-structure; and a third pseudo-structure; and wherein: the second pseudo-structure and the third pseudo-structure are close to the metal wire relative to a second direction; relative to a first direction, the first pseudo-structure is located on an opposite side of the metal wire to each of the second pseudo-structure and the third pseudo-structure; the first pseudo-structure is located at least partially between the second pseudo-structure and the third pseudo-structure relative to a second direction; and the first pseudo-structure, the second pseudo-structure, and the third pseudo-structure are at least partially aligned with the second portion of the metal wire relative to a first direction. In some embodiments, the metal wire is located in a first metal layer; the first pseudo-structure is located in a second metal layer different from the first metal layer. In some embodiments, the fusible structure further includes: a first contact pad; and a second contact pad; and wherein: a second portion is located between the first contact pad and the second contact pad relative to a first direction; the length is defined from the first contact pad to the second contact pad relative to the first direction; the width of the metal line is defined relative to a second direction; the ratio is defined as the length divided by the width; and the ratio is in the range of about 4 and about 100.In some embodiments, the width of the metal line is defined relative to a second direction; the distance is defined relative to the second direction between the metal line and the first dummy structure; and the ratio is defined as the distance divided by the width; wherein the ratio is in the range of about 0.1 and about 100. In some embodiments, the fusible structure further includes: a first contact pad; and a second contact pad; and wherein: a second portion is located relative to a first direction between the first contact pad and the second contact pad; a first length is defined relative to the first direction from the first contact pad to the second contact pad; a second length of the first dummy structure is defined relative to the first direction; and the ratio is defined as the second length divided by the first length, wherein the ratio is in the range of about 0.01 and about 0.99. In some embodiments, the first length of the first dummy structure is defined relative to the first direction; the second length of the first dummy structure is defined relative to the second direction; the ratio is defined as the second length divided by the first length; and the ratio is in the range of about 0.01 and about 100. In some embodiments, the length of the first pseudo-structure is defined relative to a second direction; the distance is defined relative to the second direction between the metal wire and the first pseudo-structure; the ratio is defined as the length divided by the distance; and the ratio is in the range of about 0.01 and about 100.

[0103] In some embodiments, a fusible structure includes: a metal wire extending along a first direction; a first pseudo-structure configured to be spaced a first distance from the metal wire relative to a second direction perpendicular to the first direction; and wherein: relative to the first direction, the metal wire includes a first portion, a second portion, and a third portion, the second portion being located between the first portion and the third portion; and the first portion is thinner than the second portion relative to a third direction perpendicular to the first and second directions. In some embodiments, the fusible structure further includes: a first contact pad; a second contact pad; a third contact pad; and a fourth contact pad; and wherein: both the first and second contact pads are substantially aligned with a first end of the metal wire relative to the first direction; the first and second contact pads are located on opposite sides of the metal wire relative to the first direction; both the third and fourth contact pads are substantially aligned with a second end of the metal wire relative to the first direction, and the third and fourth contact pads are located on opposite sides of the metal wire relative to the first direction; the first end of the metal wire is opposite to the second end of the metal wire. In some embodiments, the first contact pad and the third contact pad are located on a first side of the metal line relative to a first direction; the second contact pad and the fourth contact pad are located on a second side of the metal line relative to the first direction; a second portion is located between the first contact pad and the third contact pad relative to the first direction; and the second portion is located between the second contact pad and the fourth contact pad relative to the first direction. In some embodiments, the second portion of the metal line and the first dummy structure have substantially the same width. In some embodiments, the size of the gap between the first dummy structure and the metal line is proportional to the second thickness of the metal line.

[0104] In some embodiments, a method of manufacturing a fusible structure includes: forming a metal wire extending along a first direction, the forming of the metal wire including: configuring a mask such that the metal wire has a first portion located between a second portion and a third portion; using an optical proximity correction technique and the mask such that the first portion is thinner than each of the second and third portions; and forming a first pseudo-structure proximate to the metal wire and aligned with the first portion relative to the first direction.

[0105] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A fusible structure, comprising: Metal wire, extending along the first direction; as well as A first pseudo-structure is configured to be close to the metal wire relative to a second direction, wherein the second direction is perpendicular to the first direction; The second pseudo-structure and the first pseudo-structure are located on opposite sides of the metal wire relative to the first direction; and in: Relative to the first direction, the metal wire includes a first portion, a second portion, and a third portion, wherein the second portion is located between the first portion and the third portion; Relative to a third direction perpendicular to the first and second directions, the first portion has a first thickness, the second portion has a second thickness, the first thickness is greater than the second thickness, wherein the third direction is perpendicular to the relative arrangement direction of the first and second pseudo-structures; and The first pseudo-structure and the second pseudo-structure are close to the second portion of the metal wire, wherein the second portion is divided by a first boundary line and a second boundary line. In the first direction, the first pseudo-structure is located between the first boundary line and the second boundary line, and the second pseudo-structure has a portion located between the first boundary line and the second boundary line. The first pseudo-structure and the second pseudo-structure are located on both sides of the second portion, which is thinner than the first portion.

2. The fusible structure according to claim 1, wherein: The second portion of the metal wire and the first pseudo-structure have substantially the same width.

3. The fusible structure according to claim 1, wherein: The size of the gap between the first pseudo-structure and the metal wire is proportional to the second thickness of the metal wire.

4. The fusible structure according to claim 1, wherein: The metal wire is electrically connected to the conductor.

5. The fusible structure according to claim 1, wherein: The first pseudo-structure is substantially aligned with the second portion of the metal wire relative to the first direction.

6. The fusible structure according to claim 5, wherein: The second pseudo-structure is close to the metal wire relative to the second direction; The second pseudo-structure is substantially aligned with the second part relative to the first direction.

7. The fusible structure according to claim 6, further comprising: The third pseudo-structure and the fourth pseudo-structure; and in: The metal wire includes a fourth portion and a fifth portion relative to the first direction; The third portion and the fifth portion each have the first thickness relative to the third party; The fourth part is located between the third part and the fifth part; The fourth portion has the second thickness relative to the third party; The third pseudo-structure and the fourth pseudo-structure are close to the metal wire relative to the second direction; The third pseudo-structure and the fourth pseudo-structure are substantially aligned with the fourth portion relative to the first direction; and The third pseudo-structure and the fourth pseudo-structure are located on opposite sides of the metal wire relative to the first direction.

8. The fusible structure according to claim 5, further comprising: Third pseudo-structure; and in: The second pseudo-structure and the third pseudo-structure are close to the metal wire relative to the second direction; Relative to the first direction, the first pseudo-structure is located on the side of the metal wire opposite to each of the second and third pseudo-structures; The first pseudo-structure is located at least partially between the second pseudo-structure and the third pseudo-structure relative to the second direction; and The first pseudo-structure, the second pseudo-structure, and the third pseudo-structure are at least partially aligned with the second portion of the metal wire relative to the first direction.

9. The fusible structure according to claim 1, wherein: The metal wire is located in the first metal layer; The first pseudo-structure is located in a second metal layer that is different from the first metal layer.

10. The fusible structure according to claim 1, further comprising: First contact pad; as well as Second contact pad; and in: The second portion is located between the first contact pad and the second contact pad relative to the first direction; The length is defined relative to the first direction from the first contact pad to the second contact pad; The width of the metal wire is defined relative to the second direction; The ratio is defined as the length divided by the width; and The ratio is in the range of 4 to 100.

11. The fusible structure according to claim 1, wherein: The width of the metal wire is defined relative to the second direction; The distance is defined relative to the second direction between the metal line and the first pseudo-structure; and The ratio is defined as the distance divided by the width; wherein the ratio is in the range between 0.1 and 100.

12. The fusible structure according to claim 1, further comprising: First contact pad; as well as Second contact pad; and in: The second portion is located between the first contact pad and the second contact pad relative to the first direction; The first length is defined as the length from the first contact pad to the second contact pad relative to the first direction; The second length of the first pseudo-structure is defined relative to the first direction; and The ratio is defined as the second length divided by the first length, wherein the ratio is in the range between 0.01 and 0.

99.

13. The fusible structure according to claim 1, wherein: The first length of the first pseudo-structure is defined relative to the first direction; The second length of the first pseudo-structure is defined relative to the second direction; The ratio is defined as the second length divided by the first length; and The ratio is in the range of 0.01 to 100.

14. The fusible structure according to claim 1, wherein: The length of the first pseudo-structure is limited relative to the second direction; The distance is defined relative to the second direction between the metal line and the first pseudo-structure; The ratio is defined as the length divided by the distance; and The ratio is in the range of 0.01 to 100.

15. A fusible structure comprising: Metal wire, extending along the first direction; as well as The first pseudo-structure is configured to be a first distance away from the metal wire relative to the second direction, wherein the second direction is perpendicular to the first direction; The second pseudo-structure, and the first pseudo-structure, are disposed on opposite sides of the metal wire relative to the first direction, and in: Relative to the first direction, the metal wire includes a first portion, a second portion, and a third portion, wherein the second portion is located between the first portion and the third portion; The first portion is thinner than the second portion relative to a third direction perpendicular to the first and second directions, wherein the third direction is perpendicular to the relative arrangement direction of the first pseudo-structure and the second pseudo-structure; The first part is divided by a first dividing line and a second dividing line. In the first direction, the first pseudo-structure and the second pseudo-structure are located between the first dividing line and the second dividing line and are respectively located on both sides of the first part, which is thinner than the second part.

16. The fusible structure according to claim 15, further comprising: First contact pad; Second contact pad; Third contact pad; Fourth contact pad; and in: Both the first contact pad and the second contact pad are substantially aligned with the first end of the metal line relative to the first direction; The first and second contact pads are located on opposite sides of the metal line relative to the first direction; the third and fourth contact pads are both substantially aligned with the second end of the metal line relative to the first direction, and The third contact pad and the fourth contact pad are located on opposite sides of the metal line relative to the first direction, and the first end of the metal line is opposite to the second end of the metal line.

17. The fusible structure according to claim 16, wherein: The first contact pad and the third contact pad are located on a first side of the metal line relative to the second direction; The second contact pad and the fourth contact pad are located on the second side of the metal line relative to the second direction; The second portion is located between the first contact pad and the third contact pad relative to the first direction; and The second portion is located between the second contact pad and the fourth contact pad relative to the first direction.

18. The fusible structure according to claim 16, wherein: The second portion of the metal wire and the first pseudo-structure have substantially the same width.

19. The fusible structure according to claim 16, wherein: The size of the gap between the first pseudo-structure and the metal wire is proportional to the thickness of the metal wire.

20. A method for manufacturing a fusible structure, the method comprising: Forming a metal wire extending along a first direction, the formation of the metal wire comprising: Configure the mask such that the metal line has a first portion, which is located between a second portion and a third portion; and Using optical proximity correction techniques and masks, the first portion is made thinner than each of the second and third portions in the thickness direction; and A first pseudo-structure and a second pseudo-structure are formed close to the metal wire and aligned with the first portion relative to the first direction. The second pseudo-structure and the first pseudo-structure are located on opposite sides of the metal wire relative to the first direction, wherein the thickness direction is perpendicular to the first direction and perpendicular to the relative arrangement direction of the first pseudo-structure and the second pseudo-structure. The first part is divided by a first dividing line and a second dividing line. In the first direction, the first pseudo-structure and the second pseudo-structure are located between the first dividing line and the second dividing line, and are respectively located on both sides of the first part, which is thinner than the second part and the third part.

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