Memory cell selection

Abstract

The present application relates to memory cell selection that enables a memory device to select a target memory cell during a write operation. The memory device may apply a first pulse to a selected bit line of the target memory cell while applying a voltage to a deselected word line to prevent current leakage. If the target memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word line. If the target memory cell is not selected after the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word line. If the target memory cell is selected, the memory device may detect a snapback event after any of the pulses.

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 037930, entitled “MEMORY CELL SELECTION,” filed by Hamada et al. on June 16, 2020, and claims priority to U.S. patent application No. 16 / 460,863, entitled “MEMORY CELL SELECTION,” filed by Hamada et al. on July 2, 2019, each of which is assigned to the present assignee and is incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to memory cell selection. Background Art

[0004] The following relates generally to a system including at least one memory device, and more particularly to memory cell selection.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states in the memory device. For example, binary devices most commonly store one of two states, typically represented by a logical 1 or a logical 0. Other devices can store more than two states. To access stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memory technologies, and the like. Memory devices can be volatile or non-volatile. Generally, improvements to memory devices can include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. In some memory devices, the memory cell selection scheme may not be able to select all desired sets of memory cells (e.g., for read or write operations), resulting in higher error rates. Summary of the Invention

[0007] A method is described. The method may include: applying a first pulse having a first voltage to a memory cell including a chalcogenide material during a selection process of a write operation; applying a second pulse having a second voltage higher than the first voltage to the memory cell based on the application of the first pulse; determining that the memory cell is unselected after applying the second pulse; applying a third pulse having the second voltage to the memory cell based on the determination that the memory cell is unselected after applying the second pulse; and selecting the memory cell for the write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell.

[0008] A device is described. The device may include: a memory cell array for storing information; and a controller coupled to the memory cell array and configured to cause the device to: apply a first pulse having a first voltage to a memory cell including a chalcogenide material during a selection process of a write operation; apply a second pulse having a second voltage higher than the first voltage to the memory cell based at least in part on the application of the first pulse; apply a third pulse having the second voltage to the memory cell based at least in part on the application of the second pulse; and select the memory cell for the write operation based at least in part on the application of the first pulse, the second pulse, and the third pulse to the memory cell.

[0009] Another apparatus is described. The apparatus may include a first tile of memory cells configured to: apply a first pulse to a first memory cell of the first tile during a first duration of a selection process; determine that the first memory cell is not selected after applying the first pulse; apply a second pulse to the first memory cell during a second duration of the selection process based at least in part on determining that the first memory cell is not selected after applying the first pulse; determine that the first memory cell is selected after applying the second pulse; and write a first logic state to the first memory cell based at least in part on determining that the first memory cell is selected. The device may further include a second tiled block of memory cells, configured to: apply the first pulse to a second memory cell of the second tiled block during the first duration of the selection process; determine that the second memory cell is not selected after applying the first pulse; apply the second pulse to the second memory cell during the second duration of the selection process based at least in part on determining that the second memory cell is not selected after applying the first pulse; determine that the second memory cell is not selected after applying the second pulse; apply a third pulse to the second memory cell during a third duration of the selection process based at least in part on determining that the second memory cell is not selected after applying the second pulse; and write a second logic state to the second memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a memory device supporting memory cell selection according to examples disclosed herein is shown.

[0011] Figure 2 An example of a memory device supporting memory cell selection according to examples disclosed herein is shown.

[0012] Figure 3 An example of a memory device supporting memory cell selection according to examples disclosed herein is shown.

[0013] Figure 4A and 4B Shown is an example of a timing diagram supporting memory cell selection according to examples disclosed herein.

[0014] Figure 5 Shown is an example of a graph supporting memory cell selection according to examples disclosed herein.

[0015] Figure 6 Shown is an example of a timing diagram supporting memory cell selection according to examples disclosed herein.

[0016] Figure 7 A block diagram illustrating a memory device supporting memory cell selection according to examples disclosed herein.

[0017] Figures 8 to 10 A flowchart illustrating one or more methods of supporting memory cell selection according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0018] A memory device may implement a selection process to select one or more target memory cells on one or more memory tiles as part of a write operation or other operation. For example, the target memory cell may be located at the intersection of a selected word line and a selected bit line. Other word lines may be referred to as deselected word lines. In some examples, the memory device may select the target memory cell by applying a first voltage pulse to the memory cell. Applying the first voltage pulse may include placing the selected word line at a lower voltage, maintaining the deselected word line at a constant voltage, and gradually changing the voltage of the selected bit line from the lower voltage to a first intermediate voltage over a period of time. In some cases, applying the constant voltage to the deselected word line may prevent selection of non-target memory cells, which may prevent current leakage from the selected bit line during the first voltage pulse. Preventing current leakage may allow a higher current to reach the target memory cell and may result in selection of the target memory cell. If the target memory cell is selected, it may "snap" or produce a snapback event that may be detected by the memory device after application of the first voltage pulse. If at any time a target memory cell is selected and a snapback event is detected, the memory device can continue with the write operation (eg, or other operations) on the selected memory cell.

[0019] The memory device may not detect the snapback event and may determine that the target memory cell is not selected. The memory device may apply a second voltage pulse to the selected bit line. Thus, the memory device may raise the selected bit line to a second, higher voltage, which may be referred to as a second voltage pulse, for a period of time. In some cases, the memory device may apply a different voltage, higher than the constant voltage, to the deselected word line to prevent current leakage. In some cases, the second voltage pulse may cause the target memory cell to be selected and a snapback event may occur. In other cases, applying the second voltage pulse may not cause the target memory cell to be selected. For example, current leakage may occur along the selected bit line, and the current reaching the target memory cell may be less than the current used to select the cell. In some instances, current leakage may occur based on multiple memory tiles sharing the voltage applied to the deselected word line, which may limit the voltage.

[0020] In the event that the target memory cell is not selected with the second voltage pulse, the memory device may apply a third voltage pulse after applying the second voltage pulse by raising the selected bit line to the second voltage for a period of time. The memory device may also apply a voltage to the deselected word line during the third voltage pulse to prevent current leakage. In some cases, the memory device may apply the voltage for the deselected word line to memory tiles having memory cells that have not yet been selected, where the number of memory tiles may be less than the number of tiles during the second pulse (e.g., because some memory cells may have been selected during the second pulse). Thus, more voltage is available for application to the deselected word line and thus reduces current leakage. Such action may increase the probability of selecting the target memory cell because some memory tiles may not have the third pulse applied and may reduce current leakage across the memory device. In such cases, sufficient current may reach the target memory cell during the third voltage pulse so that the memory device can select the target memory cell and write data to the target memory cell as part of a write operation.

[0021] First, in the reference Figure 1-2 Features of the present disclosure are described in the context of the memory device described. Figure 3-6 Features of the present disclosure are described in the context of the memory devices, graphs, and timing diagrams described. Figure 7-10 These and other features of the present disclosure are further illustrated and described with reference to the device diagrams and flow diagrams described that relate to memory cell selection.

[0022] Figure 1 An example memory arrangement 100 is shown according to an example of the present disclosure. The memory arrangement 100 may also be referred to as an electronic memory device. Figure 1 1 is an illustrative representation of the various components and features of the memory device 100. Thus, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships, rather than their actual physical locations within the memory device 100. Figure 1 In the illustrative example of FIG, a memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 can be programmable to store two states represented as logic 0 and logic 1. In some examples, the memory cell 105 can be configured to store more than two logic states. In some examples, the memory cell 105 can include a memory cell. Although Figure 1 Some elements contained in the drawings are labeled with numerical designators, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the depicted features.

[0023] The 3D memory array 102 may include two or more two-dimensional (2D) memory arrays 103 formed on top of each other. This may increase the number of memory cells that can be placed or produced on a single die or substrate compared to a 2D array, which in turn may reduce production costs or improve the performance of the memory device, or both. The memory array 102 may include two levels of memory cells 105 and may therefore be considered a 3D memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned so that the memory cells 105 may be aligned with each other (exactly aligned, overlapping, or approximately aligned) across each level, thereby forming a memory cell stack 145. In some cases, the memory cell stack 145 may include multiple memory cells located on top of each other and simultaneously sharing access lines for both, as explained below. In some cases, the memory cells may be multi-level memory cells configured to store more than one bit of data using multi-level storage technology.

[0024] In some examples, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. The term access line can refer to word lines 110, bit lines 115, or a combination thereof. Word lines 110 and bit lines 115 can be perpendicular to each other (or nearly so) and can create an array of memory cells. Figure 1 As shown, two memory cells 105 in a memory cell stack 145 can share a common conductive line, such as a bit line 115. That is, the bit line 115 can be in electronic communication with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations may be possible, for example, the third layer can share a word line 110 with the lower layer. Generally speaking, one memory cell 105 can be located at the intersection of two conductive lines, such as a word line 110 and a bit line 115. This intersection can be referred to as the address of the memory cell. A target memory cell 105 can be a memory cell 105 located at the intersection of an energized word line 110 and a bit line 115; that is, the word line 110 and the bit line 115 can be energized to allow the memory cell 105 to be read or written at their intersection. Other memory cells 105 that are in electronic communication with (e.g., connected to) the same word line 110 or bit line 115 can be referred to as non-target memory cells 105.

[0025] An electrode may be coupled to memory cell 105 and word line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. An electrode may include a trace, wire, conductive line, conductive layer, etc. that provides a conductive path between elements or components of memory device 100. In some examples, memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to word line 110, and the other side of the first electrode may be coupled to the chalcogenide material. Additionally, one side of the second electrode may be coupled to bit line 115, and the other side of the second electrode may be coupled to the chalcogenide material. The first electrode and the second electrode may be the same material (e.g., carbon) or different materials.

[0026] Operations such as reading and writing can be performed on memory cells 105 by activating or selecting word lines 110 and bit lines 115. In some examples, bit lines 115 may also be referred to as digit lines. References to access lines, word lines, and bit lines, or the like, may be interchanged without affecting understanding or operation. Activating or selecting word lines 110 or bit lines 115 may include applying a voltage to the respective lines. Word lines 110 and bit lines 115 may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductively doped semiconductors, or other conductive materials, alloys, compounds, and the like.

[0027] Access to memory cells 105 can be controlled by row decoder 120 and column decoder 130. For example, row decoder 120 can receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 can receive a column address from memory controller 140 and activate the appropriate bit line 115. For example, memory array 102 can include a plurality of word lines 110 labeled WL_1 through WL_M and a plurality of bit lines 115 labeled BL_1 through BL_N, where M and N depend on the array size. Thus, by activating a word line 110 and a bit line 115, such as WL_2 and BL_3, the memory cell 105 at their intersection can be accessed.

[0028] After access, memory cell 105 can be read or sensed by sensing component 125 to determine the stored state of memory cell 105. For example, a voltage can be applied to memory cell 105 (using corresponding word line 110 and bit line 115), and the presence of the resulting current can depend on the applied voltage and the threshold voltage of memory cell 105. In some cases, more than one voltage can be applied. Furthermore, if the applied voltage does not cause current to flow, other voltages can be applied until sensing component 125 detects current. By evaluating the voltage that causes current to flow, the stored logic state of memory cell 105 can be determined. In some cases, the magnitude of the voltage can be ramped until current is detected. In other cases, predetermined voltages can be applied sequentially until current is detected. Similarly, current can be applied to memory cell 105, and the magnitude of the voltage used to generate the current can depend on the resistance or threshold voltage of memory cell 105.

[0029] In some examples, memory cell 105, which may include a memory storage element, can be programmed by applying an electrical pulse to the cell. The pulse can be applied via a first access line (e.g., word line 110) or a second access line (e.g., bit line 115), or a combination thereof. In some cases, after applying the pulse, ions can migrate within the memory storage element depending on the polarity of memory cell 105. Thus, the concentration of ions relative to the first or second side of the memory storage element can be based at least in part on the polarity of the voltage between the first access line and the second access line. In some cases, asymmetrically shaped memory storage elements can cause ions to be more crowded in portions of the element with more area. Certain portions of the memory storage element may have a higher resistivity and, therefore, may produce a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism for self-selecting memory cells to achieve the results described herein. This example of a mechanism should not be considered limiting.

[0030] The sensing component 125 may include various transistors or amplifiers to detect and amplify signal differences, which may be referred to as latches. The detected logic state of the memory cell 105 may then be output as output 135 by the column decoder 130. In some cases, the sensing component 125 may be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120. The sensing component may be associated with either the column decoder or the row decoder.

[0031] The memory cell 105 can be set or written by activating (e.g., selecting) the associated word line 110 and bit line 115, and at least one logic value can be stored in the memory cell 105. The column decoder 130 or the row decoder 120 can accept data to be written to the memory cell 105, such as the input / output 135. In some cases, the memory cell 105 can be written to store data by applying a first pulse, a second pulse, and a third pulse to the memory cell 105 after the memory cell 105 is selected. Figure 3-6 Describe this process in more detail.

[0032] The memory controller 140 can control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of the memory cell 105 through various components such as the row decoder 120, the column decoder 130, and the sensing component 125. In some cases, one or more of the row decoder 120, the column decoder 130, and the sensing component 125 can be co-located with the memory controller 140. The memory controller 140 can generate row address signals and column address signals to activate the desired word line 110 and bit line 115. The memory controller 140 can also generate or control various voltages or currents used during the operation of the memory device 100.

[0033] The memory controller 140 can be configured to perform a write operation of the programmable memory cell. For example, the memory controller 140 can be configured to apply a first pulse to the memory cell 105 during a select operation. In some examples, applying the first pulse can include applying a voltage to a first access line (e.g., to the word line 110), applying a first voltage to a second access line (e.g., the bit line 115), and applying a constant voltage to a set of access lines (e.g., unselected word lines 110). The memory controller 140 can be configured to detect a snapback event at the memory cell 105 in response to selecting the memory cell 105 after applying the first pulse. The snapback event can, for example, cause the threshold voltage of the memory cell 105 to decrease.

[0034] In some examples, the memory controller 140 may apply a second pulse to the memory cell 105 in response to failing to detect a snapback event (e.g., failing to select the memory cell 105). Applying the second pulse may include applying a second voltage to a second access line (e.g., to the bit line 115) and applying a third voltage to the set of access lines (e.g., the unselected word lines 110). The memory controller 140 may be configured to detect a snapback event at the memory cell 105 in response to applying the second pulse. In some examples, the memory controller 140 may apply a third pulse to the memory cell 105 in response to failing to detect a snapback event in order to select the memory cell 105. Applying the third pulse may include applying the second voltage to the second access line (e.g., to the bit line 115) and applying a fourth voltage to the set of access lines (e.g., the unselected word lines 110).

[0035] In some examples, the memory controller 140 can be configured to perform a write operation on the selected memory cell 105. During the write operation, the memory controller 140 can apply different pulses having different polarities to the memory cell 105 to store a logic state in the memory cell 105. As described above, the logic state stored on the memory cell 105 can be detected during a snapback event. In such an example, the memory controller 140 can store a second logic state in the memory cell 105, where the second logic state can be different from the first logic state detected as stored in the memory cell 105.

[0036] Figure 2 An example of a memory device 200 supporting memory cell selection according to aspects of the present disclosure is shown. The memory device 200 may be a reference Figure 1 1. An example of a portion of a memory array 102 is depicted. Memory device 200 can include a first array or stack 205 of memory cells positioned above substrate 204 and a second array or stack 210 of memory cells positioned on top of first array or stack 205. Memory device 200 can also include word lines 110-a and word lines 110-b and bit lines 115-a, which can be examples of word lines 110 and bit lines 115, as described with reference to FIG. Figure 1 The memory cells of the first and second stacks 205 and 210 may each have one or more memory cells (eg, memory cell 220 - a and memory cell 220 - b , respectively). Figure 2 Some elements contained in the drawings are labeled with numerical designators, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the depicted features.

[0037] The memory cells of the first stack 205 may include a first electrode 215-a, a memory cell 220-a (e.g., a chalcogenide material), and a second electrode 225-a. Additionally, the memory cells of the second stack 210 may include a first electrode 215-b, a memory cell 220-b (e.g., a chalcogenide material), and a second electrode 225-b. In some examples, the memory cells of the first stack 205 and the second stack 210 may have a common conductive line, such that corresponding memory cells of each stack 205 and 210 may share a bit line 115 or a word line 110, as described with reference to FIG. Figure 1 For example, first electrode 215-b of second stack 210 and second electrode 225-a of first stack 205 can be coupled to bit line 115-a so that bit line 115-a is shared by vertically adjacent memory cells. In some cases, memory cell 220 can be an example of a phase change memory cell or a self-select memory cell.

[0038] In some cases, the architecture of memory device 200 may be referred to as a cross-point architecture, where memory cells are formed at topological intersections between word lines and bit lines, such as Figure 2 As shown. This cross-point architecture can provide relatively high-density data storage at a lower production cost than other memory architectures. For example, the cross-point architecture can have memory cells with a reduced area compared to other architectures and, therefore, an increased memory cell density compared to other architectures. For example, the architecture can have a memory cell area of 4F2, where F is the minimum feature size, compared to other architectures, such as those with three-terminal select components, which have a memory cell area of 6F2. For example, a DRAM can use a transistor that is a three-terminal device as the select component of each memory cell and can have a larger memory cell area than a cross-point architecture.

[0039] Although Figure 2 The example of FIG200 shows two memory stacks, but other configurations are possible. In some examples, a single memory stack of memory cells can be constructed above substrate 204, which can be referred to as a two-dimensional memory. In some examples, three or four memory stacks of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture.

[0040] In some examples, one or more of the memory stacks may include memory cells 220 comprising a chalcogenide material. Memory cells 220 may, for example, comprise chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some examples, SAG alloys may include silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some examples, chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each of which may be in atomic or molecular form.

[0041] In some examples, a memory cell 220 comprising a chalcogenide material can be programmed to a logic state during a write operation. By way of example, when a particular memory cell 220 is programmed, components within the cell separate, causing ion migration. Depending on the polarity of the pulse applied to the memory cell, the ions may migrate toward a particular electrode. For example, in memory cell 220, the ions may migrate toward the negative electrode. The memory cell can then be read for sensing by applying a voltage across the cell. The threshold voltage observed during a read operation may depend on the distribution of ions in the memory cell and the polarity of the read pulse. For example, if a memory cell has a given ion distribution, the threshold voltage detected during a read operation may be different for a first read pulse having a first polarity than for a second read pulse having a second polarity. Depending on the polarity of the memory cell, this concentration of migrating ions may represent a logic "1" or logic "0" state. This description of ion migration represents an example of a mechanism for a memory cell to achieve the results described herein. This example of a mechanism should not be considered limiting.

[0042] Prior to programming, a memory cell 220 may be selected to perform a write operation. In some cases, a memory device (e.g., a memory array, a memory controller, etc.) may implement a selection process to select one or more target memory cells 220 on one or more memory tiles. For example, a target memory cell 220 may be located at the intersection of two access lines (e.g., a selected word line 110 and a selected bit line 115). Other word lines (e.g., other than the selected word line) may be referred to as deselected word lines 110. In some examples, the memory device may select the target memory cell 220 by applying a first voltage pulse to the selected bit line 115 while maintaining the deselected word line 110 at a constant voltage. In some cases, applying a constant voltage to the deselected word line 110 may prevent selection of non-target memory cells 220, which may prevent current leakage from the selected bit line 115 during the first voltage pulse. If a target memory cell 220 is selected, it may "snap" or generate a snapback event that may be detected by the memory device after application of the first voltage pulse. If a target memory cell 220 is selected at any time and a snapback event is detected, the memory device may continue to perform a write operation (e.g., or other operation) on the selected memory cell 220.

[0043] In some cases, the memory device may not detect the snapback event and may determine that the target memory cell 220 is not selected. Therefore, the memory device may apply a second voltage pulse to the selected bit line 115 while applying a different voltage, higher than the constant voltage, to the deselected word line 110 to prevent current leakage. In some cases, applying the second voltage pulse may not result in the selection of the target memory cell 220. For example, current leakage may occur along the selected bit line 115, where the current leakage may occur based on multiple memory tiles sharing the voltage applied to the deselected word line 110, which may limit the voltage.

[0044] To increase the probability of selecting the target memory cell 220, the memory device may apply a third voltage pulse to the selected bit line 115 and may apply a voltage to the deselected word line 110 to prevent current leakage. In some cases, the memory device may apply the voltage for the deselected word line 110 to memory tiles having memory cells 220 that have not yet been selected, where the number of memory tiles may be smaller than the number of tiles during the second pulse (e.g., because some memory cells 220 may have already been selected during the second pulse). As a result, more voltage is available to apply to the deselected word line 110 and thus prevent current leakage. Therefore, in some cases, sufficient current may reach the target memory cell 220 during the third voltage pulse so that the memory device can select the target memory cell 220 and write data to the cell as part of a write operation.

[0045] Figure 3 An example of a memory device 300 supporting memory cell selection according to aspects of the present disclosure is shown. The memory device 300 may include word lines 110, bit lines 115, and a memory cell array (e.g., including memory cell 305 and memory cell 310). In some examples, the memory device 300 may be an example of a cross-point architecture, a pillar architecture, or a planar architecture. The memory device 300 may be as described in reference to FIG. Figure 2 In some cases, the memory device 300 may be implemented as described with reference to Figure 1 and 2 The memory cell selection process as part of a write operation is described.

[0046] The memory device 300 may implement a selection process to select one or more memory cells 305 on one or more memory tiles, wherein one of the memory cells 305 may be located at the intersection of a word line 110-c and a bit line 115-c. In some cases, the word line 110-c and the bit line 115-c may additionally or alternatively be referred to as a selected word line 110-c and a selected bit line 115-c. Other word lines 110 (e.g., word lines 110-a, 110-b, and 110-d) may be referred to as unselected word lines 110 or deselected word lines 110, while other bit lines 115 (e.g., bit lines 115-a, 115-b, and 115-d) may be referred to as unselected bit lines 115 or deselected bit lines 115.

[0047] In some examples, the memory device 300 can select the memory cell 305 by placing the selected word line 110-c at a lower voltage, maintaining the deselected word line 110 at a constant voltage (e.g., a constant bias), and slowly changing the voltage of the bit line 115-c from the lower voltage (e.g., the lower bias) to a first intermediate voltage (e.g., the intermediate bias) over a period of time, which can be referred to as a first voltage pulse. In some cases, applying a constant voltage to the deselected word line 110 can prevent the memory cell 310 from being selected during the voltage pulse (e.g., the first voltage pulse) to the bit line 115-c. For example, the constant voltage can reduce the bias across the memory cell 310 so that the memory cell 310 can be selected without the voltage pulse. Thus, applying a constant voltage to the deselected word line 110 can prevent current from leaking 315 from the bit line 115-c during the first voltage pulse, where the current leakage 315 can pass through the memory cell 310 and along the deselected word line 110. Preventing current leakage may allow a stronger current to reach the memory cell 305 and may cause the memory cell 305 to be selected.

[0048] In some cases, the first voltage pulse to bit line 115-c may cause memory cell 305 to be selected (e.g., if memory cell 305 has a lower voltage threshold based on the stored logic state). Thus, if memory cell 305 is selected, memory cell 305 may "snap" or generate a reference voltage after application of the first voltage pulse. Figure 4A and 4B The snapback event described.

[0049] If memory cell 305 is selected and a snapback event occurs, memory device 300 may detect the snapback event (e.g., via dedicated circuitry) and may determine that memory cell 305 is selected. Thus, memory device 300 may proceed with a write operation, which may include writing to selected memory cell 305. In some cases, applying the first voltage pulse to bit line 115-c may not result in selection of memory cell 305 or an associated snapback event (e.g., where memory cell 305 has a higher voltage threshold based on the stored logic state). Thus, memory device 300 may not detect the snapback event (e.g., via dedicated circuitry), may determine that memory cell 305 is not selected, and may determine to apply the second voltage pulse to bit line 115-c.

[0050] As part of applying the second voltage pulse, the memory device 300 may raise the bit line 115-c to a second, higher voltage (e.g., a bias voltage) for a period of time. During at least a portion of the second voltage pulse, the memory device 300 may apply a different voltage, higher than the constant voltage, to the unselected word lines 110 to prevent current leakage 315 along the unselected word lines 110. In some cases, the second voltage pulse to the bit line 115-c may cause the memory cell 305 to be selected, and the memory cell 305 may generate a snapback event that can be detected by the memory device 300 (e.g., via dedicated circuitry). As a result, the memory device 300 may continue with a write operation that may include writing to the selected memory cell 305.

[0051] In some cases, applying the second voltage pulse to bit line 115-c may not select memory cell 305 or produce a related snapback event. For example, current leakage 315 may occur along bit line 115-c, and the current reaching memory cell 305 may be less than the current used to select memory cell 305. In some instances, current leakage 315 may occur if the voltage applied to the unselected word lines 110 is insufficient to prevent the memory cell 310 from being selected. In some cases, the voltage applied to the unselected word lines 110 may be shared among one or more tiles of selected memory cells 305, which may limit the voltage applied to the unselected word lines 110 in each tile. For example, a certain amount of the total voltage available to the memory device 300 for application to the unselected word lines 110 may be shared or split among tiles of unselected word lines 110. Thus, some tiles of selected memory cells 305 may not be able to apply a voltage sufficient to prevent the selection of memory cells 310, which may result in current leakage 315 from the memory cells 310 and, therefore, insufficient current for selecting the memory cells 305. In one example, applying a voltage to reduce the current leakage 315 may be effective at a voltage greater than or equal to 400 millivolts (mV). Therefore, applying a voltage greater than or equal to 400 mV to the memory tiles of the unselected word lines 110 may prevent the current leakage 315.

[0052] In the event that memory cell 305 is not selected, memory device 300 may not detect the snapback event (e.g., via dedicated circuitry) and may determine that memory cell 305 is not selected. Some memory systems may increase the time for applying the second voltage pulse to address this issue and select memory cell 305, but this approach may be limited by the amount of current available for delivery to distant memory cells (e.g., memory cells at or near the end of the conductive path of the power delivery network).

[0053] To increase the probability of selecting memory cell 305 during the selection process for all tiles, memory device 300 may apply a third voltage pulse by raising bit line 115-c to the second voltage for a period of time after applying the second voltage pulse. Memory device 300 may also apply a voltage to unselected word lines 110 during the third voltage pulse to prevent current leakage 315 along the unselected word lines 110. In some cases, memory device 300 may apply the voltage for unselected word lines 110 to memory tiles having memory cells 305 that have not yet been selected, where the number of memory tiles may be smaller than the number of tiles during the second pulse (e.g., because some memory cells 305 may have already been selected during the second pulse). Thus, more voltage is available for memory device 300 to apply to unselected word lines 110 and thus prevent current leakage 315. Consequently, in some cases, sufficient current may reach memory cell 305 during the third voltage pulse so that memory device 300 can select memory cell 305 and write data to memory cell 305 as part of a write operation.

[0054] In some cases, applying the third pulse can reduce the bit error rate associated with memory cell 305, particularly where memory cell 305 is located further away from a power supply of memory device 300. For example, the third pulse can select memory cell 305 where the first and second pulses might not have been able to do so. Thus, as part of a write operation, memory device 300 can write data to memory cell 305 and can reduce the bit error rate associated with memory cell 305.

[0055] Figure 4A and 4B Examples of timing diagrams 405 and 410 supporting memory cell selection according to examples of the present disclosure are shown. A memory cell can be configured to store a specific logic state based on one or more pulses applied to the cell. The voltage distribution within the memory cell can depict the logic states that can be stored in the memory cell.

[0056] The memory cell may include a reference Figure 1 and 2The chalcogenide material described herein. A threshold voltage distribution may represent various logical states of the memory cell during a write operation, such as during a select portion of the write operation. By applying a voltage pulse to the memory cell, a snapback event may occur. The snapback event may be characterized by a reduction in the threshold voltage distribution associated with the logical state. In other words, by applying a first pulse to the memory cell, the threshold voltage distribution associated with the logical state may shift (e.g., toward zero voltage). When a snapback event occurs, the voltage distribution may shift to near zero voltage for a duration. After the sudden shift, the voltage distribution may relax back to its original position.

[0057] Figure 4A The timing diagram 405 may depict a write operation of a memory cell. The timing diagram 405 may show a first pulse (e.g., represented by a voltage difference between access lines). The timing diagram 405 may also depict an access line (e.g., as shown in FIG. 4B ). Figure 1 The voltage 425 of the bit line 115 as described, and the voltage of the access line (eg, as referenced) measured from ground Figure 1 In some cases, the first pulse 435 and / or its component voltages 425 and 430 may represent a reference voltage. Figure 3 Any of the described first pulse, second pulse, or third pulse.To perform a select operation on a memory cell, a first voltage 425 may be applied to one access line, and a second voltage 430 may be applied to a second access line.

[0058] The memory cell associated with timing diagram 405 can store a first logic state (eg, logic "0"). As described above with reference to Figure 3 As described, to write a second logic state (e.g., logic "1") to a memory cell, a first pulse 435 may be applied to the memory cell. The first pulse 435 may be configured such that a snapback event occurs when the memory cell is selected, but does not occur when the memory cell is not selected. In some cases, a snapback event may occur if an amount of current reaches the memory cell, wherein the amount of current required to cause snapback may be based on a voltage threshold of the memory cell (e.g., associated with a logic state stored in the memory cell).

[0059] After applying the first pulse 435, a snapback event may occur, which can be described by reducing the threshold voltage distribution of the memory cells. In some examples, the snapback event may be generated by a memory controller (e.g., as described in reference to FIG. Figure 1 The memory controller 140 described herein or dedicated circuitry detects a snapback event. A snapback event may cause a threshold voltage associated with a memory cell to decrease. In some cases, a snapback event may cause the magnitude of the first pulse to decrease, as shown by first pulse 435-a.

[0060] A snapback event may occur for a fixed duration and may be followed by a period (e.g., duration 447) during which the memory cell remains in a higher conductivity state. This higher conductivity state may be referred to as a select time. To write a logic value (e.g., a logic "1") to the memory cell, a second pulse 440 may be applied.

[0061] In some examples, the second pulse 440 may not be applied during the selection time or duration 447 (e.g., because no snapback event is detected and / or no cell is selected for a write operation). As a result, the threshold voltage of the memory cell may increase to its original level. For example, in the context of timing diagram 405, if the second pulse 440 is not applied during the duration 447, the threshold voltage of the memory cell may increase to the voltage value depicted before the duration 447. In some examples, the memory cell may be selected after the duration 447 by applying a voltage that is higher than the original threshold voltage of the memory cell. For example, similar to reference 405, the threshold voltage of the memory cell may be increased to its original level. Figure 3 The voltage pulse is applied as described for the second pulse or the third pulse.

[0062] Figure 4B The timing diagram 410 may depict a portion of a write operation to a memory cell, such as a selected portion of a write operation. The timing diagram 410 may show a first pulse 445 applied to the memory cell, which may be a reference pulse. Figure 3 The timing diagram 410 may also depict access lines (e.g., as referenced in FIG. Figure 1 15) and a voltage 430-b of a second access line (eg, word line 110) are depicted.

[0063] The memory cells associated with timing diagram 410 may store a logic state (eg, logic "0"). As described above with reference to Figure 3 As described, to write a logic state (e.g., a logic "0") to the memory cell, a first pulse 445 may be applied to the memory cell. Thus, the first pulse 445 may be applied to the cell. As described above, when the memory cell stores a first logic state (e.g., a logic "1"), a snapback event may occur when a pulse is applied to the memory cell as part of a write operation.

[0064] If a sufficient amount of current fails to reach the memory cell during the first pulse, a snapback event may not occur. Therefore, as shown in timing diagram 410, no snapback event occurs, and the write operation (e.g., an attempted write operation) may continue by applying one or more additional pulses to attempt to select the memory cell and detect a snapback event. For example, similar to reference 410, a snapback event may be detected. Figure 3The absence of a snapback event can be detected (eg, at a memory controller or dedicated circuit) by not seeing a decrease in the magnitude of the first pulse 445 .

[0065] Figure 5 An example of a graph 500 supporting memory cell selection according to examples disclosed herein is shown. Graph 500 may include examples of voltages applied to one or more deselected word lines, as shown in FIG. Figure 3 In some cases, the graph 500 may represent the application of, for example, reference to Figure 2 and 3 The voltages depicted in graph 500 may be applied during a selection process as part of a write operation, as described with reference to FIG. Figure 1-3 described.

[0066] Graph 500 may represent voltages 515 applied to one or more deselected word lines when the word lines are deselected simultaneously across a small number of tiles (e.g., one tile). Similarly, graph 500 may represent voltages 510 and 505 applied to one or more deselected word lines when the word lines are deselected for an intermediate number of tiles (e.g., 16 tiles) and a larger number of tiles (e.g., 128 tiles), respectively. In some cases, the voltage applied to the deselected word lines may be shared among one or more tiles that select memory cells, which may limit the voltage applied to the deselected word lines in each tile. For example, a certain amount of total voltage may be available to the memory device for application to the deselected word lines, such that the memory device may share or split the voltage among the tiles that deselect the word lines.

[0067] For example, as mentioned above Figure 3 As described, the voltage applied to one or more deselected word lines may be power-limited, such that applying the voltage to a greater number of tiles (e.g., sharing the voltage between a greater number of tiles) may reduce the voltage delivered to the deselected word lines in each tile. For example, voltage 515 may represent a higher voltage that may be applied to the deselected word lines when the word lines are deselected simultaneously across a smaller number of tiles (e.g., one tile). Similarly, voltage 510 may represent an intermediate voltage that may be applied to the deselected word lines when the word lines are deselected simultaneously across an intermediate number of tiles (e.g., 16 tiles). Furthermore, voltage 505 may represent a lower voltage that may be applied to the deselected word lines when the word lines are deselected simultaneously across a greater number of tiles (e.g., 128 tiles).

[0068] In some cases, applying a lower voltage to the deselected word lines can cause one or more target memory cells to remain unselected during one or more pulses of the select portion of the write operation, as shown in FIG. Figure 3 As described above (e.g., due to current leakage along the deselected word line). Thus, the memory device may apply an additional (e.g., third) pulse during a select operation while supplying voltage to the deselected word line. In some cases, the voltage may be applied to the deselected word line within a segment where one or more target memory cells remain unselected. Thus, the number of tiles using the deselect voltage may be reduced, and the voltage available for application to the deselected word line may be increased. Increasing the voltage supplied to the deselected word line may result in a reduction in current leakage along the deselected word line and selection of one or more unselected target memory cells.

[0069] In one example, a memory device may apply a first pulse and a second pulse to a plurality of bit lines in order to select target memory cells across a larger number of tiles. During the second pulse, the device may apply a voltage 505 to deselected word lines across the plurality of tiles. In some cases, some of the target memory cells may be selected and some may not be selected (e.g., due to current leakage along the deselected word lines). Therefore, the device may apply a third pulse to the bit lines in order to select any unselected target cells (e.g., across a smaller number of tiles) and may apply a voltage 510 to the deselected word lines across the smaller number of tiles. In some cases, the voltage 510 may be applied to the word lines in the tiles containing the unselected target cells and not to the word lines in the other tiles, thereby generating a higher available voltage 510 to apply to the deselected word lines. Increasing the voltage supplied to the deselected word lines may result in reduced current leakage along the deselected word lines and selection of one or more unselected target memory cells.

[0070] In a second example, the memory device may apply a first pulse and a second pulse to multiple bit lines to select target memory cells across a larger number of tiles. During the second pulse, the device may apply a voltage 505 to deselected word lines across the multiple tiles. In some cases, some of the target memory cells may be selected, and some may not be selected (e.g., due to current leakage along the deselected word lines). Therefore, the device may apply a third pulse to the bit lines to select any unselected target cells (e.g., across a smaller number of tiles), and may apply a voltage 515 to the deselected word lines across the smaller number of tiles. In some cases, the voltage 515 may be applied to the word lines in the tiles containing the unselected target cells and not to the word lines in other tiles, thereby resulting in a higher available voltage 515 to apply to the deselected word lines. Increasing the voltage supplied to the deselected word lines may result in reduced current leakage along the deselected word lines and selection of one or more unselected target memory cells.

[0071] Figure 6 An example of a timing diagram 600 supporting memory cell selection according to examples disclosed herein is shown. The timing diagram 600 illustrates a process during a write operation, such as a select portion of a write operation. The select operation may correspond to a time period between t1 and t7, including a first phase 625 through a sixth phase 650. The write operation may correspond to a time period between t7 and t8, including a seventh phase 655. The timing diagram 600 illustrates a process similar to that described in reference to FIG. Figure 3 Various voltage levels associated with components of the memory device 300 are described, which may illustrate a technique for memory cell selection of one or more target memory cells in one or more memory tiles. The timing diagram may include a third voltage pulse 670 to increase the probability of selecting the target memory cell. The timing diagram 600 includes a voltage applied to a selected bit line 115-c (e.g., a bit line voltage (VBL) 615) and a voltage applied to an unselected word line 110 (e.g., an unselected word line voltage (VUWL) 610), where the selected bit line 115-c and the unselected word line 110 may correspond to portions of the memory device 300.

[0072] During an initial phase 620 (e.g., beginning at t0), which may also be referred to as an idle period, the selected bit line 115-c and the unselected word line 110 may be maintained at a constant voltage. In other words, the VUWL 610 and the VBL 615 may be maintained at a constant voltage. In some cases, the constant voltage may be zero volts, a positive voltage, or a negative voltage, and the constant voltage may be different for the VUWL 610 and the VBL 615. The initial phase may represent the time before a write operation and a corresponding select operation begin.

[0073] At t1, a first phase 625 may begin, which may include a first voltage pulse 660. VUWL 610 may be maintained at a constant voltage (e.g., the same constant voltage as during the initial phase 620) in order to prevent selection of non-target memory cells and corresponding current leakage along unselected word lines 110, as described with reference to FIG. Figure 3 As described above. The VBL 615 may be ramped up (e.g., using a stepped voltage ramp) from a constant voltage in the initial phase 620 to a first intermediate voltage (e.g., a first select voltage (VSEL, 1)) for a period of time that may be referred to as a first voltage pulse 660. The VBL 615 may be allowed to settle back to a lower voltage, a snap-back voltage (VSNAP), in order to detect a selected memory cell using a snap-back detection process. In some cases, the first voltage pulse 660 may cause a target memory cell to be selected (e.g., if the target memory cell has a lower voltage threshold based on its stored logic state). If the target memory cell is selected, it may be "snapped" or generate a reference voltage. Figure 4A and 4B The sudden return event discussed.

[0074] Thus, at time t2, VBL 615 may reach VSNAP, and if the target memory cell is selected, the memory device 300 may detect a snapback event (e.g., via dedicated circuitry) during the second phase 630 and may determine that the target memory cell is selected. In some cases, applying the first voltage pulse 660 may not select the target memory cell or generate an associated snapback event (e.g., if the target memory cell has a higher voltage threshold based on its stored logic state). Thus, the memory device 300 may not detect a snapback event (e.g., via dedicated circuitry) during the second phase 630 and may determine to apply the second voltage pulse 665 to the bit line 115-c during the third phase 635.

[0075] At t3, a third phase 635 may begin that may include a second voltage pulse 665. VUWL 610 may be raised to a voltage (e.g., a first unselect voltage (VUSEL,1)) to prevent selection of non-target memory cells and corresponding current leakage along unselected word lines 110, as described with reference to FIG. Figure 3As discussed above. In some cases, VUSEL,1 may represent the voltage applied to unselected word lines 110 in one memory tile and may represent the voltage applied to unselected word lines 110 in one or more memory tiles containing a target memory cell. VBL 615 may be raised to a second voltage (e.g., a second select voltage (VSEL,2)) for a period of time that may be referred to as a second voltage pulse 665. VBL 615 may be allowed to settle back to a lower voltage, VSNAP, in order to detect the selected memory cell using a snapback detection process. In some cases, the second voltage pulse 665 may cause the target memory cell to be selected. If the target memory cell is selected, it may be "snapped" or generate a reference voltage. Figure 4A and 4B The sudden return event discussed.

[0076] Thus, at t4, VBL 615 may relax to VSNAP, and if the target memory cell is selected, the memory device 300 may detect a snapback event (e.g., via dedicated circuitry) during the fourth phase 640 and may determine that the target memory cell is selected. In some cases, applying the second voltage pulse 665 may not select the target memory cell or generate an associated snapback event (e.g., in the event of current leakage). Thus, the memory device 300 may not detect a snapback event (e.g., via dedicated circuitry) during the fourth phase 640 and may determine to apply the third voltage pulse 670 to the bit line 115-c during the fifth phase 645.

[0077] At t5, a fifth phase 645 may begin that may include a third voltage pulse 670. VUWL 610 may be raised to a voltage (e.g., a second unselect voltage (VUSEL,2)) to prevent selection of non-target memory cells and corresponding current leakage along unselected word lines 110, as described with reference to FIG. Figure 3 In some cases, VUSEL,2 can be applied to unselected word lines 110 in memory tiles containing target memory cells that have not yet been selected, where the number of memory tiles may be less than the number of tiles during the third phase 635 (e.g., because some target memory cells may have already been selected during the third phase 635). Thus, more voltage is available for application to VUWL 610, and VUSEL,2 can be higher than VUSEL,1, and further current leakage during the fifth phase 645 can be prevented.

[0078] During the fifth phase 645, VBL 615 may be raised to a second voltage (e.g., a second select voltage (VSEL,2)) for a period of time that may be referred to as a third voltage pulse 670. VBL 615 may be allowed to settle back to a lower voltage, VSNAP, to detect the selected memory cell using a snapback detection process. In some cases, the second voltage pulse 665 may cause the target memory cell to be selected. If the target memory cell is selected, it may be "snapped" or generate a reference voltage. Figure 4A and 4B The sudden return event discussed.

[0079] At t6, VBL 615 can reach VSNAP, and if the target memory cell is selected, the memory device 300 can detect a snapback event and can determine that the target memory cell is selected during a sixth stage 650. In some cases, sufficient current can reach the target memory cell during the third voltage pulse 670 so that the target memory cell can be selected, thereby reducing the bit error rate associated with the target memory cell.

[0080] Thus, at t7, the seventh stage 655 may include ending the select operation and starting a write operation to write data to the target memory cell and any other target memory cells in other memory tiles.

[0081] Figure 7 A block diagram 700 is shown of a memory device 705 that supports memory cell selection according to examples disclosed herein. The memory device 705 may be a memory device 705 as described in reference to FIG. Figure 1-3 Memory device 705 may include a write operation component 710, a first pulse component 715, a second pulse component 720, a selection determination component 725, a third pulse component 730, a memory cell selection component 735, and a deselection component 740. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0082] The write operation component 710 can write a logic state to a memory cell based on selecting the memory cell for the write operation.

[0083] The first pulse component 715 may apply a first pulse having a first voltage to a memory cell including a chalcogenide material during a selection process of a write operation.

[0084] The second pulse component 720 may apply a second pulse having a second voltage higher than the first voltage to the memory cell based on applying the first pulse.

[0085] The selection determination component 725 may determine that the memory cell is not selected after applying the second pulse. In some examples, the selection determination component 725 may determine whether a snapback event has occurred at the memory cell. In some examples, the selection determination component 725 may determine that the memory cell is not selected after applying the first pulse, wherein applying the second pulse is based on determining that the memory cell is not selected. In some examples, the selection determination component 725 may determine whether a snapback event has occurred at the memory cell.

[0086] The third pulse component 730 can apply a third pulse having a second voltage to the memory cell based on a determination that the memory cell was not selected after applying the second pulse. In some cases, the third pulse reduces a bit error rate of the memory cell. In some cases, the memory device includes a set of tiles, and the memory cell is part of a first tile of the set. In some cases, a first number of tiles to which the second pulse is applied during the selection process is greater than a second number of tiles to which the third pulse is applied during the selection process.

[0087] The memory cell selection component 735 may select a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell.

[0088] The deselection component 740 can deselect the second memory cell, which is coupled to the digit line, during at least a portion of the third pulse. In some examples, the deselection component 740 can apply a fourth pulse to the word line coupled to the second memory cell, the fourth pulse having a third voltage configured to reduce a voltage difference across the second memory cell during a portion of the third pulse.

[0089] Figure 8 1 is a flow chart illustrating one or more methods 800 for supporting memory cell selection according to aspects of the present disclosure. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the method 800 may be implemented by a memory device or components thereof as described herein. Figure 7 The described memory device performs the operations of method 800. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0090] At 805, during a selection process of a write operation, a memory device applies a first pulse having a first voltage to a memory cell including a chalcogenide material. The operation of 805 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a first pulse having a first voltage. Figure 7 Aspects of the operations of 805 are performed by the first pulse component as described.

[0091] At 810, the memory device may apply a second pulse having a second voltage higher than the first voltage to the memory cell based on applying the first pulse. The operation of 810 may be performed according to the methods described herein. In some examples, the reference Figure 7 A second pulse component is described to perform aspects of the operation of 810.

[0092] At 815, the memory device may determine that the memory cell is not selected after applying the second pulse. The operation of 815 may be performed according to the methods described herein. In some examples, the memory cell may be selected by reference to Figure 7 The selection determines the components to perform aspects of the operations of 815 as described.

[0093] At 820, the memory device may apply a third pulse having a second voltage to the memory cell based on determining that the memory cell is not selected after applying the second pulse. The operation of 820 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a second voltage. Figure 7 A third pulse component is described to perform aspects of the operation of 820.

[0094] At 825, the memory device may select a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell. The operation of 825 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell. Figure 7 The described memory cell selection component performs aspects of the operation of 825 .

[0095] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a first pulse to a memory cell including a chalcogenide material during a selection process of a write operation, the first pulse having a first voltage, applying a second pulse having a second voltage higher than the first voltage to the memory cell based on applying the first pulse, determining that the memory cell is unselected after applying the second pulse, applying a third pulse having a second voltage to the memory cell based on determining that the memory cell is unselected after applying the second pulse, and selecting the memory cell for the write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell.

[0096] In some examples of the method 800 and apparatus described herein, determining that a memory cell may be unselected further can include operations, features, means, or instructions for determining whether a snapback event occurred at the memory cell.

[0097] Some examples of method 800 and apparatus described herein may further include operations, features, means, or instructions for deselecting a second memory cell during at least a portion of the third pulse, the memory cell coupled to the digit line and the second memory cell coupled to the digit line.

[0098] In some examples of the methods 800 and apparatus described herein, deselecting the second memory cell may further include operations, features, means, or instructions for applying a fourth pulse to a word line coupled to the second memory cell, the fourth pulse having a third voltage configured to reduce a voltage difference across the second memory cell during a portion of the third pulse.

[0099] In some examples of the methods 800 and apparatus described herein, the third pulse reduces a bit error rate of the memory cell.

[0100] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for writing a logic state to a memory cell based on selecting the memory cell for the write operation.

[0101] In some examples of the methods 800 and apparatus described herein, the memory device includes a set of tiles, the memory cell is part of a first tile of the set, and a first number of tiles to which the second pulse is applied during a selection process may be greater than a second number of tiles to which the third pulse is applied during the selection process.

[0102] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for determining that a memory cell may be unselected after applying the first pulse, wherein applying the second pulse may be based on determining that the memory cell may be unselected.

[0103] In some examples of the method 800 and apparatus described herein, determining that a memory cell may be unselected further can include operations, features, means, or instructions for determining whether a snapback event occurred at the memory cell.

[0104] Figure 9 1 is a flow chart illustrating one or more methods 900 for supporting memory cell selection according to aspects of the present disclosure. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory device or components thereof as described herein. Figure 7 The memory device described herein performs the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0105] At 905, during a selection process of a write operation, a memory device applies a first pulse having a first voltage to a memory cell including a chalcogenide material. The operation of 905 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a first pulse having a first voltage. Figure 7 Aspects of the operations of 905 are performed by the first pulse component as described.

[0106] At 910, the memory device may apply a second pulse having a second voltage higher than the first voltage to the memory cell based on applying the first pulse. The operation of 910 may be performed according to the method described herein. In some examples, the memory device may be referred to as Figure 7 The second pulse component is described to perform aspects of the operation of 910.

[0107] At 915, the memory device may determine that the memory cell is not selected after applying the second pulse. The operation of 915 may be performed according to the methods described herein. In some examples, the memory cell may be selected by reference to Figure 7 The selection determines the components to perform aspects of the operations of 915 as described.

[0108] At 920, the memory device may apply a third pulse having a second voltage to the memory cell based on determining that the memory cell is not selected after applying the second pulse. The operation of 920 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a second voltage. Figure 7 A third pulse component is described to perform aspects of the operation of 920.

[0109] At 925, the memory device may deselect the second memory cell during at least a portion of the third pulse, the memory cell coupled to the digit line and the second memory cell coupled to the digit line. The operation of 925 may be performed according to the methods described herein. In some examples, the memory device may be coupled to the digit line by reference to Figure 7 The described deselection component performs aspects of the operation of 925.

[0110] At 930, the memory device may select a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell. The operation of 930 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell. Figure 7 The described memory cell selection component performs aspects of the operation of 930 .

[0111] Figure 10 1. A flowchart illustrating one or more methods 1000 for supporting memory cell selection according to aspects of the present disclosure is shown. The operations of the method 1000 may be implemented by a memory device or components thereof as described herein. For example, the method 1000 may be implemented by a memory device or components thereof as described herein. Figure 7The described memory device performs the operations of method 1000. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0112] At 1005, during a selection process of a write operation, a memory device applies a first pulse having a first voltage to a memory cell including a chalcogenide material. The operation of 1005 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a first pulse having a first voltage. Figure 7 Aspects of the operations of 1005 are performed using the first pulse component described.

[0113] At 1010, the memory device may apply a second pulse having a second voltage higher than the first voltage to the memory cell based on applying the first pulse. The operation of 1010 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a second pulse having a second voltage higher than the first voltage based on applying the first pulse. Figure 7 The second pulse component is described to perform aspects of the operation of 1010.

[0114] At 1015, the memory device may determine that the memory cell is not selected after applying the second pulse. The operation of 1015 may be performed according to the methods described herein. In some examples, the memory device may be configured to determine that the memory cell is not selected after applying the second pulse. Figure 7 The selection determines the components to perform aspects of the operations of 1015 as described.

[0115] At 1020, the memory device may apply a third pulse having a second voltage to the memory cell based on determining that the memory cell is not selected after applying the second pulse. The operation of 1020 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a second pulse having a second voltage. Figure 7 A third pulse component is described to perform aspects of the operation of 1020.

[0116] At 1025, the memory device may select a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell. The operation of 1025 may be performed according to the methods described herein. In some examples, the memory device may be configured to generate a memory cell for a write operation based on applying the first pulse, the second pulse, and the third pulse to the memory cell. Figure 7 The described memory cell selection components perform aspects of the operations of 1025 .

[0117] At 1030, the memory device may write the logic state to the memory cell based on the memory cell selected for the write operation. The operation of 1030 may be performed according to the methods described herein. In some examples, the memory device may be configured to write the logic state to the memory cell based on the memory cell selected for the write operation. Figure 7 The write operation components are described to perform aspects of the operation of 1030.

[0118] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, portions from two or more of the described methods may be combined.

[0119] A device is described. The device may include: a memory cell array for storing information; and a controller coupled to the memory cell array and configured to cause the device to: apply a first pulse having a first voltage to a memory cell including a chalcogenide material during a selection process of a write operation; apply a second pulse having a second voltage higher than the first voltage to the memory cell based at least in part on the application of the first pulse; apply a third pulse having the second voltage to the memory cell based on the application of the second pulse; and select the memory cell for the write operation based on the application of the first pulse, the second pulse, and the third pulse to the memory cell.

[0120] Some examples may further include determining that a memory cell may be unselected after applying the second pulse, wherein applying the third pulse may be based on determining that the memory cell may be unselected. Some examples may further include determining whether a snapback event occurred at the memory cell. Some examples may further include deselecting a second memory cell during at least a portion of the third pulse, the memory cell coupled to a digit line and the second memory cell coupled to the digit line.

[0121] Some examples may further include applying a fourth pulse to a word line coupled to the second memory cell, the fourth pulse having a third voltage configured to reduce a voltage difference across the second memory cell during the portion of the third pulse. In some examples, the third pulse reduces a bit error rate of the memory cell. Some examples may further include writing a logic state to the memory cell based on selecting the memory cell for the write operation.

[0122] In some examples, a memory device includes a set of tiles, the memory cell is part of a first tile of the set, and a first number of tiles to which the second pulse is applied during the selection process may be greater than a second number of tiles to which the third pulse is applied during the selection process. Some examples may further include determining that the memory cell is likely unselected after applying the first pulse, wherein applying the second pulse may be based on determining that the memory cell is likely unselected. Some examples may further include determining whether a snapback event occurs at the memory cell.

[0123] A device is described. The device may include: a first tile of memory cells configured to: apply a first pulse to a first memory cell of the first tile during a first duration of a selection process; determine that the first memory cell is not selected after applying the first pulse; apply a second pulse to the first memory cell during a second duration of the selection process based at least in part on determining that the first memory cell is not selected after applying the first pulse; determine that the first memory cell is selected after applying the second pulse; and write a first logic state to the first memory cell based at least in part on determining that the first memory cell is selected. The device may include a second tile of memory cells configured to: apply the first pulse to a second memory cell of the second tile during the first duration of the selection process; determine that the second memory cell is not selected after applying the first pulse; apply the second pulse to the second memory cell during the second duration of the selection process based on determining that the second memory cell is not selected after applying the first pulse; determine that the second memory cell is not selected after applying the second pulse; apply a third pulse to the second memory cell during a third duration of the selection process based on determining that the second memory cell is not selected after the second pulse; and write a second logic state to the second memory cell.

[0124] In some examples, the first pulse has a first voltage, the second pulse has a second voltage higher than the first voltage, and the third pulse has the second voltage. Some examples may further include deselecting a third memory cell of the second tile during at least a portion of the third duration associated with the third pulse, the second memory cell being coupled to a digit line of the second tile and the third memory cell being coupled to the digit line. In some examples, determining that the second memory cell may not be selected may further include operations, features, means, or instructions for determining whether a snapback event occurred at the second memory cell. In some examples, the memory cells of the first tile and the memory cells of the second tile include chalcogenide materials.

[0125] The information and signals disclosed herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0126] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Thus, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. A "virtual ground" or "virtual earth ground" means connecting to approximately 0V.

[0127] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device containing the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component, such as a switch, transistor, or other component. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as a switch or transistor.

[0128] The term "coupling" refers to a condition in which a signal is moved from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed-circuit relationship in which signals are able to communicate between the components via the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive path that previously did not permit signal flow.

[0129] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If an open circuit exists between the components, the components are separated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0130] The devices discussed herein, including memory devices or memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0131] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0132] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "superior" to other examples. The detailed description contains specific details that provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0133] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0134] Any of a variety of different technologies and techniques may be used to represent the information and signals disclosed herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0135] The various illustrative blocks and modules described in conjunction with the present disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor; however, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0136] The functions described herein can be implemented by hardware, software executed by a processor, firmware, or any combination thereof. If implemented by software executed by a processor, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions can also be physically located at various locations, including distribution so that the various parts of the functions are implemented at different physical locations. In addition, as used herein, included in the claims, the "or" used in a list of items (e.g., a list of items starting with phrases such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as referring to a set of closed conditions. For example, without departing from the scope of this disclosure, exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0137] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to transmit software from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0138] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of operating a memory device, comprising: applying a first pulse having a first voltage to a memory cell including a chalcogenide material during a selection process of a write operation; After applying the first pulse, reducing the voltage applied to the memory cell from the first voltage to a third voltage; applying a second pulse having a second voltage higher than the first voltage to the memory cell based at least in part on applying the first pulse; After applying the second pulse, reducing the voltage applied to the memory cell from the second voltage to the third voltage; determining that the memory cell is unselected after applying the second pulse; applying a third pulse having the second voltage to the memory cell based at least in part on determining that the memory cell is unselected after applying the second pulse; as well as The memory cell is selected for the write operation based at least in part on applying the first pulse, the second pulse, and the third pulse to the memory cell.

2. The method of claim 1 , wherein determining that the memory cell is not selected further comprises: A determination is made as to whether a snapback event occurs at the memory cell.

3. The method according to claim 1, further comprising: A second memory cell is deselected during at least a portion of the third pulse, the memory cell being coupled to a digit line and the second memory cell being coupled to the digit line.

4. The method of claim 3 , wherein deselecting the second memory cell further comprises: A fourth pulse is applied to a word line coupled to the second memory cell, the fourth pulse having a fourth voltage configured to reduce a voltage difference across the second memory cell during the portion of the third pulse. The method of claim 1 , wherein the third pulse reduces a bit error rate of the memory cell.

6. The method according to claim 1, further comprising: A logic state is written to the memory cell based at least in part on selecting the memory cell for the write operation.

7. The method according to claim 1, wherein: The memory device comprises a plurality of tiles, the memory cell being part of a first tile of the plurality of tiles; and A first number of tiles to which the second pulse is applied during the selection process is greater than a second number of tiles to which the third pulse is applied during the selection process.

8. The method according to claim 1, further comprising: The memory cell is determined to be unselected after applying the first pulse, wherein applying the second pulse is based at least in part on determining that the memory cell is unselected.

9. The method of claim 8, wherein determining that the memory cell is not selected further comprises: A determination is made as to whether a snapback event occurs at the memory cell.

10. A memory device comprising: a memory cell array for storing information; as well as a controller coupled to the memory cell array and configured to cause the memory device to: applying a first pulse having a first voltage to a memory cell including a chalcogenide material during a selection process of a write operation; applying a second pulse having a second voltage higher than the first voltage to the memory cell based at least in part on a failure of applying the first pulse to select the memory cell; applying a third pulse having the second voltage to the memory cell based at least in part on a failure of applying the second pulse to select the memory cell; and The memory cell is selected for the write operation based at least in part on applying the first pulse, the second pulse, and the third pulse to the memory cell.

11. The memory device of claim 10 , wherein the controller is further configured to cause the memory device to: A determination is made as to whether a snapback event occurs at the memory cell.

12. The memory device of claim 10, wherein the controller is configured to cause the memory device to: A second memory cell is deselected during at least a portion of the third pulse, the memory cell being coupled to a digit line and the second memory cell being coupled to the digit line.

13. The memory device of claim 12, wherein the controller is further configured to cause the memory device to: A fourth pulse is applied to a word line coupled to the second memory cell, the fourth pulse having a third voltage configured to reduce a voltage difference across the second memory cell during the portion of the third pulse.

14. The memory device of claim 10, wherein the third pulse reduces a bit error rate of the memory cell.

15. The memory device of claim 10, wherein the controller is configured to cause the memory device to: A logic state is written to the memory cell based at least in part on selecting the memory cell for the write operation.

16. The memory device of claim 10, wherein: The memory device comprises a plurality of tiles, the memory cell being part of a first tile of the plurality of tiles; and A first number of tiles to which the second pulse is applied during the selection process is greater than a second number of tiles to which the third pulse is applied during the selection process.

17. The memory device of claim 10, wherein the controller is further configured to cause the memory device to: A determination is made as to whether a snapback event occurs at the memory cell.

18. A memory device comprising: A first tile of memory cells is configured to: applying a first pulse to a first memory cell of the first tile during a first duration of a selection process; determining that the first memory cell is unselected after applying the first pulse; applying a second pulse to the first memory cell during a second duration of the selection process based at least in part on determining that the first memory cell was not selected after applying the first pulse; determining that the first memory cell is selected after applying the second pulse; and writing a first logic state to the first memory cell based at least in part on determining that the first memory cell is selected; as well as a second tile of memory cells configured to: applying the first pulse to a second memory cell of the second tile during the first duration of the selection process; determining that the second memory cell is unselected after applying the first pulse; applying the second pulse to the second memory cell during the second duration of the selection process based at least in part on determining that the second memory cell was not selected after the first pulse; determining that the second memory cell is unselected after applying the second pulse; applying a third pulse to the second memory cell during a third duration of the selection process based at least in part on determining that the second memory cell was not selected after the second pulse; and A second logic state is written to the second memory cell.

19. The memory device of claim 18, wherein: The first pulse has a first voltage; The second pulse has a second voltage higher than the first voltage; as well as The third pulse has the second voltage.

20. The memory device of claim 18, wherein the second tile is further configured to: A third memory cell of the second tile is deselected during at least a portion of the third duration associated with the third pulse, the second memory cell being coupled to a digit line of the second tile and the third memory cell being coupled to the digit line.

21. The memory device of claim 18, wherein determining that the second memory cell is not selected further comprises: A determination is made as to whether a snapback event occurs at the second memory cell.

22. The memory device of claim 18, wherein the memory cells of the first tile and the memory cells of the second tile comprise a chalcogenide material.

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