A troubleshooting method, device and equipment based on SWD protocol and readable medium

Abstract

The application discloses a fault troubleshooting method based on an SWD protocol, which comprises the following steps: selecting a latch mode based on the scene complexity of fault troubleshooting; if the scene complexity of fault troubleshooting is not high, selecting a direct latch mode through a mode register; in response to detecting that the mode register is configured as the direct latch mode, sending a locking signal to a signal collector through a latch register, and locking the signal collector latch register to stop real-time data updating; judging whether a target signal collector has locked a target signal latch register; and if the target signal collector has locked the target signal latch register, acquiring collected data in the target signal collector through an SWD emulator, and performing fault troubleshooting based on the collected data. The application further discloses a fault troubleshooting device based on the SWD protocol, computer equipment and a readable storage medium. The application can assist in observing complex testing scenes, and saves the troubleshooting time input of testing personnel.

Description

Technical Field

[0001] This invention relates to the field of troubleshooting technology, and in particular to a troubleshooting method, apparatus, equipment and readable medium based on the SWD protocol. Background Technology

[0002] With the rapid development of the integrated circuit industry, the scale and complexity of integrated circuits have increased dramatically. The logic functions of chips have become increasingly complex, and the interaction scenarios between various design modules have also become more complex. All of these factors directly lead to increased difficulty for testers to locate faults (bugs). The manpower and time costs required to complete a chip test are enormous. Especially after the chip is taped out (the final step of the design, i.e., sent to manufacturing), in order to locate faults, repeatedly capturing relevant signals with an oscilloscope to infer the cause of the problem is often a waste of effort.

[0003] Therefore, when designing chips, it is necessary to consider not only functions, power consumption, and process technology, but also how to quickly debug the chip after the design is completed. This led to the development of DFT (design for test) technology to improve the testability of chips, help testers read or control the internal state of the chip, thereby quickly locating problems and saving testing costs.

[0004] The common types of SOC (System on Chip) debugging systems in existing technologies include the following:

[0005] Boundary scan technology based on the JTAG (Joint Test Action Group) protocol is a commonly used design for troubleshooting. The standard JTAG protocol requires a total of four pins: tck, tms, tdi, and tdo. An external emulator simulates the JTAG protocol entering the chip's JTAG interface and serially shifts the contents of the registers connected between tdi and tdo to obtain the contents of the CPU registers inside the chip and the registers of other modules in the SOC system. In this way, when encountering a bug, the cause of the problem can be quickly located by simply reading and writing a few relevant registers.

[0006] Signal monitoring technology is also a very common practice. In many SOC designs, some key signals that require observation are directly connected to the top layer. This makes it easy to obtain internal information of the SOC by observing the signals at the top layer during the front-end verification stage. After tape-out, internal information can also be obtained by observing with an oscilloscope.

[0007] Built-in Self-Test (BIST) is a design technique that incorporates additional self-test circuitry into the chip design. During testing, only external control signals are required to run the built-in self-test hardware and software, checking for defects or faults in the circuit under test. Unlike scan design, BIST test vectors are typically generated internally, rather than being externally input. BIST simplifies testing procedures and eliminates the need for expensive test instruments and equipment (such as ATE equipment), but it increases the complexity of the chip design.

[0008] Each of the above troubleshooting system designs has its applicable scope, suitable for SOC systems of different functions and scales. However, these troubleshooting system designs are difficult to effectively troubleshoot algorithm-based design modules with long processes and no registers. Summary of the Invention

[0009] In view of this, the purpose of this invention is to propose a fault diagnosis method, apparatus, device and readable medium based on the SWD protocol, to assist in testing complex scenarios and to observe the status of large-scale signal lines inside the design module, thereby saving on fault diagnosis design investment and test personnel investment.

[0010] To achieve the above objectives, one aspect of this invention provides a fault diagnosis method based on the SWD protocol, comprising the following steps: selecting a latching mode based on the complexity of the fault diagnosis scenario; if the complexity of the fault diagnosis scenario is not high, then selecting a direct latching mode through a mode register; in response to detecting that the mode register is configured as a direct latching mode, sending a locking signal to a signal acquisition unit through the latching register, and having the signal acquisition unit lock the signal latch to stop real-time data updates; determining whether the target signal acquisition unit has already locked the target signal latch; and if the target signal acquisition unit has already locked the target signal latch, then acquiring the acquisition data from the target signal acquisition unit through an SWD simulator, and performing fault diagnosis based on the acquisition data.

[0011] In some implementations, the method further includes: if the complexity of the fault diagnosis scenario is high, then selecting a condition latch mode through a mode register; in response to detecting that the mode register is configured as a condition latch mode, configuring latch conditions and storing the latch conditions in a latch condition register, and detecting the data status in real time to determine whether the data status has reached the latch conditions; in response to the data status reaching the latch conditions, sending a lock signal to the signal acquisition unit through the latch register, and having the signal acquisition unit lock the signal latch to stop real-time data updates.

[0012] In some implementations, the method further includes: in response to the data state not meeting the latching condition, continuing to detect the data state to determine whether the data state meets the latching condition.

[0013] In some implementations, the latch condition register includes an id register and a value register, and the latch condition includes an id condition and a value condition, wherein the id condition is stored in the id register and the value condition is stored in the value register.

[0014] In some implementations, the method further includes updating the status information of the signal collector to the latch status register in response to the signal collector completing the locking of the signal latch.

[0015] In some implementations, determining whether the target signal acquisition device has locked the target signal latch includes: obtaining the status information of the target signal acquisition device in the latch status register, and determining whether the target signal acquisition device has locked the target signal latch based on the status information.

[0016] In some implementations, the method further includes sending instructions from the SWD emulator to the mode register and the latch register via an SWD protocol converter and an AHB decoder.

[0017] In another aspect of this invention, a fault diagnosis device based on the SWD protocol is provided, comprising: a first module configured to select a latching mode based on the complexity of the fault diagnosis scenario; if the complexity of the fault diagnosis scenario is not high, a direct latching mode is selected through a mode register; a second module configured to, in response to detecting that the mode register is configured as direct latching mode, send a locking signal to a signal acquisition unit through a latching register, and the signal acquisition unit locks the signal latch to stop real-time data updates; a third module configured to determine whether the target signal acquisition unit has locked the target signal latch; and a fourth module configured to, if the target signal acquisition unit has locked the target signal latch, obtain the acquired data from the target signal acquisition unit through an SWD simulator and perform fault diagnosis based on the acquired data.

[0018] In another aspect, the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, wherein the instructions, when executed by the processor, implement the steps of a method including: selecting a latching mode based on the complexity of a fault-finding scenario; if the complexity of the fault-finding scenario is not high, selecting a direct latching mode through a mode register; in response to detecting that the mode register is configured as a direct latching mode, sending a locking signal to a signal acquisition unit through the latching register, and having the signal acquisition unit lock the signal latch to stop real-time data updates; determining whether a target signal acquisition unit has locked the target signal latch; and if the target signal acquisition unit has locked the target signal latch, acquiring the acquired data in the target signal acquisition unit through an SWD simulator, and performing fault-finding based on the acquired data.

[0019] In some implementations, the steps further include: if the complexity of the fault diagnosis scenario is high, then selecting a condition latch mode through a mode register; in response to detecting that the mode register is configured as a condition latch mode, configuring latch conditions and storing the latch conditions in a latch condition register, and detecting the data status in real time to determine whether the data status has reached the latch condition; in response to the data status reaching the latch condition, sending a lock signal to the signal acquisition unit through the latch register, and having the signal acquisition unit lock the signal latch to stop real-time data updates.

[0020] In some implementations, the steps further include: in response to the data state not meeting the latching condition, continuing to detect the data state to determine whether the data state meets the latching condition.

[0021] In some implementations, the latch condition register includes an id register and a value register, and the latch condition includes an id condition and a value condition, wherein the id condition is stored in the id register and the value condition is stored in the value register.

[0022] In some implementations, the steps further include: updating the status information of the signal collector to the latch status register in response to the signal collector completing the locking of the signal latch.

[0023] In some implementations, determining whether the target signal acquisition device has locked the target signal latch includes: obtaining the status information of the target signal acquisition device in the latch status register, and determining whether the target signal acquisition device has locked the target signal latch based on the status information.

[0024] In some implementations, the steps further include: sending the instructions of the SWD emulator to the mode register and the latch register via the SWD protocol converter and the AHB decoder.

[0025] In another aspect, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method steps.

[0026] This invention offers at least the following beneficial technical advantages: By utilizing a general-purpose modular signal acquisition unit, the signals to be observed can be packaged and transmitted to an external simulator via the two SWD pins. This eliminates the need for designers to design dedicated troubleshooting functions; they only need to integrate the signal acquisition unit module within the designed functional module, connect the signals to be observed to the module's reserved interface, and then, under the control of the main controller, selectively transmit a large number of internal signals to the external system via the SWD interface.

[0027] Compared to other troubleshooting methods, its advantages are: it provides a complete troubleshooting system and a universal module signal acquisition unit, so designers only need to connect the signal to be observed to the interface of the signal acquisition unit, saving designers' investment; the number of signal latches and the signals that each signal latch can monitor can be controlled through macro definitions, making it highly versatile; based on the SWD protocol, it only requires two pins, saving the number of chip pins, and the entire troubleshooting system does not rely on the internal bus path of the system. As long as the system clock exists, the desired signal value can be read through its own AHB bus; it supports both direct latching and conditional latching modes. For simple scenarios, registers can be directly configured for latching and then observed through SWD, while for complex scenarios, condition registers are provided to help testers quickly obtain the field situation in complex scenarios, thereby greatly improving verification efficiency. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of an embodiment of the fault diagnosis method based on the SWD protocol provided by the present invention;

[0030] Figure 2 A schematic diagram of an embodiment of the fault diagnosis device based on the SWD protocol provided by the present invention;

[0031] Figure 3 A schematic diagram of an embodiment of the computer device provided by the present invention;

[0032] Figure 4 A schematic diagram illustrating an embodiment of the computer-readable storage medium provided by the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0034] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0035] Based on the above objectives, the first aspect of the present invention proposes an embodiment of a fault diagnosis method based on the SWD protocol. Figure 1 The diagram shown is a schematic representation of an embodiment of the fault diagnosis method based on the SWD protocol provided by the present invention. Figure 1 As shown, the fault diagnosis method based on the SWD protocol in this embodiment of the invention includes the following steps:

[0036] 001. Select the latching mode based on the complexity of the fault diagnosis scenario. If the complexity of the fault diagnosis scenario is not high, select the direct latching mode through the mode register.

[0037] 002. In response to the detection that the mode register is configured as direct latch mode, a lock signal is sent to the signal acquisition unit through the latch register, and the signal acquisition unit locks the signal latch to stop real-time data updates.

[0038] 003. Determine whether the target signal acquisition device has locked the target signal latch; and

[0039] 004. If the target signal acquisition device has locked the target signal latch, the acquisition data in the target signal acquisition device is obtained through the SWD simulator, and the fault is troubleshooted based on the acquisition data.

[0040] In this embodiment, the mode register includes two modes: direct latching and conditional latching. In direct latching mode, after configuring latching enable, the value of the currently selected signal register will be directly latched. In conditional latching mode, after configuring latching enable, the value of the selected signal register will be latched when the selected condition signal reaches the target value; the maximum number of conditions supported is configurable. After configuring the latch register, the control signal acquisition module latches the signal value and no longer changes it in real time.

[0041] The signal acquisition unit comprises signal latches and a signal acquisition controller. The signal acquisition unit converts 32-bit signal lines into 32-bit registers, supporting read and write operations via the AHB bus. Each signal latch can acquire a maximum of 32 bits of signal, and the number of signal latches in a signal acquisition module is defined using macros. All signal acquisition units are controlled by the signal acquisition controller module, which controls the enabling and disabling of signal acquisition and latched signal values. The signal acquisition controller receives control information from the main controller module and latches the signal latches upon receiving a latch signal. In conditional latching mode, the module monitors the value of the selected signal latch and latches the signal latch when the condition register configuration value is met. Furthermore, upon receiving a fault troubleshooting enable or disable signal, the module enables or disables the fault troubleshooting function. When fault troubleshooting is disabled, all signal latches cease signal sampling, saving power; they are only enabled when fault troubleshooting is required.

[0042] In this embodiment, in simple troubleshooting scenarios, such as when only the status of a few signals needs to be monitored, the direct latch mode is used. This involves directly configuring the signal acquisition controller register to latch the register value of the signal latch when observation is needed, and completing signal monitoring through the SWD interface. The specific process is as follows: The external emulator sends a command to select the control register; the external emulator writes to the control register to enable the troubleshooting system; the external emulator writes to the control register to configure the mode as direct latch mode; the external emulator writes to the control register to lock the signal latch, preventing it from updating in real time; the external emulator queries the status of the latch registers in the control register group; if latched, the external emulator sends a command to select the register corresponding to the signal to be observed; the external emulator reads the data; finally, the external emulator writes to the control register to configure the troubleshooting system to shut down, achieving energy saving. Through this process, the selected signal status can be obtained, assisting verification personnel in quickly acquiring the internal state of the chip, thereby enabling effective troubleshooting.

[0043] In some embodiments of the present invention, the method further includes: if the complexity of the fault diagnosis scenario is high, then selecting a condition latching mode through a mode register; in response to detecting that the mode register is configured as a condition latching mode, configuring latching conditions and storing the latching conditions in a latching condition register, and detecting the data status in real time to determine whether the data status has reached the latching condition; in response to the data status reaching the latching condition, sending a lock signal to the signal acquisition unit through the latching register, and having the signal acquisition unit lock the signal latch to stop real-time data updates.

[0044] In this embodiment, in complex fault diagnosis scenarios, verification personnel do not wish to perform random signal monitoring, but rather to monitor the states of several sets of signals under certain conditions. This design provides a conditional latching mode, that is, when observation is needed, a condition register is provided, and the signal latch register value is automatically latched when the configured conditions are met. The specific usage process is as follows: The external simulator sends a command to select the control register; the external simulator writes to the control register to enable the fault diagnosis system; the external simulator writes to the control register to configure the mode as conditional latching mode; the external simulator writes to the control register to configure the latching conditions, including the register address and register value, and the number of conditions is configurable; when the waiting scenario occurs, all signal acquisition unit register values ​​are automatically latched; the external simulator queries the status of the latch registers in the control register group; if it has been latched, the external simulator sends a command to select the register corresponding to the signal to be observed and reads the data; finally, the external simulator writes to the control register to configure the fault diagnosis system to be shut down, achieving energy saving.

[0045] Compared to direct latch mode, condition latch mode has a slightly more complex usage process. However, for scenarios with high complexity, condition latch mode can more effectively and directly help verification personnel obtain the internal state information of the chip they want. This is because, in most cases, we only focus on some special static scenarios rather than real-time changes in signals.

[0046] In some embodiments of the present invention, the method further includes: in response to the data state not meeting the latching condition, continuing to detect the data state to determine whether the data state meets the latching condition.

[0047] In some embodiments of the present invention, the latch condition register includes an id register and a value register, and the latch condition includes an id condition and a value condition, wherein the id condition is stored in the id register and the value condition is stored in the value register.

[0048] In this embodiment, each condition in the latch condition register includes two registers: an id register and a value register, which enable latching when the 32-bit signal line status value register corresponding to the configured id reaches the configured value.

[0049] In some embodiments of the present invention, the method further includes: updating the status information of the signal acquisition device to the latch status register in response to the signal acquisition device completing the locking of the signal latch.

[0050] In this embodiment, the latch status register is used to reflect the latch status.

[0051] In some embodiments of the present invention, determining whether the target signal acquisition device has locked the target signal latch includes: obtaining the status information of the target signal acquisition device in the latch status register, and determining whether the target signal acquisition device has locked the target signal latch based on the status information.

[0052] In some embodiments of the present invention, the method further includes: sending the instructions of the SWD emulator to the mode register and the latch register through the SWD protocol converter and the AHB decoder.

[0053] In this embodiment, the SWD protocol converter converts the SWD protocol received from the chip's SWD pin into the AHB bus protocol. This AHB bus is independent of other buses in the system and only takes effect when the SWD protocol is driven. The SWD protocol converter provides three custom address, data, and control registers. Through the SWD protocol configuration register, it initiates AHB protocol access based on the configuration information, thus converting the SWD protocol into the AHB protocol. The AHB decoder completes the decoding based on the ID.

[0054] In some embodiments of the present invention, time information can be added to the signal acquisition module to add a timestamp to each read, thereby obtaining the changing trend of the observed signal. In addition, for SOC systems with many subsystems, a decoding module can be added to each subsystem to aggregate all the signals to be observed in the subsystem and then output to the SWD interface through the main controller, thereby reducing the wiring between subsystems. Finally, an interface is reserved for troubleshooting. If confidential content is involved and the product is not allowed to be used at the factory, a switch can be added to the interface and controlled by efuse to achieve debugging before leaving the factory and no leakage after leaving the factory.

[0055] It should be noted that the steps in each embodiment of the above-mentioned fault diagnosis method based on the SWD protocol can be interchanged, substituted, added, or deleted. Therefore, these reasonable permutations and combinations of the fault diagnosis method based on the SWD protocol should also fall within the protection scope of this invention, and the protection scope of this invention should not be limited to the embodiments.

[0056] In view of the above objectives, a second aspect of the present invention provides a fault diagnosis device based on the SWD protocol. Figure 2 The diagram shown is a schematic representation of an embodiment of the fault diagnosis device based on the SWD protocol provided by the present invention. Figure 2As shown, the fault diagnosis device based on the SWD protocol in this embodiment of the invention includes the following modules: a first module 011, configured to select a latching mode based on the complexity of the fault diagnosis scenario; if the complexity of the fault diagnosis scenario is not high, a direct latching mode is selected through a mode register; a second module 012, configured to send a locking signal to the signal acquisition unit through the latch register in response to detecting that the mode register is configured as direct latching mode, and the signal acquisition unit locks the signal latch to stop real-time data updates; a third module 013, configured to determine whether the target signal acquisition unit has locked the target signal latch; and a fourth module 014, configured to obtain the acquisition data in the target signal acquisition unit through the SWD simulator if the target signal acquisition unit has locked the target signal latch, and perform fault diagnosis based on the acquisition data.

[0057] In view of the above objectives, a third aspect of the present invention provides a computer device. Figure 3 The diagram shown is a schematic representation of an embodiment of the computer device provided by the present invention. Figure 3 As shown, the computer device of this embodiment includes the following apparatus: at least one processor 021; and a memory 022, the memory 022 storing computer instructions 023 executable by the processor, wherein the steps of the method implemented by the processor when the instructions are executed include: selecting a latching mode based on the complexity of the fault diagnosis scenario; if the complexity of the fault diagnosis scenario is not high, then selecting a direct latching mode through a mode register; in response to detecting that the mode register is configured as a direct latching mode, sending a locking signal to the signal acquisition unit through the latching register, and having the signal acquisition unit lock the signal latch to stop real-time data updates; determining whether the target signal acquisition unit has already locked the target signal latch; and if the target signal acquisition unit has already locked the target signal latch, acquiring the acquisition data in the target signal acquisition unit through an SWD simulator, and performing fault diagnosis based on the acquisition data.

[0058] In some embodiments of the present invention, the steps further include: if the complexity of the fault diagnosis scenario is high, then selecting a condition latching mode through the mode register; in response to detecting that the mode register is configured as a condition latching mode, configuring latching conditions and storing the latching conditions in the latching condition register, and detecting the data status in real time to determine whether the data status has reached the latching condition; in response to the data status reaching the latching condition, sending a lock signal to the signal acquisition unit through the latching register, and having the signal acquisition unit lock the signal latch to stop real-time data updates.

[0059] In some embodiments of the present invention, the steps further include: in response to the data state not meeting the latching condition, continuing to detect the data state to determine whether the data state meets the latching condition.

[0060] In some embodiments of the present invention, the latch condition register includes an id register and a value register, and the latch condition includes an id condition and a value condition, wherein the id condition is stored in the id register and the value condition is stored in the value register.

[0061] In some embodiments of the present invention, the steps further include: in response to the signal acquisition device completing the locking of the signal latch, updating the status information of the signal acquisition device to the latch status register.

[0062] In some embodiments of the present invention, determining whether the target signal acquisition device has locked the target signal latch includes: obtaining the status information of the target signal acquisition device in the latch status register, and determining whether the target signal acquisition device has locked the target signal latch based on the status information.

[0063] In some embodiments of the present invention, the steps further include: sending the instructions of the SWD emulator to the mode register and the latch register through the SWD protocol converter and the AHB decoder.

[0064] The present invention also provides a computer-readable storage medium. Figure 4 The diagram shown is a schematic representation of an embodiment of the computer-readable storage medium provided by the present invention. Figure 4 As shown, computer-readable storage medium 031 stores a computer program 032 that, when executed by a processor, performs the methods described above.

[0065] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program for the fault diagnosis method based on the SWD protocol can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The above computer program embodiments can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0066] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0067] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0068] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0069] In one or more exemplary designs, functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DOL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DOL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0070] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0071] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0072] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0073] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0074] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A fault diagnosis method based on the SWD protocol, characterized in that, Includes the following steps: The latching mode is selected based on the complexity of the fault diagnosis scenario. If the complexity of the fault diagnosis scenario is not high, the direct latching mode is selected through the mode register. In response to detecting that the mode register is configured as direct latch mode, a lock signal is sent to the signal acquisition unit through the latch register, and the signal acquisition unit locks the signal latch to stop real-time data updates; Determine whether the target signal acquisition device has locked the target signal latch; as well as If the target signal acquisition device has locked the target signal latch, the acquisition data in the target signal acquisition device is obtained through the SWD simulator, and the fault is troubleshooted based on the acquisition data. If the complexity of the fault diagnosis scenario is high, then the condition latch mode is selected through the mode register; In response to detecting that the mode register is configured to condition latch mode, a latch condition is configured and stored in the latch condition register, and the data status is monitored in real time to determine whether the data status meets the latch condition. In response to the data state reaching the latching condition, a lock signal is sent to the signal acquisition unit through the latch register, and the signal acquisition unit locks the signal latch to stop real-time data updates.

2. The fault diagnosis method based on the SWD protocol according to claim 1, characterized in that, Also includes: If the data state does not meet the latching condition, the data state is continuously monitored to determine whether the data state meets the latching condition.

3. The fault diagnosis method based on the SWD protocol according to claim 1, characterized in that, The latch condition register includes an id register and a value register. The latch condition includes an id condition and a value condition, wherein the id condition is stored in the id register and the value condition is stored in the value register.

4. The fault diagnosis method based on the SWD protocol according to claim 1, characterized in that, Also includes: In response to the signal acquisition device completing the locking of the signal latch, the status information of the signal acquisition device is updated in the latch status register.

5. The fault diagnosis method based on the SWD protocol according to claim 4, characterized in that, Determining whether the target signal acquisition device has locked onto the target signal latch includes: Obtain the status information of the target signal acquisition device in the latch status register, and determine whether the target signal acquisition device has locked the target signal latch based on the status information.

6. The fault diagnosis method based on the SWD protocol according to claim 1, characterized in that, Also includes: The instructions of the SWD emulator are sent to the mode register and the latch register through the SWD protocol converter and AHB decoder.

7. A fault diagnosis device based on the SWD protocol, characterized in that, include: The first module is configured to select a latching mode based on the scenario complexity of fault diagnosis. If the scenario complexity of the fault diagnosis is not high, the direct latching mode is selected through the mode register. The second module is configured to send a lock signal to the signal acquisition unit through the latch register in response to detecting that the mode register is configured as direct latch mode, and the signal acquisition unit locks the signal latch to stop real-time data updates. The third module is configured to determine whether the target signal acquisition device has locked the target signal latch. as well as The fourth module is configured to, if the target signal acquisition device has locked the target signal latch, obtain the acquisition data from the target signal acquisition device through the SWD simulator and perform fault diagnosis based on the acquisition data. And the module used to perform the following steps: If the complexity of the fault diagnosis scenario is high, then the condition latch mode is selected through the mode register; In response to detecting that the mode register is configured to condition latch mode, a latch condition is configured and stored in the latch condition register, and the data status is monitored in real time to determine whether the data status meets the latch condition. In response to the data state reaching the latching condition, a lock signal is sent to the signal acquisition unit through the latch register, and the signal acquisition unit locks the signal latch to stop real-time data updates.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-6.

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