A high-voltage-resistant antistatic structure for a transceiver

Abstract

The application provides a high-voltage anti-static structure for a transceiver, a plurality of corresponding ports are connected with high-voltage diode structures on both sides, the ports are anodes of the high-voltage diode structures which are only conducted on one side, a plurality of corresponding port circuit groups are formed, and each corresponding port circuit group forms at least two discharge channels; through the combination of reverse-biased diodes and forward-biased diodes, at least two discharge channels exist between the ports, the pressure of a single discharge channel is greatly reduced, the requirement of super-high-voltage electrostatic discharge is met, when the load of one of the discharge channels between the ports is too heavy and the load of the other discharge channel is light, a balanced discharge channel balancing device is triggered, the side with too large voltage is shunted to the side with light load through the balanced discharge channel balancing device, two-side balanced discharge is realized, the two-side balanced discharge technology effectively avoids the problem of unbalanced discharge caused by too heavy load of a single channel and light load of the other channel, and the anti-static characteristic of the device is significantly improved.

Description

TECHNICAL FIELD

[0001] The application belongs to a high-voltage anti-static structure for a transceiver, and particularly relates to a high-voltage anti-static structure for a transceiver. BACKGROUND

[0002] The transceiver is widely applied to the industrial and military fields such as automobiles and tanks, and the electrostatic discharge phenomenon of the application environment is significant. In order to save energy and reduce voltage loss, the power supply and signal voltage amplitude are high, and the normal working part of the power supply voltage amplitude is as high as 60V, and the anti-static capacity requirement is as high as 8000V.

[0003] The traditional anti-static structure adopts a reverse-biased diode and a GGNMOS structure. The reverse-biased diode has the characteristics of not being easy to produce latching, but the current discharge capacity is general. The GGNMOS structure is a connection mode in which the gate of an NMOS tube is connected to the ground, and the GGNMOS structure has the characteristics of strong current discharge capacity, but is easy to produce latching.

[0004] The single reverse-biased diode and the GGNMOS structure have low voltage resistance, and cannot meet the voltage resistance requirements of part of the power supply voltage, especially the battery voltage VBAT started in an emergency. The voltage amplitude is as high as 60V, and the single reverse-biased diode and the GGNMOS structure work under a constant voltage, and the voltage resistance is only about 12V. Under the high voltage of 60V, the normal working will cause breakdown.

[0005] The single reverse-biased diode and the GGNMOS structure have low current passing capacity, and the anti-static capacity reaches the requirement of 8000V. According to the domestic electrostatic test standard, the 8000V voltage cannot be directly measured. The current is realized by observing the current in the mode of connecting a 500-ohm resistor in series with a third discharge path at the port. The 8000V voltage passes through the 500-ohm resistor in the third discharge path, and the current is as high as 5.33A. The single reverse-biased diode and the GGNMOS structure cannot meet the requirement of discharging the super-large current of 5.33A. SUMMARY

[0006] In view of the problems in the prior art, the application provides a high-voltage anti-static structure for a transceiver.

[0007] The application is realized by the following technical scheme:

[0008] A high-voltage anti-static structure for a transceiver, characterized by comprising a plurality of corresponding ports, a high-voltage diode structure and a balanced discharge channel balancing device.

[0009] The high-voltage diode structure is connected to both sides of the plurality of corresponding ports, and the port is an anode of the high-voltage diode structure that is only conducted on one side, forming a plurality of corresponding port line groups, and each corresponding port line group forms at least two discharge channels.

[0010] The corresponding port line groups are connected in parallel with each other, for balancing discharges of the ports;

[0011] The multiple corresponding port line groups are commonly connected in parallel with the balancing discharge channel balancing device.

[0012] Further, the high-voltage diode structure comprises multiple reverse-biased diodes connected in series.

[0013] Further, the multiple reverse-biased diodes connected in series are not less than six in number.

[0014] Further, the balancing discharge channel balancing device comprises multiple GGNMOS tubes connected in series.

[0015] Further, the multiple GGNMOS tubes connected in series are not less than nine in number.

[0016] Further, the ports comprise a BP port, a BM port, a VBAT port, a WAKE port, an INH1 port and an INH2 port.

[0017] Further, the balancing device is connected to only two discharge channels formed by each corresponding port line group, for balancing voltages on both sides of the corresponding ports.

[0018] Further, the multiple corresponding port line groups are commonly connected in parallel with a zero potential, and high-voltage diode structures of the same direction are arranged on both sides of the zero potential.

[0019] Compared with the prior art, the present application has the following beneficial technical effects:

[0020] This invention provides a high-voltage anti-static structure for a transceiver, comprising multiple corresponding ports, a high-voltage diode structure, and a balancing device for equalizing discharge channels. High-voltage diode structures are connected to both sides of the multiple corresponding ports, with only one side of each port conducting the anode of the high-voltage diode structure, forming multiple corresponding port line groups. Each corresponding port line group forms at least two discharge channels. Through the combination of reverse-biased diodes and forward-biased diodes, at least two discharge channels exist between ports, significantly reducing the pressure on a single discharge channel and meeting the requirements for ultra-high voltage electrostatic discharge. Simultaneously, when one discharge channel between ports is overloaded and experiences excessive voltage, while the other discharge channel is underloaded and experiences low voltage, the balancing device for equalizing discharge channels is triggered. The side experiencing excessive voltage is diverted to the side with less load through the balancing device, achieving balanced discharge on both sides. This balanced discharge technology effectively avoids the problem of unbalanced discharge where one channel has an excessively high discharge load while the other channel has a low load, significantly improving the anti-static characteristics of the device. This invention meets the normal application requirements of power supply and signal up to 60V and the anti-static requirements up to 8000V. It proposes high withstand voltage series discharge technology, composite discharge channel ultra-high current discharge technology, and dual-sided balanced discharge technology, which greatly improves the reliability of devices in high-voltage applications and reduces the risk of electrostatic breakdown. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a high-voltage withstand and anti-static structure for a transceiver in a specific embodiment of the present invention;

[0022] Figure 2 This is a circuit diagram of the high-voltage diode structure and the equalization discharge channel balancing device in a specific embodiment of the present invention;

[0023] Figure 3 This is the discharge channel from port signal BP to zero potential GND in a specific embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the discharge channel from the port signal BP to the zero potential GND when the equalization discharge channel is triggered in a specific embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the discharge channel from zero potential GND to port signal BP when the equalization discharge channel is triggered in a specific embodiment of the present invention;

[0026] Figure 6 This is the discharge channel from the port signal VBAT to the zero potential GND in a specific embodiment of the present invention;

[0027] Figure 7 This is the discharge channel from port signal INH2 to zero potential GND in a specific embodiment of the present invention.

[0028] Fig. 1 shows a first high-voltage diode structure 20, a second high-voltage diode structure 21, a third high-voltage diode structure 22, a fourth high-voltage diode structure 23, a fifth high-voltage diode structure 24, a sixth high-voltage diode structure 25, a seventh high-voltage diode structure 26, an eighth high-voltage diode structure 27, a ninth high-voltage diode structure 28, a tenth high-voltage diode structure 29, an eleventh high-voltage diode structure 30, a twelfth high-voltage diode structure 31, a thirteenth high-voltage diode structure 32, a fourteenth high-voltage diode structure 33, a balanced discharge channel balancing device 34, a first discharge path 40, a second discharge path 41, a third discharge path 50, a fourth discharge path 51, a fifth discharge path 60, a sixth discharge path 61, a seventh discharge path 70, an eighth discharge path 71, a ninth discharge path 52, a tenth discharge path 62, and an eleventh discharge path 72. DETAILED DESCRIPTION

[0029] The application will be further described below in connection with specific embodiments, which are intended to explain the application but not to limit it.

[0030] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and in the above-described drawings are intended to distinguish similar objects and not to describe a particular sequential or chronological order. It is to be understood that the data thus designated can be interchanged, where appropriate, so that the embodiments of the application described herein can be practiced in other than the order illustrated or described herein. Furthermore, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusions, for example, processes, methods, systems, products, or devices that comprise a list of steps or units are not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products, or devices.

[0031] The application provides a high-voltage anti-static structure for a transceiver, as shown in Figure 1 comprising a plurality of corresponding ports, high-voltage diode structures, and a balanced discharge channel balancing device;

[0032] The high-voltage diode structures are connected on both sides of the plurality of corresponding ports, and the ports are only anode of the high-voltage diode structure on one side, forming a plurality of corresponding port line groups, and each corresponding port line group forms at least two discharge channels, which greatly reduces the pressure of a single discharge channel and meets the requirement of super-high-voltage electrostatic discharge;

[0033] The corresponding port line groups are connected in parallel with each other, for balancing the port discharge;

[0034] The plurality of corresponding port circuit groups are commonly connected in parallel with the equalization discharge channel balancing device, which is triggered by the voltage difference between the two discharge paths, greatly improves the reliability of the device in high-voltage application, and reduces the risk of electrostatic breakdown.

[0035] A preferred embodiment of the present application is shown in FIG. 1, wherein the high-voltage diode structure comprises a plurality of anti-bias diodes connected in series. Figure 2 Further, the number of the series-connected anti-bias diodes is not less than six, because the device process allows the low-voltage ESD protection device to be connected in series to achieve high breakdown voltage for high-voltage ESD protection. The breakdown, start, and holding voltage of the device is the sum of the corresponding parameters of each device, thus meeting the normal application requirements of power supply and signal up to 60V.

[0036] Another preferred embodiment of the present application is shown in FIG. 2, wherein the equalization discharge channel balancing device comprises a plurality of GGNMOS tubes connected in series. Figure 2 Further, the number of the series-connected GGNMOS tubes is not less than nine, because the normal withstand voltage of GGNMOS is lower than that of anti-bias NMOS, and therefore nine GGNMOS tubes are connected in series to achieve high normal withstand voltage.

[0037] Another preferred embodiment of the present application is that the ports include but are not limited to BP port, BM port, VBAT port, WAKE port, INH1 port, and INH2 port.

[0038] Another preferred embodiment of the present application is that the balancing device is connected only to the two discharge channels formed by each corresponding port circuit group, for balancing the voltages on both sides of the corresponding ports.

[0039] Another preferred embodiment of the present application is that the plurality of corresponding port circuit groups are also commonly connected in parallel with a zero potential, and the zero potential is provided with high-voltage diode structures in the same direction on both sides.

[0040] A preferred embodiment of the present application is shown in FIG. 1, wherein the high-voltage diode structure comprises a plurality of anti-bias diodes connected in series. Figure 1As shown, including a first high-voltage diode structure 20, a second high-voltage diode structure 21, a third high-voltage diode structure 22, a fourth high-voltage diode structure 23, a fifth high-voltage diode structure 24, a sixth high-voltage diode structure 25, a seventh high-voltage diode structure 26, an eighth high-voltage diode structure 27, a ninth high-voltage diode structure 28, a tenth high-voltage diode structure 29, an eleventh high-voltage diode structure 30, a twelfth high-voltage diode structure 31, a thirteenth high-voltage diode structure 32, and a fourteenth high-voltage diode structure 33;

[0041] The BP port, the BM port, the VBAT port, the WAKE port, the INH1 port, and the INH2 port, wherein the BP port and the BM port are a corresponding port group, the VBAT port and the WAKE port are a corresponding port group, and the INH1 port and the INH2 port are a corresponding port group;

[0042] The equalization discharge channel balancing device 34 and the zero potential GND;

[0043] Specifically, the two sides of the VBAT port are respectively the second high-voltage diode structure 21 and the third high-voltage diode structure 22; the two sides of the WAKE port are respectively the fourth high-voltage diode structure 23 and the fifth high-voltage diode structure 24; the two sides of the INH1 port are respectively the seventh high-voltage diode structure 26 and the eighth high-voltage diode structure 27; the two sides of the INH2 port are respectively the sixth high-voltage diode structure 25 and the thirteenth high-voltage diode structure 32; the two sides of the BP port are respectively the ninth high-voltage diode structure 28 and the eleventh high-voltage diode structure 30; the two sides of the BM port are respectively the tenth high-voltage diode structure 29 and the twelfth high-voltage diode structure 31; and the two sides of the zero potential GND are respectively the first high-voltage diode structure 20 and the fourteenth high-voltage diode structure 33; a plurality of corresponding port circuit groups are formed, and each corresponding port circuit group forms at least two discharge channels; the corresponding port circuit groups are connected in parallel two by two, and are used for equalizing port discharge; the plurality of corresponding port circuit groups are commonly connected in parallel with the equalization discharge channel balancing device, that is, a high-voltage series discharge technology, a composite channel current discharge technology, and a double-side equalization discharge technology are formed, mainly for high-reliability applications under high-voltage conditions and strong electrostatic environments of a transceiver, super-high-voltage normal applications are realized through series connection of discharge structures, current discharge is realized through two or more discharge paths, and equalization discharge is realized through opening of an interconnected channel triggered by voltage difference of the two discharge paths;

[0044] The application provides a preferred specific embodiment of the composite channel current discharge technology:

[0045] The discharge channel of the port BP to the zero potential GND is as follows Figure 3As shown, the first discharge path 40 is a static pulse passing path, passing through the ninth high-voltage diode structure 28 and the first high-voltage diode structure 20 respectively; the second discharge path 41 is another static pulse passing path, passing through the eleventh high-voltage diode structure 30 and the fourteenth high-voltage diode structure 33 respectively. The current discharge capacity is significantly improved by discharging through the two paths of the first discharge path 40 and the second discharge path 41.

[0046] The discharge path from the zero potential GND to the port BP is as shown Figure 5 As shown, the third discharge path 50 is a static pulse passing path, passing through the first high-voltage diode structure 20 and the ninth high-voltage diode structure 28 respectively; the fourth discharge path 51 is another static pulse passing path, passing through the fourteenth high-voltage diode structure 33 and the eleventh high-voltage diode structure 30 respectively.

[0047] The discharge path from the port VBAT to the zero potential GND is as shown Figure 6 As shown, the fifth discharge path 60 is a static pulse passing path, passing through the third high-voltage diode structure 22; the sixth discharge path 61 is another static pulse passing path, passing through the second high-voltage diode structure 21 and the first high-voltage diode structure 20 respectively.

[0048] The discharge path from the port INH2 to the zero potential GND is as shown Figure 7 As shown, the seventh discharge path 70 is a static pulse passing path, passing through the sixth high-voltage diode structure 25 and the first high-voltage diode structure 20 respectively; the eighth discharge path 71 is another static pulse passing path, passing through the thirteenth high-voltage diode structure 32 and the fourteenth high-voltage diode structure 33 respectively. The composite channel current discharge technology discharges static electricity through at least two paths, greatly improving the current discharge capacity, thereby enhancing the anti-static ability of the device. In addition, the composite channel current discharge technology uses shared discharge devices, such as the first high-voltage diode structure 20 and the fourteenth high-voltage diode structure 33 of the device, which has a significantly smaller area.

[0049] The present application provides a preferred specific embodiment of the double-side balanced discharge technology:

[0050] The discharge path from the port BP to the zero potential GND is as shown Figure 4 As shown, the first discharge path 40 and the second discharge path 41 form two paths, and when the voltage difference borne by the two paths is large, the discharge current difference passing through the two discharge paths is large, and the balanced discharge path balancer 34 is triggered to conduct due to the large voltage difference on both sides, forming the discharge path 42. If the voltage of the first discharge path 40 branch is significantly greater than that of the second discharge path 41 branch, the direction of the double-side balanced discharge 42 is to the right, and vice versa.

[0051] The discharge path from the zero potential GND to the port BP is shown in Fig. 3, which includes two paths of the third discharge path 50 and the fourth discharge path 51. When the voltage difference between the two paths is large, the discharge current difference between the two paths is also large. The balancing device 34 is triggered to conduct when the voltage difference between the two sides is large, forming the ninth discharge path 52. Figure 5

[0052] The discharge path from the port VBAT to the zero potential GND is shown in Fig. 4, which includes two paths of the fifth discharge path 60 and the sixth discharge path 61. When the voltage difference between the two paths is large, the discharge current difference between the two paths is also large. The balancing device 34 is triggered to conduct when the voltage difference between the two sides is large, forming the tenth discharge path 62. Figure 6

[0053] The discharge path from the port INH2 to the zero potential GND is shown in Fig. 5, which includes two paths of the seventh discharge path 70 and the eighth discharge path 71. When the voltage difference between the two paths is large, the discharge current difference between the two paths is also large. The balancing device 34 is triggered to conduct when the voltage difference between the two sides is large, forming the eleventh discharge path 72. Figure 7

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some or all of the technical features. Such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.​​​

Claims

1. A high-voltage withstand and antistatic structure for a transceiver, characterized in that, Includes multiple corresponding ports, high-voltage diode structure, and equalization discharge channel balancing device; Each of the multiple corresponding ports is connected to a high-voltage diode structure on both sides. Each port is only open on one side, forming multiple corresponding port line groups. Each corresponding port line group forms at least two discharge channels. The high-voltage diode structure includes multiple reverse-biased diodes connected in series. The number of the multiple reverse-biased diodes connected in series is not less than six. The corresponding port line groups are connected in parallel in pairs to balance port discharge; The multiple corresponding port line groups are connected in parallel with equalization discharge channel balancing devices, which include multiple GGNMOS transistors connected in series, and the number of GGNMOS transistors connected in series is not less than 9.

2. The high voltage withstand and antistatic structure for a transceiver according to claim 1, characterized in that, The ports include BP port, BM port, VBAT port, WAKE port, INH1 port, and INH2 port.

3. The high voltage withstand and antistatic structure for a transceiver according to claim 1, characterized in that, The balancer connects only the two discharge channels formed by each corresponding port line group to balance the voltage on both sides of the corresponding ports.

4. The high voltage withstand and antistatic structure for a transceiver according to claim 1, characterized in that, The multiple corresponding port line groups are also connected in parallel to a zero potential, and high-voltage diode structures in the same direction are set on both sides of the zero potential.

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