Magnetic sensor circuit

Abstract

A magnetic sensor circuit capable of reducing unexpected mode transition is provided. The magnetic sensor circuit includes a magnetic sensor outputting a first sensor signal based on a magnetic flux density in a first direction, a magnetic sensor outputting a second sensor signal based on a magnetic flux density in a second direction orthogonal to the first direction, a signal processing circuit obtaining a first detection signal and a second detection signal each causing a low level and a high level to be mutually transitioned based on the first magnetic sensor signal and the second magnetic sensor signal, a driver outputting a first output voltage based on the first detection signal, a driver outputting a second output voltage based on the second detection signal, and a voltage monitoring circuit generating a mode signal in which a signal level is transitioned based on a transition of a voltage level of the input first output voltage and the second output voltage.

Description

Technical Field

[0001] This invention relates to a magnetic sensor circuit. Background Technology

[0002] Magnetic sensor circuits are sometimes configured to combine test terminals used for switching to the mode for operation checking (hereinafter referred to as "test mode") with existing terminals due to limitations in the number of terminals. For example, a magnetic sensor circuit that combines test terminals and output terminals has been proposed (see, for example, Patent Document 1).

[0003] In the magnetic field detection device described in Patent Document 1, a mode change signal (hereinafter referred to as a "mode change signal") is forcibly input from the output terminal to change the mode from the normal operating mode to the test mode, etc. The mode change signal is at a level that would not occur in the normal mode. If the mode change signal is detected based on the level of the input signal, the magnetic field detection device changes from the normal mode to the test mode.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2009-31225 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] However, in magnetic sensor circuits such as the magnetic field detection device described in Patent Document 1, when a short circuit occurs at the output terminal, the circuit may sometimes be unintentionally switched to test mode.

[0009] In view of the aforementioned circumstances, the present invention aims to provide a magnetic sensor circuit capable of reducing unexpected mode shifts.

[0010] Technical means to solve the problem

[0011] The magnetic sensor circuit of the present invention is characterized by comprising: a first magnetic sensor for detecting magnetic flux density in a first direction and outputting a first sensor signal based on the detected magnetic flux density in the first direction; a second magnetic sensor for detecting magnetic flux density in a second direction orthogonal to the first direction and outputting a second sensor signal based on the detected magnetic flux density in the second direction; and a signal processing circuit having a mode signal input terminal for inputting a mode signal, a first sensor signal input terminal for inputting the first sensor signal, and a second sensor signal input terminal for inputting the second sensor signal, and capable of switching between a normal mode and a test mode, wherein the normal mode outputs a first detection signal that switches between low and high levels based on the first sensor signal, and on the other hand, outputs a first detection signal that switches between low and high levels based on the second sensor signal. The system comprises: a signal that outputs a second detection signal that transitions between low and high levels, wherein the test mode performs a predetermined action different from the normal mode; a first driver that inputs the first detection signal in the normal mode and, on the other hand, inputs a test signal in the test mode, and outputs a first output voltage based on the input first detection signal or the test signal; a second driver that inputs the second detection signal in the normal mode and, on the other hand, inputs the test signal in the test mode, and outputs a second output voltage based on the input second detection signal or the test signal; and a voltage monitoring circuit that generates a mode signal having multiple different signal levels corresponding to the transition types of the voltage levels of the input first output voltage and the second output voltage.

[0012] The effects of the invention

[0013] According to the present invention, unexpected mode shifts can be reduced. Attached Figure Description

[0014] Figure 1 This is a circuit diagram illustrating a first configuration example of a magnetic sensor circuit according to an implementation method.

[0015] Figure 2 It is a characteristic diagram of the first sensor signal representing the magnetic flux density relative to the first direction.

[0016] Figure 3 This is a characteristic diagram of the second sensor signal representing the magnetic flux density relative to the second direction.

[0017] Figure 4 This is a circuit diagram illustrating an example of the configuration of a voltage monitoring circuit in a magnetic sensor circuit according to an embodiment.

[0018] Figure 5This is an explanatory diagram showing the time variations of the magnetic flux density in the first direction, the magnetic flux density in the second direction, the first output voltage, the second output voltage, the first mode signal, and the second mode signal in the normal mode of the magnetic sensor circuit of the embodiment.

[0019] Figure 6 (A) is an explanatory diagram showing the time variation of the first output voltage in the test mode of the magnetic sensor circuit of the embodiment. Figure 6 (B) is an explanatory diagram showing the time variation of the second output voltage in the test mode of the magnetic sensor circuit of the embodiment. Figure 6 (C) is an explanatory diagram showing the time variation of the first mode signal under the test mode of the magnetic sensor circuit of the embodiment. Figure 6 (D) is an explanatory diagram showing the time variation of the second mode signal under the test mode of the magnetic sensor circuit of the embodiment.

[0020] Figure 7 This is an explanatory diagram illustrating the time variations of the first output voltage, second output voltage, first rising edge detection signal, first falling edge detection signal, second rising edge detection signal, and second falling edge detection signal in the action-related signals during the test mode.

[0021] Figure 8 This is an explanatory diagram illustrating the time variations of the first output voltage, second output voltage, reset signal, first clock signal, second clock signal, first mode signal, and second mode signal in the action-related signals under the first test mode.

[0022] Figure 9 This is a circuit diagram illustrating a second configuration example of the magnetic sensor circuit according to an implementation method.

[0023] Figure 10 This is a circuit diagram showing a modified example of a voltage monitoring circuit with three output voltage input terminals and two output mode signals.

[0024] Figure 11 This is a circuit diagram showing a modified example of a voltage monitoring circuit with two output voltage input terminals.

[0025] Figure 12 This is a circuit diagram showing a modified example of a voltage monitoring circuit with three output voltage input terminals.

[0026] [Explanation of Symbols]

[0027] 10, 70: Magnetic sensor circuit

[0028] 11: Magnetic sensor (first magnetic sensor)

[0029] 12: Magnetic sensor (second magnetic sensor)

[0030] 13: Magnetic sensor (third magnetic sensor)

[0031] 20, 120: Signal processing circuit

[0032] 20a: Input terminal (first sensor signal input terminal)

[0033] 20b: Input terminal (second sensor signal input terminal)

[0034] 120c: Input terminal (third sensor signal input terminal)

[0035] 20d: Input terminal (mode signal input terminal)

[0036] 20e~20f, 120e~120g: Output terminals

[0037] 31: Driver (First Driver)

[0038] 32: Driver (Second Driver)

[0039] 33: Drive (Third Drive)

[0040] 40, 60, 60A: Voltage monitoring circuit

[0041] 40a, 40b, 60a, 60b, 60c, 60Aa, 60Ab, 60Ac: Input terminals (output voltage input terminals)

[0042] 40d, 60d: Mode signal generation circuit

[0043] 40e, 40f, 60e, 60f, 60g: Output terminals

[0044] 41a: Edge detection circuit (first edge detection circuit)

[0045] 41b: Edge detection circuit (second edge detection circuit)

[0046] 43: Determination Circuit

[0047] 45a, 45b: Latch circuit (signal generation circuit)

[0048] Ss1, Ss2, Ss3: First sensor signal, second sensor signal, third sensor signal

[0049] Vx, Vz, Vy: First detection signal, second detection signal, third detection signal

[0050] Vo1, Vo2, Vo3: First output voltage, second output voltage, third output voltage

[0051] Sm0~Sm7: Mode signals Detailed Implementation

[0052] Hereinafter, the magnetic sensor circuit of an embodiment of the present invention will be described with reference to the accompanying drawings.

[0053] Figure 1 This is a circuit diagram of a magnetic sensor circuit 10, which is an example (first configuration example) of a magnetic sensor circuit as an implementation method. Figure 1 The X, Y, and Z axes shown are the X, Y, and Z axes in the XYZ three-dimensional orthogonal coordinate system. Therefore, the X, Y, and Z axes are mutually orthogonal.

[0054] Figure 2 This is a characteristic graph representing the voltage Vx as the first detection signal relative to the magnetic flux density Bx. Figure 3 This is a characteristic graph representing the voltage Vz as the second detection signal relative to the magnetic flux density Bz.

[0055] In the magnetic sensor circuit 10, it is configured to switch between a normal mode for normal operation and at least one test mode. The magnetic sensor circuit 10 is configured to detect magnetic flux density Bx, which is the X-axis component, and magnetic flux density Bz, which is the Z-axis component, existing within a detectable range, and output a first output voltage Vo1 corresponding to magnetic flux density Bx and a second output voltage Vo2 corresponding to magnetic flux density Bz.

[0056] The magnetic sensor circuit 10 includes a magnetic sensor 11, a magnetic sensor 12, a signal processing circuit 20, a driver 31, a driver 32, and a voltage monitoring circuit 40. Additionally, the magnetic sensor circuit 10 includes power supply terminals 1 and 2, and output terminals 51 and 52. A voltage VDD, serving as a first power supply voltage, is supplied to power supply terminal 1. A voltage VSS, serving as a second power supply voltage, is supplied to power supply terminal 2.

[0057] The magnetic sensor 11, which is the first magnetic sensor, detects the magnetic flux density Bx in the X-axis direction, which is the first direction, and has an output terminal that outputs a first sensor signal Ss1 based on the detected magnetic flux density Bx.

[0058] The magnetic sensor 12, which serves as the second magnetic sensor, detects the magnetic flux density Bz in the Z-axis direction, which is the second direction, and has an output terminal that outputs a second sensor signal Ss2 based on the detected magnetic flux density Bz.

[0059] The signal processing circuit 20 has an input terminal 20a as a first sensor signal input terminal, an input terminal 20b as a second sensor signal input terminal, and an input terminal 20d as a mode signal input terminal. Additionally, the signal processing circuit 20 has an output terminal 20e for outputting a first detection signal and an output terminal 20f for outputting a second detection signal.

[0060] The first detection signal and the second detection signal are generated by the signal processing circuit 20 based on the first sensor signal Ss1 and the second sensor signal Ss2, respectively. The first detection signal and the second detection signal are generated by setting a low level (in...) Figure 2 (hereinafter referred to as "L") and high level (in) Figure 2 The logic signals that transform into each other (referred to as "H" in the following diagrams) are shown. The voltage Vx as the first detection signal and the voltage Vz as the second detection signal respectively illustrate the hysteresis characteristics (see [reference]). Figure 2 and Figure 3 ).

[0061] The driver 31, serving as the first driver, has an input terminal for an input voltage Vx and an output terminal for outputting a first output voltage Vo1 based on the voltage Vx input to the input terminal. The output terminal of the driver 31 is connected to the output terminal 51.

[0062] The driver 32, serving as the second driver, has an input terminal for an input voltage Vz and an output terminal for outputting a second output voltage Vo2 based on the voltage Vz input to the input terminal. The output terminal of the driver 32 is connected to the output terminal 52.

[0063] The voltage monitoring circuit 40 has input terminals 40a and 40b for respectively inputting a first output voltage Vo1 and a second output voltage Vo2. Input terminals 40a and 40b are connected to the output terminals of driver 31 and driver 32, respectively. The connection point between input terminal 40a, the output terminal of driver 31, and output terminal 51 is node N1. The connection point between input terminal 40b, the output terminal of driver 32, and output terminal 52 is node N2.

[0064] In addition, the voltage monitoring circuit 40 has an output terminal 40e and an output terminal 40f. The output terminal 40e outputs a mode signal Sm1, which is generated as a first mode signal based on the first output voltage Vo1, and the output terminal 40f outputs a mode signal Sm2, which is generated as a second mode signal based on the second output voltage Vo2.

[0065] Mode signals Sm1 and Sm2 are signals that switch between low and high levels, respectively. The first output voltage Vo1 and the second output voltage Vo2 are generated by the voltage monitoring circuit 40 based on voltages Vx and Vz, respectively.

[0066] Output terminals 51 and 52 are respectively connected to input terminals 40a and 40b, which serve as the output voltage input terminals of the voltage monitoring circuit 40, forming a terminal group. Output terminals 51 and 52 are configured to connect to an external circuit (not shown). Furthermore, output terminal 51 is configured to supply a first output voltage Vo1 to the connected external circuit. Output terminal 52 is configured to supply a second output voltage Vo2 to the connected external circuit.

[0067] Figure 4 This is a circuit diagram showing an example of the configuration of the voltage monitoring circuit 40.

[0068] The voltage monitoring circuit 40 includes: input terminals 40a and 40b, which serve as output voltage input terminals; a mode signal generation circuit 40d that generates mode signals Sm1 and Sm2 based on the first output voltage Vo1 and the second output voltage Vo2, respectively; and output terminals 40e and 40f.

[0069] The pattern signal generation circuit 40d includes a first edge detection circuit 41a and a second edge detection circuit 41b, a determination circuit 43, and latching circuits 45a and 45b, which serve as signal generation circuits.

[0070] The first edge detection circuit 41a includes an output voltage input terminal connected to the input terminal 40a, a first output terminal connected to the first input terminal of the determination circuit 43, and a second output terminal connected to the second input terminal of the determination circuit 43.

[0071] The first edge detection circuit 41a is configured to detect the rising edge and falling edge of the first output voltage Vo1, and generate a first rising edge detection signal DTR1 corresponding to the detected rising edge and a first falling edge detection signal DTF1 corresponding to the detected falling edge.

[0072] The second edge detection circuit 41b differs from the first edge detection circuit 41a in that the output voltage processed is the second output voltage Vo2, but its structure is the same as that of the first edge detection circuit 41a. Specifically, the second edge detection circuit 41b is configured to detect the rising and falling edges of the second output voltage Vo2, generating a second rising edge detection signal DTR2 corresponding to the detected rising edge and a second falling edge detection signal DTF2 corresponding to the detected falling edge.

[0073] The determination circuit 43 includes a first input terminal to a sixth input terminal, an RST output terminal, a CLK1 output terminal, and a CLK2 output terminal. In the determination circuit 43, the first input terminal to the sixth input terminal are connected as follows.

[0074] The first input terminal is connected to the first output terminal of the first edge detection circuit 41a. The second input terminal is connected to the second output terminal of the first edge detection circuit 41a. The third input terminal is connected to input terminal 40a. The fourth input terminal is connected to the first output terminal of the second edge detection circuit 41b. The fifth input terminal is connected to the second output terminal of the second edge detection circuit 41b. The sixth input terminal is connected to input terminal 40b.

[0075] The determination circuit 43 is configured to determine whether there is a specific transition type based on the first rising edge detection signal DTR1, the first falling edge detection signal DTF1, the second rising edge detection signal DTR2, and the second falling edge detection signal DTF2, and generate a first clock signal CLK1, a second clock signal CLK2, and a reset signal RST as determination result signals representing the determination result.

[0076] The specific transition type (hereinafter referred to as "specific transition type") set in the determination circuit 43 includes multiple types. The maximum number X of specific transition types that can be set in the determination circuit 43 depends on the number of output voltages input to the determination circuit 43, i.e., n (a natural number). Specifically, X = 2 n Established. The determination circuit 43 for inputting the first output voltage Vo1 and the second output voltage Vo2, i.e., the determination circuit 43 with n=2, can be set to a maximum of 4 (=2) 2 (Number of types)

[0077] Here, the four transformation types that can be set in the determination circuit 43 are set to the first type to the fourth type.

[0078] For example, the first type is one where both the voltage levels of the first output voltage Vo1 and the second output voltage Vo2 transition from a low level to a high level within a specified time. The specified time is the time width considered as simultaneous and is preset.

[0079] The second type is one in which, within the specified time, the voltage level of the first output voltage Vo1 changes from low to high, and the voltage level of the second output voltage Vo2 changes from high to low.

[0080] The third type is the type in which, within the specified time, the voltage level of the first output voltage Vo1 changes from high to low, and the voltage level of the second output voltage Vo2 changes from low to high.

[0081] The fourth type is the type in which the voltage levels of the first output voltage Vo1 and the second output voltage Vo2 both change from high to low within a specified time.

[0082] The first latch circuit 45a and the second latch circuit 45b are composed of so-called D latch circuits, receiving power from the power supply terminal 47. The first latch circuit 45a includes an input terminal (D terminal) connected to the output terminal of CLK1, an R terminal connected to the RST output terminal of the determination circuit 43, and an output terminal (Q terminal) connected to the output terminal 40e. The second latch circuit 45b includes an input terminal (D terminal) connected to the output terminal of CLK2, an R terminal connected to the RST output terminal of the determination circuit 43, and an output terminal (Q terminal) connected to the output terminal 40f.

[0083] The function and effect of the magnetic sensor circuit 10 described above will be explained. First, the operation of the magnetic sensor circuit 10 in normal mode will be explained.

[0084] Figure 5 This is an explanatory diagram showing the time variations of magnetic flux density Bx, magnetic flux density Bz, first output voltage Vo1, second output voltage Vo2, mode signal Sm1, and mode signal Sm2 in the normal mode of the magnetic sensor circuit 10.

[0085] In normal mode, an alternating magnetic field with a 90-degree phase shift is formed around the magnetic sensor circuit 10. The magnetic flux density Bx and magnetic flux density Bz detected by the magnetic sensor circuit 10 are detected as sine waves with the same maximum amplitude and period. In addition, the magnetic flux density Bx and magnetic flux density Bz are phase-shifted by 90 degrees.

[0086] about Figure 5 The magnetic flux densities Bx and Bz illustrated herein are explained with reference to the period from t = 0 (zero) to t7 (0 ≤ t ≤ t7). Magnetic flux densities Bx and Bz are sinusoidal waves with a period from t = 0 to t = t6. Here, magnetic flux densities Bopx and Bopz are the operating points of magnetic flux densities Bx and Bz, respectively. Magnetic flux densities Brpx and Brpz are the recovery points of magnetic flux densities Bx and Bz, respectively. Furthermore, magnetic flux densities Bx and Bz > 0 represent the S pole, and magnetic flux densities Bx and Bz < 0 represent the N pole.

[0087] The magnetic flux density Bx is zero at time t = 0. Thereafter, the magnetic flux density at the south pole of Bx gradually increases, reaching Bopx at time t = t1 and its maximum value at time t = t2. After time t = t2, the magnetic flux density at the south pole of Bx gradually decreases, reaching Bopx at time t = t3, and then reaches zero (t3 < t < t4).

[0088] After the magnetic flux density Bx reaches 0, its polarity reverses, and the magnetic flux density at the N pole gradually increases, becoming the magnetic flux density Brpx at time t = t4. Then, after reaching its maximum value at the N pole (t4 < t < t5), the magnetic flux density at the N pole gradually decreases, becoming the magnetic flux density Brpx at time t = t5, and then reaching 0 at time t = t6. This increase and decrease then repeats periodically from time t = 0 to t = t6 (0 ≤ t < t6). Therefore, at time t = t7 (= t6 + t1) after t1 from time t = t6, the magnetic flux density Bx becomes the magnetic flux density Bopx.

[0089] The magnetic flux density Bz is, for example, phase-delayed by 90 degrees relative to the magnetic flux density Bx. That is, the magnetic flux density Bz reaches its maximum value at time t = 0, and then gradually decreases with time, reaching Brpz at time t = t1, and then reaching 0 at time t = t2. After reaching 0, the polarity of the magnetic flux density Bz reverses, and the magnetic flux density at the S pole gradually increases, reaching Brpz at time t = t3.

[0090] After time t = t3, the magnetic flux density at the S pole further increases and reaches its maximum value (t3 < t < t4), then decreases, reaching a magnetic flux density Bopz at time t = t4, and subsequently reaches 0 (t4 < t < t5). After reaching 0, the magnetic flux density Bz reverses polarity, and the magnetic flux density at the N pole gradually increases, reaching a magnetic flux density Brpz at time t = t5, and then reaching its maximum value at time t = t6. After time t = t6, the increase and decrease from time t = 0 to t6 (0 ≦ t < t6) repeats periodically. Therefore, at time t = t7 (= t6 + t1), after t1 from time t = t6, the magnetic flux density Bz becomes the magnetic flux density Brpz.

[0091] Magnetic sensor 11 detects magnetic flux density Bx and transmits the first sensor signal Ss1 corresponding to the detected magnetic flux density Bx to signal processing circuit 20. Magnetic sensor 12 detects magnetic flux density Bz and transmits the second sensor signal Ss2 corresponding to the detected magnetic flux density Bz to signal processing circuit 20.

[0092] When the signal processing circuit 20 receives the first sensor signal Ss1, it transmits a voltage Vx to the driver 31 that corresponds to the magnetic flux density Bx corresponding to the first sensor signal Ss1.

[0093] The voltage Vx is high during the time period t, where 0 ≤ t < t1 and t4 ≤ t < t6. On the other hand, the voltage Vx is low during the time period t, where t1 ≤ t < t4.

[0094] Furthermore, when the signal processing circuit 20 receives the second sensor signal Ss2, it transmits a voltage Vz to the driver 32 corresponding to the magnetic flux density Bz corresponding to the second sensor signal Ss2. The voltage Vz is high during the period t where 0 ≤ t < t3 and t5 ≤ t < t6. Conversely, the voltage Vz is low during the period t where t3 ≤ t < t5.

[0095] When driver 31 receives voltage Vx as a first detection signal, it transmits a first output voltage Vo1 to output terminal 51 and voltage monitoring circuit 40 based on the first detection signal. When driver 32 receives voltage Vz as a second detection signal, it transmits a second output voltage Vo2 to output terminal 52 and voltage monitoring circuit 40 based on the second detection signal.

[0096] The first output voltage Vo1 and the second output voltage Vo2 periodically switch between low and high levels. During the period t is 0 ≤ t < t6, that is, in one cycle, the first output voltage Vo1 maintains a high level during the period 0 ≤ t < t1, transitions to a low level at time t = t1, maintains a low level during the period t1 ≤ t < t4, transitions to a high level at time t = t4, and maintains a high level during the period t4 ≤ t < t6.

[0097] The second output voltage Vo2 maintains a high level during the period t = 0 ≤ t < t6, i.e., one cycle, during the period t = 0 ≤ t < t3, transitions to a low level at t = t3, maintains a low level during the period t3 ≤ t < t5, transitions to a high level at t = t5, and maintains a high level during the period t5 ≤ t < t6.

[0098] The changes in the first output voltage Vo1 and the second output voltage Vo2 after time t = t6 are the same as those during the period t = 0 ≤ t < t6. That is, the voltage level transitions of the first output voltage Vo1 and the second output voltage Vo2 are repeated periodically during the period t = 0 ≤ t < t6.

[0099] As described above, in the normal mode, the period of the first output voltage Vo1 is the same as the period of the second output voltage Vo2. Furthermore, in the normal mode, since the first output voltage Vo1 is offset by 1 / 4 period relative to the second output voltage Vo2, the voltage levels of the two output voltages will not change simultaneously.

[0100] The first output voltage Vo1 is supplied to the external circuit via voltage monitoring circuit 40 and output terminal 51 (illustration omitted). The second output voltage Vo2 is supplied to the external circuit via voltage monitoring circuit 40 and output terminal 52.

[0101] The voltage monitoring circuit 40 generates mode signals Sm1 and Sm2 corresponding to the transition types of the input first output voltage Vo1 and second output voltage Vo2, and transmits mode signals Sm1 and Sm2 to the signal processing circuit 20. As multiple mode signals, mode signals Sm1 and Sm2 each have different signal levels, including low and high levels.

[0102] When mode signals Sm1 and Sm2 are input from voltage monitoring circuit 40, signal processing circuit 20 identifies the input mode signals Sm1 and Sm2 as, for example, a two-bit signal. Therefore, signal processing circuit 20 can identify a normal mode and up to three different test modes.

[0103] For example, when a correspondence is established between the normal mode and both mode signals Sm1 and Sm2 being low, during the execution of the normal mode, such as... Figure 5 As illustrated, during the period t = 0 ≤ t < t6, both the first mode signal Sm1 and the second mode signal Sm2 are output at a low level.

[0104] Next, as an example of normal mode and test mode, the operation of the magnetic sensor circuit 10 in test mode, which includes three test modes: first test mode TM1, second test mode TM2, and third test mode TM3, will be explained.

[0105] In the magnetic sensor circuit 10, which has one normal mode and three test modes, four specific transition types are set in the voltage monitoring circuit 40, and more specifically in the determination circuit 43, among the voltage level transition types of the first output voltage Vo1 and the second output voltage Vo2.

[0106] The four specific transition types set in the determination circuit 43 are the first type to the fourth type. The first type to the fourth type, as the four specific transition types, correspond to the signal levels of mode signals Sm1 and Sm2. Furthermore, in the signal processing circuit 20, the signal levels of mode signals Sm1 and Sm2 correspond to four modes: a normal mode, a first test mode TM1, a second test mode TM2, and a third test mode TM3. Here, as an example of the correspondence between the first type to the fourth type, the signal levels of mode signals Sm1 and Sm2, and the modes, the following correspondence establishment will be explained.

[0107] The first type establishes a correspondence with the high-level mode signal Sm1 and the low-level mode signal Sm2. The high-level mode signal Sm1 and the low-level mode signal Sm2 establish a correspondence with the first test mode TM1. That is, the first type establishes a correspondence with the first test mode TM1.

[0108] The second type corresponds to the low-level mode signal Sm1 and the high-level mode signal Sm2. The low-level mode signal Sm1 and the high-level mode signal Sm2 correspond to the second test mode TM2. That is, the second type corresponds to the second test mode TM2.

[0109] The third type corresponds to the high-level mode signals Sm1 and Sm2. The high-level mode signals Sm1 and Sm2 correspond to the third test mode TM3. The third type corresponds to the third test mode TM3.

[0110] The fourth type corresponds to the low-level mode signals Sm1 and Sm2. The low-level mode signals Sm1 and Sm2 correspond to the normal mode. That is, the fourth type corresponds to the normal mode.

[0111] Figure 6 (A) and Figure 6 (B) is an explanatory diagram showing the time variation of the first output voltage Vo1 and the second output voltage Vo2 in the test mode of the magnetic sensor circuit 10. Figure 6 (C) and Figure 6 (D) is an explanatory diagram representing the time variations of mode signals Sm1 and Sm2, respectively.

[0112] Before switching to test mode, an inspection device, including external circuitry, is connected to output terminals 51 and 52. The inspection device has the function of generating a specified magnetic field and applying a first output voltage Vo1 and a second output voltage Vo2 from the outside. By applying the specified magnetic field or by applying the first output voltage Vo1 and the second output voltage Vo2 from the outside, the inspection device supplies the voltage monitoring circuit 40 with the first output voltage Vo1 and the second output voltage Vo2, whose voltage levels change according to a specific transition type.

[0113] At time t = t10, the testing device forcibly applies a first output voltage Vo1 and a second output voltage Vo2, transitioning from high to low level, to output terminals 51 and 52, respectively. At time t = t10, when the first output voltage Vo1 and the second output voltage Vo2, transitioning from high to low level, are input from output terminals 51 and 52, they are transmitted to the voltage monitoring circuit 40.

[0114] When the voltage monitoring circuit 40 receives the first output voltage Vo1 and the second output voltage Vo2 transitioning from high level to low level at time t = t10, it generates mode signals Sm1 and Sm2 corresponding to the first type establishment and transmits them to the signal processing circuit 20. The mode signals Sm1 and Sm2 transmitted to the signal processing circuit 20 are high level and low level, respectively.

[0115] When the signal processing circuit 20 receives a high-level mode signal Sm1 and a low-level mode signal Sm2, it changes the mode of the magnetic sensor circuit 10 to a mode corresponding to the signal levels of mode signals Sm1 and Sm2, namely, the first test mode TM1. The magnetic sensor circuit 10, having selected the first test mode TM1, operates according to preset parameters as the first test. These preset parameters include, for example, operating with a faster reference clock than when the normal mode is selected, and supplying a higher internal power supply voltage than when the normal mode is selected.

[0116] Next, at time t = t11, the inspection device forcibly applies a first output voltage Vo1 and a second output voltage Vo2, transitioning from low to high level, to output terminals 51 and 52, respectively. At time t = t11, when the first output voltage Vo1 and the second output voltage Vo2, transitioning from low to high level, are input from output terminals 51 and 52, they are transmitted to the voltage monitoring circuit 40.

[0117] When the voltage monitoring circuit 40 receives the first output voltage Vo1 and the second output voltage Vo2 transitioning from low level to high level at time t = t11, it generates mode signals Sm1 and Sm2 corresponding to the fourth type establishment and transmits them to the signal processing circuit 20.

[0118] When the signal processing circuit 20 receives the mode signals Sm1 and Sm2 corresponding to the fourth type of establishment at time t = t11, it causes the magnetic sensor circuit 10 to switch to the normal mode corresponding to the signal levels of the mode signals Sm1 and Sm2.

[0119] Next, before the testing device switches the magnetic sensor circuit 10 to the second test mode TM2 at time t=t13, at time t=t12, a first output voltage Vo1, which transitions from a high level to a low level, is forcibly applied from the output terminal 51.

[0120] Next, at time t = t13, the inspection device forcibly applies a first output voltage Vo1, which transitions from a low level to a high level, and a second output voltage Vo2, which transitions from a high level to a low level, respectively, from output terminal 51 and output terminal 52.

[0121] When the voltage monitoring circuit 40 receives the first output voltage Vo1 transitioning from low level to high level and the second output voltage Vo2 transitioning from high level to low level at time t = t13, it generates mode signals Sm1 and Sm2 corresponding to the second type establishment and transmits them to the signal processing circuit 20.

[0122] When the signal processing circuit 20 receives the mode signals Sm1 and Sm2 corresponding to the second type establishment at time t = t13, it causes the magnetic sensor circuit 10 to switch to the second test mode TM2. The magnetic sensor circuit 10, having selected the second test mode TM2, operates according to a preset program as the second test. The preset operation for the second test differs from the normal mode and the first test.

[0123] Next, before the testing device switches the magnetic sensor circuit 10 to normal mode at time t = t15, at time t = t14, which is before time t = t15 and after the test steps executed in the second test mode TM2 are completed, a first output voltage Vo1, transitioning from a high level to a low level, is forcibly applied from the output terminal 51. The operation of the magnetic sensor circuit 10 at times t = t14 and t15 is the same as the operation of the magnetic sensor circuit 10 at times t = t12 and t11, respectively.

[0124] Next, before the magnetic sensor circuit 10 switches to the third test mode TM3 at time t=t17, the testing device applies a second output voltage Vo2, which transitions from a high level to a low level, from the output terminal 52 at a time t=t16, which is after time t=t15 and before time t=t17.

[0125] Next, at time t = t17, the inspection device forcibly applies a first output voltage Vo1, which transitions from a high level to a low level, and a second output voltage Vo2, which transitions from a low level to a high level, from output terminal 51 and output terminal 52, respectively.

[0126] When the voltage monitoring circuit 40 receives the first output voltage Vo1 transitioning from high level to low level and the second output voltage Vo2 transitioning from low level to high level at time t = t17, it generates mode signals Sm1 and Sm2 corresponding to the third type establishment and transmits them to the signal processing circuit 20.

[0127] When the signal processing circuit 20 receives the mode signals Sm1 and Sm2 corresponding to the third type establishment at time t = t17, it causes the magnetic sensor circuit 10 to switch to the third test mode TM3. Regarding the magnetic sensor circuit 10 that has selected the third test mode TM3, the preset actions for the third test are different from those in the normal mode, the first test, and the second test.

[0128] Next, before the testing device switches the magnetic sensor circuit 10 to normal mode at time t = t19, at time t = t18, which is before time t = t19 and after the test steps executed in the third test mode TM3 are completed, a second output voltage Vo2, transitioning from a high level to a low level, is forcibly applied from the output terminal 52. The operation of the magnetic sensor circuit 10 at time t = t19 is the same as the operation of the magnetic sensor circuit 10 at times t = t11 and t15.

[0129] Next, the operation of the mode signal generation circuit 40d will be explained using the transition between the first test mode TM1 and the normal mode as an example. Furthermore, the establishment of the correspondence between the signal levels of the first test mode TM1 and the normal mode, the mode signal Sm1, and the mode signal Sm2, and the specific transition types (first mode and fourth mode) will be explained for cases similar to the example described.

[0130] Figure 7 This is an explanatory diagram illustrating the time variations of the first output voltage Vo1, the second output voltage Vo2, the first rising edge detection signal DTR1, the first falling edge detection signal DTF1, the second rising edge detection signal DTR2, and the second falling edge detection signal DTR2 in the action-related signals under the first test mode TM1.

[0131] Figure 8 This is an explanatory diagram illustrating the time variations of the first output voltage Vo1, the second output voltage Vo2, the reset signal RST, the first clock signal CLK1, the second clock signal CLK2, the mode signal Sm1, and the mode signal Sm2 in the action-related signals under the first test mode TM1.

[0132] Here, Figure 7 and Figure 8 The diagram is divided into two parts based on the relationship between the regions that can be plotted. Figure 7 The first output voltage Vo1, the second output voltage Vo2, the time axis t, and the time intervals t = t21 to t34 shown are respectively related to... Figure 8 The first output voltage Vo1, the second output voltage Vo2, the time axis t, and the time t = t21 to t34 shown are the same content.

[0133] First, the operation in the case where there is a delay relative to the first output voltage Vo1 without the generation of the second output voltage Vo2 will be explained. The operation in the case where there is a delay relative to the first output voltage Vo1 without the generation of the second output voltage Vo2 is the operation in the time period after t = t21 and before t24, which is the operation when the delay time td1 = 0.

[0134] At time t = t21, the voltage levels of both the first output voltage Vo1 and the second output voltage Vo2 transition from high to low. Therefore, the first edge detection circuit 41a detects the falling edge of the first output voltage Vo1 and, during time td, sets the first falling edge detection signal DTF1 to high. The second edge detection circuit 41b detects the falling edge of the second output voltage Vo2 and, during time td, sets the second falling edge detection signal DTF2 to high. The time td corresponds to the specified time, i.e., the time width considered as simultaneous.

[0135] In addition, the determination circuit 43 determines that the first type exists based on the low-level first rising edge detection signal DTR1, the high-level first falling edge detection signal DTF1, the low-level second rising edge detection signal DTR2, and the high-level second falling edge detection signal DTF2.

[0136] The determination circuit 43 outputs a first clock signal CLK1, a second clock signal CLK2, and a reset signal RST, corresponding to the determination result of whether a specific transition type exists. When the determination circuit 43 determines that the first type exists, it sends the high-level first clock signal CLK1 and the low-level reset signal RST to the first latch circuit 45a as a determination result signal indicating that the first type "exists", and sends the low-level second clock signal CLK2 and the low-level reset signal RST to the second latch circuit 45b.

[0137] The first latch circuit 45a receives a high-level first clock signal CLK1 and a low-level reset signal RST from the determination circuit 43, causing the mode signal Sm1 to change to a high level.

[0138] During the period td from time t = t21, the first edge detection circuit 41a maintains a high level on the first falling edge detection signal DTF1. The second edge detection circuit 41b maintains a high level on the second falling edge detection signal DTF2. The determination circuit 43 maintains a high level on the first clock signal CLK1.

[0139] At time t=t22, after time td has elapsed since time t=t21, the first edge detection circuit 41a and the second edge detection circuit 41b respectively cause the first falling edge detection signal DTF1 and the second falling edge detection signal DTF2 to change from high level to low level. On the other hand, the first latch circuit 45a maintains the high level of the mode signal Sm1.

[0140] Next, at time t = t23, the voltage levels of both the first output voltage Vo1 and the second output voltage Vo2 change from low to high. Therefore, the first edge detection circuit 41a detects the rising edge of the first output voltage Vo1 and causes the first rising edge detection signal DTR1 to go high during time td. The second edge detection circuit 41b detects the rising edge of the second output voltage Vo2 and causes the second rising edge detection signal DTR2 to go high during time td.

[0141] In addition, the determination circuit 43 determines the existence of a fourth type based on the high-level first rising edge detection signal DTR1, the low-level first falling edge detection signal DTF1, the high-level second rising edge detection signal DTR2, and the low-level second falling edge detection signal DTF2.

[0142] When the determination circuit 43 determines that a fourth type exists, it sends a low-level first clock signal CLK1 and a high-level reset signal RST to the first latch circuit 45a as a determination result signal indicating that the fourth type "exists," and sends a low-level second clock signal CLK2 and a high-level reset signal RST to the second latch circuit 45b. The first latch circuit 45a receives the high-level reset signal RST from the determination circuit 43, causing the mode signal Sm1 to go low.

[0143] During the time period td starting from time t = t23, the first edge detection circuit 41a maintains a high level on the first rising edge detection signal DTR1. The second edge detection circuit 41b maintains a high level on the second rising edge detection signal DTR2.

[0144] At time t=t24, after time td has elapsed since time t=t23, the first edge detection circuit 41a and the second edge detection circuit 41b respectively cause the first rising edge detection signal DTR1 and the second rising edge detection signal DTR2 to change from high level to low level. The determination circuit 43 causes the reset signal RST to change from high level to low level.

[0145] Next, the action is explained when the second output voltage Vo2 is delayed within a specified time relative to the first output voltage Vo1. The action when the second output voltage Vo2 is delayed within a specified time relative to the first output voltage Vo1 is the action during the time period after t = t25 and before t29, which is the action when the delay time td1 is less than or equal to time td (td1 ≦ td).

[0146] At time t = t25, the voltage level of the first output voltage Vo1 changes from high to low. Therefore, the first edge detection circuit 41a detects the falling edge of the first output voltage Vo1 and, during time td, causes the first falling edge detection signal DTF1 to go high.

[0147] At time t=26, after a delay of td1 from time t=t25, the voltage level of the second output voltage Vo2 changes from high to low. Therefore, the second edge detection circuit 41b detects the falling edge of the second output voltage Vo2 and, during time td, causes the second falling edge detection signal DTF2 to go high.

[0148] Additionally, at time t = t26, the determination circuit 43 determines that the first type exists based on the low-level first rising edge detection signal DTR1 and the high-level first falling edge detection signal DTF1 received at time t = t25, and the low-level second rising edge detection signal DTR2 and the high-level second falling edge detection signal DTF2 received at time t = t26.

[0149] When the determination circuit 43 determines that the first type exists, it sends a high-level first clock signal CLK1 and a low-level reset signal RST to the first latch circuit 45a as a determination result signal indicating that the first type "exists," and sends a low-level second clock signal CLK2 and a low-level reset signal RST to the second latch circuit 45b. The first latch circuit 45a receives the high-level first clock signal CLK1 and the low-level reset signal RST from the determination circuit 43, causing the mode signal Sm1 to go high.

[0150] The first edge detection circuit 41a maintains a high level for the first falling edge detection signal DTF1 during the time period td starting from time t = t25. The second edge detection circuit 41b maintains a high level for the second falling edge detection signal DTF2 during the time period td starting from time t = t26. The determination circuit 43 maintains a high level for the first clock signal CLK1 during the time period td starting from time t = t25, i.e., the time period td-td1 starting from time t = t26, while maintaining a high level for the first falling edge detection signal DTF1.

[0151] Next, after time td elapsed from time t = t25, and after time td - td1 elapsed from time t = t26, i.e., at time t = t27, the first edge detection circuit 41a causes the first falling edge detection signal DTF1 to transition from high to low. The determination circuit 43 causes the first clock signal CLK1 to transition from high to low. On the other hand, the first latch circuit 45a maintains the high level of the mode signal Sm1. Furthermore, after time td elapsed from time t = t26, the second edge detection circuit 41b causes the second falling edge detection signal DTF2 to transition from high to low.

[0152] Next, at time t = t28, the voltage levels of both the first output voltage Vo1 and the second output voltage Vo2 change from low to high. The voltage level transition of the first output voltage Vo1 and the second output voltage Vo2 at time t = t28 is the same as the voltage level transition of the first output voltage Vo1 and the second output voltage Vo2 described above at time t = t23. The first edge detection circuit 41a, the second edge detection circuit 41b, the determination circuit 43, and the first latch circuit 45a and the second latch circuit 45b at time t = t28 operate in the same manner as the first edge detection circuit 41a, the second edge detection circuit 41b, the determination circuit 43, and the first latch circuit 45a and the second latch circuit 45b described above at time t = t23.

[0153] Next, at time t = t29, the first edge detection circuit 41a and the second edge detection circuit 41b respectively cause the first rising edge detection signal DTR1 and the second rising edge detection signal DTR2 to change from high level to low level. The determination circuit 43 causes the reset signal RST to change from high level to low level.

[0154] Next, the operation when the second output voltage Vo2 is delayed by more than a specified time relative to the first output voltage Vo1 will be explained. The operation when the second output voltage Vo2 is delayed by more than a specified time relative to the first output voltage Vo1 is the operation during the time period after t = t30 and before t34, which is the operation when the delay time td2 is greater than the time td (td2 > td).

[0155] At time t = t30, the voltage level of the first output voltage Vo1 changes from high to low. Therefore, the first edge detection circuit 41a detects the falling edge of the first output voltage Vo1 and, during time td, sets the first falling edge detection signal DTF1 to high. Then, at time t = t31, a delay of time td from time t = t30, the first edge detection circuit 41a sets the first falling edge detection signal DTF1 to low.

[0156] At time t=32, after a delay of td2 from time t=t30, the voltage level of the second output voltage Vo2 changes from high to low. Therefore, the second edge detection circuit 41b detects the falling edge of the second output voltage Vo2 and, during time td, causes the second falling edge detection signal DTF2 to go high.

[0157] Next, at time t = t32, the determination circuit 43 determines that there is no specific transition type based on the low-level first rising edge detection signal DTR1 and high-level first falling edge detection signal DTF1 received at time t = t30, the low-level first falling edge detection signal DTF1 received at time t = t31, and the low-level second rising edge detection signal DTR2 and high-level second falling edge detection signal DTF2 received at time t = t32.

[0158] The reason for this determination is that, at time t=t32, after a time longer than time td has elapsed since the voltage level of the first output voltage Vo1 changed from high to low, the voltage level of the second output voltage Vo2 changed from high to low. That is, the reason is that the first type did not occur within the specified time.

[0159] When the determination circuit 43 determines that there is no specific transition type at time t = t32, it sends a low-level first clock signal CLK1 and a low-level reset signal RST to the first latch circuit 45a as a determination result signal indicating that there is no specific transition type. It also sends a low-level second clock signal CLK2 and a low-level reset signal RST to the second latch circuit 45b.

[0160] Next, at time t = t33, the voltage levels of both the first output voltage Vo1 and the second output voltage Vo2 change from low to high. The voltage level transition of the first output voltage Vo1 and the second output voltage Vo2 at time t = t33 is the same as the voltage level transitions of the first output voltage Vo1 and the second output voltage Vo2 described above at times t = t23 and t28. The first edge detection circuit 41a, the second edge detection circuit 41b, the determination circuit 43, and the first latch circuit 45a and the second latch circuit 45b at time t = t33 operate in the same manner as the first edge detection circuit 41a, the second edge detection circuit 41b, the determination circuit 43, and the first latch circuit 45a and the second latch circuit 45b described above at times t = t23 and t28.

[0161] Next, at time t = t34, the first edge detection circuit 41a and the second edge detection circuit 41b respectively cause the first rising edge detection signal DTR1 and the second rising edge detection signal DTR2 to change from high level to low level. The determination circuit 43 causes the reset signal RST to change from high level to low level.

[0162] Next, other configuration examples (modifications) of the magnetic sensor circuit of this embodiment will be described.

[0163] Figure 9 This is a circuit diagram of magnetic sensor circuit 70, which is an example (second configuration example) of magnetic sensor circuit in this embodiment.

[0164] The magnetic sensor circuit 70 differs from the magnetic sensor circuit 10, which has two mutually orthogonal magnetic detection axes (X-axis, Y-axis, and Z-axis), in that it is configured to have three mutually orthogonal magnetic detection axes (X-axis and Z-axis).

[0165] The magnetic sensor circuit 70 differs from the magnetic sensor circuit 10 in that it also includes a magnetic sensor 13 and a driver 33, and instead of signal processing circuit 20, it includes signal processing circuit 120, and instead of voltage monitoring circuit 40, it includes voltage monitoring circuit 60. In the magnetic sensor circuit 70, all aspects except for the aforementioned differences are the same as those in the magnetic sensor circuit 10. Signal processing circuit 120 and voltage monitoring circuit 60 are respectively configured to correspond to the three-axis magnetic detection axes relative to signal processing circuit 20 and voltage monitoring circuit 40.

[0166] The magnetic sensor 13, which serves as the third magnetic sensor, detects the magnetic flux density in the Y-axis direction, which is the third direction, and has an output terminal that outputs a third sensor signal Ss3 based on the detected magnetic flux density.

[0167] The signal processing circuit 120 has input terminals 120a, 120b, and 120c, which serve as first sensor signal input terminals, second sensor signal input terminals, and third sensor signal input terminals, an input terminal 120d, which serves as a mode signal input terminal, and output terminals 120e to 120g. Input terminals 120c and 120d (part of the third sensor signal input terminal) and output terminal 120g are additionally provided relative to the signal processing circuit 20.

[0168] The signal processing circuit 120 receives the third sensor signal Ss3 from the input terminal 120c, generates a third detection signal based on the third sensor signal Ss3, and sends it to the driver 33 from the output terminal 120g. Similar to the first and second detection signals, the third detection signal is a logic signal that switches between low and high levels, exhibiting hysteresis characteristics.

[0169] Additionally, the signal processing circuit 120 receives three mode signals from the input terminal 120d: mode signals Sm1, Sm2, and Sm3, which serve as the first mode signal, the second mode signal, and the third mode signal, respectively. The input terminal 120d is configured relative to the input terminal 20d as a mode signal input terminal containing the mode signal Sm3. The signal processing circuit 120 receives the three mode signals, namely the first mode signal Sm1, the second mode signal Sm2, and the third mode signal Sm3, as a three-bit signal. The signal processing circuit 120 can set up to 8 (= 2) modes, including the normal mode. 3 (Number of types)

[0170] The driver 33, serving as the third driver, has an input terminal for receiving a voltage of a third detection signal and an output terminal for outputting a third output voltage Vo3 based on the voltage input to the input terminal. The output terminal of the driver 33 is connected to the output terminal 53.

[0171] The voltage monitoring circuit 60 has a functionally extended mode signal generation circuit (not shown) for three detection axes, and is configured to generate three mode signals with multiple different signal levels corresponding to the voltage level transition types of the three input output voltages. The voltage monitoring circuit 60 has: input terminals 60a, 60b, and 60c, for inputting a first output voltage Vo1, a second output voltage Vo2, and a third output voltage Vo3, respectively; a mode signal generation circuit 60d, for generating mode signals Sm1, Sm2, and Sm3; and output terminals 60e, 60f, and 60g, for outputting mode signals Sm1, Sm2, and Sm3, respectively.

[0172] Input terminals 60a, 60b, and 60c are connected to the respective output terminals of drivers 31, 32, and 33. Output terminals 60e, 60f, and 60g are connected to input terminal 120d.

[0173] Output terminal 53 is connected to the output terminal of driver 33 and the input terminal 60c, which serves as the output voltage input terminal. The connection point between the output terminal of driver 33, output terminal 53, and input terminal 60c is node N3.

[0174] In the magnetic sensor circuit 70, output terminals 51, 52, and 53 constitute a terminal group. One terminal of the terminal group, namely output terminal 53, can be connected to an external circuit (not shown) and is configured to supply a third output voltage Vo3 to the connected external circuit.

[0175] In the magnetic sensor circuit 70, similarly to the magnetic sensor circuit 10, a first output voltage Vo1, a second output voltage Vo2, and a third output voltage Vo3 with specific transition types are supplied to the voltage monitoring circuit 60, thereby switching between the normal mode and the test mode. That is, the testing device applies a specified magnetic field or forcibly applies the first output voltage Vo1, the second output voltage Vo2, and the third output voltage Vo3 to the output terminals 51, 52, and 53, thereby switching the mode of the magnetic sensor circuit 70.

[0176] Additionally, a magnetic sensor circuit with three mutually orthogonal magnetic detection axes may also include a three-input, two-output voltage monitoring circuit. This circuit has three output voltage input terminals, two output terminals for outputting mode signals, and a main circuit with voltage monitoring functionality. The three-input, two-output voltage monitoring circuit is configured to output three inputs, specifically two output voltages selectable from a first output voltage Vo1, a second output voltage Vo2, and a third output voltage Vo3.

[0177] Figure 10 This is a circuit diagram of a voltage monitoring circuit 60A, which is an example of a three-input, two-output voltage monitoring circuit.

[0178] The voltage monitoring circuit 60A, for example, includes: a selection circuit 61 that selects two output voltages to be supplied to the main circuit from the input first output voltage Vo1, second output voltage Vo2, and third output voltage Vo3; and a voltage monitoring circuit 40 that has an output terminal that outputs two mode signals based on the two output voltages supplied to the main circuit.

[0179] The selection circuit 61 has three output voltage input terminals: input terminal 60Aa, input terminal 60Ab, and input terminal 60Ac, which serve as the voltage monitoring circuit 60A. The selection circuit 61 selects two output voltages to be supplied to the main circuit from a first output voltage Vo1, a second output voltage Vo2, and a third output voltage Vo3 input from input terminals 60Aa, 60Ab, and 60Ac, respectively. For example, a circuit for selecting two output voltages could include a switch capable of toggling between the two connected to input terminals 60Aa, 60Ab, and 60Ac, or between one not connected, or a logic circuit capable of performing a logic operation to select two or exclude one from the first output voltage Vo1, second output voltage Vo2, and third output voltage Vo3.

[0180] The voltage monitoring circuit 40 functions as the main circuit and output terminal of the voltage monitoring circuit 60A.

[0181] In this embodiment, the magnetic sensor circuit 10 and the magnetic sensor circuit 70 include a signal processing circuit 20 that receives the mode signal as a two-bit signal, but may also include a signal processing circuit 20 that receives the mode signal as a one-bit signal. Furthermore, the voltage monitoring circuit included in the magnetic sensor circuit 10 is not necessarily limited to the voltage monitoring circuit 40. The voltage monitoring circuit included in the magnetic sensor circuit 70 is not limited to the voltage monitoring circuit 60 or the voltage monitoring circuit 60A.

[0182] The voltage monitoring circuits included in magnetic sensor circuits 10 and 70 only need to include one normal mode and at least one test mode. Therefore, magnetic sensor circuit 10 only needs to include a voltage monitoring circuit configured to output up to four mode signals (i.e., two, three, or four modes). Similarly, magnetic sensor circuit 70 only needs to include a voltage monitoring circuit configured to output up to eight mode signals (i.e., any number from two to eight).

[0183] Figure 11 and Figure 12 These are circuit diagrams representing voltage monitoring circuit 140 and voltage monitoring circuit 160, respectively.

[0184] Instead of the voltage monitoring circuit 40 that outputs two mode signals, namely the first mode signal Sm1 and the second mode signal Sm2, the magnetic sensor circuit 10 may also have a voltage monitoring circuit 140, for example. The voltage monitoring circuit 140 has four output terminals 140d, 140e, 140f, and 140g, and outputs analog signals Sm0, Sm1, Sm2, and Sm3 as one-bit signals from the output terminals 140d, 140e, 140f, and 140g respectively (see reference). Figure 11 ).

[0185] Instead of the voltage monitoring circuit 60 that outputs three mode signals, namely the first mode signal Sm1, the second mode signal Sm2, and the third mode signal Sm3, the magnetic sensor circuit 70 may also have a voltage monitoring circuit 160, for example. The voltage monitoring circuit 160 has eight output terminals 160d, 160e, 160f, 160g, 160h, 160i, 160j, and 160k, and outputs analog signals Sm0 to Sm7 as one-bit signals from output terminals 160d to 160k respectively (see reference). Figure 12 ).

[0186] The magnetic sensor circuit according to this embodiment is configured to maintain the current mode or switch to another mode based on the voltage level changes of two or three output voltages, among multiple modes including a normal mode and at least one test mode. Therefore, the magnetic sensor circuit of this embodiment can avoid switching to an incorrect test mode even if a short circuit occurs between output terminals 51, 52, and 53, and compared with conventional magnetic sensor circuits, it can reduce accidental mode changes, i.e., unexpected mode changes.

[0187] Furthermore, the magnetic sensor circuit of this embodiment allows the transition types based on the level changes of two or three output voltages to correspond to various modes. Therefore, according to the magnetic sensor circuit of this embodiment, not only can one test mode be set, but multiple test modes can also be set. For example, the level transition types of the two output voltages can be up to four, so the magnetic sensor circuit of this embodiment can set not only one test mode, but also up to three (two or three) test modes.

[0188] Furthermore, the present invention is not limited to the embodiments described above. During the implementation phase, it can be implemented in various ways other than the examples described above, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention.

[0189] Furthermore, in the described embodiment, the transitions of the magnetic sensor circuits 10 and 70 from normal mode to test mode and from test mode to normal mode are explained, but the transitions between modes are not limited to this. In magnetic sensor circuits 10 and 70 that include multiple test modes, for example, it is also possible to directly transition from the first test mode TM1 to the second test mode TM2. That is, in the case of transitioning between test modes, the transition can be performed without going through the normal mode.

[0190] In the described embodiment, an example of a voltage monitoring circuit 60A that outputs two independent mode signals Sm1 and Sm2 was given for the magnetic sensor circuit 70. However, the two independent mode signals output from the voltage monitoring circuit 60A are not necessarily mode signals Sm1 and Sm2. The two independent mode signals output from the voltage monitoring circuit 60A can be any two that can be selected from mode signals Sm1 to Sm3.

[0191] For example, a voltage monitoring circuit 60A configured to select a first output voltage Vo1 and a third output voltage Vo3 as two output voltages can output mode signals Sm1 and Sm3. Additionally, a voltage monitoring circuit 60A configured to select a second output voltage Vo2 and a third output voltage Vo3 as two output voltages can output mode signals Sm2 and Sm3.

[0192] In the described embodiment, the case where the inspection device forcibly applies the first output voltage Vo1 and the second output voltage Vo2 to the output terminals 51 and 52 respectively has been explained, but it is not limited to this. The inspection device may also generate a predetermined magnetic field. That is, by applying magnetic flux densities Bx and Bz based on the predetermined magnetic field to the magnetic sensor circuit 10, an operation equivalent to the case where the first output voltage Vo1 and the second output voltage Vo2 are forcibly applied to the output terminals 51 and 52 respectively can be performed.

[0193] In this embodiment, a determination circuit 43 is described as an example of a circuit capable of determining that the voltage levels of two output voltages have changed within a predetermined time. The determination circuit 43 uses the time point when the voltage level of the first output voltage Vo1 changes (hereinafter referred to as the "first change point") as a reference point to determine whether the delay time from the reference point to the time point when the voltage level of the second output voltage Vo2 changes (hereinafter referred to as the "second change point") is within a predetermined time.

[0194] The determination circuit 43 can be configured to determine, using the second transition point as a reference point, whether the delay time from the reference point to the first transition point is within a predetermined time. In other words, the determination circuit 43 is configured to determine, using the first transition point as a reference point, whether the advance time from the reference point to the second transition point is within a predetermined time.

[0195] Furthermore, the determination circuit 43 may also have a switch capable of switching whether the reference point is set as the first transition point or the second transition point. In the determination circuit 43 capable of switching whether the reference point is set as the first transition point or the second transition point, the delay time when the reference point is set as the first transition point and the delay time when the reference point is set as the second transition point may be set to the same length or to different lengths.

[0196] Furthermore, in this embodiment, the case where the test mode set when the reference point is set to the first transition point is the same as the case where the test mode set when the reference point is set to the second transition point is described. However, the test mode set when the reference point is set to the first transition point and the test mode set when the reference point is set to the second transition point may also be different. In this case, the number of test modes that can be set in the magnetic sensor circuit 10 and the magnetic sensor circuit 70 can be set to a multiple of 2 relative to the number of transition types of the output voltage level.

[0197] The embodiments described herein or their variations are included within the scope or spirit of the invention, and are also included within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A magnetic sensor circuit, characterized in that, include: A first magnetic sensor detects magnetic flux density in a first direction and outputs a first sensor signal based on the detected magnetic flux density in the first direction. The second magnetic sensor detects the magnetic flux density in a second direction orthogonal to the first direction, and outputs a second sensor signal based on the detected magnetic flux density in the second direction. The signal processing circuit has a mode signal input terminal for inputting a mode signal, a first sensor signal input terminal for inputting the first sensor signal, and a second sensor signal input terminal for inputting the second sensor signal. It is capable of switching between a normal mode and a test mode. In the normal mode, based on the first sensor signal, it outputs a first detection signal that switches between low and high levels. On the other hand, based on the second sensor signal, it outputs a second detection signal that switches between low and high levels. In the test mode, it performs a prescribed action that is different from that in the normal mode. A first driver inputs the first detection signal in the normal mode and a test signal in the test mode, and outputs a first output voltage based on the input first detection signal or the test signal. The second driver inputs the second detection signal in the normal mode and the test signal in the test mode, and outputs a second output voltage based on the input second detection signal or the test signal. as well as A voltage monitoring circuit generates a pattern signal with multiple different signal levels corresponding to the voltage level transition types of the input first output voltage and the second output voltage.

2. The magnetic sensor circuit according to claim 1, wherein... The voltage monitoring circuit has: an output voltage input terminal, for inputting the first output voltage and the second output voltage. The mode signal generation circuit generates mode signals of the same number as the predetermined number of predetermined transition types, each with a different signal level, by selecting any two to four transition types from the voltage level transitions of the first output voltage input from the output voltage input terminal and the voltage level transitions of the second output voltage input from the output voltage input terminal within a specified time. The output terminal outputs the mode signal generated by the mode signal generation circuit.

3. The magnetic sensor circuit according to claim 2, wherein... The mode signal generation circuit includes: a first edge detection circuit, which detects the rising edge and falling edge of the input first output voltage, and generates a first rising edge detection signal corresponding to the detected rising edge and a first falling edge detection signal corresponding to the detected falling edge. The second edge detection circuit detects the rising edge and falling edge of the input second output voltage, and generates a second rising edge detection signal corresponding to the detected rising edge and a second falling edge detection signal corresponding to the detected falling edge. The determination circuit determines whether the predetermined transition type exists based on the first rising edge detection signal, the first falling edge detection signal, the second rising edge detection signal, and the second falling edge detection signal, and generates a determination result signal representing the determination result. as well as The signal generation circuit generates the pattern signal based on the determination result signal.

4. The magnetic sensor circuit according to claim 3, wherein... The predetermined transformation types include any one of two to four types: type one, type two, type three, and type four. The first type refers to the transition of both the voltage level of the first output voltage and the voltage level of the second output voltage from low to high within the specified time. The second type is characterized by the voltage level of the first output voltage changing from low to high and the voltage level of the second output voltage changing from high to low within the specified time. The third type is that within the specified time, the voltage level of the first output voltage changes from high to low, and the voltage level of the second output voltage changes from low to high. The fourth type is that both the voltage level of the first output voltage and the voltage level of the second output voltage change from high to low within the specified time.

5. The magnetic sensor circuit according to claim 1, comprising: The third magnetic sensor detects the magnetic flux density in a third direction orthogonal to the first and second directions, and outputs a third sensor signal based on the detected magnetic flux density in the third direction. as well as The third driver inputs a third detection signal in the normal mode and a test signal in the test mode, and outputs a third output voltage based on the input third detection signal or the test signal. The signal processing circuit has a third sensor signal input terminal for inputting the third sensor signal, and is configured to switch between a normal mode and the test mode. The normal mode outputs a third detection signal based on the third sensor signal, as well as the first detection signal and the second detection signal, wherein the third detection signal alternates between low and high levels. The voltage monitoring circuit is configured to generate a pattern signal having multiple different signal levels corresponding to the voltage level transition types of the input first output voltage, second output voltage, and third output voltage.

6. The magnetic sensor circuit according to claim 5, wherein, The voltage monitoring circuit has an output voltage input terminal, which receives the first output voltage, the second output voltage, and the third output voltage. The mode signal generation circuit, from among the voltage level changes of the first output voltage input from the output voltage input terminal, the second output voltage input from the output voltage input terminal, and the third output voltage input from the output voltage input terminal, within a predetermined time period, sets any two to eight predetermined change types, and generates mode signals with the same number of predetermined change types but each having a different signal level. The output terminal outputs the generated pattern signal.

7. The magnetic sensor circuit according to claim 6, wherein... The voltage monitoring circuit also includes a selection circuit that selects two output voltages from the first output voltage, the second output voltage, and the third output voltage input from the output voltage input terminal. The predetermined transition type is set to any number of two to four among the transition types of the voltage levels of the two output voltages selected by the selection circuit.

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