Method of programming in a flash memory device

Abstract

A method for programming a flash memory device includes: selecting a first word line from a plurality of word lines to select a selected word line, the selected word line corresponding to a target memory cell; and performing a programming cycle. The programming cycle includes applying a programming voltage to the selected word line and performing verification on the target memory cell. The verification includes applying a pre-pulse voltage to the selected word line, applying a plurality of overpass voltages to unselected word lines from the plurality of word lines, applying a series of incremental verification voltages to the selected word line after applying the pre-pulse voltage, and applying a floating voltage to a second word line from the plurality of word lines after applying the pre-pulse voltage. The second word line is adjacent to the selected word line and is programmed after the selected word line.

Description

[0001] This application is a divisional application of the invention patent application filed on August 28, 2019, with application number 201980001938.6 and entitled "Programming Method in Flash Storage Device". Technical Field

[0002] This invention relates to flash storage devices, and more particularly to programming methods in flash storage devices. Background Technology

[0003] Non-volatile memory is memory that can retain its stored data for an extended period of time without power. Flash memory devices have been developed into a widely used type of non-volatile memory for a wide range of applications. Flash memory devices are commonly used in electronic systems such as personal computers, digital cameras, digital media players, digital recorders, vehicles, wireless devices, cellular phones, and removable storage modules, and the applications of flash memory continue to expand.

[0004] Flash memory uses one of two basic architectures, known as NOR flash and NAND flash. Typically, the cell arrays for NAND flash memory devices are arranged such that strings of cells are connected in series from source to drain. Flash memory can include arrays with a large number of floating-gate transistors. NAND arrays arrange their flash cells in a matrix with rows and columns, similar to conventional NOR arrays, such that the gate of each flash cell is row-coupled to a word line. However, unlike NOR, each cell is not directly coupled to the source and column lines. Instead, the cells are arranged in strings, typically 8, 16, 32, or more. The cells in the string are connected in series from source to drain between a common source line and a column line.

[0005] Some flash memories are designed to store more than one bit of data per cell. Flash memories that store more than one bit of data per cell are called multilevel cell (MLC) flash memories. Incremental step pulse programming (ISPP) is typically used to program MLC flash memories. In Incremental step pulse programming, selected cells are programmed through multiple programming cycles. Each programming cycle includes a programming operation and a verification operation. In the programming operation, a programming voltage is applied to the selected cell to modify its state, and in the verification operation, a verification voltage is applied to the selected cell to determine if it has reached the target state. By executing the programming cycles in this manner, the selected cells are programmed incrementally, and certain programming errors such as overprogramming can be avoided. Summary of the Invention

[0006] An embodiment of a method for programming a flash memory device includes: selecting a first word line from a plurality of word lines to select a selected word line, the selected word line corresponding to a target memory cell; and performing a programming cycle. The programming cycle includes applying a programming voltage to the selected word line and performing verification on the target memory cell. The verification includes applying a pre-pulse voltage to the selected word line, applying a plurality of overpass voltages to unselected word lines from the plurality of word lines, applying a series of incremental verification voltages to the selected word line after applying the pre-pulse voltage, and applying a floating voltage to a second word line from the plurality of word lines after applying the pre-pulse voltage. The second word line is adjacent to the selected word line and is programmed after the selected word line.

[0007] An embodiment of a method for programming a flash memory device includes: selecting a first word line from a plurality of word lines to select a selected word line, the selected word line corresponding to a target memory cell; and performing a programming cycle. The programming cycle includes applying a programming voltage to the selected word line and performing verification on the target memory cell. The verification includes applying a pre-pulse voltage to the selected word line, applying a plurality of overpass voltages to unselected word lines from the plurality of word lines, applying a series of incremental verification voltages to the selected word line after applying the pre-pulse voltage, discharging a second word line from the plurality of word lines to a system voltage level after applying the pre-pulse voltage, and applying a floating voltage to the second word line after discharging the second word line to the system voltage level. The second word line is adjacent to the selected word line and is programmed after the selected word line.

[0008] An embodiment of a method for programming a flash memory device includes: selecting a first word line from a plurality of word lines to select a selected word line, the selected word line corresponding to a target memory cell; and performing a programming cycle. The programming cycle includes applying a programming voltage to the selected word line and performing verification on the target memory cell. The verification includes applying a pre-pulse voltage to the selected word line, applying a plurality of overpass voltages to unselected word lines from the plurality of word lines, applying a series of incremental verification voltages to the selected word line after applying the pre-pulse voltage, discharging a second word line from the plurality of word lines to ground after applying the pre-pulse voltage, and applying a floating voltage to the second word line after discharging the second word line to ground. The second word line is adjacent to the selected word line and is programmed after the selected word line.

[0009] These and other objectives of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of preferred embodiments illustrated in the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a diagram of a flash storage device implemented in an embodiment.

[0011] Figure 2A This is a diagram illustrating an example of the threshold voltage range for a 2-bit MLC memory cell.

[0012] Figure 2B This is a diagram illustrating an example of the threshold voltage range for a 3-bit MLC memory cell.

[0013] Figure 3 A, Figure 3 B and Figure 3 C is a diagram illustrating an incremental step pulse programming (ISPP) scheme for programming the selected memory cell.

[0014] Figure 4 This is a diagram of the storage cell string implemented in the embodiment.

[0015] Figure 5 A verification scheme for the programming method of the embodiment is shown.

[0016] Figure 6A This is a graph showing the verification time of existing technologies. Figure 6B This is a graph showing the verification time of an embodiment.

[0017] Figure 7 A verification scheme for the programming method of the embodiment is shown.

[0018] Figure 8 A verification scheme for the programming method of the embodiment is shown.

[0019] Figure 9 This is a flowchart of a method for programming flash storage devices. Detailed Implementation

[0020] Figure 1A flash memory device 100 according to an embodiment of the present invention is shown. The flash memory device 100 includes a plurality of memory cells C(1,1) to C(M,N), where M and N are positive integers. In some embodiments of the present invention, the non-volatile memory device 100 may be a NAND flash memory. N memory cells may be coupled to the same word line, and M memory cells may be coupled to the same bit line. For example, a row of memory cells C(1,1) to C(1,N) may be coupled to word line WL1, and a row of memory cells C(M,1) to C(M,N) may be coupled to word line WLM. A column of memory cells C(1,1) to C(M,1) may be coupled to bit line BL1, and a column of memory cells C(M,1) to C(M,N) may be coupled to bit line BLN. One terminal of a memory column is coupled to a bit line via a bit line transistor Tb corresponding to that column, and another terminal is coupled to a source line via a source line transistor Ts. Bit lines BL1 to BLN are coupled to a sensing circuit (e.g., a sensing amplifier) ​​300, which detects the state of a target memory cell by sensing the voltage or current on a selected bit line BLn, where n is a positive integer between 1 and N (inclusive). The flash memory device 100 further includes a control unit (not shown) for implementing programming pulses to the memory cell array.

[0021] Storage cells C(1,1) to C(M,N) can be configured as Single-Level Cell (SLC) or Multi-Level Cell (MLC). Data states are assigned to the storage cells using specific ranges of threshold voltages stored within them. SLC allows a single binary digit of data in one storage cell, while MLC allows two or more binary digits to be stored in one storage cell, depending on the range and density of the threshold voltages. For example, one bit can be represented by two threshold voltage ranges, two bits by four ranges, and three bits by eight ranges, and so on. SLC memories use two threshold voltage ranges representing 0 or 1 to store a unit of data (two ranges). MLC memories can be configured to store two bits of data (four ranges), three bits of data (eight ranges), or more bits of data.

[0022] Figure 2AThis diagram illustrates an example of the threshold voltage range for a 2-bit MLC memory cell. The memory cell can be programmed to fall within one of four different ranges, S0, S1, S2, and S3; each range represents the data state corresponding to a two-bit mode. A margin is maintained between each range S0 and S3 to prevent overlap. For example, if the cell voltage falls within the first threshold voltage range S0, the cell stores a "11" state, which typically indicates an erase state. If the cell voltage falls within the second threshold voltage range S1, the cell stores a "10" state. If the cell voltage falls within the third threshold voltage range S2, the cell stores a "00" state. If the cell voltage falls within the fourth threshold voltage range S3, the cell stores a "01" state.

[0023] Figure 2B This is a diagram illustrating an example of the threshold voltage range for a 3-bit MLC memory cell. The memory cell can be programmed to fall within one of eight different ranges: L0, L1, L2, L3, L4, L5, L6, and L7; each range represents the data state corresponding to a three-bit mode. For example, if the cell's voltage falls within the first threshold voltage range L0, the cell stores a "111" state, which typically indicates an erase state. If the cell's voltage falls within the second threshold voltage range L1, the cell stores a "110" state. If the cell's voltage falls within the third threshold voltage range L2, the cell stores a "101" state. If the cell's voltage falls within the fourth threshold voltage range L3, the cell stores a "100" state. If the cell's voltage falls within the fifth threshold voltage range L4, the cell stores a "011" state. If the cell's voltage falls within the sixth threshold voltage range L5, the cell stores a "010" state. If the voltage of a memory cell falls within the seventh threshold voltage range L6, then the cell stores a "001" state. If the voltage of a memory cell falls within the eighth threshold voltage range L7, then the cell stores a "000" state.

[0024] Flash programming involves word lines (e.g., Figure 1 WL (Chinese character line) m One or more programming voltages are applied, where m is an integer between 1 and M. This controls the gate of each memory cell C(m,1) to C(m,N). For example, the programming pulse can start at 15V and increase for each subsequent programming pulse. This programming method is the well-known Incremental Step Pulse Programming (ISPP). The programming pulse is applied to the word line WL. mSimultaneously, a voltage is applied to the substrate containing the channels of these memory cells, creating a charge transfer from the selected memory cells to the floating gate. Electrons from the channels can be injected into the floating gate via direct injection or Fowler-Nordheim tunneling. Therefore, in the programmed state, the threshold voltage tends to be greater than zero.

[0025] Figure 3 A diagram further illustrates the Incremental Step Pulse Programming (ISPP) scheme for programming selected memory cells. Figure 3 Example A is a typical ISPP scheme. A programming voltage is applied using a programming pulse to control the gate of the selected memory cell. The programming voltage level of the programming pulse increases in each successive loop.

[0026] Between programming pulses, a verification operation is performed to check the selected memory cells to determine whether they have reached their target programming state. Figure 3 In B, within a 2-bit MLC memory cell, a verification operation is performed using a series of three incremental verification voltages to determine whether the selected memory cell (e.g., C(m,n)) has been successfully programmed to the corresponding... Figure 2A The state of one of the threshold voltage distributions S0 to S3 (e.g., the target state). With Figure 3 Similarly in C, a verification operation is performed on a 3-bit MLC memory cell using a series of seven incremental verification voltages to determine whether the selected memory cell (e.g., C(m,n)) has been successfully programmed to the corresponding... Figure 2B The state of one of the threshold voltage distributions L0 to L7 in the data.

[0027] If memory cell C(m,n) has reached its target programming state, it is disabled or will not transmit data via bit line BL coupled to memory cell C(m,n). n A bias suppression voltage is applied for further programming. After the sensing operation, if any memory cells have not yet been programmed, additional programming pulses are applied. This process of applying programming pulses and then performing sensing operations continues until all selected memory cells have reached their target programming state. If the maximum number of programming pulses has been applied and some selected memory cells are still not programmed, these memory cells will be designated as defective memory cells.

[0028] Still in Figure 1 In this process, a pass voltage is applied to each unselected word line, for example, except for WL. m The word lines WL1 to WL are outside of this. M The overvoltage applied to different word lines can be different. This is related to the selected word line WL. m Adjacent word lines WL m-1A 9V overpass voltage is allowed, and other word lines can have an 8V overpass voltage. The overpass voltage is always low enough to prevent initiation of memory cell programming. Additionally, a suppression voltage is applied to bit lines not coupled to memory cell strings with selected memory cells for programming. During programming operations, alternating bit lines can be activated or deactivated for programming. For example, even-numbered bit lines such as BL2, BL4, etc., can be activated for programming memory cells coupled to these bit lines, while odd-numbered bit lines such as BL1, BL3, etc., can be deactivated to prevent programming of memory cells coupled to these bit lines. Subsequent programming operations can then deactivate the even-numbered bit lines and activate the odd-numbered bit lines.

[0029] use Figure 3 The time required for programming operations in ISPP scheme A tends to increase proportionally with the number of states in the memory cell. Furthermore, verification operations tend to account for a significant portion of the total programming time. Therefore, flash storage devices require verification schemes that reduce verification time, even when the number of programmable states in the selected memory cells is relatively large.

[0030] The following description is for reference. Figure 4 and Figure 5 . Figure 4 This is a diagram of a storage cell string implemented in an embodiment of the present invention. Figure 5 A verification scheme for the programming method according to an embodiment of the present invention is shown. In the verification operation, all word lines WL1 to WL... M It begins with the system voltage Vdd. At time t1, a pre-pulse voltage is applied to the selected word line WL. m And the first adjacent word line WL m+1 In addition, a first overvoltage Vpass1 is applied to the second adjacent word line WL. m-1 and unselected word lines (except WL) m Wl m+1 (All word lines except for those mentioned above). At time t2, the selected word line WL m And the first adjacent word line WL m+1 Discharge begins. The second overvoltage Vpass2 is applied to the second adjacent word line WL. m-1 The remaining unselected word lines remain at the level of the first overpass voltage Vpass1. At time t3, a series of incrementing verification voltages Vvry are applied to the second word line WL. m In this case, seven verification voltages are applied. Additionally, when the first adjacent word line WL... m+1 When the voltage on the line drops to the system voltage Vdd, the floating voltage is applied to the first adjacent word line WL. m+1 The second adjacent character line WL m-1The voltage on the selected word line is maintained at the second overpass voltage Vpass2, and the voltages on the remaining unselected word lines are maintained at the first overpass voltage Vpass1. At time t4, the subsequent pulse voltage is applied to the selected word line WL. m And the first adjacent word line WL m+1 The second adjacent character line WL m-1 The voltage is discharged to the level of the first overpass voltage Vpass1, and the voltages on the remaining unselected word lines remain at the first overpass voltage Vpass1. At time t5, including WL m WL m+1 and WL m-1 All word lines, including the first adjacent word line WL, are discharged to the level of the system voltage Vdd, thus completing the verification operation. When the verification voltage Vvry is applied to the selected word line WLm, the first adjacent word line WLm is discharged. m+1 The associated memory cell is still in the erase state, therefore in the first adjacent word line WL m+1 Applying a floating voltage will not affect subsequent programming operations. This is because the second adjacent word line WL... m-1 It may no longer be in an erase state, therefore the floating voltage should not be applied to the second adjacent word line WL. m-1 This is to avoid altering the programming units within it. Furthermore, during verification operations, the floating voltage is applied through the selected word line WL. m Adjacent to the first word line WL m+1 The coupling effect of the parasitic capacitor Cap between them is enhanced.

[0031] Figure 6A This is a graph showing the voltage settling time for verification in the prior art. Figure 6B This is a graph illustrating the verification voltage settling time of an embodiment of the present invention. As shown in the figure, compared to the prior art, the method of the embodiment requires less time to reach the target verification voltage Vtarget. For example, WL m WL m+1 and WL m-1 of Figure 4 The parasitic capacitance Cap between word lines will affect the voltage charging time on these word lines. For the first adjacent word line WL... m+1 When a floating voltage is applied, the effect of parasitic capacitance Cap is reduced, thereby shortening the ramp-up time for the verification voltage to reach the target verification voltage Vtarget. Therefore, it improves overall programming performance. Furthermore, by adjusting the first adjacent word line WL... m+1 Applying a floating voltage can reduce the power consumption of the circuit to some extent. Furthermore, the method can be implemented without increasing the complexity of the adder circuit in terms of design and manufacturing.

[0032] Figure 7A verification scheme for a programming method according to another embodiment of the present invention is shown. Figure 7 The verification operations shown are mostly related to Figure 5 The description is similar, except that the floating voltage is immediately applied to the first adjacent word line WL at time t2. m+1 The first adjacent character line WL m+1 The floating voltage remains constant until time t4. The remaining operations are essentially the same as... Figure 5 The diagram shown is the same.

[0033] Figure 8 A verification scheme for a programming method according to another embodiment of the present invention is shown. Figure 8 The verification operations shown are mostly related to Figure 5 The explanation is similar, except that at time t3, the first adjacent word line WL m+1 When the voltage on the first adjacent word line WL drops to ground voltage GND, m+1 A floating voltage is applied. The first adjacent word line WL m+1 The floating voltage remains constant until time t4. The remaining operations are essentially the same as... Figure 5 The diagram shown is the same.

[0034] Figure 9 This is a flowchart of a method 900 for programming a flash storage device. The method incorporates the aforementioned verification operation. System 900 includes:

[0035] S902: Select the word line corresponding to the target memory cell and set the programming loop count to 0;

[0036] S904: Determine whether the programming loop count has reached the maximum loop count; if yes, proceed to step S920; otherwise, proceed to S906.

[0037] S906: Apply programming voltage to the selected word line;

[0038] S908: Apply a pre-pulse voltage to the selected word line; and apply multiple overpass voltages to the unselected word lines; S910: Apply a series of incremental verification voltages to the selected word line; and apply a floating voltage to the first adjacent word line;

[0039] S912: Apply a post-pulse voltage to the selected word line;

[0040] S914: Discharge all word lines;

[0041] S916: Determine whether the number of memory cells with a threshold voltage greater than the target voltage is greater than a predetermined number; if yes, proceed to step S920; otherwise, proceed to step S918.

[0042] S918: Increase the programming voltage; and increment the programming cycle count by 1; proceed to step S904;

[0043] S920: Programming complete.

[0044] In summary, the programming method of this embodiment involves applying a floating voltage to the adjacent word line closest to the selected word line and programmed after the selected word line. This reduces the impact of parasitic capacitance between word lines. Therefore, it can effectively shorten the ramp-up time of the verification voltage, thereby shortening the verification time and improving overall programming performance. Furthermore, this method can reduce circuit power consumption to some extent. Moreover, the method can be implemented without increasing the complexity of the adder circuitry.

[0045] Those skilled in the art will readily observe that many modifications and alterations can be made to the described devices and methods while following the teachings of this invention. Accordingly, the foregoing disclosure should be interpreted as being limited only by the scope defined by the appended claims.

Claims

1. A method for verifying the programming of flash storage devices within a programming loop, wherein, The flash storage device includes a memory string comprising a plurality of sequentially connected memory cells, each memory cell being connected to a corresponding word line among a plurality of word lines, the plurality of word lines including selected word lines and unselected word lines, the selected word line corresponding to a target memory cell, and the unselected word line corresponding to a non-target memory cell, wherein the unselected word line includes a first word line adjacent to the selected word line, the method comprising: Apply an overpass voltage to the unselected word lines other than the first word line; Apply a verification voltage to the selected word line; and The first word line is floated, wherein the float voltage on the first word line is increased by the verification voltage on the selected word line, and the memory cell corresponding to the floated first word line is programmed after the target memory cell.

2. The method according to claim 1, further comprising: A pre-pulse voltage is applied before the verification voltage is applied to the selected word line, and the pre-pulse voltage is applied before the first word line is floated.

3. The method according to claim 1, further comprising: Apply a pre-pulse voltage to the first word line; After the pre-pulse voltage is applied, the first word line is discharged to the system voltage level; as well as After discharging the first word line to the system voltage level, the first word line is floated.

4. The method according to claim 1, further comprising: Apply a pre-pulse voltage to the first word line; After applying the pre-pulse voltage to the first word line, the first word line is discharged to ground voltage level; as well as After discharging the first word line to the ground voltage level, the first word line is floated.

5. The method of claim 1, wherein the programming cycle further comprises programming in sequence from the source-line transistor to the bit-line transistor, wherein, The first word line is located on the side of the selected word line close to the bit line transistor.

6. The method of claim 1, wherein the programming cycle further comprises discharging each of the plurality of word lines after the programming verification.

7. The method of claim 1, wherein the programming loop further comprises terminating the programming loop if the number of memory cells having a threshold voltage greater than the target voltage is greater than a predetermined number.

8. The method of claim 1, wherein the programming cycle further comprises applying a programming voltage to the selected word line prior to the programming verification.

9. The method of claim 8, wherein the programming cycle further comprises increasing the programming voltage.

10. The method of claim 1, further comprising: If the programming loop count reaches the maximum loop count, then the programming loop ends.

11. A flash storage device, comprising: A storage string, the storage string comprising a plurality of storage units connected in sequence; A plurality of word lines, each of the memory cells being connected to a corresponding word line among the plurality of word lines, the plurality of word lines including selected word lines and unselected word lines, the selected word lines corresponding to a target memory cell, and the unselected word lines corresponding to a non-target memory cell, wherein the unselected word lines include a first word line, the first word line being adjacent to the selected word line; The control unit is configured to control the flash storage device to perform the following operations during the programming verification phase of the programming cycle: Apply an overpass voltage to the unselected word lines other than the first word line; Apply a verification voltage to the selected word line; and The first word line is floated, wherein the float voltage on the first word line is increased by the verification voltage on the selected word line, and the memory cell corresponding to the floated first word line is programmed after the target memory cell.

12. The flash memory device of claim 11, wherein the control unit is further configured to apply a pre-pulse voltage before applying the verification voltage to the selected word line, and to apply the pre-pulse voltage before floating the first word line.

13. The flash storage device of claim 11, wherein the control unit is further configured to perform the following operations: Apply a pre-pulse voltage to the first word line; After applying the pre-pulse voltage, the first word line is discharged to the system voltage level; and After discharging the first word line to the system voltage level, the first word line is floated.

14. The flash storage device of claim 11, wherein the control unit is further configured to perform the following operations: Apply a pre-pulse voltage to the first word line; After applying the pre-pulse voltage, the first word line is discharged to ground voltage level; and After discharging the first word line to the ground voltage level, the first word line is floated.

15. The flash memory device of claim 14, wherein the control unit is further configured to be programmed in sequence from the source-line transistor to the bit-line transistor, wherein, The first word line is located on the side of the selected word line close to the bit line transistor.

16. The flash storage device of claim 11, wherein the control unit is further configured to discharge each of the plurality of word lines after the programming verification phase.

17. The flash storage device of claim 11, wherein the control unit is further configured to terminate the programming cycle if the number of storage cells having a threshold voltage greater than the target voltage is greater than a predetermined number.

18. The flash memory device of claim 11, wherein the control unit is further configured to apply a programming voltage to the selected word line prior to the programming verification phase.

19. The flash storage device of claim 18, wherein the control unit is further configured to further increase the programming voltage.

20. The flash storage device of claim 11, wherein the control unit is further configured to terminate the programming cycle if the programming cycle count reaches the maximum cycle count.

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