Memory device

Abstract

This technology includes a memory device. The memory device includes: a current sensing circuit configured to perform an independent current sensing operation according to the verification result of each selected programming state in an independent current sensing mode, and in a hybrid current sensing mode, after performing the independent current sensing operation, perform an overall current sensing operation according to the verification result of the overall memory cells regardless of the selected programming state; and a voltage generator configured to apply a programming voltage to a selected word line connected to the memory cells during a first time period in the independent current sensing mode in response to an operation code, and apply the programming voltage to the selected word line during a second time period greater than the first time period in the hybrid current sensing mode.

Description

Technical Field

[0001] The present disclosure relates to a memory device, and more particularly, to a memory device capable of performing a programming operation. Background Art

[0002] Memory devices may include volatile memory devices in which data stored is lost when power is cut off and non-volatile memory devices in which stored data is retained even when power is cut off.

[0003] Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include read only memory (ROM), programmable read only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and NAND flash memory, etc.

[0004] A memory device may include a memory cell array, a logic circuit, and a group of circuits collectively referred to as a peripheral circuit.

[0005] The memory cell array may include a plurality of memory cells that store data. The memory cell array may be configured by any one of various types of memory cells according to the storage capacity. A single level cell (SLC) is capable of storing one bit of data, and a multi-level cell (MLC) is capable of storing two bits of data. A three-level cell (TLC) is capable of storing three bits of data, and a four-level cell (QLC) is capable of storing four bits of data. Summary of the Invention

[0006] One embodiment of the present disclosure provides a memory device capable of preventing an increase in programming operation time due to a current sensing operation for checking the result of a programming operation.

[0007] A memory device according to an embodiment of the present disclosure includes: a plurality of memory cells; a page buffer configured to store sensed data sensed from the memory cells; a current sensing circuit configured to perform an independent current sensing operation of outputting a pass signal or a fail signal according to a verification result of each selected programming state in an independent current sensing mode in response to a sensing mode signal, and perform an overall current sensing operation of outputting a pass signal or a fail signal according to a verification result of the overall memory cells regardless of the selected programming state after performing the independent current sensing operation in a hybrid current sensing mode; a sensing mode selector configured to output a sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode in response to the pass signal or the fail signal, and output an operation code according to the sensing mode signal; and a voltage generator configured to apply a programming voltage to a selected word line connected to the memory cells during a first time period in the independent current sensing mode in response to the operation code, and apply the programming voltage to the selected word line during a second time period greater than the first time period in the hybrid current sensing mode.

[0008] A memory device according to an embodiment of the present disclosure includes: a plurality of memory cells; a page buffer configured to store sensed data sensed from the memory cells; a current sensing circuit configured to perform an independent current sensing operation of outputting a pass signal or a fail signal according to a verification result of each selected programming state in an independent current sensing mode in response to a sensing mode signal, and perform an overall current sensing operation of outputting a pass signal or a fail signal according to a verification result of the overall memory cells regardless of the selected programming state after performing the independent current sensing operation in a hybrid current sensing mode; a sensing mode selector configured to output a sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode in response to the pass signal or the fail signal, and output an operation code according to the sensing mode signal; and a voltage generator configured to, during a programming operation, after applying the programming voltage to the selected word line connected to the memory cells, discharge the selected word line during a first duration in the independent current sensing mode in response to the operation code, and discharge the selected word line during a second duration greater than the first duration in the hybrid current sensing mode.

[0009] A memory device according to an embodiment of the present disclosure includes: a plurality of memory cells; a page buffer configured to store sensed data sensed from the memory cells; a current sensing circuit configured to perform an independent current sensing operation of outputting a pass signal or a fail signal according to a verification result for each selected programming state in an independent current sensing mode in response to a sensing mode signal, and perform an overall current sensing operation of outputting a pass signal or a fail signal according to a verification result for the overall memory cells regardless of the selected programming state after performing the independent current sensing operation in a hybrid current sensing mode; a sensing mode selector configured to output a sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode in response to the pass signal or the fail signal, and output an operation code according to the sensing mode signal; and a voltage generator configured to apply a compensation voltage to the discharged selected word line during a first duration in the independent current sensing mode and apply a compensation voltage to the discharged selected word line during a second duration greater than the first duration in the hybrid current sensing mode in response to the operation code after applying a programming voltage to the selected word line connected to the memory cells and discharging the selected word line during a programming operation.

[0010] A memory device according to an embodiment of the present disclosure includes: a memory cell array; and a control circuit configured to perform a sub-programming operation and a verification operation on the memory cell array while sequentially performing an independent current sensing operation and an overall current sensing operation, wherein the control circuit substantially simultaneously completes the verification operation and the overall current sensing operation by adjusting a period of one or more subordinate operations in the sub-programming operation.

[0011] This technology can prevent an increase in the programming operation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram showing a memory cell array.

[0014] Figure 3 is a diagram showing a memory block.

[0015] Figure 4 is a diagram showing a page buffer group.

[0016] Figure 5 is a diagram showing a sensing mode selector according to an embodiment of the present disclosure.

[0017] Figure 6It is a diagram showing the threshold voltage distribution of memory cells.

[0018] Figure 7 It is a diagram showing the main programming operation.

[0019] Figure 8 It is a diagram showing an independent current sensing mode according to an embodiment of the present disclosure.

[0020] Figure 9 It is a diagram showing the hybrid current sensing mode.

[0021] Figure 10 It is a timing diagram showing the hybrid current sensing mode according to the first embodiment of the present disclosure.

[0022] Figure 11 It is a timing diagram showing the hybrid current sensing mode according to the second embodiment of the present disclosure.

[0023] Figure 12 It is a diagram showing the hybrid current sensing mode according to the third embodiment of the present disclosure.

[0024] Figure 13 It is a diagram showing a memory system including a memory device of the present disclosure.

[0025] Figure 14 It is a diagram showing a memory system including a memory device according to another embodiment of the present disclosure. Detailed Embodiments

[0026] Throughout the specification, references to "one embodiment" or "another embodiment" etc. do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. The term "embodiment" used herein does not necessarily refer to all embodiments.

[0027] Figure 1 It is a diagram showing a memory device 1100 according to an embodiment of the present disclosure.

[0028] Referring to Figure 1 , the memory device 1100 may include a memory cell array 110, a row decoder 120, a voltage generator 130, a page buffer bank 140, a column decoder 150, an input / output circuit 160, a current sensing circuit 170, and a logic circuit 180.

[0029] The memory cell array 110 may include a plurality of planes, and each plane may include a plurality of memory blocks for storing data. Each memory block may include a plurality of memory cells, and the memory cells may be implemented as a two-dimensional structure arranged parallel to the substrate or a three-dimensional structure stacked in a direction perpendicular to the substrate.

[0030] The row decoder 120 may select one memory block in the memory cell array 110 in response to a row address RADD, and send an operation voltage Vop to the selected memory block.

[0031] The voltage generator 130 may generate and output an operation voltage Vop for various operations in response to an operation code OPCD. For example, the voltage generator 130 may generate and output a programming voltage, a verification voltage, a read voltage, an erase voltage, a pass voltage, etc. The voltage generator 130 according to one embodiment may adjust the voltage applied to the word line according to a current sensing mode. For example, the voltage generator 130 may be configured to adjust the amount of time for applying the programming voltage, the amount of time for discharging the word line, and the amount of time for compensating the word line voltage.

[0032] The page buffer group 140 may be connected to the memory cell array 110 through bit lines. For example, the page buffer group 140 may include respective page buffers connected to respective bit lines. The page buffers may operate simultaneously in response to a page buffer control signal PBSIG, and may temporarily store data during a programming operation or a read operation. Each page buffer may include a plurality of latches capable of storing data. The sensed data SDT sensed during a verification operation may be stored in one of the plurality of latches included in the page buffer. During a verification operation, the plurality of page buffers may store the sensed data SDT transmitted from the bit lines. During a current sensing operation, the plurality of page buffers may transmit the sensed data SDT to the current sensing circuit 170.

[0033] The column decoder 150 may output a column selection signal CS in response to a column address CADD, and the plurality of page buffers included in the page buffer group 140 may store the data loaded on the data line DL# in response to the column selection signal CS.

[0034] The input / output circuit 160 may connect the memory device 1100 and an external device to each other through input / output lines IO. Here, the external device may be a controller capable of controlling the memory device 1100. The input / output circuit 160 may receive a command CMD, an address ADD, and data through the input / output lines IO, or output data to the external device, and may receive data from the page buffer group 140 through the data line DL#. The input / output circuit 160 may transmit the command CMD and the address ADD received through the input / output lines IO to the logic circuit 180, and may transmit data to the page buffer group 140.

[0035] The current sensing circuit 170 may perform a current sensing operation by receiving sensing data SDT from the page buffer bank 140. The current sensing operation determines whether a memory cell is programmed to a target state, and may include an individual current sensing operation and an entire current sensing operation. The individual current sensing operation determines whether a memory cell is programmed to a selected programming state, and the entire current sensing operation determines whether the programming operation of a selected page is completed. For example, an individual current sensing operation may be performed to determine one of a plurality of programming states, and an entire current sensing operation may be performed to determine the entire programming state.

[0036] The current sensing circuit 170 may selectively perform an individual current sensing operation and an entire current sensing operation in response to a sensing mode signal SMG, and may perform the entire current sensing operation after performing the individual current sensing operation. For example, the sensing mode signal SMG may be output as an individual current sensing mode signal, an entire current sensing mode signal, or a mixed current sensing mode signal. In the mixed current sensing mode, the entire current sensing operation is sequentially performed after performing the individual current sensing operation.

[0037] The current sensing circuit 170 may generate a reference current and a reference voltage in response to a set permission bit, and may generate a verification current and a verification voltage based on the sensing data SDT. The current sensing circuit 170 may output a pass signal PS or a fail signal FS by comparing the reference voltage and the verification voltage with each other.

[0038] During the individual current sensing operation, when the number of memory cells in which the verification operation fails among the memory cells to be programmed to the selected programming state is equal to or less than a set number, the current sensing circuit 170 may determine that the verification operation for the selected programming state passes, and may output a pass signal PS. When the number of memory cells in which the verification operation fails is greater than the set number, the current sensing circuit 170 may determine that the verification operation for the selected programming state fails, and may output a fail signal FS. Here, the selected programming state represents the target programming state of the memory cell. For example, in the multi-level cell method of storing 2-bit data in one memory cell, the memory cell may have one erased state or may be programmed to one of three programming states. Alternatively, in the three-level cell method of storing 3-bit data in one memory cell, the memory cell may have one erased state or may be programmed to any one of seven programming states. In the individual current sensing mode, the current sensing circuit 170 may perform a current sensing operation for each of the respective programming states of the memory cell.

[0039] In the independent current sensing mode, the current sensing circuit 170 may determine whether the verification operations performed for each of the above-described programming states pass or fail, and may output a pass signal PS or a fail signal FS according to the result of the determination.

[0040] In the global current sensing mode, regardless of the selected programming state, when the number of memory cells determined to have failed among all the memory cells to be programmed is equal to or less than a set number, the current sensing circuit 170 may determine that the verification operation passes, and may output a pass signal PS. That is, when the number of fail bits is greater than the set number, the current sensing circuit 170 may determine that the verification operation fails, and may output a fail signal FS. The set number of memory cells in the global current sensing mode is different from the set number in the independent current sensing mode. For example, it may be determined whether the verification operation for all the memory cells to be programmed in the memory cells of the selected page passes or fails in the global current sensing mode, and it may be determined whether the verification operation for the memory cells to be programmed to the selected programming state among the memory cells included in the selected page passes or fails in the independent current sensing mode. Therefore, the set number used in the global current sensing mode may be greater than the set number used in the independent current sensing mode.

[0041] In the hybrid current sensing mode, the current sensing circuit 170 may perform an independent current sensing operation and then perform a global current sensing operation. The set number used in the independent current sensing operation is different from the set number used in the global current sensing mode. For example, the set numbers used in each independent current sensing operation and the global current sensing operation may be set according to different set permission bits. Therefore, the current sensing circuit 170 may select a permission bit in response to a sensing mode signal SMG, and may use the set number set according to the selected permission bit in the selected mode.

[0042] The logic circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, the logic circuit 180 may include software that executes algorithms for various operations in response to a command CMD, and hardware configured to output various signals according to the address ADD and the algorithms.

[0043] During a programming operation, the logic circuit 180 may output a sense mode signal SMG in response to a pass signal PS or a fail signal FS. For example, the logic circuit 180 may include a sense mode selector 190 configured to output the sense mode signal SMG in response to the pass signal PS or the fail signal FS. The sense mode selector 190 may count the number of programming cycles performed during the programming operation in response to the fail signal FS to obtain an accumulated number, and output the sense mode signal SMG according to the accumulated number of programming cycles. When the pass signal PS is input, the sense mode selector 190 may initialize the counting of the number of programming cycles. In addition, the logic circuit 180 may output an operation code OPCD to adjust the time interval during which the verification voltage applied to the selected word line is changed in each of the independent current sense mode and the hybrid current sense mode.

[0044] Figure 2 is a diagram showing a memory cell array.

[0045] Referring to Figure 2 , the memory cell array 110 may include a plurality of planes PL1 to PL4. Figure 1 Each page buffer group 140 of may be connected to the planes PL1 to PL4. Each of the planes PL1 to PL4 may include a plurality of memory blocks BLK1 to BLKi (where i is a positive integer of 2 or greater). Different row addresses may be set in the plurality of memory blocks BLK1 to BLKi. A programming operation may be performed in the memory block selected according to the row address RADD output from the Figure 1 logic circuit 180 of. Different local lines including word lines may be connected to the plurality of memory blocks BLK1 to BLKi, and bit lines may be commonly connected to the plurality of memory blocks BLK1 to BLKi.

[0046] The independent current sense mode may be performed during the programming operation of the selected page in each of the planes PL1 to PL4, and when all the selected memory cells in the selected page of the planes PL1 to PL4 are programmed to the selected programming state or the target programming state, the independent current sense operation may pass. In the overall current sense mode, when at least one page in which the programming operation is completed is detected in the planes PL1 to PL4, even if there is a plane in the memory cell array 110 in which the programming operation is not completed, the overall current sense operation may be determined to have passed.

[0047] Figure 2 One of the plurality of memory blocks BLK1 to BLKi shown is specifically described as follows.

[0048] Figure 3 is a diagram showing a memory block.

[0049] Refer to Figure 3 which shows Figure 2 any one of the multiple memory blocks BLK1 to BLKi shown, namely memory block BLKi, as one embodiment.

[0050] The memory block BLKi may include multiple strings ST connected between the first bit line BL1 to the m-th bit line BLm (where m is a positive integer of 2 or greater) and the source line SL. Each string ST may include a source selection transistor SST, a first memory cell C1 to an n-th memory cell Cn, and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1 to the m-th bit line BLm.

[0051] Figure 3 An exemplary configuration of the memory block is shown. Therefore, the number of source selection transistors SST, the first memory cell C1 to the n-th memory cell Cn, and the drain selection transistors DST is not limited to Figure 3 the number shown.

[0052] The gates of the source selection transistors SST connected to different strings ST may be connected to the source selection line SSL, the gates of each of the first memory cell C1 to the n-th memory cell Cn may be connected to the first word line WL1 to the n-th word line WLn, and the gates of the drain selection transistors DST may be connected to the drain selection line DSL.

[0053] A group of memory cells connected to the same word line and included in different strings ST may configure a page PG. The programming operation may be performed in units of the page PG. For example, the sub-programming operation and the verification operation may be performed in units of the page PG. For example, after performing the sub-programming operation on the selected page, the verification operation on the selected page may be performed.

[0054] Figure 4 is a diagram showing the page buffer group 140.

[0055] Refer to Figure 4 and the page buffer group 140 may include a first page buffer PB1 to an m-th page buffer PBm (where m is a positive integer of 2 or greater). The first page buffer PB1 to the m-th page buffer PBm may be respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first page buffer PB1 to the m-th page buffer PBm may include multiple latches, and may sense the current or voltage of the first bit line BL1 to the m-th bit line BLm that changes according to the threshold voltage of the memory cell during the verification operation, and store the sensed data in the selected latch.

[0056] Figure 5FIG. is a diagram showing a sensing mode selector 190 according to an embodiment of the present disclosure.

[0057] Referring Figure 5 , the sensing mode selector 190 may include a counter 190a, a mode selector 190b, and a code generator 190c.

[0058] The counter 190a may count the number of programming cycles in response to a pass signal PS or a fail signal FS, and manage the counted number or the cumulative number AN of the programming cycles. For example, the counter 190a may increment the cumulative number AN of the programming cycles by 1 in response to the fail signal FS, and output the cumulative number AN. In addition, when the pass signal PS is input, the counter 190a may initialize the count of the cycle number to 0.

[0059] The mode selector 190b may compare the cumulative number AN output from the counter 190a with a reference number, and output a sensing mode signal SMG according to the comparison result. The output sensing mode signal SMG may correspond to a mode selected from an independent current sensing mode, an overall current sensing mode, and a hybrid current sensing mode. For example, when the cumulative number AN is less than the reference number, the mode selector 190b may output a sensing mode signal SMG corresponding to the independent current sensing mode. When AN is equal to or greater than the reference number, the mode selector 190 may output a sensing mode signal SMG corresponding to the hybrid current sensing mode. That is, after the main programming operation starts, when AN is less than the reference number, the independent current sensing operation may be performed, and when AN is equal to or greater than the reference number, the independent current sensing operation and the overall current sensing operation may be sequentially performed.

[0060] The code generator 190c may change and output an operation code OPCD in response to the sensing mode signal SMG output from the mode selector 190b. For example, when receiving the sensing mode signal SMG corresponding to the independent current sensing mode, the code generator 190c may set a first time interval (e.g., Figure 8 T3 to T4 in Figure 10 ) for discharging the selected word line between the sub-programming operation and the verification operation. Alternatively, when receiving the sensing mode signal SMG corresponding to the hybrid current sensing mode, the code generator 190c may set a second time interval shorter or longer than the first time interval (e.g., T3' to T4 as shown in Figure 11 or T3 to T4' as shown in

[0061] Figure 6 ) for discharging the selected word line between the sub-programming operation and the verification operation. The code generator 190c may output an operation code to reflect the set time interval.It is a diagram showing the threshold voltage distribution of memory cells.

[0062] Referring to Figure 6 , the programming operation can be any one of various methods according to the number of bits stored in the memory cell. For example, the method of storing 3-bit data in one memory cell is called the triple-level cell (TLC) method, and the method of storing 4-bit data in one memory cell is called the quad-level cell (QLC) method.

[0063] In the TLC method, the state of the memory cell can be the erased state ER or any one of the seven programming states P1 to P7. In the QLC method, the state of the memory cell can be the erased state ER or any one of the fifteen programming states P1 to P15.

[0064] In other embodiments, the number of bits that can be stored in one memory cell can be 5 or more, in which case other suitable programming methods can be used. The present invention is not limited to any specific number of bits that can be stored in the memory cell.

[0065] Verification operations using various verification voltages can be performed to program the memory cell to different programming states. The overall programming operation of the selected page can be defined as a main programming operation including multiple programming cycles, and each programming cycle can include a sub-programming operation and a verification operation. The programming cycle is specifically described as follows.

[0066] Figure 7 It is a diagram showing the main programming operation.

[0067] Referring to Figure 7 , the main programming operation can include the first programming cycle LP1 to the nth programming cycle LPn. For example, when starting the main programming operation of the selected page, the first programming cycle LP1 to the nth programming cycle LPn can be sequentially executed. The variable n representing the number of executed cycles can be a positive integer of 2 or more, and can vary according to the result of the verification operation performed in each programming cycle. Here, the maximum value of n is preset in advance, and when the verification operation fails in each of the n programming cycles, the selected memory block can be regarded as a bad block.

[0068] Each of the first programming cycle LP1 to the nth programming cycle LPn can include a sub-programming operation and a verification operation. In the sub-programming operation, a programming pulse is applied to the selected word line, and the verification operation determines whether the threshold voltage of the memory cell increases to the target voltage.

[0069] Figure 7The main programming operation of the TLC method is shown as an embodiment. In the main programming operation of the TLC method, a memory cell can be programmed into seven programming states. Therefore, at least seven verification voltages can be used in the verification operation. For example, in the sub-programming operation of the first programming cycle LP1, a first programming pulse Vp1 can be applied to the selected word line. The first programming pulse Vp1 can be the start program pulse of the main programming operation. The first programming pulse Vp1 can be a positive voltage higher than 0V, and the threshold voltage of the selected memory cell can be increased by the first programming pulse Vp1. In this sub-programming operation, the selected memory cell can be connected to the bit line to which the programming enable voltage is applied, and the unselected memory cell can be connected to the bit line to which the programming inhibit voltage is applied. The programming enable voltage can be 0V, and the programming inhibit voltage can be the power supply voltage. In the verification operation of the first programming cycle LP1, a first verification voltage V1 can be applied to the selected word line. The first verification voltage V1 can be a positive voltage higher than 0V for determining whether the selected memory cell is programmed into the first programming state. When the verification operation of the first programming cycle LP1 fails, a second programming cycle LP2 can be executed.

[0070] In the second programming cycle LP2, a sub-programming operation can be performed using a second programming pulse Vp2 whose voltage is higher than that of the first programming pulse Vp1, and verification operations for the first programming state and the second programming state can be successively performed. For example, in the verification operation of the second programming cycle LP2, the verification operation for the first programming state and the verification operation for the second programming state can be sequentially performed. The first verification voltage V1 can be used in the verification operation for the first programming state, and a second verification voltage V2 higher than the first verification voltage V1 can be used in the verification operation for the second programming state.

[0071] In the third programming cycle LP3, a sub-programming operation can be performed using a third programming pulse Vp3 whose voltage is higher than that of the second programming pulse Vp2, and verification operations for the first programming state to the third programming state can be successively performed. The first verification voltage V1 can be used in the verification operation for the first programming state, the second verification voltage V2 higher than the first verification voltage V1 can be used in the verification operation for the second programming state, and a third verification voltage V3 higher than the second verification voltage V2 can be used in the verification operation for the third programming state. In Figure 7 this, an independent current sensing operation I_CSC is started from the third programming cycle LP3, but the cycle in which the independent current sensing operation is started can be set differently according to the programming operation. As Figure 7As shown, when the probability that the verification operation for the first programming state passes in the first programming loop LP1 and the second programming loop LP2 is low, the independent current sensing operation I_CSC can be started from the third programming loop LP3. The independent current sensing operation I_CSC can be sequentially executed starting from the low programming state. Therefore, when the independent current sensing operation I_CSC is first executed in the third programming loop LP3, the independent current sensing operation can be performed to determine whether the first programming state passes or fails. When the independent current sensing operation I_CSC for the first programming state executed in the third programming loop LP3 passes, the verification operation using the first verification voltage V1 is not performed in the fourth programming loop LP4.

[0072] In the fourth programming loop LP4, a sub-programming operation can be performed using a fourth programming pulse Vp4 having a voltage higher than that of the third programming pulse Vp3, and verification operations for the second to fourth programming states can be sequentially performed. In the verification operation for the fourth programming state, a fourth verification voltage V4 higher than the third verification voltage V3 can be used. As Figure 7 illustrated, the independent current sensing operation I_CSC performed in the fourth programming loop LP4 can be performed on the second programming state. When the independent current sensing operation I_CSC performed in the fourth programming loop LP4 fails, the independent current sensing operation I_CSC for the second programming state can also be performed in the fifth programming loop LP5.

[0073] After the cumulative number AN of programming loops reaches the threshold number THL, an overall current sensing operation A_CSC can be additionally performed. For example, assuming that the threshold number THL is set to (n - 3), the overall current sensing operation A_CSC can be started from the (n - 2)-th programming loop LP(n - 2) until the programming operation of the selected page ends. For example, in the (n - 2)-th programming loop LP(n - 2), the overall current sensing operation A_CSC can be performed after the independent current sensing operation I_CSC is performed.

[0074] The overall current sensing operation A_CSC in each of the (n - 2)-th programming loop LP(n - 2) to the n-th programming loop LPn can be performed in all planes included in the memory cell array. When the overall current sensing operation A_CSC performed in at least one plane passes, the main programming operation can be ended.

[0075] According to the above method, the memory cells included in the selected page can be programmed to the first to seventh programming states. The main programming operation can vary according to the physical and electrical characteristics of the memory cells.

[0076] The sub-programming operations when performing the independent current sensing operation I_CSC and the overall current sensing operation A_CSC are described as follows.

[0077] Figure 8 FIG. is a diagram showing an independent current sensing mode according to an embodiment of the present disclosure.

[0078] Referring to Figure 8 , in the independent current sensing mode, the independent current sensing operation can be performed among the independent current sensing operation and the overall current sensing operation. The independent current sensing mode is specifically described as follows.

[0079] When the sub-programming operation starts (T1), the programming voltage Vpgm can be applied to the selected word line Sel_WL, and the pass voltage Vpass can be applied to the unselected word line Unsel_WL. The programming voltage Vpgm can be used to increase the threshold voltage of the selected memory cell, and the pass voltage Vpass can be used to turn on the unselected memory cell.

[0080] The independent current sensing operation I_CSC can be performed at time point T2. The independent current sensing operation I_CSC can be performed by Figure 1 the current sensing circuit 170, and since sensing takes time, the sub-programming operation can continue to be performed when the independent current sensing operation I_CSC is being performed.

[0081] When the programming voltage Vpgm is applied to the selected word line Sel_WL for a long enough time (T1 to T3), the selected word line Sel_WL and the unselected word line Unsel_WL can be discharged. The discharge operation of the word lines Sel_WL and Unsel_WL can be performed in the time period T3 to T4.

[0082] At time point T4, for the verification operation after the sub-programming operation, a compensation operation for matching the potentials of the word lines Sel_WL and Unsel_WL to be equal can be performed. For example, before T3, there may be a difference in the voltages applied to the selected word line Sel_WL and the unselected word line Unsel_WL. In this case, when the discharge operation is performed at time point T3, coupling may occur between the word lines Sel_WL and Unsel_WL, and thus a potential difference may appear between the word lines Sel_WL and Unsel_WL. Therefore, a compensation operation for reducing the potential difference between the word lines Sel_WL and Unsel_WL can be performed in the time period T4 to T5. During the compensation operation, the compensation voltage Vcm can be applied to the word lines Sel_WL and Unsel_WL. After the compensation operation is completed, the word lines Sel_WL and Unsel_WL can be discharged. For example, the compensation voltage Vcm can be set to a voltage higher than 0V and lower than the pass voltage Vpass.

[0083] In the independent current sensing mode, since the independent current sensing operation I_CSC can end before the sub-programming operation ends at time point T5, the time taken to perform the main programming operation does not increase even if the independent current sensing operation I_CSC is performed.

[0084] Figure 9 is a diagram showing the hybrid current sensing mode.

[0085] Referring to Figure 9 , in the hybrid current sensing mode, the independent current sensing operation I_CSC and the overall current sensing operation A_CSC can be sequentially performed. For example, the overall current sensing operation A_CSC can be performed after the independent current sensing operation I_CSC ends. In the overall current sensing operation A_CSC, since the overall current sensing operation A_CSC determines whether the programming operation of the selected page in multiple planes is completed, it may take a certain amount of time. Since the next operation can only be performed when the overall current sensing operation A_CSC has ended, when the overall current sensing operation A_CSC ends after the end time of the corresponding sub-programming operation (i.e., Figure 9 the time point T5 in), the time required for the main programming operation may increase by the time amount between the completion of the corresponding sub-programming operation and the completion of the overall current sensing operation A_CSC.

[0086] Therefore, in one embodiment, the increase in the time required for the main programming operation can be prevented by adjusting at least one of the first period D1 between T2 when the independent current sensing operation I_CSC starts and T3 when the discharge of the word lines Sel_WL and Unsel_WL starts, the second period D2 between T3 and T4 when the discharge of the word lines Sel_WL and Unsel_WL is completed, and the third period D3 between T4 and T5 during which the compensation operation is performed.

[0087] Figure 10 is a timing diagram showing the hybrid current sensing mode according to the first embodiment of the present disclosure.

[0088] Referring to Figure 10 , in the first embodiment, the first period D1 can be adjusted. For example, the time point T3 when the discharge of the word lines Sel_WL and Unsel_WL starts can be adjusted. When the time point T3 is delayed (i.e., changed to the time point T3'), since the first period D1 increases, the time points T4 and T5 are also delayed correspondingly with the increase of the first period D1. That is, the first period D1 increases, but the second period D2 and the third period D3 can be kept unchanged. The delay from T3 to T3' can be set to the time amount between T5 and the time when the overall current sensing operation A_CSC ends.

[0089] Figure 11 is a timing diagram showing a hybrid current sensing mode according to a second embodiment of the present disclosure.

[0090] Referring to Figure 11 , in the second embodiment, the second period D2 can be adjusted. For example, the time point T4 at which the discharge of the word lines Sel_WL and Unsel_WL is completed can be adjusted. When the time point T4 changes (i.e., is delayed to the time point T4'), since the second period D2 increases, the time point T5 is also delayed correspondingly with the increase of the second period D2. That is to say, the second period D2 increases, but the first period D1 and the third period D3 can be kept unchanged. The amount of time of the delay from T4 to T4' can be set as the amount of time between T5 and the end time of the overall current sensing operation A_CSC.

[0091] Figure 12 is a diagram showing a hybrid current sensing mode according to a third embodiment of the present disclosure.

[0092] Referring to Figure 12 , in the third embodiment, the third period D3 can be adjusted. For example, the time point T5 at which the compensation operation is completed can be adjusted. When the time point T5 changes (i.e., is delayed to the time point T5'), the third period D3 increases. The delay from T5 to T5' can be set such that T5' is the end time of the overall current sensing operation A_CSC.

[0093] As described above, when performing the independent current sensing operation I_CSC and the overall current sensing operation A_CSC, the time required for the main programming operation can be reduced by adjusting the duration for applying voltage to or discharging the word lines Sel_WL and Unsel_WL. The above first to third embodiments can be independently applied to the main programming operation, all of the first to third embodiments can be applied, or some of the embodiments can be selectively applied.

[0094] Figure 13 is a diagram showing a memory system 1000 including a memory device of the present disclosure.

[0095] Referring to Figure 13 , the memory system 1000 may include a memory device 1100 for storing data and a controller 1200 for communicating between the memory device 1100 and the host 2000.

[0096] The memory system 1000 may include a plurality of memory devices 1100, and each memory device may be connected to a controller 1200 via at least one channel. For example, each of the plurality of memory devices 1100 may be connected to the controller 1200 via its own channel, all the memory devices 1100 may be connected to the controller 1200 via the same channel, or the memory devices 1100 may be divided into groups, each group having its own channel, such that all the memory devices in a given group are connected to the controller 1200 via the same channel.

[0097] The controller 1200 may communicate between the host 2000 and the memory devices 1100. The controller 1200 may control the memory devices 1100 according to requests from the host 2000, or may perform background operations for improving the performance of the memory system 1000 without requests from the host 2000. The host 2000 may generate requests for various operations and may output the generated requests to the memory system 1000. For example, the requests may include: a programming request that may control a programming operation, a read request that may control a read operation, an erase request that may control an erase operation, etc.

[0098] The host 2000 may communicate with the memory system 1000 through any one of various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0099] Figure 14 FIG. is a diagram showing another memory system 7000 including the memory device of the present disclosure.

[0100] Referring to Figure 14 , the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a semiconductor memory device 1100, a controller 1200, and a card interface 7100.

[0101] The controller 2100 may control data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but the present invention is not limited thereto.

[0102] The card interface 7100 can interface the data exchange between the host 60000 and the controller 1200 according to the protocol of the host 60000. According to one embodiment, the card interface 7100 can support the Universal Serial Bus (USB) protocol and the Inter-Chip (IC)-USB protocol. Here, the card interface 7100 can refer to the hardware capable of supporting the protocol used by the host 60000, the software installed in the hardware, or the signal transmission method.

[0103] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., a personal computer, a tablet computer, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box), the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100.

[0104] Although the present invention has been shown and described in conjunction with various embodiments, those skilled in the art will recognize that various modifications can be made to any disclosed embodiment within the spirit and scope of the present invention according to the present disclosure. The present invention includes all such modifications that fall within the scope of the claims.

[0105] Cross-reference to related applications

[0106] This application claims the priority of Korean Patent Application No. 10-2020-0098794, filed on August 6, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A plurality of memory cells; A page buffer configured to store sensed data sensed from the memory cells; A current sensing circuit configured to, in response to a sensing mode signal, perform an independent current sensing operation of outputting a pass signal or a fail signal according to a verification result of each selected programming state in an independent current sensing mode, and perform an overall current sensing operation of outputting the pass signal or the fail signal according to a verification result of overall memory cells regardless of the selected programming state after performing the independent current sensing operation in a hybrid current sensing mode; A sensing mode selector configured to output the sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode in response to the pass signal or the fail signal, and output an operation code according to the sensing mode signal; And A voltage generator configured to, in response to the operation code, apply a programming voltage to a selected word line connected to a selected memory cell during a first time period in the independent current sensing mode, and apply the programming voltage to the selected word line during a second time period greater than the first time period in the hybrid current sensing mode.

2. The memory device according to claim 1, wherein, The sensing mode selector includes: A counter configured to count the number of programming cycles in response to the pass signal or the fail signal, and output an accumulated quantity; A mode selector configured to compare the accumulated quantity with a reference quantity, and output the sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode according to a comparison result; and A code generator configured to output the operation code to the voltage generator in response to the sensing mode signal, so as to apply the programming voltage to the selected word line during the first time period or the second time period.

3. The memory device according to claim 2, wherein, The counter increments the accumulated quantity whenever the fail signal is input, outputs the accumulated quantity, and initializes the accumulated quantity when the pass signal is input.

4. The memory device according to claim 2, wherein, When the accumulated quantity is less than the reference quantity, the mode selector outputs the sensing mode signal as a signal corresponding to the independent current sensing mode, and when the accumulated quantity is equal to or greater than the reference quantity, the mode selector outputs the sensing mode signal as a signal corresponding to the hybrid current sensing mode.

5. The memory device according to claim 2, wherein, When the sensing mode signal is a signal corresponding to the independent current sensing mode, the code generator outputs the operation code so as to apply the programming voltage to the selected word line during the first time period, and when the sensing mode signal is a signal corresponding to the hybrid current sensing mode, the code generator outputs the operation code so as to apply the programming voltage to the selected word line during the second time period.

6. The memory device according to claim 1, wherein, The current sensing circuit performs the independent current sensing operation or the overall current sensing operation by comparing a set number with the number of failed bits detected during the verification operation in the previous programming cycle.

7. The memory device according to claim 6, wherein, The set number used in the independent current sensing operation is different from the set number used in the overall current sensing operation.

8. The memory device according to claim 1, wherein, The voltage generator is configured to discharge the selected word line during a set time period and apply a compensation voltage to the selected word line after applying the programming voltage to the selected word line during the first time period or the second time period.

9. The memory device according to claim 1, wherein, The difference between the second time period and the first time period is set to be the time difference between the end time of the sub-programming operation in the independent current sensing mode and the end time of the overall current sensing operation in the hybrid current sensing mode.

10. A memory device, the memory device comprising: A plurality of memory cells; A page buffer configured to store sensed data sensed from the memory cells; A current sensing circuit configured to, in response to a sensing mode signal, in an independent current sensing mode, perform an independent current sensing operation of outputting a pass signal or a fail signal according to a verification result of each selected programming state, and in a hybrid current sensing mode, perform an overall current sensing operation of outputting the pass signal or the fail signal according to a verification result of overall memory cells regardless of the selected programming state after performing the independent current sensing operation; A sensing mode selector configured to output the sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode in response to the pass signal or the fail signal, and output an operation code according to the sensing mode signal; And A voltage generator configured to, during a programming operation, after applying a programming voltage to a selected word line connected to a selected memory cell, in response to the operation code, discharge the selected word line during a first duration in the independent current sensing mode and discharge the selected word line during a second duration greater than the first duration in the hybrid current sensing mode.

11. The memory device according to claim 10, wherein, The sensing mode selector includes: A counter configured to count the number of programming cycles in response to the pass signal or the fail signal and output an accumulated number; A mode selector configured to compare the accumulated number with a reference number and output the sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode according to a comparison result; and A code generator configured to output the operation code to the voltage generator in response to the sensing mode signal so that the voltage generator discharges the selected word line during the first duration or the second duration.

12. The memory device according to claim 11, wherein, The counter increments the cumulative quantity whenever the failure signal is input, outputs the cumulative quantity, and initializes the cumulative quantity when the pass signal is input.

13. The memory device according to claim 11, wherein, When the cumulative quantity is less than the reference quantity, the mode selector outputs the sense mode signal as a signal corresponding to the independent current sensing mode, and when the cumulative quantity is equal to or greater than the reference quantity, the mode selector outputs the sense mode signal as a signal corresponding to the hybrid current sensing mode.

14. The memory device according to claim 11, wherein, When the sense mode signal is a signal corresponding to the independent current sensing mode, the code generator outputs the opcode to cause the voltage generator to discharge the selected word line during the first duration, and when the sense mode signal is a signal corresponding to the hybrid current sensing mode, the code generator outputs the opcode to cause the voltage generator to discharge the selected word line during the second duration.

15. The memory device according to claim 10, wherein, The current sensing circuit performs the independent current sensing operation or the overall current sensing operation by comparing a set quantity with the number of failed bits detected in the verification operation of the previous programming cycle.

16. The memory device according to claim 15, wherein, The set quantity used in the independent current sensing operation is different from the set quantity used in the overall current sensing operation.

17. The memory device according to claim 10, wherein, The voltage generator is configured to discharge the selected word line during the first duration or the second duration, and then apply a compensation voltage to the selected word line.

18. A memory device, the memory device comprising: A plurality of memory cells; A page buffer configured to store sense data sensed from the memory cells; A current sensing circuit configured to, in response to a sense mode signal, in an independent current sensing mode, perform an independent current sensing operation of outputting a pass signal or a failure signal according to the verification result of each selected programming state, and in a hybrid current sensing mode, after performing the independent current sensing operation, perform an overall current sensing operation of outputting the pass signal or the failure signal according to the verification result of the overall memory cells regardless of the selected programming state; A sense mode selector configured to output the sense mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode in response to the pass signal or the failure signal, and output an opcode according to the sense mode signal; And A voltage generator configured to, during a programming operation, after applying a programming voltage to a selected word line connected to a selected memory cell and discharging the selected word line, in response to the opcode, apply a compensation voltage to the discharged selected word line during a first duration in the independent current sensing mode, and apply the compensation voltage to the discharged selected word line during a second duration greater than the first duration in the hybrid current sensing mode.

19. The memory device according to claim 18, wherein, The sense mode selector includes: A counter configured to count a cumulative number of programming cycles in response to the pass signal or the fail signal and output the cumulative number; A mode selector configured to compare the cumulative number with a reference number and output a sensing mode signal corresponding to the independent current sensing mode or the hybrid current sensing mode according to a comparison result; and A code generator configured to output the opcode to the voltage generator in response to the sensing mode signal so that the voltage generator applies the compensation voltage to the selected word line during the first duration or the second duration.

20. The memory device according to claim 19, wherein, When the sensing mode signal is a signal corresponding to the independent current sensing mode, the code generator outputs the opcode so that the voltage generator applies the compensation voltage during the first duration, and when the sensing mode signal is a signal corresponding to the hybrid current sensing mode, the code generator outputs the opcode so that the voltage generator applies the compensation voltage during the second duration.

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