Pixel array substrate

Abstract

A pixel array substrate includes a plurality of pixel structures. Each pixel structure includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode located within an opening of the color filter pattern.

Description

Technical Field

[0001] The invention relates to a pixel array substrate. Background Art

[0002] With the development of display technology, people's demands for display devices are no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect display devices to have narrow borders or even no borders.

[0003] Generally speaking, a display device includes a plurality of pixel structures arranged in a display area, a data driving circuit arranged below the display area, and a gate driving circuit arranged on the left, right, or both sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is arranged on the lower side of the display area, the gate lines arranged in the vertical direction must be electrically connected to the gate driving circuit through the adapter wires arranged in the horizontal direction. However, the gate turn-on pulse signal of the adapter wire will affect the potential of other pixel structures that are still being charged, thereby causing display abnormalities (for example: oblique bright lines). Therefore, how to improve the problem of display abnormalities is one of the challenges faced by current ultra-narrow frame display devices. In addition, how to improve the aperture ratio of the display device and make it less prone to bubble problems is another topic. Summary of the invention

[0004] The invention provides a pixel array substrate with a high aperture ratio.

[0005] The pixel array substrate of the present invention comprises a substrate and a plurality of pixel structures arranged on the substrate. Each pixel structure comprises a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor, wherein the first portion of the conductive pattern is arranged on the first common electrode. The first insulating layer is arranged on the conductive pattern and has an opening overlapping with the conductive pattern. The color filter pattern is arranged on the first insulating layer and has an opening overlapping with the conductive pattern. The second insulating layer is arranged on the color filter pattern and has an opening overlapping with the conductive pattern. The pixel electrode is arranged on the second insulating layer and is electrically connected to the conductive pattern through the opening of the first insulating layer and the opening of the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode located within the opening of the color filter pattern.

[0006] In one embodiment of the present invention, each of the above-mentioned pixel structures further includes a second common electrode. The second common electrode is separated from the first common electrode. The second portion of the conductive pattern is disposed on the second common electrode. In a top view of the pixel array substrate, the second portion of the conductive pattern covers all edges of the second common electrode located within the opening of the color filter pattern.

[0007] In one embodiment of the present invention, the above-mentioned conductive pattern also has a third part; in the top view of the pixel array substrate, the third part of the conductive pattern is located between the first common electrode and the second common electrode, and the opening of the first insulating layer and the opening of the second insulating layer are located on the third part of the conductive pattern.

[0008] In an embodiment of the present invention, in the top view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the second common electrode and do not overlap the first common electrode and the second common electrode.

[0009] In one embodiment of the present invention, each of the above-mentioned pixel structures further includes a third common electrode. The third common electrode is separated from the first common electrode and the second common electrode. The fourth portion of the conductive pattern is disposed on the third common electrode. In a top view of the pixel array substrate, the fourth portion of the conductive pattern covers all edges of the third common electrode located within the opening of the color filter pattern.

[0010] In an embodiment of the present invention, the edge of the first portion of the conductive pattern is substantially aligned with the edge of the opening of the color filter pattern.

[0011] In one embodiment of the present invention, the conductive pattern further has a fifth portion; in a top view of the pixel array substrate, the fifth portion of the conductive pattern overlaps with the first common electrode and is located outside the opening of the color filter pattern.

[0012] In one embodiment of the present invention, the above-mentioned thin film transistor has a gate separated from the first common electrode; the second part of the conductive pattern is arranged on the gate; in the top view of the pixel array substrate, the second part of the conductive pattern covers all edges of the gate located in the opening of the color filter pattern.

[0013] In one embodiment of the present invention, the above-mentioned conductive pattern also has a third portion; in the top view of the pixel array substrate, the third portion of the conductive pattern is located between the first common electrode and the gate, and the opening of the first insulating layer and the opening of the second insulating layer are located on the third portion of the conductive pattern.

[0014] In one embodiment of the present invention, in the top view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the gate, and the opening of the first insulating layer and the opening of the second insulating layer do not overlap the first common electrode and the gate.

[0015] In one embodiment of the present invention, the above-mentioned multiple pixel structures are arranged into multiple pixel rows, and the multiple pixel rows are arranged in the first direction. The pixel array substrate also includes multiple scan lines, multiple data lines and multiple adapters. The multiple scan lines are arranged in the second direction and electrically connected to the multiple pixel structures, wherein the first direction and the second direction are staggered. The multiple data lines are arranged in the first direction and electrically connected to the multiple pixel rows. The multiple adapters are arranged in the first direction and electrically connected to the multiple scan lines. The multiple scan lines include the xnth scan line to the xth scan line arranged in sequence in the second direction, x is a positive integer greater than or equal to 2, n is a positive integer and less than x, and the opening time of the gate drive signal of the xth scan line overlaps with the closing time of the gate drive signal of the xnth scan line in timing. The multiple adapters include the xnth adapter and the xth adapter, which are electrically connected to the xnth scan line and the xth scan line, respectively. The plurality of pixel rows include a k-1th pixel row, a kth pixel row, and a k+1th pixel row arranged in sequence in a first direction, where k is a positive integer greater than or equal to 2. The plurality of data lines include a k-1th data line, a kth data line, and a k+1th data line, which are electrically connected to the k-1th pixel row, the kth pixel row, and the k+1th pixel row, respectively. In a top view of the pixel array substrate, an xnth adapter line is disposed between the k-1th data line and the kth data line, and an xth adapter line is disposed between the kth data line and the k+1th data line.

[0016] In one embodiment of the present invention, the above-mentioned multiple scan lines include the xnth scan line to the x+nth scan line arranged in sequence in the second direction. The end time of the gate pulse signal of the xth scan line overlaps with the start time of the gate pulse signal of the x+nth scan line in timing. The multiple adapters also include the x+nth adapter, which is electrically connected to the x+nth scan line. The multiple pixel rows also include the k+2th pixel row. The k-1th pixel row, the kth pixel row, the k+1th pixel row and the k+2th pixel row are arranged in sequence in the first direction. The multiple data lines also include the k+2th data line, which is electrically connected to the k+2th pixel row. In the top view of the pixel array substrate, the x+nth adapter is arranged between the k+1th data line and the k+2th data line.

[0017] In one embodiment of the present invention, the plurality of pixel rows further include a k+2th pixel row. The k-1th pixel row, the kth pixel row, the k+1th pixel row and the k+2th pixel row are arranged in sequence in the first direction. The plurality of data lines further include a k+2th data line electrically connected to the k+2th pixel row. The pixel array substrate further includes a first common line. In a top view of the pixel array substrate, the first common line is disposed between the k+1th data line and the k+2th data line.

[0018] In one embodiment of the present invention, the above-mentioned multiple pixel rows also include a k+2-th pixel row. The k-1-th pixel row, the k-th pixel row, the k+1-th pixel row and the k+2-th pixel row are arranged in sequence in the first direction. The multiple data lines also include a k+2-th data line, which is electrically connected to the k+2-th pixel row. The multiple scan lines include an m-th scan line. The multiple adapter lines also include an m-th adapter line, which is electrically connected to the m-th scan line. m is a positive integer greater than 2, and |xm| is not equal to n. In the top view of the pixel array substrate, the m-th adapter line is arranged between the k+1-th data line and the k+2-th data line.

[0019] In one embodiment of the present invention, the above-mentioned multiple scan lines include the ynth scan line to the yth scan line arranged in sequence in the second direction, y is a positive integer greater than or equal to 2, n is a positive integer and less than y, and the start time of the gate pulse signal of the yth scan line overlaps with the end time of the gate pulse signal of the ynth scan line in timing. The multiple adapters include the ynth adapter and the yth adapter, which are electrically connected to the ynth scan line and the yth scan line, respectively. The multiple pixel rows include the q-1th pixel row, the qth pixel row and the q+1th pixel row arranged in sequence in the first direction, and q is a positive integer greater than or equal to 2. The multiple data lines include the q-1th data line, the qth data line and the q+1th data line, which are electrically connected to the q-1th pixel row, the qth pixel row and the q+1th pixel row, respectively. In the top view of the pixel array substrate, the y-th switching line is disposed between the q-1-th data line and the q-th data line, and the yn-th switching line is disposed between the q-th data line and the q+1-th data line.

[0020] In one embodiment of the present invention, the plurality of pixel rows further include a q+2th pixel row. The q-1th pixel row, the qth pixel row, the q+1th pixel row and the q+2th pixel row are arranged in sequence in the first direction. The plurality of data lines further include a q+2th data line electrically connected to the q+2th pixel row. The pixel array substrate further includes a second common line. In a top view of the pixel array substrate, the second common line is disposed between the q+1th data line and the q+2th data line.

[0021] In one embodiment of the present invention, the above-mentioned multiple pixel rows also include a q+2th pixel row. The q-1th pixel row, the qth pixel row, the q+1th pixel row and the q+2th pixel row are arranged in sequence in the first direction. The multiple data lines also include a q+2th data line, which is electrically connected to the q+2th pixel row. The multiple scan lines include a pth scan line. The multiple adapter lines also include a pth adapter line, which is electrically connected to the pth scan line. p is a positive integer greater than 2, and |yp| is not equal to n. In the top view of the pixel array substrate, the pth adapter line is arranged between the q+1th data line and the q+2th data line.

[0022] In one embodiment of the present invention, the above n=4.

[0023] In one embodiment of the present invention, the above n=8.

[0024] In one embodiment of the present invention, one of the plurality of scan lines belongs to the first conductive layer. One of the plurality of adapter lines belongs to the second conductive layer. The pixel array substrate further includes an insulating layer disposed between the first conductive layer and the second conductive layer and having a contact window. One of the plurality of scan lines is electrically connected to one of the plurality of adapter lines through the contact window of the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0026] Figure 2 Show Figure 1 The gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n are HGx-n ~S HGx+n .

[0027] Figure 3 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention.

[0028] Figure 4 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate 100 according to an embodiment of the present invention.

[0029] Figure 5 FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

[0030] Figure 6 1 to 18 of the scanning lines HG1 to HG18 according to an embodiment of the present invention. HG1 ~S HG18 .

[0031] Figure 7 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0032] Figure 8 Show Figure 7 The gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n are HGx-n ~S HGx+n .

[0033] Fig. 9FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0034] Fig.10 Show Fig. 9 The gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n are HGx-n ~S HGx+n .

[0035] Fig.11 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0036] Fig.12 Show Fig.11 The gate pulse signals S of the yn-th scanning line HGy-n to the y-th scanning line HGy are HGy-n ~S HGy .

[0037] Fig.13 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0038] Fig.14 Show Fig.13 The gate pulse signals S of the yn-th scanning line HGy-n to the y-th scanning line HGy are HGy-n ~S HGy .

[0039] Fig.15 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100A according to an embodiment of the present invention.

[0040] Fig.16 Show Fig.15 The gate pulse signals S of the first scanning line HG1 to the ninth scanning line HG9 are HG1 ~S HG9 .

[0041] Fig.17 FIG. 1 is a cross-sectional schematic diagram of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention.

[0042] Fig.18 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention.

[0043] Fig.19 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention.

[0044] Fig. 20FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

[0045] Fig.21 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

[0046] Fig. 22 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention.

[0047] Fig.23 FIG. 1 is a cross-sectional schematic diagram of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention.

[0048] Description of reference numerals:

[0049] 100, 100A, 100B, 100C, 100D: Pixel array substrate

[0050] 110: Base

[0051] 122: first common electrode

[0052] 122e, 124e, 126e, 142e, 142-1e, 162e, Tcs: Edge

[0053] 124: Second common electrode

[0054] 126: Third common electrode

[0055] 130: Insulation layer

[0056] 132: Contact window

[0057] 142: Conductive pattern

[0058] 142-1: Part 1

[0059] 142-2: Part 2

[0060] 142-3: Part 3

[0061] 142-4: Part 4

[0062] 142-5: Part 5

[0063] 150: First insulation layer

[0064] 152, 172, 162, 192: Opening

[0065] 160: Color filter pattern

[0066] 164: Sidewall

[0067] 170: Second insulation layer

[0068] 180: Transparent conductive layer

[0069] 190: The third insulation layer

[0070] 194: Pixel electrode

[0071] A: Area

[0072] DL, DLk-1, DLk, DLk+1, DLk+2, DLq-1, DLq, DLq+1, DLq+2, DL1~DL23: data lines

[0073] d1: first direction

[0074] d2: second direction

[0075] HG, HGm, HGp, HGx-n~HGx+n, HGy-n~HGy, HG1~HG18: Scan line

[0076] PX: Pixel structure

[0077] R, Rk-1, Rk, Rk+1, Rk+2, Rq-1, Rq, Rq+1, Rq+2, R1~R23: pixel rows

[0078] S HGx-n ~S HGx+n , S HGy-n ~S HGy , S HG1 ~S HG18 , S VGx-n , S VGx , S VGx+n , S VG1 ~S VG18 : Gate pulse signal

[0079] T: Thin Film Transistor

[0080] Ta: Source

[0081] Tb: drain

[0082] Tc: Gate

[0083] Td: Semiconductor pattern

[0084] Tp: Pulse time length

[0085] t: length of time delay

[0086] tonx, tonx+n, tony, ton1, ton3, ton5, ton7, ton9, ton11, ton13, ton14, ton15, ton16, ton17, ton18: start time

[0087] toffx-n, toffx, toffy-n, toff1, toff3, toff5, toff6, toff7, toff8, toff9, toff10: end time

[0088] VG, VGp, VGm, VGx-n, VGx, VGx+n, VGy-n, VGy, VG1~VG18: Adapter cable

[0089] VGa: At least part

[0090] Vgh: High potential

[0091] Vgl: low potential

[0092] VSS1, VSS1a, VSS1b, VSS1c, VSS1d: First common line

[0093] VSS2: Second common line

[0094] I-I', II-II', III-III', IV-IV', V-V': hatching line DETAILED DESCRIPTION

[0095] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0096] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other elements between two elements.

[0097] As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without a single standard deviation.

[0098] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0099] Figure 1 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0100] Figure 2 Show Figure 1 The gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n are HGx-n ~S HGx+n .

[0101] Figure 3 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention. Figure 3 correspond Figure 1 Area A.

[0102] Figure 4 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate 100 according to an embodiment of the present invention. Figure 4 correspond Figure 3 Section line I-I'.

[0103] Please refer to Figure 1 and Figure 4 , the pixel array substrate 100 includes a substrate 110. For example, in this embodiment, the material of the substrate 110 may be glass. However, the present invention is not limited thereto, and in other embodiments, the material of the substrate 110 may also be quartz, organic polymer, opaque / reflective material (e.g., wafer, ceramic, etc.), or other applicable materials.

[0104] Please refer to Figure 1The pixel array substrate 100 further includes a plurality of pixel structures PX disposed on the substrate 110. The plurality of pixel structures PX are arranged into a plurality of pixel rows R. The plurality of pixel rows R are arranged in a first direction d1.

[0105] Please refer to Figure 1 and Figure 3 Each pixel structure PX includes a thin film transistor T and a pixel electrode 194. The thin film transistor T has a source Ta, a drain Tb, a gate Tc and a semiconductor pattern Td. The insulating layer 130 (drawn on Figure 4 ) is sandwiched between the gate electrode Tc and the semiconductor pattern Td. The insulating layer 130 can also be called a gate insulating layer. The source electrode Ta and the drain electrode Tb are electrically connected to two different regions of the semiconductor pattern Td, respectively, and the pixel electrode 194 is electrically connected to the drain electrode Tb.

[0106] For example, in the present embodiment, the gate Tc of the thin film transistor T may belong to the first conductive layer, and the source Ta and the drain Tb of the thin film transistor T may belong to the second conductive layer, but the present invention is not limited thereto.

[0107] In this embodiment, the first conductive layer may be a first metal layer; that is, the material of the first conductive layer may be metal. However, the present invention is not limited thereto, and in other embodiments, the material of the first conductive layer may be other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0108] In this embodiment, the second conductive layer may be a second metal layer; that is, the material of the second conductive layer may be metal. However, the present invention is not limited thereto, and in other embodiments, the material of the second conductive layer may also be other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0109] Please refer to Figure 1 and Figure 3 , the pixel array substrate 100 further includes a plurality of scan lines HG arranged in a second direction d2, wherein the first direction d1 is interlaced with the second direction d2. For example, in the present embodiment, the first direction d1 and the second direction d2 may be perpendicular, but the present invention is not limited thereto. The plurality of scan lines HG are electrically connected to the plurality of pixel structures PX. In detail, the plurality of scan lines HG are electrically connected to the plurality of gates Tc of the plurality of thin film transistors T of the plurality of pixel structures PX. In the present embodiment, the scan lines HG may belong to the first conductive layer, but the present invention is not limited thereto.

[0110] Please refer to Figure 1 and Figure 3, the pixel array substrate 100 further includes a plurality of data lines DL arranged in the first direction d1 and electrically connected to the plurality of pixel rows R. Specifically, in the present embodiment, the plurality of data lines DL are electrically connected to the plurality of source electrodes Ta of the plurality of thin film transistors T of the plurality of pixel rows R, and the plurality of source electrodes Ta of the plurality of pixel structures PX of the same pixel row R are electrically connected to the same data line DL. In the present embodiment, the data lines DL may belong to the second conductive layer, but the present invention is not limited thereto.

[0111] Please refer to Figure 1 and Figure 3 The pixel array substrate 100 further includes a plurality of transfer lines VG arranged in the first direction d1 and electrically connected to the plurality of scan lines HG. Figure 1 , Figure 3 and Figure 4 For example, in this embodiment, the scanning line HG belongs to the first conductive layer, and at least a portion VGa (indicated at Figure 4 ) belongs to the second conductive layer; the insulating layer 130 is disposed between the first conductive layer and the second conductive layer and has a contact window 132 (marked at Figure 4 ); at least a portion VGa of the transfer line VG is electrically connected to the scan line HG through the contact window 132 of the insulating layer 130.

[0112] Please refer to Figure 1 The plurality of scan lines HG include an xnth scan line HGx-n to an x+nth scan line HGx+n arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x.

[0113] Please refer to Figure 1 and Figure 2 , the xnth scanning line HGx-n to the x+nth scanning line HGx+n respectively have gate pulse signals S HGx-n To the gate pulse signal S HGx+n Specifically, the xn-th scanning line HGx-n has a gate pulse signal S HGx-n , the x-n+1th scanning line HGx-n+1 has a gate pulse signal S HGx-n+1 , the x-n+2th scanning line HGx-n+2 has a gate pulse signal S HGx-n+2 , ..., the x-th scanning line HGx has a gate pulse signal S HGx , the x+1th scanning line HGx+1 has a gate pulse signal S HGx+1 , the x+2th scanning line HGx+2 has a gate pulse signal S HGx+2 , ..., the x+nth scanning line HGx+n has a gate pulse signal S HGx+n .

[0114] Please refer to Figure 1 and Figure 2 In this embodiment, the xnth scanning line HGx-n to the x+nth scanning line HGx+n are sequentially turned on with a time delay, wherein the length of the time delay is t (shown in FIG. Figure 2 ), gate pulse signal S HGx-n To the gate pulse signal S HGx+n The pulse time length of each is Tp (plotted on Figure 2 ), and n=Tp / t. The gate pulse signal S of the x-th scanning line HGx HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HGx-n HGx-n The end time toffx-n of the x-th scanning line HGx overlaps in timing. HGx The period from the low potential Vgl to the high potential Vgh and the gate pulse signal S HGx-n The period from the high potential Vgh to the low potential Vgl at least partially overlaps in timing. HGx The end time toffx of the x+nth scanning line HGx+n is HGx+n The start time tonx+n of the x-th scanning line HGx overlaps in timing. HGx The period from the high potential Vgh to the low potential Vgl and the gate pulse signal S HGx+n The period from the low potential Vgl to the high potential Vgh at least partially overlaps in timing.

[0115] Please refer to Figure 1 The plurality of adapter wires VG include the xnth adapter wire VGx-n, the xth adapter wire VGx, and the x+nth adapter wire VGx+n, which are electrically connected to the xnth scan line HGx-n, the xth scan line HGx, and the x+nth scan line HGx+n, respectively. Figure 1 and Figure 2 , the xnth transfer line VGx-n, the xth transfer line VGx and the x+nth transfer line VGx+n respectively have gate pulse signals S VGx-n , gate pulse signal S VGx And the gate pulse signal S VGx+n , where the gate pulse signal S of the xnth transfer line VGx-n VGx-n , the gate pulse signal S of the xth transfer line VGx VGx and the gate pulse signal S of the x+nth transfer line VGx+n VGx+nThe gate pulse signal S of the xn-th scanning line HGx-n is respectively HGx-n , the gate pulse signal S of the x-th scanning line HGx HGx and the gate pulse signal S of the x+nth scanning line HGx+n HGx+n same.

[0116] Please refer to Figure 1 , multiple pixel rows R include a k-1th pixel row Rk-1, a kth pixel row Rk and a k+1th pixel row Rk+1 arranged in sequence in the first direction d1, k is a positive integer greater than or equal to 2; multiple data lines DL include a k-1th data line DLk-1, a kth data line DLk and a k+1th data line DLk+1, which are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk and the k+1th pixel row Rk+1, respectively.

[0117] Please refer to Figure 1 It is worth noting that, in the top view of the pixel array substrate 100, the xnth transfer line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, and the xth transfer line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1. In other words, the xnth transfer line VGx-n and the xth transfer line VGx are adjacent to the same kth data line DLk, and are respectively located on the left and right sides of the same kth data line DLk. Please refer to Figure 1 and Figure 2 , in particular, due to the gate pulse signal S of the xth transfer line VGx VGx The start time tonx and the gate pulse signal S of the xnth transfer line VGx-n VGx-n The end time toffx-n overlaps in timing, so the capacitive coupling effect between the xn-th transfer line VGx-n and the k-th data line DLk and the capacitive coupling effect between the x-th transfer line VGx and the k-th data line DLk can be offset, so that the pixel electrode 194 (drawn in FIG. 1 ) of the pixel structure PX located in the k-th pixel row Rk and electrically connected to the x-th scan line HGx Figure 3 ) is not likely to deviate excessively from the ideal value due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the k-th pixel row Rk and electrically connected to the x-th scan line HGx is not likely to have abnormal brightness (e.g., too bright), thereby improving the problem of oblique bright lines described in the prior art. The following is a specific example with other figures.

[0118] Figure 5 FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

[0119] Figure 61 to 18 of the scanning lines HG1 to HG18 according to an embodiment of the present invention. HG1 ~S HG18 .

[0120] Please refer to Figure 5 , a plurality of pixel structures PX are disposed on the substrate 110 and arranged into the first pixel row R1 to the 23rd pixel row R23, wherein the first pixel row R1 to the 23rd pixel row R23 are arranged in the first direction d1. A plurality of scan lines HG include the first scan line HG1 to the 18th scan line HG18, which are arranged in sequence in the second direction d2. A plurality of data lines DL include the first data line DL1 to the 23rd data line DL23, which are electrically connected to the first pixel row R1 to the 23rd pixel row R23, respectively.

[0121] Please refer to Figure 5 and Figure 6 , the first scanning line HG1 to the eighteenth scanning line HG18 respectively have gate pulse signals S HG1 To the gate pulse signal S HG18 In this embodiment, the first scanning line HG1 to the eighteenth scanning line HG18 are sequentially turned on with a time delay, wherein the length of the time delay is t (shown in FIG. Figure 6 ), gate pulse signal S HG1 To the gate pulse signal S HG18 The pulse time length of each is Tp (plotted on Figure 6 ), n=Tp / t, n is 8, for example, but the present invention is not limited thereto.

[0122] Please refer to Figure 5 The plurality of adapter wires VG include the first adapter wire VG1 to the eighteenth adapter wire VG18, which are electrically connected to the first scan line HG1 to the eighteenth scan line HG18, respectively. Figure 5 and Figure 6 , the 1st adapter wire VG1 to the 18th adapter wire VG18 respectively have gate pulse signals S VG1 To the gate pulse signal S VG18 , where the gate pulse signal S of the first adapter VG1 VG1 Gate pulse signal S to the 18th adapter VG18 VG18 The gate pulse signal S HG1 The gate pulse signal S to the 18th scanning line HG18 HG18 same.

[0123] Please refer to Figure 1 and Figure 2The plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x; the gate pulse signal S of the xth scan line HGx HGx The start time tonx and the gate pulse signal S of the xnth scanning line HG HGx-n The end time toffx-n overlaps in timing; the gate pulse signal S HGx The end time toffx of the x+nth scanning line HG is related to the gate pulse signal S HGx+n The start time tonx+n overlaps in timing; multiple transfer lines VG include an xn-th transfer line VGx-n, an x-th transfer line VGx and an x+n-th transfer line VGx+n, which are electrically connected to the xn-th scan line HGx-n, the x-th scan line HGx and the x+n-th scan line HGx+n, respectively; multiple pixel rows R include a k-1-th pixel row Rk-1, a k-th pixel row Rk and a k+1-th pixel row Rk+1 arranged in sequence in the first direction d1, where k is a positive integer greater than or equal to 2; multiple data lines DL include a k-1-th data line DLk-1, a k-th data line DLk and a k+1-th data line DLk+1, which are electrically connected to the k-1-th pixel row Rk-1, the k-th pixel row Rk and the k+1-th pixel row Rk+1, respectively. In the top view of the pixel array substrate 100, the xnth transfer line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, and the xth transfer line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1; Figure 5 and Figure 6 Take this as an example.

[0124] Please refer to Figure 5 and Figure 6 In one place of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 9, and 2 respectively (ie, n=8, x=9, k=2). Figure 5 and Figure 6 In one place of the pixel array substrate 100 of the present embodiment, the plurality of scan lines HG include the first scan line HG1 to the seventeenth scan line HG17 sequentially arranged in the second direction d2; the gate pulse signal S of the ninth scan line HG9 HG9 The start time ton9 and the gate pulse signal S of the first scanning line HG1 HG1 The end time toff1 of the 9th scanning line HG9 overlaps in timing; the gate pulse signal S HG9 The end time toff9 is related to the gate pulse signal S of the 17th scanning line HG17. HG17The start time ton17 overlaps in timing; the plurality of adapter wires VG include the first adapter wire VG1, the ninth adapter wire VG9 and the seventeenth adapter wire VG17, which are electrically connected to the first scan line HG1, the ninth scan line HG9 and the seventeenth scan line HG17 respectively; the plurality of pixel rows R include the first pixel row R1, the second pixel row R2 and the third pixel row R3 arranged in sequence in the first direction d1; the plurality of data lines DL include the first data line DL1, the second data line DL2 and the third data line DL3, which are electrically connected to the first pixel row R1, the second pixel row R2 and the third pixel row R3 respectively. In the top view of the pixel array substrate 100, the first adapter wire VG1 is disposed between the first data line DL1 and the second data line DL2, and the ninth adapter wire VG is disposed between the second data line DL2 and the third data line DL3.

[0125] Please refer to Figure 5 In other words, the first adapter line VG1 and the ninth adapter line VG9 are adjacent to the second data line DL2 and are located on the left and right sides of the second data line DL2, respectively. Figure 5 and Figure 6 In particular, due to the gate pulse signal S of the 9th adapter VG9 VG9 The start time ton9 and the gate pulse signal S of the first transfer line VG1 VG1 The end time toff1 of the first switching line VG1 overlaps in timing, so the capacitive coupling effect between the first switching line VG1 and the second data line DL2 and the capacitive coupling effect between the ninth switching line VG9 and the second data line DL2 can be offset, so that the pixel electrode 194 (drawn in FIG. 1 ) of the pixel structure PX located in the second pixel row R2 and electrically connected to the ninth scanning line HG9 Figure 3 ) is not likely to deviate excessively from the ideal value due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the second pixel row R2 and electrically connected to the ninth scan line HG9 is not likely to have abnormal brightness (e.g., too bright), thereby improving the problem of oblique bright lines in the prior art.

[0126] Please refer to Figure 1 and Figure 2 The plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n arranged in sequence in the second direction d2, and the gate pulse signal S of the xth scan line HGx is HGx The end time toffx of the x+nth scanning line HGx+n is HGx+nThe start time tonx+n overlaps in timing; the multiple transfer lines VG also include the x+nth transfer line VGx+n, which is electrically connected to the x+nth scan line HGx+n; the multiple pixel rows R also include the k+2th pixel row Rk+2, the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1 and the k+2th pixel row Rk+2 are arranged in sequence in the first direction d1; the multiple data lines DL also include the k+2th data line DLk+2, which is electrically connected to the k+2th pixel row Rk+2; in the top view of the pixel array substrate 100, the x+nth transfer line VGx+n is arranged between the k+1th data line DLk+1 and the k+2th data line DLk+2; the following is Figure 5 and Figure 6 Take this as an example.

[0127] Please refer to Figure 5 and Figure 6 In one place of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 9, and 2 respectively (ie, n=8, x=9, k=2). Figure 5 and Figure 6 In one place of the pixel array substrate 100 of the present embodiment, the plurality of scan lines HG include the first scan line HG1 to the seventeenth scan line HG17 sequentially arranged in the second direction d2, and the gate pulse signal S of the ninth scan line HG9 HG9 The end time toff9 is related to the gate pulse signal S of the 17th scanning line HG17. HG17 The start time ton17 overlaps in timing; the multiple adapter lines VG also include the 17th adapter line VG17, which is electrically connected to the 17th scan line HG17; the multiple pixel rows R also include the 4th pixel row R4, and the 1st pixel row R1, the 2nd pixel row R2, the 3rd pixel row R3 and the 4th pixel row R4 are arranged in sequence in the first direction d1; the multiple data lines DL also include the 4th data line DL4, which is electrically connected to the 4th pixel row R4; in the top view of the pixel array substrate 100, the 17th adapter line VG17 is arranged between the 3rd data line DL3 and the 4th data line DL4.

[0128] Please refer to Figure 5 In other words, the 9th adapter line VG9 and the 17th adapter line VG17 are adjacent to the 3rd data line DL3 and are located on the left and right sides of the 3rd data line DL3 respectively. Figure 5 and Figure 6 Similarly, due to the gate pulse signal S of the 9th adapter line VG9 VG9 The end time toff9 and the gate pulse signal S of the 17th adapter line VG17 VG17The start time ton17 of the pixel structure PX overlaps in timing, so the capacitive coupling effect between the 9th transfer line VG9 and the 3rd data line DL3 and the capacitive coupling effect between the 17th transfer line VG9 and the 3rd data line DL3 can be offset, so that the pixel electrode 194 (drawn in FIG. 194 ) of the pixel structure PX located in the 3rd pixel row R3 and electrically connected to the 17th scan line HG17 Figure 3 ) is not likely to deviate excessively from the ideal value due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the third pixel row R3 and electrically connected to the 17th scan line HG17 is not likely to have abnormal brightness (e.g., too bright), thereby improving the problem of oblique bright lines in the prior art.

[0129] Figure 7 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0130] Figure 8 Show Figure 7 The gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n are HGx-n ~S HGx+n .

[0131] Please refer to Figure 7 and Figure 8 The plurality of scan lines HG include the xnth scan line HGx-n to the xth scan line HGx arranged in sequence in the second direction d2, x is a positive integer greater than or equal to 2, n is a positive integer less than x, and the gate pulse signal S of the xth scan line HGx is HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HGx-n HGx-nThe end times toffx-n overlap in timing; the plurality of adapter lines VG include an xn-th adapter line VGx-n and an x-th adapter line VGx, which are electrically connected to the xn-th scan line HGx-n and the x-th scan line HGx, respectively; the plurality of pixel rows R include a k-1-th pixel row Rk-1, a k-th pixel row Rk, a k+1-th pixel row Rk+1, and a k+2-th pixel row Rk+2 arranged in sequence in the first direction d1, where k is a positive integer greater than or equal to 2; the plurality of data lines DL include a k-1-th data line DLk-1, a k-th data line DLk, a k+1-th data line DLk+1, and a k+2-th data line DL k+2, are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1 and the k+2th pixel row Rk+2 respectively; the pixel array substrate 100 also includes a first common line VSS1; in the top view of the pixel array substrate 100, the xnth transfer line VGx-n is arranged between the k-1th data line DLk-1 and the kth data line DLk, the xth transfer line VGx is arranged between the kth data line DLk and the k+1th data line DLk+1, and the first common line VSS1 is arranged between the k+1th data line DLk+1 and the k+2th data line DLk+2; the following is Figure 5 and Figure 6 Take this as an example.

[0132] Please refer to Figure 5 and Figure 6 In one place of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 17, and 3 respectively (ie, n=8, x=17, k=3). Figure 5 and Figure 6 The plurality of scan lines HG include the 9th scan line HG9 to the 17th scan line HG17 sequentially arranged in the second direction d2, and the gate pulse signal S of the 17th scan line HG17 is HG17 The start time ton17 and the gate pulse signal S of the 9th scanning line HG9 HG9The end time toff9 overlaps in timing; the plurality of adapter lines VG include a 9th adapter line VG9 and a 17th adapter line VG17, which are electrically connected to the 9th scan line HG9 and the 17th scan line HG17 respectively; the plurality of pixel rows R include a 2nd pixel row R2, a 3rd pixel row R3, a 4th pixel row R4 and a 5th pixel row R5 arranged in sequence in the first direction d1; the plurality of data lines DL include a 2nd data line DL2, a 3rd data line DL3, a 4th data line DL4 and a 5th data line DL5, which are respectively The pixel array substrate 100 is electrically connected to the second pixel row R2, the third pixel row R3, the fourth pixel row R4 and the fifth pixel row R5; the pixel array substrate 100 also includes a first common line VSS1a; in the top view of the pixel array substrate 100, the 9th transfer line VG9 is arranged between the second data line DL2 and the third data line DL3, the 17th transfer line VG17 is arranged between the third data line DL3 and the fourth data line DL4, and the first common line VSS1a is arranged between the fourth data line DL4 and the fifth data line DL5.

[0133] Please refer to Figure 5 and Figure 6 In another part of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the first two paragraphs may be regarded as 8, 11, and 11 respectively (ie, n=8, x=11, k=11). Figure 5 and Figure 6 The plurality of scan lines HG include the third scan line HG3 to the eleventh scan line HG11 sequentially arranged in the second direction d2, and the gate pulse signal S of the eleventh scan line HG11 is HG11 The start time ton11 and the gate pulse signal S of the third scanning line HG3 HG3The end time toff3 overlaps in timing; the plurality of adapter lines VG include a third adapter line VG3 and an eleventh adapter line VG11, which are electrically connected to the third scan line HG3 and the eleventh scan line HG11, respectively; the plurality of pixel rows R include a tenth pixel row R10, an eleventh pixel row R11, a twelfth pixel row R12, and a thirteenth pixel row R13 arranged in sequence in the first direction d1; the plurality of data lines DL include a tenth data line DL10, an eleventh data line DL11, a twelfth data line DL12, and a thirteenth data line DL13, which are electrically connected to the third scan line HG3 and the eleventh scan line HG11, respectively; The pixel array substrate 100 is electrically connected to the 10th pixel row R10, the 11th pixel row R11, the 12th pixel row R12 and the 13th pixel row R13; the pixel array substrate 100 also includes a first common line VSS1b; in the top view of the pixel array substrate 100, the third transfer line VG3 is arranged between the 10th data line DL10 and the 11th data line DL11, the 11th transfer line VG11 is arranged between the 11th data line DL11 and the 12th data line DL12, and the first common line VSS1b is arranged between the 12th data line DL12 and the 13th data line DL13.

[0134] Please refer to Figure 5 and Figure 6 In another part of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the first three paragraphs can also be regarded as 8, 18, and 15 respectively (that is, n=8, x=18, k=15). Figure 5 and Figure 6 The plurality of scan lines HG include the 10th scan line HG10 to the 18th scan line HG18 sequentially arranged in the second direction d2, and the gate pulse signal S of the 18th scan line HG18 HG18 The start time ton18 and the gate pulse signal S of the 10th scanning line HG10 HG10The end time toff10 overlaps in timing; the plurality of adapter lines VG include a 10th adapter line VG10 and an 18th adapter line VG18, which are electrically connected to the 10th scan line HG10 and the 18th scan line HG18, respectively; the plurality of pixel rows R include a 14th pixel row R14, a 15th pixel row R15, a 16th pixel row R16 and a 17th pixel row R17 arranged in sequence in the first direction d1; the plurality of data lines DL include a 14th data line DL14, a 15th data line DL15, a 16th data line DL16 and a 17th data line DL17, respectively Electrically connected to the 14th pixel row R14, the 15th pixel row R15, the 16th pixel row R16 and the 17th pixel row R17; the pixel array substrate 100 also includes a first common line VSS1c; in the top view of the pixel array substrate 100, the 10th transfer line VG10 is arranged between the 14th data line DL14 and the 15th data line DL15, the 18th transfer line VG18 is arranged between the 15th data line DL15 and the 16th data line DL16, and the first common line VSS1c is arranged between the 16th data line DL16 and the 17th data line DL17.

[0135] Please refer to Figure 5 and Figure 6 In another part of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the first four paragraphs can also be regarded as 8, 14, and 18 respectively (ie, n=8, x=14, k=18). Figure 5 and Figure 6 The plurality of scan lines HG include the sixth scan line HG6 to the fourteenth scan line HG14 sequentially arranged in the second direction d2, and the gate pulse signal S of the fourteenth scan line HG14 is HG14 The start time ton14 and the gate pulse signal S of the sixth scanning line HG6 HG6The end time toff6 overlaps in timing; the plurality of adapter lines VG include a 6th adapter line VG6 and a 14th adapter line VG14, which are electrically connected to the 6th scan line HG6 and the 14th scan line HG14 respectively; the plurality of pixel rows R include a 17th pixel row R17, an 18th pixel row R18, a 19th pixel row R19 and a 20th pixel row R20 arranged in sequence in the first direction d1; the plurality of data lines DL include a 17th data line DL17, an 18th data line DL18, a 19th data line DL19 and a 20th data line DL20, which are electrically connected to the 6th scan line HG6 and the 14th scan line HG14 respectively. The 6th data line VG6 is arranged between the 17th data line DL17 and the 18th data line DL18, the 14th data line VG14 is arranged between the 18th data line DL18 and the 19th data line DL19, and the first common line VSS1d is arranged between the 19th data line DL19 and the 20th data line DL20.

[0136] Fig. 9 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0137] Fig.10 Show Fig. 9 The gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n are HGx-n ~S HGx+n .

[0138] Please refer to Fig. 9 and Fig.10 The plurality of scan lines HG include the xnth scan line HGx-n to the xth scan line HGx arranged in sequence in the second direction d2, x is a positive integer greater than or equal to 2, n is a positive integer less than x, and the gate pulse signal S of the xth scan line HGx is HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HGx-n HGx-nThe end times toffx-n overlap in timing; the plurality of scan lines HG further include the m-th scan line HGm, where m is a positive integer greater than 2, and |xm| is not equal to n; the plurality of adapter lines VG include the xn-th adapter line VGx-n, the x-th adapter line VGx, and the m-th adapter line VGm, which are electrically connected to the xn-th scan line HGx-n, the x-th scan line HGx, and the m-th scan line HGm, respectively; the plurality of pixel rows R include the k-1-th pixel row Rk-1, the k-th pixel row Rk, the k+1-th pixel row Rk+1, and the k+2-th pixel row Rk+2 arranged in sequence in the first direction d1, where k is a positive integer greater than or equal to 2; the plurality of data lines DL include the k- The 1st data line DLk-1, the kth data line DLk, the k+1th data line DLk+1 and the k+2th data line DLk+2 are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1 and the k+2th pixel row Rk+2, respectively; in the top view of the pixel array substrate 100, the xnth transfer line VGx-n is arranged between the k-1th data line DLk-1 and the kth data line DLk, the xth transfer line VGx is arranged between the kth data line DLk and the k+1th data line DLk+1, and the mth transfer line VGm is arranged between the k+1th data line DLk+1 and the k+2th data line DLk+2; the following is Figure 5 and Figure 6 Take this as an example.

[0139] Please refer to Figure 5 and Figure 6 In one place of the pixel array substrate 100 of this embodiment, the n, x, k, and m mentioned in the previous paragraph can be regarded as 8, 16, 21, and 4 respectively (that is, n=8, x=16, k=21, and m=4). Figure 5 and Figure 6 The plurality of scan lines HG include the eighth scan line HG8 to the sixteenth scan line HG16 sequentially arranged in the second direction d2, and the gate pulse signal S of the sixteenth scan line HG16 is HG16 The start time ton16 and the gate pulse signal S of the eighth scanning line HG8 HG8The end time toff8 overlaps in timing; the plurality of scan lines HG also include the fourth scan line HG4, 4 is a positive integer greater than 2, |16-4| is not equal to 8; the plurality of adapter lines VG include the eighth adapter line VG8, the sixteenth adapter line VG16 and the fourth adapter line VG4, which are electrically connected to the eighth scan line HG8, the sixteenth scan line HG16 and the fourth scan line HG4 respectively; the plurality of pixel rows R include the 20th pixel row R20, the 21st pixel row R21, the 22nd pixel row R22 and the 23rd pixel row R23 arranged in sequence in the first direction d1; the plurality of data lines DL include the 20th data line The 8th data line DL20, the 21st data line DL21, the 22nd data line DL22 and the 23rd data line DL23 are electrically connected to the 20th pixel row R20, the 21st pixel row R21, the 22nd pixel row R22 and the 23rd pixel row R23, respectively; in the top view of the pixel array substrate 100, the 8th adapter line VG8 is arranged between the 20th data line DL20 and the 21st data line DL21, the 16th adapter line VG16 is arranged between the 21st data line DL21 and the 22nd data line DL22, and the 4th adapter line VG4 is arranged between the 22nd data line DL22 and the 23rd data line DL23.

[0140] That is, in this embodiment, at one location of the pixel array substrate 100, the gate pulse signals (e.g., S G ) of the plurality of adapter wires VG (e.g., the eighth adapter wire VG8 and the sixteenth adapter wire VG16) located on the left and right sides of the same data line DL (e.g., the twenty-first data line DL21) are VG8 , S VG16 ) may differ by n time lengths t of the time delay (e.g., 8 t); however, at another location of the pixel array substrate 100, the gate pulse signals (e.g., S S ) of the plurality of adapter wires VG (e.g., the 16th adapter wire VG16 and the 4th adapter wire VG4) located on the left and right sides of the same data line DL (e.g., the 22nd data line DL22) may differ by n time lengths t of the time delay (e.g., 8 t); VG16 , S VG4 )’s start time (e.g. ton16, ton4) may not differ by n t’s (e.g. 12 t’s).

[0141] Fig.11 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0142] Fig.12 Show Fig.11 The gate pulse signals S of the yn-th scanning line HGy-n to the y-th scanning line HGy are HGy-n ~S HGy .

[0143] Please refer to Fig.11 The plurality of scan lines HG include a ynth scan line HGy-n to a yth scan line HGy arranged in sequence in the second direction d2, y is a positive integer greater than or equal to 2, and n is a positive integer less than y.

[0144] Please refer to Fig.11 and Fig.12 , the ynth scanning line HGy-n to the yth scanning line HGy respectively have gate pulse signals S HGy-n To the gate pulse signal S HGy Specifically, the yn-th scanning line HGy-n has a gate pulse signal S HGy-n , the y-n+1th scanning line HGy-n+1 has a gate pulse signal S HGy-n+1 , the y-n+2th scanning line HGy-n+2 has a gate pulse signal S HGy-n+2 , ..., the y-th scanning line HGy has a gate pulse signal S HGy .

[0145] Please refer to Fig.11 and Fig.12 , sequentially open the yn-th scanning line HGy-n to the y-th scanning line HGy with a time delay, wherein the length of the time delay is t (plotted on Fig.12 ), gate pulse signal S HGy-n To the gate pulse signal S HGy The pulse time length of each is Tp (plotted on Fig.12 ), and n=Tp / t. The gate pulse signal S of the y-th scanning line HGy HGy The start time tony and the gate pulse signal S of the ynth scanning line HGy-n HGy-n The end times toffy-n overlap in timing.

[0146] Please refer to Fig.11 The plurality of transfer lines VG include the ynth transfer line VGy-n and the yth transfer line VGy, which are electrically connected to the ynth scan line HGy-n and the yth scan line HGy, respectively. Fig.11 and Fig.12 The ynth transfer line VGy-n and the yth transfer line VGy have gate pulse signals S VGy-n And the gate pulse signal S VGy , where the gate pulse signal S of the ynth transfer line VGy-n VGy-n and the gate pulse signal S of the yth transfer line VGy VGy The gate pulse signal S HGy-n and the gate pulse signal S of the y-th scanning line HGy HGy same.

[0147] Please refer to Fig.11 , the multiple pixel rows R include the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+2th pixel row Rq+2 arranged in sequence in the first direction d1, q is a positive integer greater than or equal to 2; the multiple data lines DL include the q-1th data line DLq-1, the qth data line DLq, the q+1th data line DLq+1 and the q+2th data line DLq+2, which are electrically connected to the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+2th pixel row Rq+2, respectively, and q is a positive integer greater than or equal to 2.

[0148] Please refer to Fig.11 It is worth noting that in the top view of the pixel array substrate 100, the y-th transfer line VGy is disposed between the q-1-th data line DLq-1 and the q-th data line DLq, and the yn-th transfer line VGy-n is disposed between the q-th data line DLq and the q+1-th data line DLq+1; Figure 5 and Figure 6 Take this as an example.

[0149] Please refer to Figure 5 and Figure 6 In one place of the pixel array substrate 100 of this embodiment, the corresponding Fig.11 and Fig.12 The n, y, and q of are considered to be 8, 13, and 6 respectively (i.e., n=8, y=13, q=6). Figure 5 and Figure 6 In one place of the pixel array substrate 100 of the present embodiment, the plurality of scan lines HG include the fifth scan line HG5 to the thirteenth scan line HG13 sequentially arranged in the second direction d2; the gate pulse signal S of the thirteenth scan line HG13 HG13 The start time ton13 and the gate pulse signal S of the fifth scanning line HG5 HG5 The end time toff5 of the plurality of adapter lines VG includes a fifth adapter line VG5 and a thirteenth adapter line VG13, which are electrically connected to the fifth scan line HG5 and the thirteenth scan line HG13, respectively. The fifth adapter line VG5 and the thirteenth adapter line VG13 respectively have gate pulse signals S VG5 And the gate pulse signal S VG13 , where the gate pulse signal S of the 5th adapter VG5 VG5 and the gate pulse signal S of the 13th adapter VG13 VG13 The gate pulse signal S HG5 and the gate pulse signal S of the 13th scanning line HG13HG13 The plurality of pixel rows R include a fifth pixel row R5, a sixth pixel row R6, a seventh pixel row R7, and an eighth pixel row R8 sequentially arranged in the first direction d1; the plurality of data lines DL include a fifth data line DL5, a sixth data line DL6, a seventh data line DL7, and an eighth data line DL8, which are electrically connected to the fifth pixel row R5, the sixth pixel row R6, the seventh pixel row R7, and the eighth pixel row R8, respectively.

[0150] Please refer to Figure 5 It is worth noting that, in the top view of the pixel array substrate 100, the 13th adapter line VG13 is disposed between the 5th data line DL5 and the 6th data line DL6, and the 5th adapter line VG5 is disposed between the 6th data line DL6 and the 7th data line DL7. Similarly, the 13th adapter line VG13 and the 5th adapter line VG5 are adjacent to the 6th data line DL6 and are located on the left and right sides of the 6th data line DL6, respectively. Please refer to Figure 5 and Figure 6 Similarly, due to the gate pulse signal S of the fifth adapter line VG5 VG5 The end time toff5 and the gate pulse signal S of the 13th adapter line VG13 VG13 The start time ton13 of the 13th switching line VG13 overlaps in timing, so the capacitive coupling effect between the 13th switching line VG13 and the 6th data line DL6 and the capacitive coupling effect between the 5th switching line VG5 and the 6th data line DL6 can be offset, so that the pixel electrode 194 (drawn in FIG. 194 ) of the pixel structure PX located in the 6th pixel row R6 and electrically connected to the 13th scan line HG13 Figure 3 ) is not likely to deviate excessively from the ideal value due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the sixth pixel row R6 and electrically connected to the thirteenth scan line HG13 is not likely to have abnormal brightness (e.g., too bright), thereby improving the problem of oblique bright lines in the prior art.

[0151] It should be noted that the two adapter lines VG located on the left and right sides of the same data line DL and arranged in sequence in the first direction d1 can offset the multiple capacitance effects of the same data line DL; however, the present invention does not limit the start time of the gate pulse signal of one of the adapter lines VG arranged first in the first direction d1 to be earlier than the start time of the gate pulse signal of the other adapter line VG arranged later; the present invention also does not limit the start time of the gate pulse signal of one of the adapter lines VG arranged first in the first direction d1 to be later than the start time of the gate pulse signal of the other adapter line VG arranged later.

[0152] For example, in Figure 5In one place of the pixel array substrate 100, two adapter lines (for example, the first adapter line VG1 and the ninth adapter line VG9) are arranged on the left and right sides of the same data line (for example, the second data line DL2) and arranged in sequence in the first direction d1. The multiple capacitance effects of the two adapter lines VG1 and the ninth adapter line VG9 with the same data line (for example, the second data line DL2) can offset each other, and the start time of the gate pulse signal of one of the adapter lines VG arranged first in the first direction d1 can be earlier than the start time of the gate pulse signal of the other adapter line VG arranged later (for example, the gate pulse signal S of the first adapter line VG1 arranged first in the first direction d1) VG1 The start time ton1 can be earlier than the gate pulse signal S of the 9th adapter VG9 arranged later. VG9 The start time of ton9); but Figure 5 At another location of the pixel array substrate 100, a plurality of adapter wires (for example, the 13th adapter wire VG13 and the 5th adapter wire VG5) are arranged on the left and right sides of the same data line (for example, the 6th data line DL6) and are sequentially arranged in the first direction d1. The plurality of capacitance effects of the adapter wires and the same data line (for example, the 6th data line DL6) can offset each other. The start time of the gate pulse signal of the first adapter wire VG arranged in the first direction d1 can be later than the start time of the gate pulse signal of the second adapter wire VG arranged in the second direction d1 (for example, the gate pulse signal S of the 13th adapter wire VG13 arranged in the first direction d1) can be later than the start time of the gate pulse signal of the second adapter wire VG arranged in the second direction d1. VG13 The start time ton13 may be later than the gate pulse signal S of the fifth transfer line VG5 arranged later. VG5 The start time ton5).

[0153] Please refer to Fig.11 and Fig.12 , the pixel array substrate 100 further includes a second common line VSS2; in a top view of the pixel array substrate 100, the yth transfer line VGy is disposed between the q-1th data line DLq-1 and the qth data line DLq, the ynth transfer line VGy-n is disposed between the qth data line DLq and the q+1th data line DLq+1, and the second common line VSS2 is disposed between the q+1th data line DLq+1 and the q+2th data line DLq+2; Figure 5 and Figure 6 Take this as an example.

[0154] Please refer to Figure 5 In one place of the pixel array substrate 100 of this embodiment, the corresponding Fig.11 and Fig.12 The n, y, and q of are considered to be 8, 13, and 6 respectively (i.e., n=8, y=13, q=6). Figure 5In the top view of the pixel array substrate 100, the 13th adapter line VG13 is arranged between the 5th data line DL5 and the 6th data line DL6, the 5th adapter line VG5 is arranged between the 6th data line DL6 and the 7th data line DL7, and the second common line VSS2 is arranged between the 7th data line DL7 and the 8th data line DL8.

[0155] Fig.13 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0156] Fig.14 Show Fig.13 The gate pulse signals S of the yn-th scanning line HGy-n to the y-th scanning line HGy are HGy-n ~S HGy .

[0157] Please refer to Fig.13 and Fig.14 The plurality of scan lines HG include the ynth scan line HGy-n to the yth scan line HGy arranged in sequence in the second direction d2, y is a positive integer greater than or equal to 2, n is a positive integer less than y, and the gate pulse signal S of the yth scan line HGy is HGy The start time tony and the gate pulse signal S of the ynth scanning line HGy-n HGy-n The end time toffy-n overlaps in timing; the plurality of scan lines HG also includes the pth scan line HGp; the plurality of adapter lines VG include the ynth adapter line VGy-n and the yth adapter line VGy, which are electrically connected to the ynth scan line HGy-n and the yth scan line HGy, respectively; the plurality of adapter lines VG also include the pth adapter line VGp, which is electrically connected to the pth scan line HGp; the plurality of pixel rows R include the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+2th pixel row Rq+2 arranged in sequence in the first direction d1, where q is a positive integer greater than or equal to 2; the plurality of data lines DL include the q-1th data line DLq-1, the qth data line DLq-2, the qth data line DLq-3, the qth data line DLq-4, the qth data line DLq-5, the qth data line DLq-6, the qth data line DLq-7, the qth data line DLq-8, the qth data line DLq-9, the qth data line DLq-11, the qth data line DLq-12, the qth data line DLq-13, the qth data line DLq-14, the qth data line DLq The yth data line DLq, the q+1th data line DLq+1 and the q+2th data line DLq+2 are electrically connected to the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+2th pixel row Rq+2, respectively; in the top view of the pixel array substrate 100, the yth transfer line VGy is arranged between the q-1th data line DLq-1 and the qth data line DLq, the ynth transfer line VGy-n is arranged between the qth data line DLq and the q+1th data line DLq+1, and the pth transfer line VGp is ​​arranged between the q+1th data line DLq+1 and the q+2th data line DLq+2; in particular, p is a positive integer greater than 2, and |yp| is not equal to n; the following is Figure 5 and Figure 6 Take this as an example.

[0158] Please refer to Figure 5 and Figure 6 In one place of the pixel array substrate 100 of this embodiment, the corresponding Fig.13 and Fig.14 The n, y, q, and p of are respectively regarded as 8, 15, 9, and 3 (i.e., n=8, y=15, q=9, and p=3). Figure 5 and Figure 6 In the top view of the pixel array substrate 100, the plurality of scan lines HG include the seventh scan line HG7 to the fifteenth scan line HG15 sequentially arranged in the second direction d2, and the gate pulse signal S of the fifteenth scan line HG15 is HG15 The start time ton15 and the gate pulse signal S of the seventh scanning line HG7 HG7 The end time toff7 overlaps in timing; the plurality of scan lines HG also includes the third scan line HG3; the plurality of adapter lines VG include the seventh adapter line VG7 and the fifteenth adapter line VG15, which are electrically connected to the seventh scan line HG7 and the fifteenth scan line HG15, respectively; the plurality of adapter lines VG also include the third adapter line VG3, which is electrically connected to the third scan line HG3; the plurality of pixel rows R include the eighth pixel row R8, the ninth pixel row R9, the tenth pixel row R10 and the eleventh pixel row R11 arranged in sequence in the first direction d1; the plurality of data lines DL include the eighth data line DL8, the ninth data line DL9, the tenth pixel row R10 and the eleventh pixel row R11; L9, the 10th data line DL10 and the 11th data line DL11 are electrically connected to the 8th pixel row R8, the 9th pixel row R9, the 10th pixel row R10 and the 11th pixel row R11, respectively; in the top view of the pixel array substrate 100, the 15th adapter line VG15 is arranged between the 8th data line DL8 and the 9th data line DL9, the 7th adapter line VG7 is arranged between the 9th data line DL9 and the 10th data line DL10, and the 3rd adapter line VG3 is arranged between the 10th data line DL10 and the 11th data line DL11; in particular, 3 is a positive integer greater than 2, and |15-3| is not equal to 8.

[0159] That is, in this embodiment, at one location of the pixel array substrate 100, the gate pulse signals (e.g., S G ) of two adapter wires VG (e.g., the 15th adapter wire VG15 and the 7th adapter wire VG7) located on the left and right sides of the same data line DL (e.g., the 9th data line DL9) are VG15 , S VG7) may differ by n time lengths t of the time delay (e.g., 8 t; however, at another location of the pixel array substrate 100, gate pulse signals (e.g., S VG7 , S VG3 )’s start time (e.g. ton7, ton3) may also not differ by n t’s (e.g., by 4 t’s).

[0160] In the above description, Tp / t=n=8 is used as an example. However, the present invention is not limited to this. In other embodiments, Tp / t=n, and n can also be a positive integer other than 8. Fig.15 and Fig.16 Give an example.

[0161] Fig.15 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100A according to an embodiment of the present invention.

[0162] Fig.16 Show Fig.15 The gate pulse signals S of the first scanning line HG1 to the ninth scanning line HG9 are HG1 ~S HG9 .

[0163] Please refer to Figure 1 and Figure 2 The plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x; the gate pulse signal S of the xth scan line HGx HGx The start time tonx and the gate pulse signal S of the xnth scanning line HG HGx-n The end time toffx-n overlaps in timing; the gate pulse signal S HGx The end time toffx of the x+nth scanning line HGx+n is HGx+nThe start time tonx+n overlaps in timing; the plurality of adapter lines VG include the xnth adapter line VGx-n, the xth adapter line VGx and the x+nth adapter line VGx+n, which are electrically connected to the xnth scan line HGx-n, the xth scan line HGx and the x+nth scan line HGx+n respectively; the plurality of pixel rows R include the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1 pixel row Rk+1 and k+2 pixel row Rk+2, k is a positive integer greater than or equal to 2; a plurality of data lines DL include a k-1th data line DLk-1, a kth data line DLk, a k+1th data line DLk+1 and a k+2th data line DLk+2, which are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1 and the k+2th pixel row Rk+2, respectively. In the top view of the pixel array substrate 100, the xnth transfer line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, the xth transfer line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1, and the x+nth transfer line VGx+n is disposed between the k+1th data line DLk+1 and the k+2th data line DLk+2; Fig.15 and Fig.16 Take this as an example.

[0164] In one place of the pixel array substrate 100A of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 4, 5, and 2 respectively (ie, n=4, x=5, k=2). Fig.15 and Fig.16 The plurality of scan lines HG include the first scan line HG1 to the ninth scan line HG9 sequentially arranged in the second direction d2; the gate pulse signal S of the fifth scan line HG5 HG5 The start time ton5 of the first scanning line HG and the gate pulse signal S HG1 The end time toff1 of the fifth scanning line HG5 overlaps in timing; HG5 The end time toff5 is related to the gate pulse signal S of the 9th scanning line HG9. HG9The start time ton9 overlaps in timing; the plurality of adapter lines VG include the 1st adapter line VG1, the 5th adapter line VG5 and the 9th adapter line VG9, which are electrically connected to the 1st scan line HG1, the 5th scan line HG5 and the 9th scan line HG9 respectively; the plurality of pixel rows R include the 1st pixel row R1, the 2nd pixel row R2, the 3rd pixel row R3 and the 4th pixel row R4 arranged in sequence in the first direction d1; the plurality of data lines DL include the 1st data line DL1, the 2nd data line DL2, the 3rd data line DL3 and the 4th data line DL4, which are electrically connected to the 1st pixel row R1, the 2nd pixel row R2, the 3rd pixel row R3 and the 4th pixel row R4 respectively. In the top view of the pixel array substrate 100, the first adapter line VG1 is disposed between the first data line DL1 and the second data line DL2, the fifth adapter line VG5 is disposed between the second data line DL2 and the third data line DL3, and the ninth adapter line VG9 is disposed between the third data line DL3 and the fourth data line DL4.

[0165] Fig.17 FIG. 1 is a cross-sectional schematic diagram of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention. Fig.17 correspond Figure 3 Section line II-II'.

[0166] The following match Figure 3 and Fig.17 The specific structure of the pixel structure PX according to an embodiment of the present invention is described by way of example. The pixel structure PX can be selectively applied in the aforementioned pixel array substrate 100 or 100A.

[0167] Please refer to Figure 3 and Fig.17 In addition to the aforementioned thin film transistor T and the pixel electrode 194 electrically connected to the thin film transistor T, the pixel structure PX further includes a first common electrode 122. The first common electrode 122 partially overlaps with the pixel electrode 194 to form a storage capacitor.

[0168] In this embodiment, the pixel structure PX may selectively include a second common electrode 124 separated from the first common electrode 122. Figure 3 In the top view of the pixel array substrate 100 , the first common electrode 122 , the second common electrode 124 , and the scan line HG are arranged in the second direction d2 and are separated from each other.

[0169] For example, in the present embodiment, the first common electrode 122, the second common electrode 124 and the scan line HG may belong to the first conductive layer and be separated from each other, the gate Tc of the thin film transistor T may belong to the first conductive layer, and the gate Tc of the thin film transistor T may be directly connected to the scan line HG; the source Ta and the drain Tb of the thin film transistor T may belong to the second conductive layer and be separated from each other, the data line DL may belong to the second conductive layer, and the data line DL may be directly connected to the source Ta of the thin film transistor T; but the present invention is not limited to this.

[0170] Please refer to Figure 3 and Fig.17 , the pixel structure PX further includes a conductive pattern 142 electrically connected to the thin film transistor T. Specifically, the conductive pattern 142 is electrically connected to the drain electrode Tb of the thin film transistor T. For example, in the present embodiment, the conductive pattern 142 and the drain electrode Tb of the thin film transistor T may belong to the same second conductive layer and may be directly connected, but the present invention is not limited thereto.

[0171] The conductive pattern 142 has a first portion 142-1, which is disposed on the first common electrode 122. Specifically, the conductive pattern 142 is disposed on the insulating layer 130, and the first portion 142-1 of the conductive pattern 142 overlaps the first common electrode 122. In the present embodiment, the conductive pattern 142 further has a second portion 142-2, which is disposed on the second common electrode 124. Specifically, the conductive pattern 142 is disposed on the insulating layer 130, and the second portion 142-2 of the conductive pattern 142 overlaps the second common electrode 124. In the present embodiment, the conductive pattern 142 further has a third portion 142-3, which is connected between the first portion 142-1 and the second portion 142-2. In the top view of the pixel array substrate 100, the third portion 142-3 of the conductive pattern 142 is located between the first common electrode 122 and the second common electrode 124, and does not overlap the first common electrode 122 and the second common electrode 124.

[0172] Please refer to Figure 3 and Fig.17 , the pixel structure PX further includes a first insulating layer 150, which is disposed on the conductive pattern 142 and has an opening 152 overlapping the conductive pattern 142. In the present embodiment, the opening 152 of the first insulating layer 150 may overlap the third portion 142-3 of the conductive pattern 142. For example, in the present embodiment, the material of the first insulating layer 150 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0173] Please refer to Figure 3 and Fig.17The pixel structure PX further includes a color filter pattern 160 disposed on the first insulating layer 150 and having an opening 162 overlapping the conductive pattern 142. Figure 3 For example, in the top view of the pixel array substrate 100 , the opening 152 of the first insulating layer 150 may be located within the opening 162 of the color filter pattern 160 .

[0174] Please refer to Figure 3 and Fig.17 The pixel structure PX further includes a second insulating layer 170 disposed on the color filter pattern 160 and having an opening 172 overlapping the conductive pattern 142. For example, in the present embodiment, the second insulating layer 170 may be made of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0175] In the present embodiment, the pixel array substrate 100 may selectively include a transparent conductive layer 180 disposed on the second insulating layer 170. The transparent conductive layer 180 is disposed between the film layer to which the transfer line VG belongs and the film layer to which the pixel electrode 194 belongs to shield the pixel electrode 194 so that the potential of the pixel electrode 194 is not easily affected by the transfer line VG. For example, in the present embodiment, the material of the transparent conductive layer 180 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto.

[0176] The pixel electrode 194 is disposed on the second insulating layer 170, and is electrically connected to the conductive pattern 142 through the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170. For example, in the present embodiment, the pixel structure PX may selectively include a third insulating layer 190, which is disposed on the second insulating layer 170 and covers the transparent conductive layer 180; the third insulating layer 190 has an opening 192, which overlaps the conductive pattern 142; the pixel electrode 194 may be disposed on the third insulating layer 190, and is electrically in contact with the third portion 142-3 of the conductive pattern 142 through the opening 192 of the third insulating layer 190, the opening 172 of the second insulating layer 170, and the opening 152 of the first insulating layer 150, but the present invention is not limited thereto.

[0177] In this embodiment, the opening 192 of the third insulating layer 190, the opening 172 of the second insulating layer 170 and the opening 152 of the first insulating layer 150 may be located on the third portion 142-3 of the conductive pattern 142; the opening 192 of the third insulating layer 190, the opening 172 of the second insulating layer 170 and the opening 152 of the first insulating layer 150 may be substantially aligned; however, the present invention is not limited thereto.

[0178] In this embodiment, in the top view of the pixel array substrate 100 , the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 may be located between the first common electrode 122 and the second common electrode 124 and do not overlap the first common electrode 122 and the second common electrode 124 .

[0179] Please refer to Figure 3 It is worth noting that, in the top view of the pixel array substrate 100, the first portion 142-1 of the conductive pattern 142 covers all edges 122e of the first common electrode 122 located in the opening 162 of the color filter pattern 160. Figure 3 and Fig.17 That is, in the opening 162 of the color filter pattern 160, there will be no overlap or intersection of the edge 142e of the conductive pattern 142 and the edge 122e of the first common electrode 122, and the first common electrode 122, the conductive pattern 142 and the insulating layer 130 sandwiched therebetween are not likely to form a stacked structure with steep sidewalls. Near the edge 122e of the first common electrode 122, the second insulating layer 170 does not need to be formed on the stacked structure with steep sidewalls, but can be well disposed on the first insulating layer 150. Therefore, the second insulating layer 170 can well cover the color filter pattern 160 and its sidewall 164, so that the gas in the color filter pattern 160 is not likely to pass through the second insulating layer 170 and leak out of the pixel array substrate 100, causing a bubble problem in the display panel.

[0180] Please refer to Figure 3 In this embodiment, in the top view of the pixel array substrate 100, the second portion 142-2 of the conductive pattern 142 covers all edges 124e of the second common electrode 124 located in the opening 162 of the color filter pattern 160. Figure 3 and Fig.17 That is, in the opening 162 of the color filter pattern 160, there will be no overlap or intersection of the edge 142e of the conductive pattern 142 and the edge 124e of the second common electrode 124, and the second common electrode 124, the conductive pattern 142 and the insulating layer 130 sandwiched therebetween are not likely to form a stacked structure with steep sidewalls. Near the edge 124e of the second common electrode 124, the second insulating layer 170 does not need to be formed on the stacked structure with steep sidewalls, but can be well disposed on the first insulating layer 150. Therefore, the second insulating layer 170 can well cover the color filter pattern 160 and its sidewall 164, so that the gas in the color filter pattern 160 is not likely to pass through the second insulating layer 170 and leak out of the pixel array substrate 100, causing a bubble problem in the display panel.

[0181] Fig.18FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention.

[0182] Fig.19 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention. Fig.19 correspond Fig.18 Section line III-III'.

[0183] Fig.18 and Fig.19 The pixel structure PX may also be selectively applied in the aforementioned pixel array substrate 100 or 100A.

[0184] Fig.18 and Fig.19 The pixel structure PX and Figure 3 and Fig.17 The pixel structure PX of is similar to that of , so the same or similar elements are represented by the same or similar reference numerals. The differences between the two are described below. For the same or similar points between the two, please refer to the above description, which will not be repeated here.

[0185] Please refer to Fig.18 and Fig.19 In this embodiment, the pixel structure PX may not include Figure 3 and Fig.17 In addition, the pixel structure PX may not include the second common electrode 124 of the embodiment. Figure 3 and Fig.17 The third insulating layer 190 and the transparent conductive layer 180 of the embodiment.

[0186] Please refer to Fig.18 and Fig.19 In this embodiment, the second portion 142-2 of the conductive pattern 142 may be disposed on the gate Tc of the thin film transistor T. Fig.18 In the top view of the pixel array substrate 100B, the second portion 142 - 2 of the conductive pattern 142 may cover all edges Tcs of the gate Tc located within the opening 162 of the color filter pattern 160 .

[0187] In the top view of the pixel array substrate 100B, the third portion 142-3 of the conductive pattern 142 is located between the first common electrode 122 and the gate Tc, the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 are located on the third portion 142-3 of the conductive pattern 142, and the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 do not overlap with the first common electrode 122 and the gate Tc.

[0188] Fig. 20FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

[0189] Fig.21 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention. Fig.21 correspond Fig. 20 Section line IV-IV'.

[0190] Fig. 20 and Fig.21 The pixel structure PX may also be selectively applied in the aforementioned pixel array substrate 100 or 100A.

[0191] Fig. 20 and Fig.21 The pixel structure PX and Figure 3 and Fig.17 The pixel structure PX of is similar to that of , so the same or similar elements are represented by the same or similar reference numerals. The differences between the two are described below. For the same or similar points between the two, please refer to the above description, which will not be repeated here.

[0192] and Figure 3 and Fig.17 The pixel structure PX is different in that Fig. 20 and Fig.21 In the embodiment of the present invention, the pixel structure PX further includes a third common electrode 126, which is separated from the first common electrode 122 and the second common electrode 124. In the present embodiment, the third common electrode 126 may belong to the first conductive layer. Fig. 20 The conductive pattern 142 further includes a fourth portion 142-4 disposed on the third common electrode 126. In the top view of the pixel array substrate 100C, the fourth portion 142-4 of the conductive pattern 142 covers all edges 126e of the third common electrode 126 located in the opening 162 of the color filter pattern 160.

[0193] Fig. 22 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention.

[0194] Fig.23 FIG. 1 is a cross-sectional schematic diagram of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention. Fig.23 correspond Fig. 22 The section line V-V'.

[0195] Fig. 22 and Fig.23 The pixel structure PX may also be selectively applied in the aforementioned pixel array substrate 100 or 100A.

[0196] Fig. 22 and Fig.23 The pixel structure PX and Figure 3 and Fig.17 The pixel structure PX of is similar to that of , so the same or similar elements are represented by the same or similar reference numerals. The differences between the two are described below. For the same or similar points between the two, please refer to the above description, which will not be repeated here.

[0197] exist Figure 3 and Fig.17 In the embodiment of the present invention, an edge 142-1e (indicated by Figure 3 ) and an edge 162e (indicated by Figure 3 ) are substantially flush. That is, Figure 3 and Fig.17 In the embodiment of FIG. 1 , the first portion 142 - 1 of the conductive pattern 142 does not extend beyond the opening 162 of the color filter pattern 160 .

[0198] exist Fig. 22 and Fig.23 In the embodiment of FIG. 1 , the conductive pattern 142 further has a fifth portion 142 - 5 ; in the top view of the pixel array substrate 100D, the fifth portion 142 - 5 of the conductive pattern 142 overlaps with the first common electrode 122 and is located outside the opening 162 of the color filter pattern 160 . Fig. 22 and Fig.23 In the embodiment of the present invention, the conductive pattern 142 may extend beyond the opening 162 of the color filter pattern 160 .

Claims

1. A pixel array substrate, comprising: a base; as well as A plurality of pixel structures are disposed on the substrate, wherein each of the plurality of pixel structures comprises: a first common electrode; a thin film transistor; a conductive pattern electrically connected to the thin film transistor, wherein a first portion of the conductive pattern is disposed on the first common electrode; a first insulating layer, disposed on the conductive pattern and having an opening overlapping the conductive pattern; a color filter pattern, disposed on the first insulating layer and having an opening overlapping with the conductive pattern; a second insulating layer, disposed on the color filter pattern and having an opening overlapping the conductive pattern; and a pixel electrode, disposed on the second insulating layer and electrically connected to the conductive pattern through the opening of the first insulating layer and the opening of the second insulating layer; Wherein, in the top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode located in the opening of the color filter pattern.

2. The pixel array substrate according to claim 1, wherein each of the plurality of pixel structures further comprises: a second common electrode separated from the first common electrode, wherein a second portion of the conductive pattern is disposed on the second common electrode; In the top view of the pixel array substrate, the second portion of the conductive pattern covers all edges of the second common electrode located in the opening of the color filter pattern.

3. The pixel array substrate as described in claim 2, wherein the conductive pattern further has a third portion; in a top view of the pixel array substrate, the third portion of the conductive pattern is located between the first common electrode and the second common electrode, and the opening of the first insulating layer and the opening of the second insulating layer are located on the third portion of the conductive pattern.

4. The pixel array substrate as described in claim 2, wherein in a top view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the second common electrode and do not overlap the first common electrode and the second common electrode.

5. The pixel array substrate as claimed in claim 2, wherein each of the plurality of pixel structures further comprises: a third common electrode, separated from the first common electrode and the second common electrode, wherein a fourth portion of the conductive pattern is disposed on the third common electrode; In the top view of the pixel array substrate, the fourth portion of the conductive pattern covers all edges of the third common electrode located in the opening of the color filter pattern. 6 . The pixel array substrate as claimed in claim 1 , wherein an edge of the first portion of the conductive pattern is substantially aligned with an edge of the opening of the color filter pattern. 7 . The pixel array substrate as claimed in claim 1 , wherein the conductive pattern further has a fifth portion; in a top view of the pixel array substrate, the fifth portion of the conductive pattern overlaps with the first common electrode and is located outside the opening of the color filter pattern.

8. A pixel array substrate as described in claim 1, wherein the thin film transistor has a gate separated from the first common electrode; a second portion of the conductive pattern is disposed on the gate; in a top view of the pixel array substrate, the second portion of the conductive pattern covers all edges of the gate located within the opening of the color filter pattern.

9. The pixel array substrate as described in claim 8, wherein the conductive pattern further has a third portion; in a top view of the pixel array substrate, the third portion of the conductive pattern is located between the first common electrode and the gate, and the opening of the first insulating layer and the opening of the second insulating layer are located on the third portion of the conductive pattern.

10. The pixel array substrate as described in claim 8, wherein in a top view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the gate, and the opening of the first insulating layer and the opening of the second insulating layer do not overlap with the first common electrode and the gate.

11. The pixel array substrate according to claim 1, wherein the plurality of pixel structures are arranged into a plurality of pixel rows, the plurality of pixel rows are arranged in a first direction, and the pixel array substrate further comprises: A plurality of scan lines are arranged in a second direction and electrically connected to the plurality of pixel structures, wherein the first direction is interlaced with the second direction; A plurality of data lines are arranged in the first direction and electrically connected to the plurality of pixel rows; as well as A plurality of adapter lines are arranged in the first direction and electrically connected to the plurality of scan lines; The plurality of scan lines include an xn-th scan line to an x-th scan line arranged in sequence in the second direction, x is a positive integer greater than or equal to 2, n is a positive integer and less than x, and a turn-on time of a gate driving signal of the x-th scan line overlaps with a turn-off time of a gate driving signal of the xn-th scan line in timing sequence; The plurality of adapter lines include an xn-th adapter line and an x-th adapter line, which are electrically connected to the xn-th scan line and the x-th scan line respectively; The plurality of pixel rows include a k-1th pixel row, a kth pixel row and a k+1th pixel row arranged in sequence in the first direction, where k is a positive integer greater than or equal to 2; The plurality of data lines include a k-1th data line, a kth data line and a k+1th data line, which are electrically connected to the k-1th pixel row, the kth pixel row and the k+1th pixel row respectively; In the top view of the pixel array substrate, the xnth transfer line is disposed between the k-1th data line and the kth data line, and the xth transfer line is disposed between the kth data line and the k+1th data line.

12. The pixel array substrate of claim 11 , wherein the plurality of scan lines include the xnth scan line to the x+nth scan line arranged in sequence in the second direction, and an end time of the gate pulse signal of the xth scan line overlaps with a start time of a gate pulse signal of the x+nth scan line in timing; the plurality of adapters also include an x+nth adapter electrically connected to the x+nth scan line; the plurality of pixel rows also include a k+2th pixel row, and the k-1th pixel row, the kth pixel row, the k+1th pixel row and the k+2th pixel row are arranged in sequence in the first direction; the plurality of data lines also include a k+2th data line electrically connected to the k+2th pixel row; in a top view of the pixel array substrate, the x+nth adapter is disposed between the k+1th data line and the k+2th data line.

13. The pixel array substrate of claim 11, wherein the plurality of pixel rows further comprises a k+2th pixel row, the k-1th pixel row, the kth pixel row, the k+1th pixel row and the k+2th pixel row are arranged in sequence in the first direction; the plurality of data lines further comprises a k+2th data line electrically connected to the k+2th pixel row; the pixel array substrate further comprises: A first common line, wherein in a top view of the pixel array substrate, the first common line is disposed between the k+1th data line and the k+2th data line.

14. A pixel array substrate as described in claim 11, wherein the multiple pixel rows also include a k+2th pixel row, the k-1th pixel row, the kth pixel row, the k+1th pixel row and the k+2th pixel row are arranged in sequence in the first direction; the multiple data lines also include a k+2th data line electrically connected to the k+2th pixel row; the multiple scan lines include an mth scan line; the multiple transfer lines also include an mth transfer line electrically connected to the mth scan line; m is a positive integer greater than 2, |xm| is not equal to n; in the top view of the pixel array substrate, the mth transfer line is arranged between the k+1th data line and the k+2th data line.

15. The pixel array substrate as claimed in claim 11, wherein the plurality of scan lines include the ynth scan line to the yth scan line arranged in sequence in the second direction, y is a positive integer greater than or equal to 2, n is a positive integer and less than y, and a start time of a gate pulse signal of the yth scan line overlaps with an end time of a gate pulse signal of the ynth scan line in timing; the plurality of transfer lines include an ynth transfer line and a yth transfer line, which are electrically connected to the ynth scan line and the yth scan line respectively; the plurality of pixel rows include A q-1th pixel row, a qth pixel row and a q+1th pixel row are arranged in sequence in the first direction, q is a positive integer greater than or equal to 2; the multiple data lines include a q-1th data line, a qth data line and a q+1th data line, which are electrically connected to the q-1th pixel row, the qth pixel row and the q+1th pixel row respectively; in the top view of the pixel array substrate, the yth adapter line is arranged between the q-1th data line and the qth data line, and the ynth adapter line is arranged between the qth data line and the q+1th data line.

16. The pixel array substrate of claim 15, wherein the plurality of pixel rows further comprises a q+2th pixel row, the q-1th pixel row, the qth pixel row, the q+1th pixel row and the q+2th pixel row are arranged in sequence in the first direction; the plurality of data lines further comprises a q+2th data line electrically connected to the q+2th pixel row; the pixel array substrate further comprises: A second common line, wherein in the top view of the pixel array substrate, the second common line is disposed between the q+1th data line and the q+2th data line.

17. A pixel array substrate as described in claim 15, wherein the multiple pixel rows also include a q+2th pixel row, the q-1th pixel row, the qth pixel row, the q+1th pixel row and the q+2th pixel row are arranged in sequence in the first direction; the multiple data lines also include a q+2th data line electrically connected to the q+2th pixel row; the multiple scan lines include a pth scan line; the multiple transfer lines also include a pth transfer line electrically connected to the pth scan line; p is a positive integer greater than 2, |yp| is not equal to n; in the top view of the pixel array substrate, the pth transfer line is arranged between the q+1th data line and the q+2th data line. The pixel array substrate according to claim 11 , wherein n=4. The pixel array substrate according to claim 11 , wherein n=8.

20. The pixel array substrate as described in claim 11, wherein one of the plurality of scanning lines belongs to a first conductive layer, and one of the plurality of switching lines belongs to a second conductive layer; the pixel array substrate further comprises an insulating layer, which is arranged between the first conductive layer and the second conductive layer and has a contact window; one of the plurality of scanning lines is electrically connected to one of the plurality of switching lines through the contact window of the insulating layer.

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