Display device

Abstract

A display device includes a substrate including a display region and a transmissive region; a barrier layer arranged in the display region of the substrate and including a first barrier layer and a second barrier layer, the second barrier layer being arranged on the first barrier layer; an insulating layer arranged on the barrier layer; a transistor arranged on the insulating layer; and a light-emitting element connected to the transistor, wherein a first reflectance of the first barrier layer is smaller than a second reflectance of the second barrier layer, and a first absorption coefficient of the first barrier layer is smaller than a second absorption coefficient of the second barrier layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0096067, filed on July 31, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Display devices may include optical components such as sensors or cameras. These optical components may be arranged within the bezel area of ​​the display device (the area surrounding the display screen) to avoid interfering with the image displayed on the screen.

[0005] By reducing the bezels of a display device, the screen-to-body ratio can be increased. The screen-to-body ratio is defined as the ratio of the area occupied by the display screen to the entire front surface area of ​​the display device. The screen-to-body ratio is considered an important factor reflecting the technological advancements of display device manufacturers and plays a significant role in consumer product perception and choice.

[0006] The reduction in bezel size of display devices makes it difficult to place optics within the bezel area; therefore, techniques for placing optics within the display screen have been developed and adopted. However, when optics are placed within the display screen, their visibility can be affected by light flowing around them.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background of this disclosure, and may contain information that does not form prior art known to those skilled in the art. Summary of the Invention

[0008] According to embodiments of the present disclosure, optical components are arranged in the display screen of a display device, and the blocking layer of the display device can prevent the influence of light that may flow into the vicinity of the optical components.

[0009] Obviously, the purpose of this disclosure is not limited to the above-mentioned purposes, but can be extended in various ways without departing from the spirit and scope of this disclosure.

[0010] The display device according to an embodiment includes: a substrate including a display area and a transmissive area; a barrier layer disposed in the display area of ​​the substrate and including a first barrier layer and a second barrier layer, the second barrier layer being disposed on the first barrier layer; an insulating layer disposed on the barrier layer; a transistor disposed on the insulating layer; and a light-emitting element connected to the transistor, wherein a first reflectivity of the first barrier layer is less than a second reflectivity of the second barrier layer, and a first absorption coefficient of the first barrier layer may be less than a second absorption coefficient of the second barrier layer.

[0011] The first barrier layer may include a metal oxide, an organic material, or amorphous silicon, and the second barrier layer may include a metal.

[0012] The first barrier layer may include molybdenum oxide, and the second barrier layer may include molybdenum.

[0013] In addition to molybdenum oxide, the first barrier layer may also include tantalum, and the first barrier layer may include 8 wt% or more of tantalum.

[0014] In addition to molybdenum oxide, the first barrier layer may also include titanium, and the first barrier layer may include approximately 50 wt% titanium.

[0015] The display device may further include a first insulating layer disposed between the substrate and the first barrier layer, and the first insulating layer may include silicon.

[0016] The first insulating layer may include at least one of silicon oxynitride, amorphous silicon, silicon nitride, and silicon oxide.

[0017] The insulating layer may include a second insulating layer disposed between the second barrier layer and the transistor, and the second insulating layer may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0018] The second insulating layer includes a first layer and a second layer disposed on the first layer, wherein the first layer may include silicon nitride and the second layer includes silicon oxide.

[0019] A display device according to another embodiment includes: a first display area including a first pixel area; a second display area including a second pixel area and a transmissive area arranged adjacent to each other, wherein no pixel is arranged in the transmissive area; an optical device overlapping the second display area; and a blocking layer arranged in the second pixel area and including a first blocking layer and a second blocking layer, the second blocking layer being arranged on the first blocking layer, wherein a first reflectivity of the first blocking layer may be less than a second reflectivity of the second blocking layer, and a first absorption coefficient of the first blocking layer may be less than a second absorption coefficient of the second blocking layer.

[0020] The blocking layer may have an opening that overlaps with the transmission area, and the opening may have a cross-shaped planar shape.

[0021] The edges of the opening can have recessed and protruding portions.

[0022] The blocking layer may have an opening that overlaps with the transmission area, and the opening may have a circular planar shape.

[0023] A display device according to another embodiment includes: a substrate including a display area and a transmissive area; a barrier layer disposed in the display area of ​​the substrate and including a first barrier layer and a second barrier layer, the second barrier layer being disposed on the first barrier layer; an insulating layer disposed on the barrier layer; a transistor disposed on the insulating layer; and a light-emitting element connected to the transistor, wherein the first barrier layer may include a metal oxide and the second barrier layer may include a metal.

[0024] A display device according to another embodiment includes: a substrate including a display area and a transmissive area; a barrier layer disposed in the display area of ​​the substrate and including a first barrier layer and a second barrier layer, the second barrier layer being disposed on the first barrier layer; an insulating layer disposed on the barrier layer; a transistor disposed on the insulating layer; and a light-emitting element connected to the transistor, wherein the first barrier layer may include an organic material, and the second barrier layer may include a metal.

[0025] A display device according to another embodiment includes: a substrate including a display area and a transmissive area; a barrier layer disposed in the display area of ​​the substrate and including a first barrier layer and a second barrier layer, the second barrier layer being disposed on the first barrier layer; an insulating layer disposed on the barrier layer; a transistor disposed on the insulating layer; and a light-emitting element connected to the transistor, wherein the first barrier layer may include amorphous silicon and the second barrier layer may include metal.

[0026] According to an embodiment, the display area of ​​a display device can be expanded by arranging optical components in the display area, and the influence of light that may flow into the vicinity of the optical components can be prevented.

[0027] This disclosure is not limited to the embodiments disclosed herein, and it should be understood that various extensions may be made without departing from the spirit and scope of this disclosure. Attached Figure Description

[0028] Figure 1 This is a schematic top view of a display device according to an embodiment.

[0029] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment.

[0030] Figure 3 This is a schematic layout diagram of a portion of a first display area and a second display area of ​​a display device according to an embodiment.

[0031] Figure 4 This is a schematic layout diagram of a portion of the second display area of ​​a display device according to another embodiment.

[0032] Figure 5 This is a schematic layout diagram of a portion of the second display area of ​​a display device according to another embodiment.

[0033] Figure 6 This is a schematic layout diagram of the first display area and the second display area of ​​the display device according to an embodiment.

[0034] Figure 7 According to the embodiments, Figure 6 A schematic enlarged view of region A in the diagram.

[0035] Figure 8 According to another embodiment, Figure 6 A schematic enlarged view of region A in the diagram.

[0036] Figure 9 According to yet another embodiment, Figure 6 A schematic enlarged view of region A in the diagram.

[0037] Figure 10 This is a schematic layout diagram of the first display area and the second display area of ​​a display device according to another embodiment.

[0038] Figure 11 According to the embodiments, Figure 10 A schematic enlarged view of region BB in the diagram.

[0039] Figure 12 According to another embodiment, Figure 10 A schematic enlarged view of region BB in the diagram.

[0040] Figure 13 According to yet another embodiment, Figure 10 A schematic enlarged view of region BB in the diagram.

[0041] Figure 14 This is a cross-sectional view of a portion of the second display area of ​​the display device according to an embodiment.

[0042] Figure 15 This is a schematic diagram illustrating the path of light in a display device according to an embodiment.

[0043] Figure 16 This is a schematic diagram illustrating a portion of the manufacturing process of a display device according to an embodiment.

[0044] Figure 17 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0045] Figure 18 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0046] Figure 19 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0047] Figure 20 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0048] Figure 21 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0049] Figure 22 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0050] Figure 23 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0051] Figure 24 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0052] Figure 25 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0053] Figure 26 This is a cross-sectional view of a portion of the second display area of ​​a display device according to another embodiment.

[0054] Figure 27 These are electron micrographs showing the results based on experimental examples.

[0055] Figure 28A , Figure 28B and Figure 28C It is a graph showing the results based on the experimental example.

[0056] Figure 29A and Figure 29B It is a graph showing the results based on the experimental example.

[0057] Figure 30 It is a graph showing the results based on the experimental example.

[0058] Figure 31 It is a graph showing the results based on the experimental example.

[0059] Figure 32 These are electron micrographs showing the results based on experimental examples.

[0060] Figure 33 These are electron micrographs showing the results based on experimental examples. Detailed Implementation

[0061] The present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0062] The accompanying drawings and descriptions are to be regarded as exemplary rather than limiting in nature, and throughout the specification, the same reference numerals refer to the same elements.

[0063] In the accompanying drawings, the dimensions and thicknesses of the components are arbitrarily illustrated for ease of description, and this disclosure is not necessarily limited to the illustrations in the drawings. In the drawings, the thicknesses of layers, films, panels, regions, etc., may be exaggerated for clarity and ease of description.

[0064] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be one or more intermediate elements between them. Conversely, when an element is referred to as being "directly" on another element, there may be no intermediate elements between them. Furthermore, in the specification, the words "on" or "above" may mean being placed on or below the object part, and not necessarily placed on top of the object part based on the direction of gravity.

[0065] Additionally, unless there is an explicit description to the contrary, the words “including” and variations such as “comprising” will be understood to mean including the stated elements, but not excluding any other elements.

[0066] Furthermore, throughout the instruction manual, the phrase "in a plan view" means viewing the target portion from the top, and the phrase "in a cross-sectional view" means viewing the cross-section formed by vertically cutting the target portion from the side.

[0067] Furthermore, in this specification, the expression "connected to" means not only that two or more components are directly connected to each other, but also that two or more components are electrically connected to each other through another component, as well as indirectly connected and physically connected to each other, or that they may be referred to by different names depending on their location and / or function, but may be integrally formed.

[0068] In the accompanying drawings, the symbol x, used to indicate direction, refers to a first direction, y refers to a second direction perpendicular to the first direction, and z refers to a third direction perpendicular to both the first and second directions.

[0069] Referring to the accompanying drawings, an emitting display device including a light-emitting element is described as an example of a display device according to one or more embodiments.

[0070] Figure 1 This is a schematic top plan view of the display device 1 according to an embodiment, and Figure 2 This is a schematic cross-sectional view of the display device 1 according to an embodiment.

[0071] refer to Figure 1 and Figure 2 The display device 1 may include a display panel 10, a flexible printed circuit film 20 connected to the display panel 10, a driver including an integrated circuit chip 30, and an optical device 40.

[0072] Display panel 10 may include a display area DA on which an image is displayed, and a non-display area NA arranged around the display area DA that does not display an image. The display area DA may correspond to the display screen of display panel 10. Display panel 10 displays images and detects touch input.

[0073] Multiple pixels PX are arranged in the display area DA. Here, a pixel PX is the smallest unit used to display an image, and each pixel PX can display a specific color according to the input image signal, such as one of red, green, and blue with various brightness levels.

[0074] In the non-display area NA, circuitry and / or signal lines are arranged for generating and / or transmitting various signals applied to the display area DA. Signal lines such as gate lines, data lines, and drive voltage lines can be connected to each pixel PX, and the pixel PX can receive gate signals, data voltages, and drive voltages from these signal lines.

[0075] The display area DA includes a first display area DA1 and a second display area DA2. The second display area DA2 may have a higher transmittance than the first display area DA1, and it may perform other functions in addition to displaying an image. Here, transmittance refers to the transmittance of light passing through the display panel 10 in the third direction z. The light may be visible light and / or light with wavelengths outside the visible light spectrum (e.g., infrared light). The second display area DA2 may have a smaller pixel density PX than the first display area DA1. Here, pixel density PX may refer to the number of pixels PX per unit area.

[0076] Within the display area DA, the second display area DA2 can be arranged differently. In the illustrated embodiment, the second display area DA2 is arranged within and surrounded by the first display area DA1.

[0077] The second display area DA2 can be arranged to contact the non-display area NA. The second display area DA2 can be arranged on the upper left, right, and / or center of the display area DA. The second display area DA2 can be arranged to be divided into two or more areas. The second display area DA2 can be arranged across the top of the display area DA along a first direction x. The second display area DA2 can be arranged across the left and / or right ends of the display area DA along a second direction y. The second display area DA2 can have various shapes, such as polygons (e.g., quadrilaterals and triangles), circles, and ellipses.

[0078] Drivers that generate and / or process various signals used to drive the display panel 10 may be arranged in the non-display area NA of the display panel 10. The drivers may include data drivers that apply data voltages to data lines, gate drivers that apply gate signals to gate lines, and signal controllers (also known as timing controllers) that control the data drivers and gate drivers.

[0079] The driver can be integrated with the display panel 10 and can be arranged on the left and right sides or one side of the display area DA. The integrated circuit chip 30 (also referred to as the driver IC chip) may include a data driver and a signal controller, and the integrated circuit chip 30 can be mounted on the flexible printed circuit film 20 for electrical connection to the display panel 10. The integrated circuit chip 30 can be mounted on the non-display area NA of the display panel 10, or partially mounted on the display area DA of the display panel 10 and partially mounted on the non-display area NA of the display panel 10.

[0080] The touch sensing area capable of detecting touch input can approximately match the display area DA. Multiple touch electrodes TE (see...) Figure 6 A touch electrode TE is disposed in the touch sensing area. In one embodiment, a touch electrode TE may be arranged across multiple pixels PX. The touch electrode TE can detect user contact and / or non-contact touch input. Each touch electrode TE can sense touch input by a self-capacitance sensing method, or adjacent touch electrodes TE can sense touch input by a mutual capacitance sensing method. The display panel 10 may be referred to as a touch screen panel. The display device 1 may include a touch driver that generates signals for driving the touch electrodes TE and processes signals received from the touch electrodes TE. The touch driver may be provided in or as an integrated circuit chip 30.

[0081] The display panel 10 may include a substrate SB, and a plurality of pixels PX may be formed on the substrate SB. The substrate SB may be arranged continuously across a first display area DA1 and a second display area DA2.

[0082] The display panel 10 may include an encapsulation layer EN that can completely cover the pixels PX. The encapsulation layer EN can encapsulate the first display area DA1 and the second display area DA2 to prevent moisture or oxygen from penetrating into the display panel 10.

[0083] The touch electrode TE, in which the touch sensor layer TS is disposed, can be arranged on the encapsulation layer EN. The touch electrode TE may include a metal mesh. The touch electrode TE may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The touch electrode TE may be formed as a single layer or multiple layers.

[0084] An anti-reflective layer (AR) to reduce the reflection of external light can be disposed on the touch sensor layer (TS). The anti-reflective layer (AR) may include a polarization layer and / or a phase retardation layer. The anti-reflective layer (AR) may include light-shielding components and color filters.

[0085] Optical components 40 can be arranged to overlap with the display panel 10 on the back side of the display panel 10. Optical components 40 may include a camera, sensor, or flash, etc. If optical components 40 include sensors, they may include a distance sensor or an illuminance sensor. Light of the wavelength used by optical components 40 can pass through a second display area DA2 that may have a higher transmittance than the first display area DA1. In addition to optical components 40, various electronic devices may be arranged on the back side of the display panel 10.

[0086] Optical device 40 can emit light L of a predetermined wavelength range toward an object OB disposed in front of display panel 10 and / or receive light L reflected from object OB. The light L of the predetermined wavelength range can be processed by optical device 40 and can include visible light and / or infrared light. The light L of the predetermined wavelength range can primarily pass through the transmission area corresponding to the second display area DA2. When optical device 40 uses infrared light, the light L of the predetermined wavelength range can be in the wavelength range of approximately 900 nm to 1000 nm. Optical device 40 can receive light L of the predetermined wavelength range that can illuminate the front surface of display panel 10. Optical device 40 can be arranged to correspond to the entire second display area DA2, or it can be arranged to correspond only to a portion of the second display area DA2. Multiple optical devices 40 can be arranged in the second display area DA2.

[0087] Figure 3 This is a schematic layout diagram of a portion of the first display area DA1 and the second display area DA2 of the display device 1 according to an embodiment.

[0088] refer to Figure 3The first display area DA1 includes a plurality of first pixel areas PA1, and the second display area DA2 includes a plurality of second pixel areas PA2, a plurality of transmission areas TA, and a plurality of wiring areas WA disposed between the plurality of second pixel areas PA2 and the plurality of transmission areas TA. Each of the plurality of wiring areas WA can be positioned to surround the plurality of transmission areas TA.

[0089] The size of a first pixel region PA1 and the size of a second pixel region PA2 can be the same or different from each other.

[0090] In the first display area DA1, the first pixel area PA1 can be arranged in a matrix in the first direction x and the second direction y. In the second display area DA2, the second pixel area PA2 and the transmissive area TA can be arranged in a matrix. The second pixel area PA2 and the transmissive area TA can be arranged in a checkerboard pattern, and the second pixel area PA2 and the transmissive area TA can be uniformly mixed. That is, the transmissive area TA can be arranged to be adjacent to a second pixel area PA2 in the first direction x and the second direction y, and the second pixel area PA2 can be arranged to be adjacent to a transmissive area TA in the first direction x and the second direction y. At least one second pixel area PA2 and at least one transmissive area TA can be alternately arranged in the first direction x and / or the second direction y.

[0091] according to Figure 3 In the embodiment shown, eight second pixel regions PA2 can be arranged in regions corresponding to a transmissive region TA, and in the second display region DA2, the area ratio of the transmissive region TA to the area of ​​the second pixel regions PA2 can be approximately 8:1. Furthermore, in the second display region DA2, the ratio of the sum of the areas of the second pixel regions PA2 to the sum of the areas of the transmissive regions TA can be approximately 1:1. However, it should be understood that in other embodiments, the number of second pixel regions PA2 arranged in regions corresponding to a transmissive region TA can be varied without departing from the scope of this disclosure.

[0092] Each transmissive region TA can have the same size or different sizes. The settings and sizes of the second pixel region PA2 and the transmissive region TA can be changed without departing from the scope of this disclosure.

[0093] Each pixel region PA1 and PA2 may include at least one pixel PX. Pixel PX may include pixel circuitry and a light-emitting unit. Pixel circuitry refers to circuitry used to drive light-emitting elements such as light-emitting diodes (LEDs), and may include transistors, capacitors, etc. Light-emitting units correspond to the areas where light emitted from the light-emitting elements is emitted. Furthermore, in the second display region DA2, pixel circuitry may be arranged in the non-display region NA, and the pixel circuitry and the pixel PX arranged in the second pixel region PA2 may be connected by interconnecting wiring that may be made of a transparent material to improve the efficiency of the optics 40.

[0094] Figure 4 This is a schematic layout diagram of a portion of the second display area DA2 of a display device 1 according to another embodiment.

[0095] according to Figure 4 In the embodiment shown, eight second pixel regions PA2 can be arranged in regions corresponding to one transmissive region TA, and in the second display region DA2, the area ratio of the transmissive region TA to the area of ​​the second pixel regions PA2 can be approximately 8:1. Furthermore, in the second display region DA2, the ratio of the sum of the areas of the second pixel regions PA2 to the sum of the areas of the transmissive regions TA can be approximately 1:3. In the second display region DA2, multiple transmissive regions TA can be arranged along a first direction x and a second direction y to surround the periphery of the eight second pixel regions PA2.

[0096] Compared with the previous Figure 3 Compared to the embodiment shown, the area of ​​the transmission region TA in the second display region DA2 is relatively large compared to the area of ​​the second pixel region PA2. Therefore, the efficiency of the optical devices 40 arranged in the second display region DA2 can be improved.

[0097] Figure 5 This is a schematic layout diagram of a portion of the second display area DA2 of a display device 1 according to another embodiment.

[0098] according to Figure 5 In the embodiment shown, eight second pixel regions PA2 can be arranged in a region corresponding to a transmissive region TA, and in the second display region DA2, the area ratio of the transmissive region TA to the area of ​​the second pixel regions PA2 can be approximately 8:1. Furthermore, in the second display region DA2, the ratio of the sum of the areas of the second pixel regions PA2 to the sum of the areas of the transmissive region TA can be approximately 3:1. In the second display region DA2, the eight grouped second pixel regions PA2 can be arranged along a first direction x and a second direction y to surround the periphery of a transmissive region TA.

[0099] With the above Figure 3Compared to the embodiment shown, the area of ​​the second pixel region PA2 is relatively larger than the area of ​​the transmission region TA. Therefore, the efficiency of the multiple pixels PX arranged in the second display region DA2 can be improved, and a more accurate image can be displayed.

[0100] refer to Figures 3 to 5 The settings of the second pixel region PA2 and the transmissive region TA of the second display area DA2 of the described display device 1 are merely examples, and in other embodiments, the area and settings of the pixel region and the transmissive region may be changed.

[0101] The size of a second pixel region PA2 and the size of a transmissive region TA can be substantially the same or can be different from each other. Each of the transmissive regions TA can have substantially the same size or different sizes. The settings and sizes of the second pixel region PA2 and the transmissive regions TA can be varied. The ratio of the sum of the areas of the transmissive regions TA in the second display region DA2 to the sum of the areas of the second pixel regions PA2 can be approximately 1:2n-1 (where n is a natural number), for example, but not limited to 1:3 or approximately 1:7 and 1:15. The pixel density and transmittance of the second display region DA2 can vary depending on the ratio of the sum of the areas of the transmissive regions TA to the sum of the areas of the second pixel regions PA2. Pixel density and transmittance can be in a trade-off relationship.

[0102] Figure 6 This is a schematic layout diagram of the first display area DA1 and the second display area DA2 of the display device 1 according to an embodiment, and Figure 7 According to the embodiments, Figure 6 A schematic enlarged view of region A in the diagram.

[0103] The first pixel region PA1 and the second pixel region PA2 may each include at least one pixel PX. Figure 6 The pixel PX shown can correspond to a light-emitting unit. The light-emitting unit can be rhomboid, rectangular, or circular. The pixel PX can emit light substantially in the third direction z. The touch electrode portion TES can be arranged in the first pixel region PA1 and the second pixel region PA2. The touch electrode portion TES can be formed by a metal mesh in which metal wiring is wound like a net, and the metal mesh can be arranged without covering the light-emitting unit. Multiple touch electrode portions TES can be connected to each other to form a touch electrode TE.

[0104] The transmissive region TA may not include pixel circuitry and light-emitting units. In the transmissive region TA, pixel circuitry, light-emitting units, and touch electrodes TE that may interfere with light transmission may not be placed at all, or may be almost entirely absent, in order to provide a higher transmittance than the first pixel region PA1 and the second pixel region PA2.

[0105] The wiring area WA can be arranged around the second pixel area PA2, and multiple signal lines such as gate line GL and data line DL can be arranged in the first pixel area PA1, the second pixel area PA2, and the wiring area WA.

[0106] according to Figure 6 In the illustrated embodiment, each of the first pixel region PA1 and the second pixel region PA2 may include one red pixel R, two green pixels G, and one blue pixel B. Alternatively, the pixel settings of the first pixel region PA1 and the second pixel region PA2 may be different from each other. A set of red pixels R, green pixels G, and blue pixels B included in each pixel region PA1 and PA2 is referred to as a unit pixel. In another embodiment, a unit pixel may include one red pixel R, one green pixel G, and one blue pixel B. A unit pixel may include at least one of the red pixel R, green pixel G, and blue pixel B, and may also include a white pixel.

[0107] Pixels R, G, and B contained in the first display area DA1 and the second display area DA2 can form a pixel row in the first direction x.

[0108] In each pixel row of the first display area DA1 and the second display area DA2, pixels R, G, and B can be set in the first direction x. For example, pixels R, G, and B can be repeatedly set in the first direction x in the order of red pixel R, green pixel G, blue pixel B, and green pixel G. The setting of pixels R, G, and B contained in a pixel row can be varied. For example, pixels R, G, and B can be repeatedly set in the first direction x in the order of blue pixel B, green pixel G, red pixel R, and green pixel G, or in the order of red pixel R, blue pixel B, green pixel G, and blue pixel B.

[0109] Pixels R, G, and B in the first pixel region PA1 and the second pixel region PA2 can also form pixel columns in the second direction y. Within each pixel column, pixels R, G, and B can be set in the second direction y. Within each pixel column, pixels PX of the same color can be arranged, or pixels PX of two or more colors can be arranged alternately in the second direction y. The settings of pixels R, G, and B contained in a pixel column can be varied.

[0110] Pixels R, G, and B in the second pixel region PA2 can be cross-sectional emission type pixels, such as top-emission type pixels that emit light in the third direction z. In other embodiments, pixels R, G, and B in the second pixel region PA2 can be bottom-emission type or double-sided emission type.

[0111] refer to Figure 7In the second display area DA2, the second pixel area PA2 and the transmissive area TA can be arranged adjacent to each other, and the second pixel area PA2 includes a red pixel R, a green pixel G, and a blue pixel B. Gate lines GL that transmit gate signals to pixels R, G, and B can extend in a first direction x, and data lines DL that transmit data signals can extend in a second direction y. One data line DL can be arranged in each pixel column. Each data line DL can extend across the first display area DA1 and the second display area DA2. Gate on-time voltages of different timings can be transmitted to each pixel row, and two or more gate lines GL can be arranged in each pixel row. Figure 7 The embodiments shown differ; multiple data lines DL can be provided to each pixel column, or a single data line DL can be provided to multiple pixel columns.

[0112] The gate line GL and data line DL can be arranged in the wiring area WA to prevent the degradation of the transmittance of the transmission area TA. The wiring area WA is arranged at the boundary of the adjacent transmission area TA.

[0113] The blocking layer BL can be disposed in the second pixel region PA2, and the blocking layer BL can have an opening OPN disposed in the transmission region TA. The blocking layer BL can also be disposed in the wiring region WA arranged to surround the periphery of the transmission region TA to prevent light passing through the transmission region TA from diffracting around the transmission region TA, thereby preventing performance degradation of the optical device 40 caused by ambient light.

[0114] according to Figure 7 In one embodiment, the opening OPN of the barrier layer BL can have an approximately cross-shaped planar shape, and the dimensions of the upper protrusion, lower protrusion, left protrusion, and right protrusion of the cross-shaped opening OPN can be substantially the same.

[0115] The blocking layer BL may include metal and can prevent light from the outside from flowing into the second pixel area PA2 and prevent light passing through the transmission area TA from diffracting around the transmission area TA.

[0116] The opening OPN in the barrier layer BL, which has an approximately cross shape, can reduce the diffraction of light that may occur around the opening OPN in the barrier layer BL.

[0117] The blocking layer BL can be arranged to overlap with the wiring area WA in which the signal line that transmits the signal to the second pixel area PA2 is arranged, so as to prevent light from flowing to the signal line arranged in the wiring area WA and to prevent light from being reflected from the surface of the signal line and being identified on one side of the transmission area TA.

[0118] Figure 8 According to another embodiment, Figure 6 A schematic enlarged view of region A in the diagram. According to... Figure 8 In one embodiment, the opening OPN of the barrier layer BL has a planar shape that approximates a cross, and the dimensions of the upper, lower, left, and right protruding portions of the opening OPN can be substantially the same. Furthermore, the edges of the opening OPN of the barrier layer BL do not need to be straight lines, but can have an embossed shape in which recessed and protruding portions repeat.

[0119] The opening OPN of the barrier layer BL, which is formed in an approximately cross shape and has an edge formed in an embossed shape, can reduce the diffraction of light that may occur around the opening OPN of the barrier layer BL.

[0120] Figure 9 According to yet another embodiment, Figure 6 A schematic enlarged view of region A in the diagram. According to... Figure 9 In one embodiment, the opening OPN of the barrier layer BL has an approximately circular planar shape.

[0121] The opening OPN of the barrier layer BL, which is formed by an approximately circular planar shape, can reduce the diffraction of light that may occur around the opening OPN of the barrier layer BL.

[0122] Figure 10 This is a schematic layout diagram of the first display area DA1 and the second display area DA2 of the display device 1 according to another embodiment, and Figure 11 According to the embodiments, Figure 10 A schematic enlarged view of region BB in the diagram.

[0123] With the above Figure 6 and Figure 7 Similar to the display device 1 shown, each of the first pixel region PA1 and the second pixel region PA2 may include at least one pixel PX.

[0124] refer to Figure 10 and Figure 11 The first pixel region PA1 and the second pixel region PA2 may include a blue pixel B, a red pixel R, and a green pixel G, but they may have different unit pixel configurations without departing from the scope of this disclosure. Pixel PX may have a rectangular planar shape.

[0125] The planar size of blue pixel B can be larger than the planar size of red pixel R and green pixel G. For example, the planar size of blue pixel B can be approximately twice the planar size of red pixel R and green pixel G.

[0126] Pixels R, G, and B contained in the first display area DA1 and the second display area DA2 can form pixel rows in the first direction x, respectively.

[0127] In each pixel row of the first display area DA1 and the second display area DA2, pixels R, G, and B can be arranged in a row approximately in the first direction x. In each pixel row, a blue pixel B and its adjacent red pixel R and green pixel G in the second direction y can be repeatedly arranged in the first direction x. The arrangement of pixels R, G, and B contained in a pixel row can be varied.

[0128] Pixels R, G, and B in the first pixel region PA1 and the second pixel region PA2 can also form pixel columns in the second direction y. Within each pixel column, pixels R, G, and B can be set in the second direction y. Within each pixel column, pixels PX of the same color can be arranged, or pixels PX of two or more colors can be arranged alternately in the second direction y. The settings of pixels R, G, and B contained in a pixel column can be varied.

[0129] Pixels R, G, and B in the second pixel region PA2 can be cross-sectional emission type pixels, such as top-emission type pixels that emit light in the third direction z. In other embodiments, pixels R, G, and B in the second pixel region PA2 can be bottom-emission type or double-sided emission type.

[0130] according to Figure 11 In one embodiment, the opening OPN of the barrier layer BL can have an approximately cross-shaped planar shape, and the dimensions of the upper protrusion, lower protrusion, left protrusion, and right protrusion of the cross-shaped opening OPN can be substantially the same.

[0131] The approximately cross-shaped opening OPN in the barrier layer BL can reduce the effects of light diffraction that may occur around the opening OPN in the barrier layer BL.

[0132] Figure 12 According to another embodiment, Figure 10 A schematic enlarged view of region BB. According to... Figure 12 In one embodiment, the opening OPN of the barrier layer BL has a planar shape that approximates a cross, and the dimensions of the upper, lower, left, and right protruding portions of the opening OPN can be substantially the same. Furthermore, the edges of the opening OPN of the barrier layer BL do not need to be straight lines, but can have an embossed shape in which recessed and protruding portions repeat.

[0133] The opening OPN of the barrier layer BL, which is formed in an approximately cross shape and has an edge formed in an embossed shape, can reduce the diffraction of light that may occur around the opening OPN of the barrier layer BL.

[0134] Figure 13 According to yet another embodiment, Figure 10 A schematic enlarged view of region BB in the diagram. According to... Figure 13 In one embodiment, the opening OPN of the barrier layer BL can have an approximately circular planar shape.

[0135] The opening OPN of the barrier layer BL, which is formed by an approximately circular planar shape, can reduce the diffraction of light that may occur around the opening OPN of the barrier layer BL.

[0136] Figure 14 This is a cross-sectional view of a portion of the second display area DA2 of the display device 1 according to an embodiment. Figure 14 In the embodiment shown, the display device 1 includes a first transistor TR1, a second transistor TR2, and a light-emitting diode (LED), and further includes a second pixel region PA2 capable of displaying an image, a transmissive region TA, and a wiring region WA disposed around the second pixel region PA2. For ease of understanding and description, the first transistor TR1, the second transistor TR2, and the LED connected to the second transistor TR2 are primarily described; however, it should be understood that this disclosure is not limited thereto and may further include additional transistors. The first transistor TR1 may be referred to as a switching transistor, and the second transistor TR2 may be referred to as a driving transistor.

[0137] The substrate SB may comprise a polymer such as polyimide or polyamide, or an insulating material such as glass, and may be optically transparent. Figure 14 In the embodiment shown, the substrate SB may include a first transparent layer 110a and a second transparent layer 110b that overlap each other, and a first barrier layer 1100 disposed between the first transparent layer 110a and the second transparent layer 110b.

[0138] The first transparent layer 110a and the second transparent layer 110b may comprise polymers such as polyimide and polyamide, for example, at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose propionate.

[0139] The first barrier layer 1100 can prevent the penetration of moisture, etc., and may include materials such as silicon dioxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y The first barrier layer 1100 may include an inorganic insulating material.

[0140] The second barrier layer 1101 can be disposed on the substrate SB. The second barrier layer 1101 can prevent the penetration of unwanted components such as impurities or moisture while making the surface flat. The second barrier layer 1101 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon.

[0141] A barrier layer BL can be disposed on the second barrier layer 1101. The barrier layer BL can prevent light from flowing in from the bottom of the substrate SB and being identified. Specifically, the barrier layer BL is disposed in the second pixel region PA2 and the wiring region WA, excluding the transmissive region TA, to prevent light leakage around the transmissive region TA, thereby preventing performance degradation of electronic devices that can be disposed below the transmissive region TA due to external light.

[0142] The barrier layer BL may include a first barrier layer BL1 and a second barrier layer BL2 disposed on the first barrier layer BL1.

[0143] The absorption coefficient k of the second blocking layer BL2 can be greater than that of the first blocking layer BL1. The reflectivity n of the second blocking layer BL2 can be greater than that of the first blocking layer BL1. The absorption coefficient k and reflectivity n of the first blocking layer BL1 and the second blocking layer BL2 can be measured based on the visible light region (e.g., light in the wavelength range of approximately 380 nm to approximately 780 nm).

[0144] The first blocking layer BL1 of the blocking layer BL may include a material with low light reflectivity. Therefore, light can be prevented from being reflected from the blocking layer BL and incident on the optical device 40, thereby preventing the optical device 40 from being identified.

[0145] The first barrier layer BL1 of the barrier layer BL may include a metal oxide, an organic material, or amorphous silicon. When the first barrier layer BL1 includes an organic material, the same organic material can be used as a pixel-defining layer (e.g., Figure 14 The pixel-defining layer 350 shown may include a material with black color.

[0146] The metal oxide contained in the first barrier layer BL1 can be a molybdenum oxide. The first barrier layer BL1 may include metal impurities in the molybdenum oxide. For example, the first barrier layer BL1 may include tantalum or titanium in the molybdenum oxide.

[0147] The first barrier layer BL1 may include, for example, molybdenum tantalum oxide (MoTaO). x ) or molybdenum titanium oxide (MoTiO) xThe molybdenum oxide contains tantalum or titanium. The inclusion of tantalum or titanium in the molybdenum oxide can improve the heat resistance of the first barrier layer BL1, thereby maintaining the optical properties of the first barrier layer BL1 even after high-temperature processing.

[0148] For example, the first barrier layer BL1 may comprise molybdenum tantalum oxide (MoTaO) having a tantalum content of approximately 8 wt% or more. x In this case, the optical properties of the first barrier layer BL1 can be maintained even after a high-temperature process of approximately 450°C.

[0149] In another example, the first barrier layer BL1 may comprise molybdenum titanium oxide (MoTiO2) having a titanium content of approximately 50 wt% (e.g., 45-55 wt%). x In this case, the optical properties of the first barrier layer BL1 can be maintained even after a high-temperature process of approximately 450°C.

[0150] The thickness of the first barrier layer BL1 can be Or smaller, specifically or larger and Or smaller.

[0151] The second barrier layer BL2 of the barrier layer BL may include a metal. For example, the second barrier layer BL2 may include molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu).

[0152] Since the blocking layer BL includes a first blocking layer BL1 with a relatively small absorption coefficient k and a second blocking layer BL2 with a relatively large absorption coefficient k, light flowing in from the bottom of the display device 1 can be prevented from being reflected by the blocking layer BL and flowing to the side of the optical device 40 that can be arranged below the substrate SB.

[0153] The buffer layer 111 can be disposed on the second barrier layer 1101 and the blocking layer BL. The buffer layer 111 can have a single-layer or multi-layer structure. The buffer layer 111 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y ).

[0154] The second semiconductor layer 130 may be disposed on the buffer layer 111. The second semiconductor layer 130 may include a polysilicon material, such as a polycrystalline semiconductor. The second semiconductor layer 130 may include a channel region 132 and source regions 131 and drain regions 133 located on each side of the channel region 132.

[0155] The source region 131 of the second semiconductor layer 130 can be connected to the second source electrode SE2, and the drain region 133 of the second semiconductor layer 130 can be connected to the second drain electrode DE2.

[0156] The first gate insulating layer 141 can be disposed on the second semiconductor layer 130. The first gate insulating layer 141 can have a single-layer or multi-layer structure including silicon nitride, silicon oxide, or silicon oxynitride.

[0157] The second gate lower electrode GE2-L can be disposed on the first gate insulating layer 141. The second gate lower electrode GE2-L may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer or multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti).

[0158] The second gate insulating layer 142 can be disposed on the second gate lower electrode GE2-L. The second gate insulating layer 142 may include silicon nitride, silicon oxide, silicon oxynitride, etc. The second gate insulating layer 142 may have a single-layer or multi-layer structure including silicon nitride, silicon oxide and / or silicon oxynitride.

[0159] The second gate upper electrode GE2-U and the gate line GL can be disposed on the second gate insulating layer 142. The second gate lower electrode GE2-L and the second gate upper electrode GE2-U can overlap each other, with the second gate insulating layer 142 disposed therebetween. The second gate upper electrode GE2-U and the second gate lower electrode GE2-L can form the second gate electrode GE2. The second gate electrode GE2 can overlap with the channel region 132 of the second semiconductor layer 130 in a direction perpendicular to the substrate SB (i.e., the third direction z). The second gate upper electrode GE2-U and the gate line GL can comprise molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc., and can be a single-layer or multi-layer structure comprising molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc.

[0160] A metal barrier layer BML, located on the same layer as the second gate electrode GE2-U and the gate line GL, can be disposed on the second gate insulating layer 142. The metal barrier layer BML can overlap with the first transistor TR1.

[0161] The second semiconductor layer 130, the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2 can form a second transistor TR2. The second transistor TR2 can be a driving transistor connected to a light-emitting diode (LED) and can include polycrystalline semiconductor.

[0162] The first interlayer insulating layer 161 can be disposed on the second gate electrode GE2. The first interlayer insulating layer 161 may include silicon nitride, silicon oxide, or silicon oxynitride, etc. The first interlayer insulating layer 161 may have a multilayer structure in which layers including silicon nitride and silicon oxide are stacked. In this case, the layer including silicon nitride can be placed closer to the substrate SB than the layer including silicon oxide.

[0163] The first semiconductor layer 135 may be disposed on the first interlayer insulating layer 161. The first semiconductor layer 135 may overlap with the metal barrier layer BML.

[0164] The first semiconductor layer 135 may include an oxide semiconductor, which includes at least one of the following: a monometallic oxide such as indium (In) oxide, tin (Sn) oxide, or zinc (Zn) oxide; a binary metal oxide such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, or In-Ga oxide; or an oxide such as In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, or In-Ce-Zn oxide. Ternary metal oxides such as In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides; and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides. For example, the first semiconductor layer 135 may include indium gallium zinc oxide (IGZO) as an In-Ga-Zn oxide.

[0165] The first semiconductor layer 135 may include a channel region 137 and source regions 136 and drain regions 138 disposed on each side of the channel region 137. The source region 136 of the first semiconductor layer 135 may be connected to a first source electrode SE1, and the drain region 138 of the first semiconductor layer 135 may be connected to a first drain electrode DE1.

[0166] The third gate insulating layer 143 can be disposed on the first semiconductor layer 135. The third gate insulating layer 143 may include silicon nitride, silicon oxide, silicon oxynitride, etc. Figure 14 In some embodiments, the third gate insulating layer 143 may be disposed on the first semiconductor layer 135 and the first interlayer insulating layer 161. Therefore, the third gate insulating layer 143 may cover the upper and side surfaces of the source region 136, the channel region 137 and the drain region 138 of the first semiconductor layer 135.

[0167] In the process of realizing a high-resolution display device, the pixel size can be reduced, and therefore the length of the semiconductor channel can be reduced. If the third gate insulating layer 143 does not cover the upper surface of the source region 136 and the drain region 138, some material of the first semiconductor layer 135 can move to the side of the third gate insulating layer 143. In this embodiment, the third gate insulating layer 143, which is arranged to cover the entire surface of the first semiconductor layer 135 and the first interlayer insulating layer 161, can prevent short circuits between the first semiconductor layer 135 and the first gate electrode GE1 that may occur due to the diffusion of metal particles.

[0168] However, this disclosure is not limited thereto, and the third gate insulating layer 143 may not cover the entire surface of the first semiconductor layer 135 and the first interlayer insulating layer 161. For example, the third gate insulating layer 143 may only be disposed between the first gate electrode GE1 and the first semiconductor layer 135. That is, the third gate insulating layer 143 may overlap with the channel region 137 of the first semiconductor layer 135, but may not overlap with the source region 136 and the drain region 138.

[0169] The first gate electrode GE1 can be disposed on the third gate insulating layer 143. The first gate electrode GE1 can overlap with the channel region 137 of the first semiconductor layer 135 in a direction perpendicular to the substrate SB (i.e., the third direction z). The first gate electrode GE1 may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer or multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti). For example, the first gate electrode GE1 may include a lower layer containing titanium and an upper layer containing molybdenum, and the lower layer containing titanium can prevent the diffusion of fluorine (F) used as an etching gas during dry etching of the upper layer.

[0170] The first semiconductor layer 135, the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 can form a first transistor TR1. The first transistor TR1 can be a switching transistor for switching a second transistor TR2, and can include an oxide semiconductor.

[0171] The second interlayer insulating layer 162 can be disposed on the first gate electrode GE1. The second interlayer insulating layer 162 may include silicon nitride, silicon oxide, or silicon oxynitride. The second interlayer insulating layer 162 may have multiple layers stacked, including layers comprising silicon nitride and layers comprising silicon oxide.

[0172] The first source electrode SE1 and the first drain electrode DE1, as well as the second source electrode SE2 and the second drain electrode DE2, can be disposed on the second interlayer insulating layer 162. Each of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer or multi-layer structure including them. For example, each of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may have a three-layer structure comprising: a lower layer containing a refractory metal or alloy thereof such as molybdenum, chromium, tantalum, and titanium; an intermediate layer containing a metal with low resistivity such as aluminum, silver, and copper; and an upper layer containing a refractory metal such as molybdenum, chromium, tantalum, and titanium.

[0173] The second interlayer insulating layer 162 and the third gate insulating layer 143 may have a first opening OP1 and a second opening OP2, and the second interlayer insulating layer 162, the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141 may have a third opening OP3 and a fourth opening OP4. The first opening OP1 may overlap with the first source electrode SE1, the second opening OP2 may overlap with the first drain electrode DE1, the third opening OP3 may overlap with the second source electrode SE2, and the fourth opening OP4 may overlap with the second drain electrode DE2.

[0174] The first source electrode SE1 can be connected to the source region 136 of the first semiconductor layer 135 through the first opening OP1. The first drain electrode DE1 can be connected to the drain region 138 of the first semiconductor layer 135 through the second opening OP2. The second source electrode SE2 can be connected to the source region 131 of the second semiconductor layer 130 through the third opening OP3. The second drain electrode DE2 can be connected to the drain region 133 of the second semiconductor layer 130 through the fourth opening OP4.

[0175] The first planarization layer 170 may be disposed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The first planarization layer 170 may include an organic layer. For example, the first planarization layer 170 may include an organic insulating material such as a general polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having phenolic groups, an acrylic polymer, an imide polymer, a polyimide, or a siloxane polymer.

[0176] The connection electrode CE and the data line DL can be disposed on the first planarization layer 170. The connection electrode CE and the data line DL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer or multi-layer structure including them.

[0177] The first planarization layer 170 has a first contact hole 165, and the connecting electrode CE is connected to the second drain electrode DE2 through the first contact hole 165.

[0178] The second planarization layer 180 can be disposed on the first planarization layer 170, the connection electrode CE, and the data line DL. The second planarization layer 180 can remove steps and planarize the surface to improve the luminous efficiency of the light-emitting element to be formed thereon. The second planarization layer 180 may comprise an organic insulating material such as a general-purpose polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having phenolic groups, an acrylic polymer, an imide polymer, a polyimide, or a siloxane polymer.

[0179] The second planarization layer 180 has a second contact hole 185. The second contact hole 185 of the second planarization layer 180 may overlap with the second drain electrode DE2.

[0180] The anode 191 can be disposed on the second planarization layer 180. The anode 191 can be connected to the second drain electrode DE2 through the second contact hole 185 of the second planarization layer 180.

[0181] An anode 191 may be provided for each pixel PX. The anode 191 may include metals such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg) and gold (Au), and may also include transparent conductive oxides (TCOs) such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0182] Pixel defining layer 350 may be disposed on anode 191. Pixel defining layer 350 may comprise organic insulating materials such as general polymers (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide or siloxane polymers.

[0183] An opening overlapping the anode 191 can be formed in the pixel defining layer 350. The light-emitting element layer 370 can be arranged in the opening of the pixel defining layer 350.

[0184] The light-emitting element layer 370 may include a material layer that uniquely emits primary colors of light, such as red, green, or blue. The light-emitting element layer 370 (also referred to as the emitting layer) may have a structure in which multiple material layers emitting different colors of light are stacked.

[0185] The cathode 270 can be disposed on the light-emitting element layer 370 and the pixel defining layer 350. The cathode 270 can be commonly provided to all pixels PX and can receive a common voltage. The cathode 270 may comprise a reflective metal containing barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), and calcium (Ca), or a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO). The cathode 270 may be removed from the transmission region TA to improve the transmittance of the transmission region TA.

[0186] Anode 191, light-emitting element layer 370 and cathode 270 can form a light-emitting diode (LED).

[0187] The first transistor TR1, or the switching transistor, may comprise an oxide semiconductor, and the second transistor TR2, or the driving transistor, may comprise a polycrystalline semiconductor. For high-speed driving, the motion of moving images or videos can be represented more naturally by increasing the driving frequency from approximately 60 Hz to approximately 120 Hz, but this may increase the driving voltage. The frequency of driving still images can be reduced to compensate for the increased driving voltage. For example, when driving still images, the display device 1 may be driven at approximately 1 Hz. When the driving frequency is reduced in this way, leakage current may occur. In the display device 1 according to the embodiment, the first transistor TR1 comprises an oxide semiconductor, such that the leakage current can be reduced or minimized. In addition, since the second transistor TR2 comprises a polycrystalline semiconductor, high electron mobility can be achieved. In other words, by making the switching transistor and the driving transistor comprise different semiconductor materials, the display device 1 can be driven more stably while providing high reliability.

[0188] The blocking layer BL, arranged in the second pixel region PA2, can also be arranged in the wiring region WA. The gate line GL and the data line DL can be arranged in the wiring region WA. The cathode 270 can extend into the wiring region WA, and the edge of the cathode 270 can overlap perpendicularly with the edge of the blocking layer BL.

[0189] In the transmission region TA, the first interlayer insulating layer 161, the third gate insulating layer 143, and the second interlayer insulating layer 162 disposed in the second pixel region PA2 can be removed. The first planarization layer 170, the second planarization layer 180, and the pixel defining layer 350 disposed in the second pixel region PA2 can also be removed in the transmission region TA.

[0190] The edge portion of the blocking layer BL disposed in the second pixel region PA2 can form the opening OPN of the transmission region TA. Features related to the shape of the blocking layer BL and the opening OPN of the transmission region TA according to the above embodiment can be applied to other embodiments of this disclosure.

[0191] Thus, the transmission region TA has an opening OPN, the blocking layer BL disposed in the second pixel region PA2 is removed from the opening OPN, and light can be transmitted through the substrate SB to an optical device (e.g., disposed on the rear surface of the substrate SB). Figure 2 (40) of the optical device or transmitted from the optical device. The optical device may be a sensor, camera or flash.

[0192] The encapsulation layer 600 covering the surface of the substrate SB can be disposed over the entire area including the light-emitting diode (LED) of the display area DA, the pixel defining layer 350, and the transmissive area TA. The encapsulation layer 600 can be coupled with... Figure 2 The encapsulation layer EN corresponds to it.

[0193] Encapsulation layer 600 can be formed by alternately stacking at least one inorganic layer and at least one organic layer, and multiple inorganic or organic layers can be stacked. Figure 14 In the embodiment shown, the encapsulation layer 600 includes a first inorganic encapsulation layer 610, an organic encapsulation layer 620, and a second inorganic encapsulation layer 630. The organic encapsulation layer 620 may be disposed between the first inorganic encapsulation layer 610 and the second inorganic encapsulation layer 630.

[0194] The first inorganic encapsulation layer 610 and the second inorganic encapsulation layer 630 may include silicon nitride, silicon oxide, titanium oxide, or aluminum oxide, etc., and the organic encapsulation layer 620 may include an acrylic organic layer. However, the materials contained in the encapsulation layer 600 are not limited to these and may include other materials.

[0195] The encapsulation layer 600 can seal and protect the display device 1. A first protective layer 710, comprising an inorganic insulating material such as silicon nitride and silicon oxide, can be disposed on the encapsulation layer 600.

[0196] The touch electrode TE can be disposed on the first protective layer 710. The touch electrode TE may include metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), silver (Ag), chromium (Cr), and nickel (Ni). The touch electrode TE may be in the form of a mesh with openings overlapping the light-emitting unit. The touch electrode TE may include conductive nanomaterials such as silver nanowires and carbon nanotubes. The touch electrode TE may include transparent conductive materials such as ITO or IZO.

[0197] The touch electrode TE can be electrically connected to the touch driver via wiring, which can be arranged on the same layer as the layer including the touch electrode TE or on a different layer. Adjacent touch electrodes TE in the first direction x or the second direction y can be electrically connected via a bridge, which can be arranged on the same layer as the layer including the touch electrode TE or on a different layer. A second protective layer 720 can be arranged on the touch electrode TE to protect it.

[0198] Meanwhile, the cross-sectional structure of the first pixel region PA1 of the first display region DA1 can correspond to the cross-sectional structure of the second pixel region PA2.

[0199] Figure 15 This is a schematic diagram illustrating the path of light in the display device 1 according to an embodiment. (See reference) Figure 15 In (a), a blocking layer BL disposed on the substrate SB blocks light incident from below the substrate SB (i.e., from the rear side of the substrate SB), making the optical device 40 disposed in the transmission region TA on the rear surface of the substrate SB recognizable by the user. A portion a1 of the light a incident from the rear side of the substrate SB can be absorbed into the blocking layer BL, while another portion a2 of the light a can be reflected from the surface of the blocking layer BL and incident on one side of the optical device 40. As a result, the light incident on the surface of the optical device 40 may cause interference and be transmitted through the substrate SB and recognized by the user, thereby degrading the quality of the optical device 40.

[0200] refer to Figure 15 (b) According to the embodiment, the display device 1 includes a dual-layer barrier layer BL, which includes a first barrier layer BL1 having a small absorption coefficient k and a second barrier layer BL2 having a large absorption coefficient k. In this case, interference caused by light incident from the outside being reflected from the surface of the barrier layer BL and incident on the optical device 40 can be prevented.

[0201] Specifically, the first light q of incident light a can be reflected from the surface of the first blocking layer BL1, the second light c of light a can be absorbed by the first blocking layer BL1 into the second blocking layer BL2, and the third light p corresponding to a portion of the second light c can be reflected from the surface between the first blocking layer BL1 and the second blocking layer BL2.

[0202] The first blocking layer BL1 may comprise a material with low light reflectivity, and thus the amount of first light q reflected from the surface of the first blocking layer BL1 can be very small. Furthermore, the third light p reflected from the surface of the second blocking layer BL2 can destructively interfere with the first light q reflected from the surface of the first blocking layer BL1, thereby reducing its influence.

[0203] In this way, the barrier layer BL, formed by a double-layer structure of a first barrier layer BL1 with a small absorption coefficient k and a second barrier layer BL2 with a large absorption coefficient k, can prevent light reflected from the surface of the barrier layer BL from entering the optical device 40 and be identified by the user.

[0204] In addition, the second barrier layer BL2 of the barrier layer BL, which includes a metal with a large absorption coefficient k, can absorb light incident from the rear surface of the substrate SB, thereby preventing light from being identified around the transmission region TA and thus preventing quality degradation that may otherwise occur due to external light received by or emitted from the optical device 40 disposed on the rear surface of the substrate SB.

[0205] Figure 16 This is a schematic diagram illustrating a portion of the manufacturing process of the display device 1 according to an embodiment. (See reference) Figure 16 A barrier layer BL is formed on a substrate SB, and multiple insulating layers and element layers LL, such as thin-film transistors (e.g., first transistor TR1 and second transistor TR2), an anode 191, an organic emitting layer (e.g., light-emitting element layer 370), etc., are formed on the substrate SB. A cathode 270 is formed on the entire surface of the substrate SB. Using the barrier layer BL as a mask, a laser is irradiated onto the rear surface of the substrate SB to remove a portion of the cathode 270 and remove the cathode 270 in the transmission region TA, thus preventing degradation of the transmittance of the transmission region TA. The barrier layer BL, including a first barrier layer BL1 comprising a molybdenum oxide containing tantalum or titanium, can have high heat resistance, so that the optical properties of the barrier layer BL can be maintained when this portion of the cathode 270 is removed by the laser.

[0206] Figure 17 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 17 Display device 1 and according to reference Figure 14The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0207] In the display device 1 according to this embodiment, and according to... Figure 14 Unlike the display device 1 in the embodiment shown, the barrier layer BL can be arranged below the substrate SB, that is, on the rear surface of the substrate SB.

[0208] The second barrier layer BL2 of the barrier layer BL can be directly disposed below the substrate SB, and the first barrier layer BL1 can be disposed below the second barrier layer BL2.

[0209] The first blocking layer BL1 may include a material with low light reflectivity to prevent light from being reflected from the blocking layer BL and incident on the optical device 40, thus preventing it from being unnecessarily identified. The absorption coefficient k of the second blocking layer BL2 may be greater than the absorption coefficient k of the first blocking layer BL1.

[0210] The second barrier layer BL2 of the barrier layer BL may include metals, such as molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu), etc.

[0211] The blocking layer BL, which includes a first blocking layer BL1 with a small absorption coefficient k and a second blocking layer BL2 with a large absorption coefficient k, can prevent light flowing in from the bottom of the display device 1 from being reflected by the blocking layer BL and flowing to one side of the optical device 40 that can be arranged below the substrate SB.

[0212] Therefore, the barrier layer BL can prevent light reflected from the surface of the barrier layer BL from interfering with light directly incident on the optical device 40, thereby preventing quality degradation of the optical device 40 placed on the rear surface of the substrate SB due to external light. In addition, the second barrier layer BL2 of the barrier layer BL, which includes a metal with a large absorption coefficient, can absorb light incident from the rear surface of the substrate SB, thus preventing light from being identified around the transmission region TA.

[0213] Figure 18 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 18 Display device 1 and according to Figure 14 The display device 1 shown in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0214] In the display device 1 according to this embodiment, and according to... Figure 14The display device 1 shown in the embodiment is different. The first gate insulating layer 141 and the second gate insulating layer 142 arranged in the second pixel region PA2 can be removed in the transmission region TA, and the edge portions of the first gate insulating layer 141 and the second gate insulating layer 142 together with the edge portions of the first interlayer insulating layer 161, the third gate insulating layer 143 and the second interlayer insulating layer 162 can overlap with the edge of the transmission region TA.

[0215] The light transmittance in the transmission region TA can be further increased by additionally removing the first gate insulating layer 141 and the second gate insulating layer 142 in the transmission region TA.

[0216] The barrier layer BL disposed on the substrate SB in the second pixel region PA2 and the wiring region WA can prevent the optical device 40 from being degraded due to light scattering that may occur due to the inflow of external light into the second display region DA2, excluding the transmission region TA.

[0217] Figure 19 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 19 Display device 1 and according to reference Figure 14 The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0218] In the display device 1 according to this embodiment, and the reference... Figure 14 In a different embodiment, the first gate insulating layer 141 and the second gate insulating layer 142 disposed in the second pixel region PA2 can be removed in the transmission region TA, and the edge portions of the first gate insulating layer 141 and the second gate insulating layer 142, together with the edge portions of the first interlayer insulating layer 161, the third gate insulating layer 143 and the second interlayer insulating layer 162, can overlap with the edge of the transmission region TA.

[0219] Furthermore, in the display device 1 according to this embodiment, and according to... Figure 14 Unlike the display device 1 in the embodiment shown, the barrier layer BL can be arranged below the substrate SB, that is, behind the substrate SB.

[0220] The second barrier layer BL2 of the barrier layer BL can be directly disposed below the substrate SB, and the first barrier layer BL1 can be disposed below the second barrier layer BL2.

[0221] Figure 20 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 20 Display device 1 and according to reference Figure 14The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0222] In the display device 1 according to this embodiment, and according to... Figure 14 The display device 1 shown in the embodiment is different. The first gate insulating layer 141 and the second gate insulating layer 142 arranged in the second pixel region PA2 can be removed in the transmission region TA, and the first gate insulating layer 141 and the second gate insulating layer 142 together with the first interlayer insulating layer 161, the third gate insulating layer 143 and the second interlayer insulating layer 162 can be removed in the transmission region TA.

[0223] Furthermore, in the display device 1 according to this embodiment, and according to... Figure 14 The display device 1 shown in the embodiment is different, and the buffer layer 111 arranged on the blocking layer BL may include a first buffer layer 111a and a second buffer layer 111b.

[0224] The buffer layer 111, including a first buffer layer 111a and a second buffer layer 111b, can maintain the entire thickness of the buffer layer 111 while increasing the contact characteristics between the layers formed below the buffer layer 111 and the layers formed on the buffer layer 111 and reducing the refractive index difference between them. For example, the first buffer layer 111a may include silicon nitride, and the second buffer layer 111b may include silicon oxide.

[0225] The buffer layer 111, which includes a first buffer layer 111a and a second buffer layer 111b, can prevent moisture from flowing in from the outside and increase the light transmittance in the transmission region TA.

[0226] Figure 21 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 21 Display device 1 and according to reference Figure 14 The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0227] In the display device 1 according to this embodiment, and according to... Figure 14 The display device 1 shown in the embodiment is different, and the barrier layer BL is formed by a single layer.

[0228] The thickness T of the barrier layer BL can be approximately Or larger. Even if the barrier layer BL is formed as a monolayer containing molybdenum oxide, it has approximately Alternatively, a thicker barrier layer (BL) can also block light while preventing light reflection.

[0229] Figure 22 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 22 The display device 1 includes several layers, wiring, and components formed on a substrate SB. These components may include transistors TR, capacitors, and light-emitting diodes (LEDs). The substrate SB may include an insulating material such as glass and may be optically transparent. A second barrier layer 1101 may be disposed on the substrate SB. A blocking layer BL may be disposed on the second barrier layer 1101. The blocking layer BL may include a first blocking layer BL1 and a second blocking layer BL2 disposed on the first blocking layer BL1. A buffer layer 111 may be disposed on the second barrier layer 1101 and the blocking layer BL.

[0230] The semiconductor layer AL of the transistor TR can be disposed on the buffer layer 111. The semiconductor layer AL may include a channel region and source and drain regions disposed on each side of the channel region. The semiconductor layer AL may include polysilicon. In addition, the semiconductor layer AL may include semiconductor materials such as amorphous silicon, oxide semiconductor, etc.

[0231] A first gate insulating layer 141, comprising an inorganic insulating material, may be disposed on a semiconductor layer AL. For example, the first gate insulating layer 141 may have a single-layer or multi-layer structure comprising silicon nitride, silicon oxide, or silicon oxynitride.

[0232] On the first gate insulating layer 141, a first conductive layer including the gate line GL and the transistor TR, a first gate electrode GE1, can be disposed. The first gate electrode GE1 may overlap with the channel region of the semiconductor layer AL. The first conductive layer is a single-layer or multi-layer structure comprising a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti).

[0233] The first interlayer insulation layer 161 may be disposed on the first conductor layer. The first interlayer insulation layer 161 may include silicon nitride, silicon oxide, silicon oxynitride, etc.

[0234] A second conductor layer, including a second gate electrode GE2 that overlaps with the first gate electrode GE1, can be disposed on the first interlayer insulating layer 161. The second conductor layer may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0235] The second interlayer insulating layer 162 can be disposed on the second conductor layer. The second interlayer insulating layer 162 may include silicon nitride, silicon oxide, or silicon oxynitride, etc. The second interlayer insulating layer 162 may be formed by stacking multiple layers including layers including silicon nitride and layers including silicon oxide.

[0236] On the second interlayer insulating layer 162, a third conductor layer, including the source electrode SE and drain electrode DE of a data line DL, a drive voltage line, or a transistor TR, can be disposed. The source electrode SE and drain electrode DE can be connected to the source region and drain region of the semiconductor layer AL, respectively, through corresponding contact holes formed in the first gate insulating layer 141, the first interlayer insulating layer 161, and the second interlayer insulating layer 162. The third conductor layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), and / or copper (Cu), and may be a single-layer or multi-layer structure. For example, the third conductor layer may have a three-layer structure comprising: a lower layer containing a refractory metal or alloy thereof such as molybdenum, chromium, tantalum and titanium; an intermediate layer with low resistivity such as aluminum, silver and copper; and an upper layer containing a refractory metal such as molybdenum, chromium, tantalum and titanium.

[0237] The first gate electrode GE1, source electrode SE, and drain electrode DE together with the semiconductor layer AL form a transistor TR. The first gate electrode GE1 and the second gate electrode GE2 may form a capacitor together with the first interlayer insulating layer 161 disposed therebetween. The pixel circuit including the transistor TR and the capacitor may be arranged in the second pixel region PA2, but may not be arranged in the transmissive region TA.

[0238] A second planarization layer 180, which may include an organic insulating material, may be disposed on the second interlayer insulating layer 162 and the third conductor layer. The second planarization layer 180 may remove steps and planarize the surface to increase the luminous efficiency of the light-emitting element to be formed thereon. For example, the second planarization layer 180 may include an organic insulating material such as a general-purpose polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having phenolic groups, an acrylic polymer, an imide polymer, a polyimide, or a siloxane polymer.

[0239] The anode 191 of the light-emitting diode (LED) of pixel PX can be disposed on the second planarization layer 180. The anode 191 can be provided for each pixel PX. The anode 191 can include metals such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg), and gold (Au), and can also include transparent conductive oxides (TCOs) such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0240] Pixel defining layer 350 may be disposed on anode 191. Pixel defining layer 350 may comprise organic insulating materials such as general polymers (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide or siloxane polymers.

[0241] An opening overlapping the anode 191 can be formed in the pixel defining layer 350. The light-emitting element layer 370 can be arranged in the opening of the pixel defining layer 350.

[0242] The light-emitting element layer 370 may include a material layer that uniquely emits primary colors of light, such as red, green, or blue. The light-emitting element layer 370 may have a structure in which multiple material layers emitting different colors of light are stacked.

[0243] The cathode 270 can be disposed on the light-emitting element layer 370 and the pixel defining layer 350. The cathode 270 can be commonly provided to all pixels PX and can receive a common voltage. The cathode 270 may include reflective metals comprising barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), and calcium (Ca), or transparent conductive oxides (TCOs) such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0244] The cathode 270 can be removed from the transmission region TA to improve the transmittance of the transmission region TA.

[0245] Anode 191, light-emitting element layer 370 and cathode 270 can form a light-emitting diode (LED).

[0246] The blocking layer BL, which is placed in the second pixel region PA2, can also be placed in the wiring region WA. The gate line GL and the data line DL can be placed in the wiring region WA.

[0247] In the transmission region TA, the first gate insulating layer 141, the first interlayer insulating layer 161, the second interlayer insulating layer 162, the second planarization layer 180, and the pixel defining layer 350 arranged in the second pixel region PA2 can be removed.

[0248] The edge portion of the blocking layer BL arranged in the second pixel region PA2 can form the opening OPN of the transmission region TA.

[0249] The features of the shape of the opening OPN in the barrier layer BL and the transmission region TA according to the above embodiments can be applied to other embodiments of this disclosure.

[0250] The transmission region TA may have an opening OPN, from which the blocking layer BL disposed in the second pixel region PA2 is removed, and light can pass through an optical device (e.g., disposed on the rear surface of the substrate SB). Figure 2 Optical devices 40). Optical devices can be sensors, cameras, or flashes.

[0251] Furthermore, in the transmission region TA where the blocking layer BL is removed, the first gate insulating layer 141, the first interlayer insulating layer 161, and the second interlayer insulating layer 162, which may be inorganic insulating layers, may also be removed together with the second planarization layer 180, which may be an organic insulator, and the pixel defining layer 350, thereby increasing the light transmittance in the transmission region TA.

[0252] Although not shown, a thin-film encapsulation layer completely covers the substrate SB (e.g., Figure 2 Encapsulation layer EN, Figure 14 The encapsulation layer 600 or encapsulation substrate can be disposed over the entire area including the light-emitting diode (LED) of the display area DA, the pixel defining layer 350, and the transmissive area TA. When disposing of the encapsulation substrate, a glass frit can be used.

[0253] In addition, although not shown, it includes a touch layer (e.g., Figure 2 The touch sensor layer (TS) or touch wiring of the touch substrate can be arranged on a thin film encapsulation layer or encapsulation substrate.

[0254] Meanwhile, the cross-sectional structure of the first pixel region PA1 of the first display region DA1 can correspond to the cross-sectional structure of the second pixel region PA2.

[0255] Figure 23 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 23 Display device 1 and according to the above reference Figure 22 The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0256] In the display device 1 according to this embodiment, and according to... Figure 22 Unlike the display device 1 in the embodiment shown, the barrier layer BL can be arranged below the substrate SB, that is, behind the substrate SB.

[0257] The second barrier layer BL2 of the barrier layer BL can be directly disposed below the substrate SB, and the first barrier layer BL1 can be disposed below the second barrier layer BL2.

[0258] The absorption coefficient k of the second barrier layer BL2 can be greater than the absorption coefficient k of the first barrier layer BL1.

[0259] The reflectivity n of the second barrier layer BL2 can be greater than the reflectivity n of the first barrier layer BL1.

[0260] Since the first blocking layer BL1 of the blocking layer BL comprises a material with low light reflectivity, light can be prevented from being reflected by the blocking layer BL and incident on the optical device 40 and thus unnecessarily identified.

[0261] In addition, the second barrier layer BL2, which includes a metal with a large absorption coefficient, can absorb light incident from the rear surface of the substrate SB to prevent the light from being identified around the transmission region TA.

[0262] Figure 24 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 24 Display device 1 and according to reference Figure 22 The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0263] In the display device 1 according to this embodiment, and according to... Figure 22 The display device 1 shown in the embodiment is different, and the buffer layer 111 arranged on the blocking layer BL may include a first buffer layer 111a and a second buffer layer 111b.

[0264] The buffer layer 111, including a first buffer layer 111a and a second buffer layer 111b, can maintain the entire thickness of the buffer layer 111 while increasing the contact characteristics between the layers formed below the buffer layer 111 and the layers formed on the buffer layer 111 and reducing the refractive index difference between them. For example, the first buffer layer 111a may include silicon nitride, and the second buffer layer 111b may include silicon oxide.

[0265] The buffer layer 111, which includes a first buffer layer 111a and a second buffer layer 111b, can prevent moisture from flowing in from the outside and increase the light transmittance in the transmission region TA.

[0266] Figure 25 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 25 Display device 1 and according to reference Figure 22 The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0267] In the display device 1 according to this embodiment, and according to... Figure 22 The display device 1 shown in the embodiment differs from that in the example where the buffer layer 111 disposed on the blocking layer BL may include a first buffer layer 111a and a second buffer layer 111b. Furthermore, in the display device 1 according to this embodiment, unlike the example shown in the example where... Figure 22 Unlike the display device 1 in the embodiment shown, the barrier layer BL can be arranged below the substrate SB, that is, behind the substrate SB.

[0268] The second barrier layer BL2 of the barrier layer BL can be directly disposed below the substrate SB, and the first barrier layer BL1 can be disposed below the second barrier layer BL2.

[0269] Figure 26 This is a cross-sectional view of a portion of the second display area DA2 of a display device 1 according to another embodiment. (See reference) Figure 26 Display device 1 and according to reference Figure 22 The display device 1 described in the embodiment is similar. Detailed descriptions of the same constituent elements are omitted.

[0270] In the display device 1 according to this embodiment, and according to... Figure 22 Unlike the display device 1 shown in the embodiment, the barrier layer BL can be formed from a single layer.

[0271] The thickness T of the barrier layer BL can be approximately Or larger. Even if the barrier layer BL is formed as a monolayer containing molybdenum oxide, it has approximately Alternatively, a thicker barrier layer (BL) can also block light while preventing light reflection.

[0272] Figure 27 These are electron micrographs showing the results based on experimental examples. In the experimental examples, reflectance was measured for five different cases and is shown in Table 1: a first case (a) forming a barrier layer BL comprising a single layer of metal; a second case (b) forming a barrier layer BL comprising a first barrier layer BL1 made of metal oxide and a second barrier layer BL2 made of a metal layer; a third case (c) forming a barrier layer BL comprising a first barrier layer BL1 made of metal oxide and a second barrier layer BL2 made of a metal layer; a fourth case (d) forming a barrier layer BL comprising a second barrier layer 1101 made of silicon oxynitride; a fifth case (e) forming a barrier layer BL comprising a first barrier layer BL1 made of black organic layer and a second barrier layer BL2 made of a metal layer; and a fifth case (e) forming a barrier layer BL comprising a second barrier layer 1101 made of silicon oxynitride. The reflected light in each of the five cases was measured and... Figure 27 The image shown is a photograph.

[0273] (Table 1)

[0274]

[0275] refer to Figure 27 And as shown in Table 1, compared to the first case in which the blocking layer BL is formed from a single layer of metal, in the case where the blocking layer BL is formed to include a first blocking layer BL1 and a second blocking layer BL2, the average reflectivity is greatly reduced and the reflected light is not recognized.

[0276] Figures 28A to 28C This is a graph showing the results based on an experimental example. According to an embodiment of display device 1, the blocking layer BL includes a first blocking layer BL1 made of a metal oxide and a second blocking layer BL2 made of a metal layer. The first blocking layer BL1 may be formed of molybdenum titanium oxide, and the second blocking layer BL2 may be formed of molybdenum (Mo), titanium (Ti), and copper (Cu), respectively. The light transmittance was measured while varying the thickness of the first blocking layer BL1, and... Figures 28A to 28C The light transmittance is shown in . Figure 28A The results show the case where a second barrier layer BL2 is formed from molybdenum. Figure 28B The results show the case where a second barrier layer BL2 is formed from titanium, and Figure 28C The results show the case where a second barrier layer BL2 is formed from copper.

[0277] refer to Figures 28A to 28C Even when the thickness of the first barrier layer BL1 is not formed to be significantly thick but only approximately [thickness missing], Or even higher, with low reflectivity. As mentioned above, the reflectivity of the barrier layer BL can be kept below a certain value, regardless of which metal is contained in the second barrier layer BL2.

[0278] Figure 29A and Figure 29B This is a graph showing the results based on an experimental example. According to an embodiment of display device 1, the first barrier layer BL1 can be formed of molybdenum titanium oxide or molybdenum tantalum oxide. Figure 29A The reflectance of the first barrier layer BL1, formed from molybdenum titanium oxide and annealed with nitrogen at 400°C for one hour, is shown. Figure 29B The reflectance of the first barrier layer BL1, formed of molybdenum tantalum oxide and annealed with nitrogen at 400°C for one hour, is shown.

[0279] refer to Figure 29A and Figure 29B Even after annealing at a high temperature of 400°C for 1 hour, the reflectivity of the first barrier layer BL1 remains low. Although the reflectivity increases at some wavelengths when the first barrier layer BL1 is formed of molybdenum tantalum oxide, the wavelength range at which the reflectivity increases is narrow, and the reflectivity does not increase in most wavelength ranges.

[0280] In this way, even if the first barrier layer BL1 is formed and processed at high temperature (e.g., annealing), the reflectivity can be kept low.

[0281] Figure 30 This is a graph showing the results based on an experimental example. In this example, the first blocking layer BL1 can be formed of molybdenum-tantalum oxide, the second blocking layer BL2 can be formed of molybdenum, and the reflectivity is measured while varying the thickness of the first blocking layer BL1. For reflectivity, the average reflectivity is measured, and the reflectivity of light is measured at a wavelength of 550 nm.

[0282] refer to Figure 30 In the case where the first barrier layer BL1 is formed of molybdenum tantalum oxide and the second barrier layer BL2 is formed of molybdenum, specifically, the thickness of the first barrier layer BL1 can be approximately or larger and In cases where the reflectivity is even lower, it is kept below a specific value.

[0283] Figure 31 This is a graph showing the results based on an experimental example. In this experimental example, the first barrier layer BL1 can be formed of molybdenum tantalum oxide, and the thickness of the first barrier layer BL1 can be approximately... The reflectivity, which depends on the wavelength of light, was measured while the material of the second barrier layer BL2 was changed.

[0284] refer to Figure 31 The first barrier layer BL1 is formed of molybdenum tantalum oxide and the thickness of the first barrier layer BL1 is approximately up to approximately Within the range (e.g.) In the case of ), regardless of the material of the second barrier layer BL2, the first barrier layer BL1 can have low reflectivity at approximately 400 nm to 680 nm.

[0285] Figure 32 These are electron micrographs showing the results based on an experimental example. In this experimental example, the barrier layer BL was batch-etched with a first barrier layer BL1 of molybdenum tantalum oxide and a second barrier layer BL2 of molybdenum.

[0286] refer to Figure 32 After the barrier layer BL is etched in batches, the barrier layer BL is well etched without any protrusions, and therefore, it can be confirmed that fine pattern formation can be obtained.

[0287] Figure 33These are electron micrographs showing the results based on an experimental example. In this experimental example, for the first case without the formation of a barrier layer BL and the second case with a double-layer barrier layer BL, light reflection was measured and shown after the wiring was formed to a width of approximately 2.5 μm.

[0288] refer to Figure 33 In the first case without the barrier layer BL, reflections may occur on the wiring, while in the second case with a double barrier layer BL, the wiring may not be well identified due to reduced light reflection.

[0289] Although this disclosure has been described in conjunction with various embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalents included within the spirit and scope of this disclosure, including the appended claims.

Claims

1. A display device, comprising: The substrate includes both the display area and the transmission area; A barrier layer disposed in the display area of ​​the substrate and including a first barrier layer and a second barrier layer, wherein the second barrier layer is disposed on the first barrier layer; An insulating layer disposed on the barrier layer; Transistors disposed on the insulating layer; as well as The light-emitting element connected to the transistor, Wherein the first reflectivity of the first blocking layer is less than the second reflectivity of the second blocking layer, and The first absorption coefficient of the first barrier layer is less than the second absorption coefficient of the second barrier layer.

2. The display device according to claim 1, wherein, The first barrier layer comprises a metal oxide, an organic material, or amorphous silicon, and The second barrier layer comprises metal.

3. The display device according to claim 1, wherein, The first barrier layer comprises molybdenum oxide, and The second barrier layer comprises molybdenum.

4. The display device according to claim 3, wherein, In addition to the molybdenum oxide, the first barrier layer also includes tantalum.

5. The display device according to claim 4, wherein, The first barrier layer comprises 8 wt% or more tantalum.

6. The display device according to claim 3, wherein, In addition to the molybdenum oxide, the first barrier layer also includes titanium.

7. The display device according to claim 6, wherein, The first barrier layer comprises 45-55 wt% titanium.

8. The display device according to claim 1, further comprising: A first insulating layer disposed between the substrate and the first barrier layer. The first insulating layer comprises at least one of silicon oxynitride, amorphous silicon, silicon nitride, and silicon oxide.

9. The display device according to claim 8, wherein, The insulating layer includes a second insulating layer disposed between the second barrier layer and the transistor. The second insulating layer comprises at least one of silicon nitride, silicon oxide, and silicon oxynitride.

10. The display device according to claim 9, wherein, The second insulating layer includes a first layer and a second layer disposed on the first layer, and The first layer comprises silicon nitride, and the second layer comprises silicon oxide.

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