Display panel and display device

Abstract

The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device for improving the reliability of the display device. The display panel includes a substrate, a planarization layer, a conductive connection pattern, a spacer layer, and a source-drain conductive layer. The planarization layer is disposed on the substrate, and the planarization layer is provided with a first slot penetrating through the planarization layer; the conductive connection pattern is disposed between the substrate and the planarization layer, and both ends of the conductive connection pattern extend out of both side boundaries of the first slot along a second direction; the spacer layer is disposed between the substrate and the planarization layer and covers the conductive connection pattern; the source-drain conductive layer is disposed between the spacer layer and the planarization layer, and the source-drain conductive layer includes a signal line having a break, and two parts of the signal line separated by the break are respectively electrically connected to the conductive connection pattern through vias penetrating through the spacer layer. By overlapping the signal line with the conductive connection pattern, the problem of water vapor intrusion into the display area of the display panel is improved, and the reliability of the display device is enhanced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of electronic products, AMOLED (Active Matrix Organic Light-Emitting Diode) display devices have been widely used because they can achieve full-screen, narrow bezel, high resolution, curling and wearable, folding, etc.

[0003] Currently, how to prevent water vapor from invading the AMOLED display device and improve the reliability and service life of the display device has been a problem that the industry has been exploring. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel and a display device, aiming to reduce the invasion of water vapor in the display panel, so as to improve the reliability of the display device and extend its service life.

[0005] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a display panel is provided, including a display area and a bonding area located on one side of the display area.

[0007] The display panel includes: a substrate, a planarization layer, a conductive connection pattern, a spacer layer, and a source-drain conductive layer.

[0008] Wherein, the planarization layer is disposed on the substrate; the planarization layer is provided with a first slot penetrating through the planarization layer, the first slot is located between the display area and the bonding area, and extends along a first direction; the first direction is the extending direction of the side of the display area where the bonding area is located.

[0009] The conductive connection pattern is disposed between the substrate and the planarization layer; the orthographic projection of the conductive connection pattern on the substrate overlaps with the orthographic projection of the first slot on the substrate, and both ends of the conductive connection pattern extend out of both side boundaries of the first slot along a second direction; the second direction is perpendicular to the first direction.

[0010] The spacer layer is disposed between the substrate and the planarization layer and covers the conductive connection pattern; the spacer layer is provided with a first via hole and a second via hole, and the first via hole and the second via hole are respectively located on both sides of the first slot in the second direction.

[0011] The source-drain conductive layer is disposed between the spacer layer and the planarization layer; the source-drain conductive layer includes a signal line with a break, and the orthographic projection of the break on the substrate overlaps with the orthographic projection of the first slot on the substrate; the signal line is divided into a first sub-signal line and a second sub-signal line by the break, the boundary of the first sub-signal line at the break is closer to the display area relative to the first slot, and the boundary of the second sub-signal line at the break is closer to the bonding area relative to the first slot; the first sub-signal line is electrically connected to the conductive connection pattern through the first via, and the second sub-signal line is electrically connected to the conductive connection pattern through the second via.

[0012] By disconnecting the signal line in the source-drain conductive layer at a position corresponding to the first slot and electrically connecting the two disconnected parts of the signal line through the conductive connection pattern on the side of the spacer layer away from the planarization layer, damage to the signal line during the formation of the first slot or the remaining planarization layer material at the first slot is avoided. In the embodiments of the present disclosure, the first slot exposes the spacer layer, and the signal line will not be damaged during the formation of the first slot. At the same time, it can ensure that the planarization layer material corresponding to the first slot is fully removed, thereby avoiding the problem of external water vapor invading the display area of the display panel due to the remaining planarization layer material at the first slot.

[0013] In some embodiments, the display panel further includes: a bottom shielding layer, a buffer layer, a first active layer, a first gate insulating layer, a first gate conductive layer, a first interlayer dielectric layer, a second gate conductive layer, a second interlayer dielectric layer, a second active layer, a second gate insulating layer, a third gate conductive layer, and a third interlayer dielectric layer, which are arranged in a direction perpendicular to the substrate and away from the substrate; the conductive connection pattern is disposed on the bottom shielding layer and / or the third gate conductive layer.

[0014] In some embodiments, the conductive connection pattern is disposed on the bottom shielding layer; the spacer layer includes at least one of the buffer layer, the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second gate insulating layer, and the third interlayer dielectric layer, and the first via and the second via penetrate through each film layer included in the spacer layer.

[0015] In some embodiments, the conductive connection pattern is disposed on the third gate conductive layer; the spacer layer includes the third interlayer dielectric layer, and the first via and the second via penetrate through the third interlayer dielectric layer.

[0016] In some embodiments, the conductive connection pattern includes a first sub-conductive connection pattern and a second sub-conductive connection pattern, the first sub-conductive connection pattern is disposed on the bottom shielding layer, and the second sub-conductive connection pattern is disposed on the third gate conductive layer.

[0017] The spacer layer includes the third interlayer dielectric layer, and further includes at least one of the buffer layer, the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, and the second gate insulating layer.

[0018] The first via hole includes a first sub-via hole and a second sub-via hole, the second via hole includes a third sub-via hole and a fourth sub-via hole, the first sub-via hole and the third sub-via hole penetrate through each film layer included in the spacer layer, and the second sub-via hole and the fourth sub-via hole penetrate through the third interlayer dielectric layer.

[0019] The first sub-signal line is electrically connected to the first sub-conductive connection pattern through the first sub-via hole, and is electrically connected to the second sub-conductive connection pattern through the second sub-via hole; the second sub-signal line is electrically connected to the first sub-conductive connection pattern through the third sub-via hole, and is electrically connected to the second sub-conductive connection pattern through the fourth sub-via hole.

[0020] In some embodiments, along the second direction, both ends of the first conductive connection pattern extend beyond the boundaries of both ends of the second conductive connection pattern, and the second sub-via hole is closer to the first slot than the first sub-via hole, and the fourth sub-via hole is closer to the first slot than the third sub-via hole.

[0021] In some embodiments, the display panel further includes: a bottom shielding layer, a buffer layer, a first active layer, a first gate insulating layer, a first gate conductive layer, a first interlayer dielectric layer, a second gate conductive layer, and a second interlayer dielectric layer, which are arranged in a direction perpendicular to the substrate and away from the substrate; the conductive connection pattern is disposed on the bottom shielding layer; the spacer layer includes at least one of the buffer layer, the first gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer, and the first via hole and the second via hole penetrate through each film layer included in the spacer layer.

[0022] In some embodiments, the bottom shielding layer further includes a bottom shielding pattern, and a positive projection of the bottom shielding pattern on the substrate covers a positive projection of the first active layer on the substrate.

[0023] In some embodiments, the third gate conductive layer further includes a scanning signal line, and the scanning signal line is configured to transmit a scanning signal.

[0024] In some embodiments, the first slotted opening includes a first sub-slotted opening and a second sub-slotted opening. The first sub-slotted opening and the second sub-slotted opening extend along the first direction and are arranged side by side along the second direction. The first sub-slotted opening is closer to the display area than the second sub-slotted opening. The orthographic projection of the conductive connection pattern on the substrate overlaps with the orthographic projections of the first sub-slotted opening and the second sub-slotted opening on the substrate. Along the second direction, the end of the conductive connection pattern closer to the display area extends beyond the side boundary of the first sub-slotted opening closer to the display area, and the end of the conductive connection pattern closer to the bonding area extends beyond the side boundary of the second sub-slotted opening closer to the bonding area.

[0025] In some embodiments, the display panel further includes a peripheral area disposed around the display area, and the bonding area is disposed on a side of the peripheral area away from the display area.

[0026] Wherein, the display panel further includes: a first dam and a second dam, which are disposed in the peripheral area and surround the display area. The first dam and the second dam are spaced apart, and the first dam is closer to the display area than the second dam. In the peripheral area close to the bonding area, the first dam is disposed between the first sub-slotted opening and the second sub-slotted opening, and the second dam is disposed on a side of the second sub-slotted opening closer to the bonding area.

[0027] In some embodiments, both the first dam and the second dam include a plurality of sub-layers stacked along the thickness direction of the substrate, and at least one layer of the plurality of sub-layers is located in the planarization layer.

[0028] In some embodiments, the display panel further includes a peripheral area disposed around the display area, and the bonding area is disposed on a side of the peripheral area away from the display area.

[0029] Wherein, the planarization layer further includes: a second slotted opening, which is disposed in the peripheral area, and the second slotted opening communicates with the first slotted opening to form a ring surrounding the display area.

[0030] In some embodiments, the signal line includes a first power line and / or a second power line. The first power line is configured to transmit a first voltage signal, and the second power line is configured to transmit a second voltage signal.

[0031] In some embodiments, the source-drain conductive layer includes two groups of signal lines, each group includes at least one signal line, and the two groups of signal lines are respectively located on opposite sides of the median line extending along the second direction in the bonding area. Each signal line in each group of signal lines is provided with a break, and a conductive connection pattern is correspondingly provided at the break of the signal line, and the signal line is electrically connected to the corresponding conductive connection pattern.

[0032] On the other hand, a display device is provided, including the display panel according to any one of the above embodiments.

[0033] The display panel and the display device provided by the embodiments of the present disclosure have the following beneficial effects:

[0034] By disconnecting the signal line in the source-drain conductive layer at the position corresponding to the first slot, and electrically connecting the two disconnected parts of the signal line through the conductive connection pattern located on the side of the spacer layer away from the planarization layer, that is, the signal line is conducted through the film layer on the side of the spacer layer away from the planarization layer at the position corresponding to the first slot, the exposure of the signal line by the first slot is avoided, thereby avoiding damage to the signal line caused by over-deep grooving or residual planarization layer material at the first slot due to under-deep grooving during the formation of the first slot, and preventing external moisture from invading the display area of the display panel along the planarization layer and the residual planarization material, improving the reliability of the display device and extending its service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required for some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0036] Figure 1 Structural diagram of a display device provided according to some embodiments;

[0037] Figure 2 Top view of a display panel provided according to some embodiments;

[0038] Figure 3 For Figure 2 A structural diagram corresponding to region B in

[0039] Figure 4 For Figure 3 A cross-sectional view along the section line C-C' in

[0040] Figure 5 For Figure 2 Another structural diagram corresponding to region B in

[0041] Figure 6 For Figure 5 A cross-sectional view along the section line H-H' in

[0042] Figure 7 For Figure 2 A cross-sectional view along the section line D-D' in

[0043] Figure 8 Another sectional view along the section line C-C' in Figure 3 ;

[0044] Figure 9 Another sectional view along the section line C-C' in Figure 3 ;

[0045] Figure 10 Another sectional view along the section line C-C' in Figure 3 ;

[0046] Figure 11 Another sectional view along the section line D-D' in Figure 2 ;

[0047] Figure 12 Another sectional view along the section line C-C' in Figure 3 ;

[0048] Figure 13 Another top view of a display panel provided according to some embodiments;

[0049] Figure 14 For Figure 13 a structural diagram corresponding to region E in

[0050] Figure 15 Another sectional view along the section line G-G' in Figure 14 ;

[0051] Figure 16 For Figure 13 a structural diagram corresponding to region F in Detailed implementation manners

[0052] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third-person singular form "comprises" and the present participle form "comprising" are construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc. are intended to indicate that the specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0055] When describing some embodiments, the expressions "electrically connected" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0056] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0057] As used herein, "parallel", "perpendicular", and "equal" include the stated cases as well as cases similar to the stated cases, where the similar cases are within an acceptable deviation range, and the acceptable deviation range is determined by one of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal values is less than or equal to 5% of either one of them.

[0058] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] Figure 1 A top view structure of a display device is shown. As Figure 1As shown, some embodiments of the present disclosure provide a display device 100, which can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images), and whether text or otherwise. More specifically, the expected embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 In [the figure], the display device 1000 is taken as an example of a mobile phone for illustration.

[0061] The display device 100 includes a display panel 200. The display panel 200 can be an electroluminescent display panel or a photoluminescent display panel. When the display panel 200 is an electroluminescent display panel, the electroluminescent display panel can be an Organic Light-Emitting Diode (OLED) display panel or a Quantum Dot Light Emitting Diode (QLED) display panel. When the display panel 200 is a photoluminescent display panel, the photoluminescent display device can be a quantum dot photoluminescent display panel.

[0062] For the display panel 200 provided by some embodiments of the present disclosure, the display panel 200 is taken as an example of an Organic Light-Emitting Diode (OLED) display panel for description.

[0063] Figure 2 Shows Figure 1 A top view of the display panel 200 in [the figure]. As Figure 2 Shown, the display panel 200 includes a display area AA and a bonding area V located on one side of the display area AA.

[0064] Figure 3 Shows Figure 2 An enlarged view of the area shown by the dashed box B in [the figure], Figure 4 Shows a cross-sectional view along Figure 3 The section line C-C' in [the figure].

[0065] As Figure 4As shown, in some embodiments, the display panel 200 includes a substrate 10.

[0066] Exemplarily, the substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may include a polyimide layer and a buffer layer stacked in sequence. Again, for example, the substrate 10 may include multiple pairs of polyimide layers and buffer layers stacked in sequence. The material of the buffer layer may include silicon nitride and / or silicon oxide to achieve the effects of water and oxygen barrier and alkaline ion barrier.

[0067] As Figure 4 shown, the display panel 200 further includes a planarization layer 20 (Planarization Layer, abbreviated as PLN) disposed on the substrate 10.

[0068] Exemplarily, the planarization layer 20 may be a single-layer structure or a multi-layer structure.

[0069] Exemplarily, the material of the planarization layer 20 may include organic materials. For example, the material of the planarization layer 20 may include polyimide, acrylic-based polymer, or silicon-based polymer, etc.

[0070] The planarization layer 20 is provided with a first slot K1 penetrating through the planarization layer 20. As Figure 2 shown, the first slot K1 is located between the display area AA and the bonding area V and extends along the first direction X.

[0071] It should be noted that, as Figure 2 and Figure 3 shown, the first direction X is the extension direction of the side of the display area AA where the bonding area V is located.

[0072] Exemplarily, after the planarization layer 20 is formed, by removing part of the material of the planarization layer 20 between the display area AA and the bonding area V, the first slot K1 is formed. For example, a planarization film is formed, and part of the material of the planarization film is removed by etching to form the first slot K1.

[0073] Since the material of the planarization layer 20 includes polar polymer materials with many polar groups on its main chain, the planarization layer 20 has strong water absorption, and the water vapor outside the display panel 200 is easy to extend along the planarization layer 20 to the display area AA. Therefore, by disposing the first slot K1 between the display area AA and the bonding area V, the planarization layer 20 is disconnected in the area between the display area AA and the bonding area V, thereby interrupting the path of water vapor invading the display area AA along the planarization layer 20 from the side of the display panel 200 where the bonding area V is set, and avoiding reliability problems caused by the invasion of the display area AA by water vapor.

[0074] It should be noted that in the embodiments of the present disclosure, "reliability" refers to the ability of a product (such as a display device) to still maintain normal operation after operating in the use environment for a period of time. In the present disclosure, when water vapor invades the display area, it is easy to damage the components (such as light-emitting components) located in the display area, thereby causing reliability problems.

[0075] As Figure 4 shown, the display panel 200 further includes a conductive connection pattern P disposed between the substrate 10 and the planarization layer 20. The orthographic projection of the conductive connection pattern P on the substrate 10 overlaps with the orthographic projection of the first slotted opening K1 on the substrate 10, and both ends of the conductive connection pattern P in the second direction Y extend out of the two side boundaries of the first slotted opening K1. For example Figure 3 shown, both ends of the conductive connection pattern P in the second direction Y respectively extend out of the first side boundary H1 of the first slotted opening K1 and the second side boundary H2 of the first slotted opening K1.

[0076] It should be noted that as Figure 2 and Figure 3 shown, the second direction Y is perpendicular to the first direction X.

[0077] Exemplarily, the first direction X may be the horizontal direction of the display device 100, and the second direction Y may be the vertical direction of the display device 100.

[0078] Exemplarily, as Figure 3 shown, the conductive connection pattern P may extend along the second direction Y, and one end thereof close to the display area AA is closer to the display area AA than the first slotted opening K1, and one end thereof close to the bonding area V is closer to the bonding area V than the first slotted opening K1.

[0079] Exemplarily, the material of the conductive connection pattern P is a metal material, for example, molybdenum.

[0080] As Figure 4 shown, the display panel 200 further includes a spacer layer 30 disposed between the substrate 10 and the planarization layer 20, and the spacer layer 30 covers the conductive connection pattern P. The spacer layer 30 is provided with a first via 31 and a second via 32, and the first via 31 and the second via 32 are respectively located on both sides of the first slotted opening K1 in the second direction Y.

[0081] Exemplarily, as Figure 3 shown, the first via 31 is located on one side of the first slotted opening K1 close to the display area AA, and the second via 32 is located on one side of the first slotted opening K1 close to the bonding area V.

[0082] Exemplarily, the spacer layer 30 is a multi-layer structure, and at least one layer in the multi-layer structure is an insulating material. For example, one layer of the spacer layer 30 exposed by the first slotted opening K1 is an insulating material.

[0083] Exemplarily, the spacer layer 30 is an insulating material, for example, an inorganic non-metallic material.

[0084] As Figure 4 shown, the display panel 200 further includes a source-drain conductive layer 40 disposed between the spacer layer 30 and the planarization layer 20.

[0085] The source-drain conductive layer 40 includes a signal line L provided with a break Q, and the orthographic projection of the break Q on the substrate 10 overlaps with the orthographic projection of the first slot K1 on the substrate 10; the signal line L is divided into a first sub-signal line L1 and a second sub-signal line L2 by the break Q. The boundary of the first sub-signal line L1 at the break Q is closer to the display area AA relative to the first slot K1, and the boundary of the second sub-signal line L2 at the break Q is closer to the bonding area V relative to the first slot K1. That is, the signal line L is disconnected at the position corresponding to the first slot K1 to prevent the first slot K from exposing the signal line L.

[0086] The first sub-signal line L1 is electrically connected to the conductive connection pattern P through a first via 31, and the second sub-signal line L2 is electrically connected to the conductive connection pattern P through a second via 32. That is, the signal line L is disconnected at the position corresponding to the first slot K1, and the two disconnected parts are respectively electrically connected to the conductive connection pattern P located below the spacer layer 30. While realizing the conduction of the signal line L, the first slot K1 is prevented from exposing the signal line L, thereby solving the problem that in the process of forming the first slot K1, if the groove is dug too deep, it will damage the signal line L, and if the groove is not dug sufficiently, the material of the planarization layer 20 will remain at the first slot K1.

[0087] Exemplarily, as Figure 4 shown, the display panel 200 further includes a protective layer 50 disposed above the planarization layer 20, and the protective layer 50 may include a plurality of encapsulation layers.

[0088] Exemplarily, as Figure 2 and Figure 3 shown, the source-drain conductive layer 40 includes a plurality of signal lines L provided with breaks Q, and each signal line L is electrically connected to a conductive connection pattern P.

[0089] Exemplarily, the signal line L includes a first power supply line and / or a second power supply line. The first power supply line is configured to transmit a first voltage signal, and the second power supply line is configured to transmit a second voltage signal.

[0090] In the related art, as Figure 5 and Figure 6As shown, the source-drain conductive layer 40' is provided with a plurality of signal lines L'. The source-drain conductive layer 40' is located below the planarization layer 20'. During the process of etching the planarization film to form the first slot K1', over-etching easily damages the signal lines L' located below the first slot K'. Under-etching, on the other hand, easily leaves behind the material of the planarization layer 20' at the position of the first slot K1'. The material of the planarization layer 20' easily adsorbs water vapor. Therefore, the water vapor adsorbed from the outside will extend along the planarization layer 20' to the first slot K1'. Since there is residual material of the planarization layer 20' in the first slot K1', the intrusion path of the water vapor will not be interrupted by the first slot K1', but will instead extend through the residual material of the planarization layer 20' until it invades the display area AA, causing reliability problems in the display device 100 and affecting the service life of the display device 100.

[0091] In the above embodiments of the present application, by disconnecting the signal line L at the position corresponding to the first slot K1, and connecting the two disconnected parts thereof (i.e., the first sub-signal line L1 and the second sub-signal line L2) through the conductive connection pattern P located on the side of the spacer layer 30 away from the planarization layer 20, the signal line L is prevented from passing below the first slot K1. Thus, during the formation of the first slot K1, the material of the planarization layer 20 corresponding to the first slot K1 can be fully removed, avoiding the problem of water vapor invading the display area AA due to the residual material of the planarization layer 20 at the first slot K1. At the same time, the signal line L is protected from being damaged due to over-etching of the planarization layer 20, thereby solving the reliability problem of the display device 100 and extending its service life.

[0092] The display panel 200 provided by the present disclosure includes a plurality of conductive layers. In display panels 200 with different structures, the conductive layer where the conductive connection pattern P is located can be different, and the film layer structures of the corresponding spacer layers 30 are also different.

[0093] In some embodiments, as Figure 7 shown, the display panel 200 includes a plurality of pixel driving circuits disposed on the substrate 10, and each pixel driving circuit includes at least one thin film transistor (for example Figure 7The first transistor T1 to the fourth transistor T4 shown). The display panel 200 adopts LTPO (i.e., Low Temperature Polycrystalline Oxide, abbreviated as LTPO) technology, that is, each pixel driving circuit includes two types of thin film transistors, namely Low Temperature Poly-Silicon (LTPS) thin film transistors and Oxide thin film transistors. In this case, the display panel 200 has two types of active layers at the same time. Among them, the material of the active layer pattern of the LTPS thin film transistor is low temperature polycrystalline silicon, and the material of the active layer pattern of the oxide thin film transistor is oxide.

[0094] In an embodiment where the display panel 200 adopts LTPO technology, the display panel 200 further includes a bottom shielding layer 51, a buffer layer 52, a first active layer 53, a first gate insulating layer 54, a first gate conductive layer 55, a first interlayer dielectric layer 56, a second gate conductive layer 57, a second interlayer dielectric layer 58, a second active layer 59, a second gate insulating layer 60, a third gate conductive layer 61, and a third interlayer dielectric layer 62, which are arranged in a direction perpendicular to the substrate 10 and away from the substrate 10.

[0095] The bottom shielding layer 51 is provided on one side of the substrate 10.

[0096] Exemplarily, as Figure 7 shown, the bottom shielding layer 51 is provided with a bottom shielding pattern 51N, and the orthographic projection of the bottom shielding pattern 51N on the substrate 10 covers the orthographic projection of the first active layer 53 on the substrate 10. The bottom shielding pattern 51N can be used as a light shielding layer to reduce the influence of external light incident from one side of the substrate 10 on the first active layer 53. For example, the bottom shielding pattern 51N is Bottom Shield Metal (BSM).

[0097] The first active layer 53 is provided on the side of the bottom shielding layer 51 away from the substrate 10. Exemplarily, the first active layer 53 is made of low temperature polycrystalline silicon (LTPS) material.

[0098] The buffer layer 52 is disposed between the bottom shielding layer 51 and the first active layer 53.

[0099] The first gate conductive layer 55 is provided on the side of the first active layer 53 away from the substrate 10. The overlapping part of the first gate conductive layer 55 and the first active layer 53 respectively forms low temperature polycrystalline silicon thin film transistors. For example, it forms Figure 7 shown, the third transistor T3 and the fourth transistor T4. The first gate insulating layer 54 is disposed between the first active layer 53 and the first gate conductive layer 55.

[0100] The second gate conductive layer 57 is disposed on a side of the first gate conductive layer 55 away from the substrate 10. Exemplarily, as Figure 7 shown, the upper electrode Cst1 and the lower electrode Cst2 of the capacitor device Cst are respectively provided in the first gate conductive layer 55 and the second gate conductive layer 57. The first interlayer dielectric layer 56 is disposed between the first gate conductive layer 55 and the second gate conductive layer 57.

[0101] The second active layer 59 is disposed on a side of the second gate conductive layer 57 away from the substrate 10, and is electrically connected to the first active layer 53 through the first connection pattern M1. Exemplarily, the second active layer 59 is made of an oxide material. The overlapping portions of the second gate conductive layer 57 and the second active layer 59 respectively form oxide thin film transistors. For example, the Figure 7 shown first transistor T1 and second transistor T2 are formed. The second interlayer dielectric layer 58 is disposed between the second gate conductive layer 57 and the second active layer 59.

[0102] The third gate conductive layer 61 is disposed on a side of the second active layer 59 away from the substrate 10. The third gate conductive layer 61 and the second gate conductive layer 57 at least partially overlap, so that the oxide thin film transistor forms a double-gate structure. The third gate insulating layer 60 is disposed between the second active layer 59 and the third gate conductive layer 61.

[0103] Exemplarily, as Figure 7 shown, the third gate conductive layer 61 further includes a scan signal line Sc, and the scan signal line Sc is configured to transmit a scan signal.

[0104] The source-drain conductive layer 40 is disposed on a side of the third gate conductive layer 61 away from the substrate 10. The third interlayer dielectric layer 62 is disposed between the source-drain conductive layer 40 and the third gate conductive layer 61.

[0105] Exemplarily, in the display area AA, the display panel 200 further includes a light-emitting device layer EL disposed on a side of the source-drain conductive layer 40 away from the substrate 10. The planarization layer 20 is disposed between the source-drain conductive layer 40 and the light-emitting device layer EL.

[0106] Exemplarily, at least one thin film transistor in the pixel driving circuit is connected to the light-emitting device EL (not shown in the figure). Exemplarily, at least one thin film transistor in the pixel driving circuit is electrically connected to a conductive pattern in the source-drain conductive layer 40. For example Figure 7 shown, the fourth transistor T4 is electrically connected to the data line Data located in the source-drain conductive layer 40.

[0107] Exemplarily, the display panel 200 further includes a protective layer 50 disposed above the planarization layer 20. The protective layer 50 may include multiple encapsulation sub-layers. For example, the protective layer 50 may include a first encapsulation sub-layer, a second encapsulation sub-layer, and a third encapsulation sub-layer sequentially arranged along the thickness direction Z of the substrate 10 and away from the substrate 10. Exemplarily, the materials of the first encapsulation sub-layer and the third encapsulation sub-layer include inorganic materials, and the material of the second encapsulation sub-layer includes organic materials. The first encapsulation sub-layer and the third encapsulation sub-layer function to block water vapor and oxygen, while the second encapsulation sub-layer has certain flexibility and the function of absorbing water vapor, etc.

[0108] Based on the display panel 200 adopting LTPO technology, the conductive connection pattern P is disposed on the bottom shielding layer 51 and / or the third gate conductive layer 61.

[0109] By using the conductive layers (such as the bottom shielding layer 51 and the third gate conductive layer 61) of the above display panel 200 to set the conductive connection pattern P, it is possible to transfer the part of the signal line L corresponding to the first slot K1 to other film layers, avoiding the problem of water vapor intrusion into the display area AA caused by the residue of the planarization layer 20 material at the first slot K1 during the formation of the first slot K1; at the same time, the foregoing embodiments do not add new manufacturing processes and do not increase the thickness of the display panel 200.

[0110] In some embodiments, as Figure 8 shown, based on the display panel 200 adopting LTPO technology, the conductive connection pattern P is disposed on the bottom shielding layer 51.

[0111] On this basis, the spacer layer 30 includes at least one of a buffer layer 52, a first gate insulating layer 54, a first interlayer dielectric layer 56, a second interlayer dielectric layer 58, a second gate insulating layer 60, and a third interlayer dielectric layer 62, and the first via 31 and the second via 32 penetrate through the respective film layers included in the spacer layer 30.

[0112] The first sub-signal line L1 is electrically connected to the conductive connection pattern P disposed on the bottom shielding layer 51 through the first via 31, and the second sub-signal line L2 is electrically connected to the conductive connection pattern P disposed on the bottom shielding layer 51 through the second via 32.

[0113] By providing a conductive connection pattern P on the original film layer, i.e., the bottom shielding layer 51, the transfer line transmission at the position of the signal line L corresponding to the first slot K1 in the source-drain conductive layer 40 can be achieved without adding extra manufacturing processes and the thickness of the display panel 200. This avoids the direct contact between the first slot K1 and the signal line L. At this time, the first slot K1 contacts the third interlayer dielectric layer 62, and the third interlayer dielectric layer 62 does not need to transmit signals. Therefore, during the formation of the first slot K1, a certain damage can be caused to the third interlayer dielectric layer 62, so as to ensure that the planarization layer 20 material at the position of the first slot K1 is fully removed, avoiding the problem of water vapor intrusion into the display area AA due to the residue of the planarization layer 20 material, thereby improving the reliability problem of the display device 100 and extending its service life.

[0114] In some embodiments, such as Figure 9 shown, the conductive connection pattern P is provided on the third gate conductive layer 61.

[0115] On this basis, the spacer layer 30 includes the third interlayer dielectric layer 62, and the first via 31 and the second via 32 penetrate through the third interlayer dielectric layer 62.

[0116] The first sub-signal line L1 is electrically connected to the conductive connection pattern P provided on the third gate conductive layer 61 through the first via 31, and the second sub-signal line L2 is electrically connected to the conductive connection pattern P provided on the third gate conductive layer 61 through the second via 32.

[0117] By providing a conductive connection pattern P on the original film layer, i.e., the third gate conductive layer 61, the transfer line transmission at the position of the signal line L corresponding to the first slot K1 in the source-drain conductive layer 40 can be achieved without adding extra manufacturing processes and the thickness of the display panel 200. This avoids the direct contact between the first slot K1 and the signal line L. At this time, the first slot K1 contacts the third interlayer dielectric layer 62, and the third interlayer dielectric layer 62 does not need to transmit signals. Therefore, during the formation of the first slot K1, a certain damage can be caused to the third interlayer dielectric layer 62, so as to ensure that the planarization layer 20 material at the position of the first slot K1 is fully removed, avoiding the problem of water vapor intrusion into the display area AA due to the residue of the planarization layer 20 material, thereby improving the reliability problem of the display device 100 and extending its service life.

[0118] In some embodiments, such as Figure 10 shown, the conductive connection pattern P includes a first sub-conductive connection pattern P1 and a second sub-conductive connection pattern P2. The first sub-conductive connection pattern P1 is provided on the bottom shielding layer 51, and the second sub-conductive connection pattern P2 is provided on the third gate conductive layer 62.

[0119] On this basis, the spacer layer 30 includes a third interlayer dielectric layer 62, and also includes at least one of a buffer layer 52, a first gate insulating layer 54, a first interlayer dielectric layer 56, a second interlayer dielectric layer 58, and a second gate insulating layer 60.

[0120] The first via 31 includes a first sub-via 311 and a second sub-via 312, the second via 32 includes a third sub-via 321 and a fourth sub-via 322. The first sub-via 311 and the third sub-via 321 penetrate through each film layer included in the spacer layer 30, and the second sub-via 312 and the fourth sub-via 322 penetrate through the third interlayer dielectric layer 62.

[0121] The first sub-signal line L1 is electrically connected to the first sub-conductive connection pattern P1 through the first sub-via 311, and is electrically connected to the second sub-conductive connection pattern P2 through the second sub-via 312; the second sub-signal line L2 is electrically connected to the first sub-conductive connection pattern P1 through the third sub-via 321, and is electrically connected to the second sub-conductive connection pattern P2 through the fourth sub-via 322.

[0122] That is, the first sub-conductive connection pattern P1 and the second sub-conductive connection pattern P2 are connected in parallel between the signal lines L.

[0123] By providing the conductive connection pattern P on the original film layers (the bottom shielding layer 51 and the third gate conductive layer 61), the transfer line transmission of the signal line L at the position corresponding to the first slot K1 in the source-drain conductive layer 40 can be realized without adding extra manufacturing processes and the thickness of the display panel 200, thereby solving the problem of water vapor intrusion into the display area AA and improving the reliability problem of the display device 100; in addition, the signal line L is electrically connected to the first sub-conductive connection pattern P1 and the second sub-conductive connection pattern P2 at the same time, effectively improving the impedance problem generated during the transfer line process of the signal line L, and to a certain extent controlling the impedance of the signal line L after the transfer line to be closer to the impedance before the transfer line, avoiding the influence of the too large resistance value of the first sub-conductive connection pattern P1 or the second sub-conductive connection pattern P2 on the signal transmission of the signal line L.

[0124] In some embodiments, as Figure 10 shown, along the second direction Y, both ends of the first conductive connection pattern P1 extend beyond the boundaries of both ends of the second conductive connection pattern P2, and the second sub-via 312 is closer to the first slot K1 than the first sub-via 311, and the fourth sub-via 322 is closer to the first slot K1 than the third sub-via 321. This design facilitates the electrical connection of the signal line L to the first conductive connection pattern P1 and the second conductive connection pattern P2 respectively, avoiding crosstalk.

[0125] Exemplarily, both the first conductive connection pattern P1 and the second conductive connection pattern P2 extend along the second direction Y. The widths of the first conductive connection pattern P1 and the second conductive connection pattern P2 along the first direction X are substantially equal, and the length of the first conductive connection pattern P1 along the second direction Y is greater than the length of the second conductive connection pattern P2 along the second direction Y.

[0126] In some embodiments, as Figure 11 shown, the display panel 200 includes a plurality of pixel driving circuits disposed on the substrate 10, and each pixel driving circuit includes at least one thin film transistor (e.g., Figure 11 the transistor T shown). The display panel 200 adopts low temperature poly-silicon (LTPS) technology, that is, each pixel driving circuit includes an LTPS thin film transistor, that is, the material of the active layer pattern of the thin film transistor of the display panel 200 is low temperature poly-silicon.

[0127] In the embodiment where the display panel 200 adopts LTPS technology, the display panel 200 further includes: a bottom shielding layer 51, a buffer layer 52, a first active layer 53, a first gate insulating layer 54, a first gate conductive layer 55, a first interlayer dielectric layer 56, a second gate conductive layer 57, and a second interlayer dielectric layer 58, which are disposed along a direction perpendicular to the substrate 10 and away from the substrate 10.

[0128] The bottom shielding layer 51 is disposed on one side of the substrate 10.

[0129] Exemplarily, as Figure 11 shown, the bottom shielding layer 51 is provided with a bottom shielding pattern 51N, and the orthographic projection of the bottom shielding pattern 51N on the substrate 10 covers the orthographic projection of the first active layer 53 on the substrate 10. The bottom shielding pattern 51N can serve as a light shielding layer to reduce the influence of external light incident from one side of the substrate 10 on the first active layer 53 and improve the performance of the first active layer 53. For example, the bottom shielding pattern 51N is a bottom shield metal (BSM).

[0130] The first active layer 53 is disposed on the side of the buffer layer 52 away from the substrate 10. Exemplarily, the first active layer 53 is made of low temperature poly-silicon (LTPS) material. The buffer layer 52 is disposed between the bottom shielding layer 51 and the first active layer 53.

[0131] The first gate conductive layer 55 is disposed on the side of the first active layer 53 away from the substrate 10. The overlapping portion of the first gate conductive layer 55 and the first active layer 53 forms a low temperature poly-silicon thin film transistor. The first gate insulating layer 54 is disposed between the first active layer 53 and the first gate conductive layer 55.

[0132] The second gate conductive layer 57 is disposed on a side of the first gate conductive layer 55 away from the substrate 10. Exemplarily, as Figure 11 shown, the upper electrode Cst1 and the lower electrode Cst2 of the capacitor device Cst are respectively provided in the first gate conductive layer 55 and the second gate conductive layer 57. The first interlayer dielectric layer 56 is disposed between the first gate conductive layer 55 and the second gate conductive layer 57.

[0133] The source-drain conductive layer 40 is disposed on a side of the second gate conductive layer 57 away from the substrate 10. The second interlayer dielectric layer 58 is disposed between the source-drain conductive layer 40 and the second gate conductive layer 57.

[0134] Exemplarily, the source-drain conductive layer 40 is provided with a second connection pattern M2, and the second connection pattern M2 is configured to transmit the signal of the source or drain of the thin film transistor to the outside.

[0135] Exemplarily, in the display area AA, the display panel 200 further includes a light-emitting device layer EL disposed on a side of the source-drain conductive layer 40 away from the substrate 10. The planarization layer 20 is disposed between the source-drain conductive layer 40 and the light-emitting device layer EL.

[0136] Exemplarily, the display panel 200 further includes a protective layer 50 disposed above the planarization layer 20. The protective layer 50 may include multiple encapsulation sub-layers. For example, the protective layer 50 may include a first encapsulation sub-layer, a second encapsulation sub-layer, and a third encapsulation sub-layer sequentially disposed along the thickness direction Z of the substrate 10 and away from the substrate 10. Exemplarily, the materials of the first encapsulation sub-layer and the third encapsulation sub-layer include inorganic materials, and the material of the second encapsulation layer includes organic materials. The first encapsulation sub-layer and the third encapsulation sub-layer have the function of blocking moisture and oxygen, while the second encapsulation sub-layer has certain flexibility and the function of absorbing moisture, etc.

[0137] Based on the display panel 200 adopting the LTPS technology, the conductive connection pattern P is disposed on the bottom shielding layer 51.

[0138] On this basis, as Figure 12 shown, the spacer layer 30 includes at least one of a buffer layer 52, a first gate insulating layer 54, a first interlayer dielectric layer 56, and a second interlayer dielectric layer 58. The first via 31 and the second via 32 penetrate through each film layer included in the spacer layer 30.

[0139] The first sub-signal line L1 is electrically connected to the conductive connection pattern P disposed on the bottom shielding layer 51 through the first via 31, and the second sub-signal line L2 is electrically connected to the conductive connection pattern P disposed on the bottom shielding layer 51 through the second via 32.

[0140] By using the conductive layer (such as the bottom shielding layer 51) of the above-mentioned display panel 200 to set the conductive connection pattern P, the part of the signal line L corresponding to the first slotted groove K1 can be transferred to other film layers, avoiding the problem that the material of the planarization layer 20 remains at the first slotted groove K1 during the formation of the first slotted groove K1, which may cause water vapor to invade the display area AA; at the same time, the foregoing embodiments do not add new manufacturing processes and do not increase the thickness of the display panel 200.

[0141] In some embodiments, as Figure 13 shown, the first slotted groove K1 includes a first sub-slotted groove K11 and a second sub-slotted groove K12. Both the first sub-slotted groove K11 and the second sub-slotted groove K12 extend along the first direction X and are arranged side by side along the second direction Y. The first sub-slotted groove K11 is closer to the display area AA than the second sub-slotted groove K12. By opening a plurality of slotted grooves (such as the first sub-slotted groove K11 and the second sub-slotted groove K12) on the planarization layer 20, the probability of water vapor invading the display area AA through the planarization layer 20 can be further reduced, and the reliability of the display device 200 can be further optimized.

[0142] On this basis, as Figure 14 shown, the orthographic projection of the conductive connection pattern P on the substrate 10 overlaps with the orthographic projections of the first sub-slotted groove K11 and the second sub-slotted groove K12 on the substrate 10. Along the second direction Y, the end of the conductive connection pattern P close to the display area AA extends beyond the side boundary of the first sub-slotted groove K11 close to the display area AA, and the end of the conductive connection pattern P close to the bonding area V extends beyond the side boundary of the second sub-slotted groove K12 close to the bonding area V. That is, the conductive connection pattern P straddles the first sub-slotted groove K11 and the second sub-slotted groove K12 along the second direction.

[0143] Exemplarily, Figure 13 and Figure 14 the foregoing embodiments can be applied to the display panel 200 using LTPO technology or the display panel 200 using LTPS technology, that is Figure 13 and Figure 14 the foregoing embodiments can be combined with Figures 7 to 12 the corresponding embodiments.

[0144] In some embodiments, as Figure 13 shown, the display panel 200 further includes a peripheral area S disposed around the display area AA, and the bonding area V is disposed on a side of the peripheral area S away from the display area AA.

[0145] Among them, the planarization layer 20 further includes: a second slotted groove K2, provided in the peripheral area S, and the second slotted groove K2 communicates with the first slotted groove K1 to form a ring surrounding the display area AA. That is, the planarization layer 20 includes a ring-shaped groove (formed by the first slotted groove K1 and the second slotted groove K2) provided around the display area AA, which can interrupt the path of water vapor invading the display area AA along the planarization layer 20 from different orientations of the display area AA.

[0146] Exemplarily, as Figure 13 shown, the second slotted groove K2 includes a third sub-slotted groove K21 and a fourth sub-slotted groove K22. Among them, the third sub-slotted groove K21 communicates with the first sub-slotted groove K11 to form a ring surrounding the display area AA, and the fourth sub-slotted groove K22 communicates with the second sub-slotted groove K12 to form a ring surrounding the display area AA. That is, two ring-shaped grooves are formed. The ring-shaped grooves can interrupt the path of water vapor invading the display area AA along the planarization layer 20 from different orientations of the display area AA, and the two ring-shaped grooves can further strengthen the interruption effect on the path of water vapor invading the display area AA.

[0147] In some embodiments, as Figure 13 shown, the display panel 200 further includes a first barrier dam D1 and a second barrier dam D2, provided in the peripheral area S and surrounding the display area AA. The first barrier dam D1 and the second barrier dam D2 are arranged at intervals, and the first barrier dam D1 is closer to the display area AA than the second barrier dam D2. In the peripheral area S close to the bonding area V, the first barrier dam D1 is arranged between the first sub-slotted groove K11 and the second sub-slotted groove K12, and the second barrier dam D2 is arranged on the side of the second sub-slotted groove K12 close to the bonding area V.

[0148] During the preparation process of the display panel 200, ink is sprayed on the display side of the display panel 200 by ink-jet printing (abbreviated as IJP) technology, and an organic encapsulation film layer (such as the second encapsulation layer) of the protective layer 50 is formed after the ink is dried. The first barrier dam D1 and the second barrier dam D2 are arranged around the four sides of the display area AA, which can block the flow of ink to prevent ink overflow.

[0149] In some embodiments, as Figure 15 shown, both the first barrier dam D1 and the second barrier dam D2 include a plurality of sub-layers stacked along the thickness direction Z of the substrate 10, and at least one layer of the plurality of sub-layers is located in the planarization layer 20.

[0150] In an alternative embodiment, as Figure 15As shown, the source-drain conductive layer 40 includes a first source-drain conductive layer 41 and a second source-drain conductive layer 42 that are sequentially arranged along the thickness direction Z of the substrate 10. Correspondingly, the planarization layer 20 includes a first sub-planarization layer 21 and a second sub-planarization layer 22. The first sub-planarization layer 21 is disposed between the first source-drain conductive layer 41 and the second source-drain conductive layer 42, and the second sub-planarization layer 22 is disposed on the side of the second source-drain conductive layer 42 away from the substrate 10.

[0151] The second sub-planarization layer 22 is provided with a first sub-groove K11 and a second sub-groove K12.

[0152] Exemplarily, the first source-drain conductive layer 41 and the second source-drain conductive layer 42 are electrically connected. The first source-drain conductive layer 41 is electrically connected to the conductive connection pattern P through a first via 31 and a second via 32.

[0153] Exemplarily, at least one layer of the multiple sub-layers is located in the second sub-planarization layer 22. For example, at least one layer of the first barrier D1 is located in the second sub-planarization layer 22, and at least one layer of the second barrier D2 is located in the second sub-planarization layer 22.

[0154] Exemplarily, at least one layer of the multiple sub-layers is located in the first sub-planarization layer 21. For example, at least one layer of the second barrier D2 is located in the first sub-planarization layer 21.

[0155] Exemplarily, along the thickness direction Z of the substrate 10, the height of the second barrier D2 is greater than the height of the first barrier D1. That is, the barrier relatively farther away from the display area AA has a higher height, thereby forming a more effective barrier to the ink.

[0156] Exemplarily, the light-emitting device layer EL of the display panel 200 further includes a pixel definition layer PDL. The pixel definition layer PDL has a plurality of openings, and the openings in the display area AA correspond one-to-one to the positions of the sub-pixels, so as to define the light-emitting regions of the light-emitting devices corresponding to each sub-pixel.

[0157] At least one layer of the multiple sub-layers is located in the pixel definition layer PDL. For example, both the first barrier D1 and the second barrier D2 include the pixel definition layer PDL, so that the heights of the first barrier D1 and the second barrier D2 along the thickness direction Z of the substrate 10 can be increased, and the barrier effect of the first barrier D1 and the second barrier D2 on the ink can be improved.

[0158] Exemplarily, at least one layer of the multiple sub-layers is located in the first source-drain conductive layer 41 and / or the second source-drain conductive layer 42.

[0159] Exemplarily, the second via 32 is disposed at the position where the second barrier D2 is located, or the second via 32 is disposed on the side of the second barrier D2 close to the bonding area V.

[0160] In some embodiments, as Figure 16 shown, the source-drain conductive layer 40 includes two sets of signal lines, each set including at least one signal line L, and the two sets of signal lines are respectively located on opposite sides of the median line Md (as Figure 13 shown) extending along the second direction Y of the bonding region V; each signal line L in each set of signal lines is provided with a break Q, and a conductive connection pattern P is correspondingly provided at the break Q of the signal line L, and the signal line L is electrically connected to the corresponding conductive connection pattern P.

[0161] Exemplarily, as Figure 16 shown, the signal lines L in the source-drain conductive layer 40 can transmit different signals respectively. For example, the signal lines L include a first power supply line and / or a second power supply line, the first power supply line is configured to transmit a first voltage signal, and the second power supply line is configured to transmit a second voltage signal.

[0162] Exemplarily, the first voltage signal is a high-level voltage and the second voltage signal is a low-level voltage.

[0163] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that, Comprising: A display area and a bonding area located on one side of the display area; The display panel comprises: A substrate; A planarization layer disposed on the substrate; the planarization layer is provided with a first slotted opening penetrating through the planarization layer, the first slotted opening is located between the display area and the bonding area and extends along a first direction; the first direction is the extending direction of the side of the display area where the bonding area is located; A conductive connection pattern disposed between the substrate and the planarization layer; the orthographic projection of the conductive connection pattern on the substrate overlaps with the orthographic projection of the first slotted opening on the substrate, and both ends of the conductive connection pattern extend out of both side boundaries of the first slotted opening along a second direction; the second direction is perpendicular to the first direction; A spacer layer disposed between the substrate and the planarization layer and covering the conductive connection pattern; the spacer layer is provided with a first via hole and a second via hole, and the first via hole and the second via hole are respectively located on both sides of the first slotted opening in the second direction; A source-drain conductive layer disposed between the spacer layer and the planarization layer; the source-drain conductive layer includes a signal line with a break, and the orthographic projection of the break on the substrate overlaps with the orthographic projection of the first slotted opening on the substrate; the signal line is divided into a first sub-signal line and a second sub-signal line by the break, the boundary of the first sub-signal line at the break is closer to the display area relative to the first slotted opening, and the boundary of the second sub-signal line at the break is closer to the bonding area relative to the first slotted opening; the first sub-signal line is electrically connected to the conductive connection pattern through the first via hole, and the second sub-signal line is electrically connected to the conductive connection pattern through the second via hole; The source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer sequentially arranged along the thickness direction of the substrate; the planarization layer includes a first sub-planarization layer and a second sub-planarization layer; the first sub-planarization layer is located between the first source-drain conductive layer and the second source-drain conductive layer, and the second sub-planarization layer is located on the side of the second source-drain conductive layer away from the substrate; the first slotted opening includes a first sub-slotted opening and a second sub-slotted opening, the first sub-slotted opening and the second sub-slotted opening extend along the first direction and are arranged side by side along the second direction, and the first sub-slotted opening is closer to the display area relative to the second sub-slotted opening; the orthographic projection of the conductive connection pattern on the substrate overlaps with the orthographic projections of the first sub-slotted opening and the second sub-slotted opening on the substrate; The display panel further includes a peripheral area disposed around the display area, and the bonding area is disposed on the side of the peripheral area away from the display area; The display panel further comprises: A first dam and a second dam disposed in the peripheral area and surrounding the display area; the first dam and the second dam are spaced apart, and the first dam is closer to the display area relative to the second dam; in the peripheral area close to the bonding area, the first dam is disposed between the first sub-slotted opening and the second sub-slotted opening, and the second dam is disposed on the side of the second sub-slotted opening close to the bonding area; Both the first blocking dam and the second blocking dam include a plurality of sub-layers stacked in the thickness direction of the substrate. Any one of the plurality of sub-layers of the first blocking dam is not located in the first sub-flattening layer, and at least one of the plurality of sub-layers of the second blocking dam is located in the first sub-flattening layer.

2. The display panel according to claim 1, characterized in that, Further included are: A bottom shielding layer, a buffer layer, a first active layer, a first gate insulating layer, a first gate conductive layer, a first interlayer dielectric layer, a second gate conductive layer, a second interlayer dielectric layer, a second active layer, a second gate insulating layer, a third gate conductive layer, and a third interlayer dielectric layer disposed in a direction perpendicular to the substrate and away from the substrate; The conductive connection pattern is disposed on the bottom shielding layer and / or the third gate conductive layer.

3. The display panel according to claim 2, characterized in that, The conductive connection pattern is disposed on the bottom shielding layer; The spacer layer includes at least one of the buffer layer, the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second gate insulating layer, and the third interlayer dielectric layer. The first via hole and the second via hole penetrate through each film layer included in the spacer layer.

4. The display panel according to claim 2, characterized in that, The conductive connection pattern is disposed on the third gate conductive layer; The spacer layer includes the third interlayer dielectric layer, and the first via hole and the second via hole penetrate through the third interlayer dielectric layer.

5. The display panel according to claim 2, characterized in that, The conductive connection pattern includes a first sub-conductive connection pattern and a second sub-conductive connection pattern. The first sub-conductive connection pattern is disposed on the bottom shielding layer, and the second sub-conductive connection pattern is disposed on the third gate conductive layer; The spacer layer includes the third interlayer dielectric layer and at least one of the buffer layer, the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, and the second gate insulating layer; The first via hole includes a first sub-via hole and a second sub-via hole, and the second via hole includes a third sub-via hole and a fourth sub-via hole. The first sub-via hole and the third sub-via hole penetrate through each film layer included in the spacer layer, and the second sub-via hole and the fourth sub-via hole penetrate through the third interlayer dielectric layer; The first sub-signal line is electrically connected to the first sub-conductive connection pattern through the first sub-via hole and is electrically connected to the second sub-conductive connection pattern through the second sub-via hole; the second sub-signal line is electrically connected to the first sub-conductive connection pattern through the third sub-via hole and is electrically connected to the second sub-conductive connection pattern through the fourth sub-via hole.

6. The display panel according to claim 5, characterized in that, In a second direction, both ends of the first sub-conductive connection pattern extend beyond the two end boundaries of the second sub-conductive connection pattern, and the second sub-via hole is closer to the first slot than the first sub-via hole, and the fourth sub-via hole is closer to the first slot than the third sub-via hole.

7. The display panel according to claim 1, characterized in that, Further included are: A bottom shielding layer, a buffer layer, a first active layer, a first gate insulating layer, a first gate conductive layer, a first interlayer dielectric layer, a second gate conductive layer, and a second interlayer dielectric layer disposed in a direction perpendicular to the substrate and away from the substrate; The conductive connection pattern is disposed on the bottom shielding layer; The spacer layer includes at least one of the buffer layer, the first gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer, and the first via hole and the second via hole penetrate through each film layer included in the spacer layer.

8. The display panel according to any one of claims 2 to 7, characterized in that, The bottom shielding layer further includes a bottom shielding pattern, and a positive projection of the bottom shielding pattern on the substrate covers a positive projection of the first active layer on the substrate.

9. The display panel according to any one of claims 2 to 6, characterized in that, The third gate conductive layer further includes a scan signal line located thereon, and the scan signal line is configured to transmit a scan signal.

10. The display panel according to any one of claims 1 to 7, characterized in that, Along the second direction, one end of the conductive connection pattern close to the display area extends beyond a side boundary of the first sub-groove close to the display area, and one end of the conductive connection pattern close to the bonding area extends beyond a side boundary of the second sub-groove close to the bonding area.

11. The display panel according to any one of claims 1 to 7, characterized in that, It further includes a peripheral area disposed around the display area, and a bonding area is provided on a side of the peripheral area away from the display area; The planarization layer further includes: a second groove disposed in the peripheral area, and the second groove communicates with the first groove to form a ring surrounding the display area.

12. The display panel according to any one of claims 1 to 7, characterized in that, The signal line includes a first power supply line and / or a second power supply line, the first power supply line is configured to transmit a first voltage signal, and the second power supply line is configured to transmit a second voltage signal.

13. The display panel according to any one of claims 1 to 7, characterized in that, The source-drain conductive layer includes two groups of signal lines, each group includes at least one signal line, and the two groups of signal lines are respectively located on opposite sides of a midline extending in the second direction in the bonding area; Each signal line in each group of signal lines is provided with a break, a conductive connection pattern is correspondingly provided at the break of the signal line, and the signal line is electrically connected to the corresponding conductive connection pattern.

14. A display device, characterized in that, It includes a display panel according to any one of claims 1 to 13.

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