Error correction memory device with fast data access

Abstract

This application is directed to an error correction memory device with fast data access. For example, during a read operation, the memory device can be configured to output data indicated by the read operation in parallel with performing an error correction operation. If the memory device detects an error, the memory device can indicate the error to a host device and, in some cases, output corrected data to the host device. During a write operation, the memory device can store error detection or correction information associated with data to be stored at the memory device. The memory device can, in some cases, store error detection or correction information generated by the host device.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT / US2020 / 030097, filed April 27, 2020, entitled "Error Correction Memory Device with Fast Data Access," filed by Schaefer et al., which claims U.S. Patent Application No. 16 / 858,281, filed April 24, 2020, entitled "Error Correction Memory Device with Fast Data Access," and Schaefer et al., filed May 23, 2019, entitled "Error Correction Memory Device with Fast Data Access." The priority of U.S. Provisional Patent Application No. 62 / 851,800, entitled “ACCESS”, is assigned to the assignee by reference, and each of these documents is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to an error-correcting memory device with fast data access. Background Technology

[0004] The following generally relates to a system comprising at least one memory device, and more specifically to an error-correcting memory device with fast data access.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states, typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write the state into the memory device or program the state.

[0006] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile memories such as FeRAM can maintain their stored logic state for a long time, even without external power. Volatile memory devices such as DRAM may lose their stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memories but can also have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

[0007] In some cases, data stored in a memory device may become corrupted. Some memory devices can be configured to internally correct this data corruption or error (e.g., data corruption), thereby recovering the data stored before the corruption. These memory devices may be referred to as Error Correction Code (ECC) memory or memory with on-die or in-line ECC. Improvements to the ECC functionality within ECC memory devices may be required. Generally, improvements to memory devices may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data integrity, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the Invention

[0008] Describe a method. The method may include: receiving a read command from a host device at a memory device comprising a memory array; reading first data from the memory array based at least in part on the read command; performing an error correction operation on the first data to obtain second data and an indicator of an error in the first data; and outputting the first data and the indicator of the error to the host device in parallel with at least a portion of performing the error correction operation.

[0009] Describe an apparatus. The apparatus may include: an array of memory cells, each including a capacitive storage element; an interface configured to receive a read command from a host device; a first circuit configured to read first data from the array based at least in part on the read command; and a second circuit coupled to the first circuit and configured to perform an error correction operation on the first data to obtain second data and an indicator of an error in the first data, wherein the interface is configured to transmit the first data and the indicator of the error in the first data to the host device.

[0010] Describe a method. The method may include: receiving a write command from a host device at a memory device comprising a memory array; receiving first data and error detection or correction information associated with the write command from the host device; performing an error correction operation on the first data using the received error detection or correction information to obtain second data; and storing the second data and the received error detection or correction information at the memory array, at least in part, based on the write command. Attached Figure Description

[0011] Figure 1 Examples of systems supporting error-correcting memory devices with fast data access, based on the examples disclosed herein, are shown.

[0012] Figure 2 Examples of memory dies supporting error-correcting memory devices with fast data access are shown, based on the examples disclosed herein.

[0013] Figures 3 to 5 Examples of systems supporting error-correcting memory devices with fast data access, as disclosed herein, are shown.

[0014] Figure 6 and 7 Examples of process flows supporting error-correcting memory devices with fast data access as disclosed herein are shown.

[0015] Figure 8 A block diagram of an error-correcting memory device with fast data access, as disclosed herein, is shown.

[0016] Figures 9 to 11 The flowchart illustrates one or more methods supporting error-correcting memory devices with fast data access as disclosed herein. Detailed Implementation

[0017] Memory devices can operate as part of electronic devices under various conditions, such as personal computers, wireless communication devices, servers, Internet of Things (IoT) devices, electronic components of motor vehicles, and so on. In some cases, memory devices supporting certain implementations (e.g., motor vehicles, in some cases having autonomous or semi-autonomous driving capabilities) may be subject to increased reliability constraints. Therefore, memory devices (e.g., DRAM) used in some applications are expected to operate with reliability subject to relatively high industry standards or specifications (e.g., higher reliability constraints).

[0018] In some cases, data stored in a memory device may be corrupted (e.g., due to leakage, parasitic coupling, or electromagnetic interference (EMI)). Data corruption can refer to an unintentional change in the logical value of data stored in the memory device, and therefore can refer to an unintended change in the logical value stored by one or more memory cells (e.g., from logic one (1) to logic zero (0), or vice versa). For example, a memory device may perform a read operation to determine the logical value of data stored in the memory device, and one or more of the memory cells may have been corrupted. Deviations between the stored logical value of a bit and its initial and expected logical values ​​may be called errors, bit errors, or data errors, and may be caused by corruption. Some memory devices may be configured to internally detect and, in at least some cases, correct (repair) such data corruption or errors, thereby recovering data stored prior to corruption. This error detection and correction may rely on one or more error correction codes (ECCs) (e.g., block codes, convolutional codes, Hamming codes, low-density parity-check codes, turbine codes, polar codes), and related processes and operations. These technologies may be referred to as ECC processes, ECC operations, ECC technologies, or in some cases simply as ECC or ECC. Error detection and correction of data previously stored in the memory device within the memory device is generally referred to as internal or on-die ECC (whether in a single-die or multi-die memory device), and memory devices that support internal or on-die ECC may be called ECC memory or on-die ECC memory.

[0019] Alternatively, data transmitted from the host device to the memory device (e.g., during a write operation) may be corrupted in some cases (e.g., due to parasitic effects, electromagnetic interference, or inter-symbol interference). In some examples, if corruption occurs during a write operation, on-die ECC may not detect the error. In addition to data from the host device (e.g., during a write operation), the memory device may also be configured to correct and / or detect these errors by relying on transmitted error detection or correction information. In addition to data transmitted to the host device (e.g., during a read operation), the memory device may also generate and transmit error detection or correction information. Error detection and correction of data transmitted between the memory device and the host device may be referred to as link ECC.

[0020] Alternatively, the host device may generate ECC information and provide additional bits containing the ECC information within the data (e.g., during a write operation). The host device may then inspect the data and ECC information (e.g., during a read operation). Using additional data bits to carry host-generated ECC information is referred to as inline ECC. Inline ECC can check for channel errors (e.g., errors occurring at the channel between the memory device and the host device) and errors generated within the memory device (e.g., data corruption at the memory device). In some cases, inline ECC may include error correction and detection at a higher granularity than on-die ECC (e.g., more ECC information provides greater error correction and detection capabilities).

[0021] In some cases, performing error detection and correction operations within a memory device (e.g., on-die ECC) can increase the latency of access operations (e.g., read operations, write operations). For example, error detection and correction operations may take several nanoseconds, and corrected data may not be available until the internal on-die error detection and correction operations are complete. It may be necessary to reduce the latency associated with access operations. In one instance, the memory device may bypass internal error detection and correction operations and perform access operations without using or generating corresponding error detection or correction information. However, suppressing the use of error detection or correction may reduce the reliability of data bits read from the memory device array.

[0022] This paper describes a technique for an error-correcting memory device with fast data access. The memory device can perform internal error detection and correction operations in parallel while outputting data that bypasses these operations. Therefore, internal error detection and correction operations can be performed on the data to increase reliability, while the latency of access operations (e.g., read, write) is unaffected by the internal error detection and correction operations. If an error is detected or corrected, the memory device can output an indication of the detected error. In some cases, the memory device can output corrected data retrospectively (e.g., with or without an indication of a detected error). During a write operation, the memory device can store data and some corresponding error correction and detection information generated by the host device. Here, the latency introduced by performing error detection and correction operations at the memory device can be bypassed while still maintaining the reliability associated with storing the error detection or correction information.

[0023] First, as referenced Figure 1-5 The features of this disclosure are described in the context of the memory system and memory die described herein. Reference is then made to... Figure 6 and 7 The features of this disclosure are described in the context of a process flow. Further by Figure 8-11The device diagrams and flowcharts relating to configurable error correction modes are shown and described with reference to the device diagrams and flowcharts. These and other features of this disclosure are described.

[0024] Figure 1 An example of a system 100 utilizing one or more memory devices according to the examples disclosed herein is shown. System 100 may include an external memory controller 105, a memory device 110, and multiple channels 115 coupling the external memory controller 105 to the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0025] System 100 may include aspects of electronic devices such as computing devices, mobile computing devices, wireless devices, or graphics processing devices. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. Memory device 110 may be a component of the system configured to store data of one or more other components of system 100. In some instances, system 100 is configured for bidirectional wireless communication with other systems or devices using a base station or access point. In some instances, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0026] At least some parts of system 100 may be instances of host devices. This host device may be an instance of a device that uses memory to execute processes, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, or some other fixed or portable electronic device. In some cases, a host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some instances, system 100 is a graphics card.

[0027] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / spaces that system 100 may use or reference. Memory device 110 may be configurable to work with at least one or more different types of system 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packages of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0028] Memory device 110 may be configured to store data of components of system 100. In some cases, memory device 110 may act as a slave device of system 100 (e.g., responding to and executing commands provided by system 100 via external memory controller 105). These commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) supporting the desired or specified capacity for data storage. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0029] System 100 may further include processor 120, basic input / output system (BIOS) component 125, one or more peripheral components 130, and input / output (I / O) controller 135. The components of system 100 can be electrically communicated with each other via bus 140.

[0030] Processor 120 may be configured as at least some part of control system 100. Processor 120 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these types of components. In these cases, processor 120 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances exist.

[0031] BIOS component 125 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100. BIOS component 125 may also manage data flow between processor 120 and various components of system 100, such as peripheral components 130, I / O controllers 135, etc. BIOS component 125 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0032] Peripheral component 130 can be any input or output device, or an interface to such a device, which can be integrated into or with system 100. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, Universal Serial Bus (USB) controller, serial or parallel port, or peripheral card slot, such as Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 can be any other component that a person skilled in the art would understand as a peripheral device.

[0033] I / O controller 135 manages data communication between processor 120 and peripheral components 130, input devices 145, or output devices 150. I / O controller 135 can manage peripheral devices not integrated into system 100 or not integrated with said system. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0034] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface, or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0035] Output 150 may represent a device or signal external to system 100, configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, audio speaker, printing apparatus, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0036] The components of system 100 may consist of general-purpose or special-purpose circuit systems designed to perform their functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, gates, amplifiers, or other active or passive elements configured to perform the functions described herein.

[0037] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., a grid), wherein each memory cell is configured to store at least one bit of digital data. Reference Figure 2 The characteristics of memory array 170 and / or memory cells are described in more detail.

[0038] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array. For example, a 2D memory device may comprise a single memory die 160. A 3D memory device may comprise two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked vertically and close to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, hierarchy, layer, or die. A 3D memory device may comprise any number of stacked memory dies 160-N (e.g., dual-block, triple-block, quad-block, quintuple-block, hexa-block, hepta-block, octa-block). Compared to a single 2D memory device, this can increase the number of memory cells that can be positioned on the substrate, thereby reducing manufacturing costs or improving the performance of the memory array, or both. In some 3D memory devices, different stacks may share at least one common access line so that some stacks may share at least one of word lines, digital lines and / or board lines.

[0039] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Thus, device memory controller 155 may include hardware, firmware, and software enabling memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information concerning memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, the one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command instructing memory device 110 to store specific data on behalf of a component of system 100 (e.g., processor 120); or memory device 110 may receive a read command instructing memory device 110 to provide specific data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, the device memory controller 155 may be combined with the local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating signals and transmitting signals to the external memory controller 105, logic, amplifiers, filters, etc.

[0040] A local memory controller 165 (e.g., locally on memory die 160) may be configured to control the operation of memory die 160. Furthermore, the local memory controller 165 may be configured to communicate with device memory controller 155 (e.g., to receive and transmit data and / or commands). The local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110, as described herein. In some cases, memory device 110 may not include device memory controller 155, and either local memory controller 165 or external memory controller 105 may perform the various functions described herein. Therefore, local memory controller 165 may be configured to communicate with device memory controller 155, communicate with other local memory controllers 165, or communicate directly with external memory controller 105 or processor 120.

[0041] External memory controller 105 may be configured to enable communication of information, data, and / or commands between components of system 100 (e.g., processor 120) and memory device 110. External memory controller 105 may act as a liaison between components of system 100 and memory device 110, allowing components of system 100 to communicate without needing to know the operational details of the memory device. Components of system 100 may present requests (e.g., read or write commands) to external memory controller 105 that external memory controller 105 may fulfill. External memory controller 105 may translate or interpret the communications exchanged between components of system 100 and memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0042] In some cases, the external memory controller 105 or other components of system 100, or the functions thereof described herein, may be implemented by processor 120. For example, external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by processor 120 or other components of system 100. Although external memory controller 105 is depicted as being external to memory device 110, in some cases, external memory controller 105, or the functions thereof described herein, may be implemented by memory device 110. For example, external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165. In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110, such that portions of external memory controller 105 are implemented by processor 120, and other portions are implemented by device memory controller 155 or local memory controller 165. Similarly, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may be performed by the external memory controller 105 (separate from or included in the processor 120).

[0043] Components of system 100 can exchange information with memory device 110 using multiple channels 115. Channels 115 enable communication between external memory controller 105 and memory device 110. Each channel 115 may contain one or more signal paths or transmitting media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal containing one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins may be instances of conductive input or output points of devices of system 100, and pins may be configured to act as part of a channel.

[0044] In some cases, the pins or pads of the terminals may be part of the signal path of channel 115. Additional signal paths may be coupled to the terminals of the channel to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths within memory device 110 or its components, such as within memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0045] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting a specific type of information. In some cases, channel 115 can be an aggregated channel and therefore can contain multiple individual channels. For example, data channel 190 can be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), and so on. Signals transmitted via the channel can use dual data rate (DDR) signaling. For example, some symbols of the signal can be registered on the rising edge of the clock signal, and other symbols of the signal can be registered on the falling edge of the clock signal. Signals transmitted via the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be registered for each clock cycle.

[0046] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, containing control information (e.g., address information) associated with the commands. For example, CA channel 186 may contain a read command for the address of desired data. In some cases, CA channel 186 may be registered on the rising and / or falling clock edges. In some cases, CA channel 186 may contain any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0047] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between high and low states and coordinate the operation of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK_t and CK_c signals), and the signal paths of CK channel 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channel 188 may contain any number of signal paths. In some cases, clock signals CK (e.g., CK_t and CK_c signals) may provide a timing reference for command and addressing operations of memory device 110 or for other system-wide operations of memory device 110. Clock signals CK may therefore be referred to differently as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK can be generated by the system clock and may contain one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0048] In some cases, channel 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transmit data and / or control information between external memory controller 105 and memory device 110. For example, data channel 190 may transmit information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110. Data channel 190 may transmit signals that can be modulated using various different modulation schemes (e.g., NRZ, PAM4).

[0049] In some cases, error detection information associated with data accessed may be transmitted using one or more of channels 115. The memory device 110 may use the error detection information to detect or correct errors introduced into the data when transmitted from the host device to the memory device 110. The error detection information may include ECC bits for detecting or correcting errors in the associated data. The ECC bits may be SEC ECC bits or SECDED ECC bits, depending on the type of ECC implemented by system 100. In some other cases, the ECC bits may correspond to other types of ECC implemented by system 100 (e.g., other than SEC or SECDED ECC). The error detection process for detecting or correcting errors in data transmitted between the memory device 110 and the host device may be referred to as link ECC. The error detection information may be transmitted via one or more of the other channels 192. Data may be transmitted via DQ channel 190, and the error detection information may be transmitted during the same burst period. Alternatively or concurrently, error detection information may be transmitted via DQ channel 190. This error detection information may be referred to as hierarchical error detection information. When using hierarchical error detection, the external memory controller 105 and / or memory device 110 may adjust the burst length of the data burst to include both the data associated with the access operation and the error detection information associated with the data.

[0050] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may contain any number of signal paths.

[0051] In some cases, other channels 192 may include one or more write clock (WCK) channels. While the 'W' in WCK may nominally stand for "write," the write clock signals WCK (e.g., WCK_t and WCK_c signals) provide a timing reference typically used for access operations of memory device 110 (e.g., a timing reference for both read and write operations). Accordingly, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t and WCK_c signals), and the signal paths of the WCK channel may be configured accordingly. The WCK channel may contain any number of signal paths. The data clock signal WCK can be generated by a data clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0052] Channel 115 can use various architectures to couple external memory controller 105 to memory device 110. Examples of various architectures may include buses, point-to-point connections, cross switches, high-density in-cell modules such as silicon in-cell modules, or channels formed in an organic substrate, or combinations thereof. For example, in some cases, the signal path may at least partially include high-density in-cell modules, such as silicon in-cell modules or glass in-cell modules.

[0053] Various modulation schemes can be used to modulate the signal transmitted on channel 115. In some cases, binary symbol (or binary hierarchy) modulation schemes can be used to modulate the signal transmitted between external memory controller 105 and memory device 110. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals two. Each symbol in a binary symbol modulation scheme can be configured to represent a bit of digital data (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include (but are not limited to) non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and so on.

[0054] In some cases, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. A multi-symbol modulation scheme may be an example of an M-ary modulation scheme where M is greater than or equal to 3. Each symbol in a multi-symbol modulation scheme can be configured to represent more than one bit of digital data (e.g., a symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include (but are not limited to) PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal or PAM4 signal can be a signal modulated using a modulation scheme comprising at least three levels for encoding information of more than one bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0055] Memory device 110 can be configured to bypass internal error correction operations during access operations. During a read operation, memory device 110 can output data that has not yet undergone internal error detection and correction operations. Memory device 110 can perform internal error detection and correction operations on the data while performing access operations. If an error is detected or corrected, memory device 110 can output an indication of the detected error retroactively and, in some cases, output corrected data. During a write operation, memory device 110 can store data generated by external memory controller 105 and corresponding error correction and detection information (e.g., link ECC bits). Here, the latency introduced by performing error detection and correction operations at memory device 110 can be bypassed while maintaining the reliability associated with storing error detection or correction information.

[0056] Figure 2 An example of a memory die 200 according to the examples disclosed herein is shown. The memory die 200 may be as described in [reference]. Figure 1 An example of the described memory die 160. In some cases, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, a memory cell 205 may be configured to store one bit of digital logic at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0057] Memory cell 205 may store states representing digital data (e.g., polarization states or dielectric charges). In a FeRAM architecture, memory cell 205 may include a capacitor containing ferroelectric material to store charges and / or polarizations representing programmable states. In a DRAM architecture, memory cell 205 may include a capacitor containing dielectric material to store charges representing programmable states. In other memory architectures, other memory devices and components are possible. For example, nonlinear dielectric materials may be used.

[0058] Operations such as reading and writing can be performed on memory cells 205 by activating or selecting access lines such as word lines 210, digital lines 215, and / or board lines 220. In some cases, digital line 215 may also be referred to as a bit line. The references to access lines, word lines, digital lines, board lines, or the like are interchangeable without affecting understanding or operation. Activating or selecting word line 210, digital line 215, or board line 220 may involve applying voltage to the corresponding line.

[0059] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a grid-like pattern. Memory cells 205 may be located at the intersection of word lines 210, digital lines 215, and / or board lines 220. A single memory cell 205 can be accessed at its intersection by biasing word lines 210, digital lines 215, and board lines 220 (e.g., by applying a voltage to word lines 210, digital lines 215, or board lines 220).

[0060] Memory access unit 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 can receive row addresses from local memory controller 265 and activate word lines 210 based on the received row addresses. Column decoder 230 receives column addresses from local memory controller 265 and activates digital lines 215 based on the received column addresses. Board driver 235 can receive board addresses from local memory controller 265 and activate board lines 220 based on the received board addresses. For example, memory die 200 can include multiple word lines 210 labeled WL_1 to WL_M, multiple digital lines 215 labeled DL_1 to DL_N, and multiple board lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Therefore, by activating word line 210, digital line 215, and board line 220 (e.g., WL_1, DL_3, and PL_1), the memory cell 205 at their intersection can be accessed. In a two-dimensional or three-dimensional configuration, the intersection of word line 210 and digital line 215 can be referred to as the address of memory cell 205. In some cases, the intersection of word line 210, digital line 215, and board line 220 can be referred to as the address of memory cell 205.

[0061] Memory cell 205 may include, for example, a logic storage component such as capacitor 240, and a switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to board line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two (2) components.

[0062] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. Capacitor 240 can be electrically connected to digital line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 can be isolated from digital line 215, and when switch assembly 245 is activated, capacitor 240 can be coupled to digital line 215. In some cases, switch assembly 245 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source is greater than or less than the transistor's threshold voltage. In some cases, switch assembly 245 can be a p-type transistor or an n-type transistor. Word line 210 can be electrically connected to the gate of switch assembly 245, and switch assembly 245 can be activated / deactivated based on the voltage applied to word line 210.

[0063] Word line 210 may be a conductive line electrically connected to the memory cell 205 for performing access operations on the memory cell 205. In some architectures, word line 210 may be electrically connected to the gate of a switching component 245 of the memory cell 205 and may be configured to control the switching component 245 of the memory cell. In some architectures, word line 210 may be electrically connected to the node of a capacitor in the memory cell 205, and the memory cell 205 may not include a switching component.

[0064] Digital line 215 may be a conductive line connecting memory cell 205 to sensing component 250. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be configured to selectively couple and / or isolate capacitor 240 of memory cell 205 from digital line 215. In some architectures, memory cell 205 may be electrically connected (e.g., constant) to digital line 215.

[0065] The board line 220 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. The board line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of the capacitor 240. The board line 220 may be configured to cooperate with the digital line 215 to bias the capacitor 240 during access operations of the memory cell 205.

[0066] Sensing component 250 may be configured to detect the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. In some cases, the charge stored by memory cell 205 may be extremely small. Therefore, sensing component 250 may include one or more sense amplifiers to amplify the signal output of memory cell 205. The sense amplifier may detect minute changes in charge on digital line 215 during a read operation and may generate a signal corresponding to logic 0 or logic 1 based on the detected charge. During a read operation, capacitor 240 of memory cell 205 may output a signal (e.g., discharge) to its corresponding digital line 215. The signal may cause a voltage change in digital line 215. Sensing component 250 may be configured to compare the signal received from memory cell 205 across digital line 215 with a reference signal 255 (e.g., a reference voltage). Sensing component 250 may determine the storage state of memory cell 205 based on the comparison. For example, in binary signaling, if digital line 215 has a higher voltage than reference signal 255, sensing component 250 can determine that the storage state of memory cell 205 is logic 1, and if digital line 215 has a lower voltage than reference signal 255, sensing component 250 can determine that the storage state of memory cell 205 is logic 0. Sensing component 250 may include various transistors or amplifiers to detect and amplify signal differences. The detected logic state of memory cell 205 can be output by I / O 260 via ECC block 270. Here, ECC block 270 can perform error detection and correction operations on the detected logic state of memory cell 205, and output data (e.g., raw data or corrected data) by I / O 260. In some other cases, the detected logic state of memory cell 205 can bypass ECC block 270 and be output by I / O 260. In some cases, the detected logic state of memory cell 205 may be output via I / O 260 through and around ECC block 270. Here, the detected logic state of memory cell 205 may be output from memory die 200 simultaneously with the error detection and correction operations performed by ECC block 270 on the detected logic state of memory cell 205. In some cases, sensing component 250 may be part of another component (e.g., column decoder 230, row decoder 225). In some cases, sensing component 250 may be electronically connected to row decoder 225, column decoder 230, and / or board driver 235.

[0067] The local memory controller 265 can control the operation of the memory cell 205 via various components (e.g., row decoder 225, column decoder 230, board driver 235, sensing component 250, ECC block 270). The local memory controller 265 may be used as a reference. Figure 1 An example of the described local memory controller 165. In some cases, one or more of the row decoder 225, column decoder 230, board driver 235, sensing component 250, and ECC block 270 may be co-located with the local memory controller 265. The local memory controller 265 may be configured to receive signals from an external memory controller 105 (or referenced). Figure 1 The described device memory controller 155 receives commands and / or data, translates the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, and, in response to performing said one or more operations, transfers data from the memory die 200 to an external memory controller 105 (or device memory controller 155). A local memory controller 265 can generate row, column, and / or board line address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may differ for the various operations discussed during operation of the memory die 200.

[0068] In some cases, the local memory controller 265 may be configured to perform a precharge operation on the memory die 200. The precharge operation may include precharging one or more components and / or access lines of the memory die 200 to one or more predetermined voltage levels. In some cases, memory cells 205 and / or portions of the memory die 200 may be precharged between different access operations. In some cases, digital lines 215 and / or other components may be precharged before a read operation.

[0069] In some cases, the local memory controller 265 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify the target memory cell 205 on which a write operation will be performed. The local memory controller 265 may identify a target word line 210, a target digital line 215, and / or a target board line 220 that are electrically connected to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digital line 215, and / or the target board line 220 (e.g., by applying voltage to the word line 210, the digital line 215, or the board line 220) to access the target memory cell 205. The local memory controller 265 may apply a specific signal (e.g., voltage) to digital line 215 and a specific signal (e.g., voltage) to board line 220 during a write operation to store a specific state in capacitor 240 of memory cell 205, the specific state indicating the desired logic state.

[0070] ECC block 270 or local memory controller 265 may perform one or more error detection and correction operations on data received from the host device as part of a write operation. For example, ECC block 270 may receive data from the host device as part of a write operation. ECC block 270 may determine or generate error detection or correction information associated with the data. In some cases, ECC block 270 may include error detection logic or cause error detection logic (not shown) to perform the error detection operations described herein. ECC block 270 may cause data and error detection or correction information to be stored in one or more memory cells 205 as part of a write operation. In another example, ECC block 270 may receive data and associated error detection or correction information from a memory array as part of a read operation. ECC block 270 may perform error detection and correction operations based on the data and error detection or correction information.

[0071] Error detection and correction operations at the memory device can increase the latency of access operations (e.g., read operations, write operations). For example, error detection and correction operations may take several nanoseconds, and data (e.g., corrected data) may not be available until the error detection and correction operations are complete. It may be necessary to reduce the latency associated with access operations. In one instance, the memory device may suppress operation of ECC block 270 and perform access operations without using or generating corresponding error detection or correction information. However, suppressing operation of ECC block 270 reduces the reliability of the memory system.

[0072] The memory die 200 can perform internal error detection and correction operations in parallel, while simultaneously outputting data that bypasses these operations. In some cases, the memory die 200 can bypass the ECC block 270 during access operations. During a read operation, data 252 from the sensing component 250 can bypass the ECC block 270 to be output via I / O 260, and also sent to the ECC block 270. When data 252 is output via I / O 260, the ECC block 270 can perform internal error detection and correction operations on the data 252. If the ECC block 270 detects and / or corrects an error, it can output an indication 271 of the detected error (e.g., via I / O 260). In some cases, the ECC block 270 can output corrected data 272 (e.g., via I / O 260) (e.g., retrospectively). Alternatively, ECC block 270 may store an error-corrected indication 271 and output the indication to a host device via a sideband or control channel (e.g., the host device may read a register storing the error-corrected indication 271). Additionally or alternatively, memory die 200 may support pass-through ECC for write operations. During a write operation, the memory device may store data generated by the host device and corresponding error correction and detection information (e.g., link ECC information). Here, the latency introduced by performing error detection and correction operations at ECC block 270 can be bypassed while maintaining the reliability associated with storing error detection or correction information.

[0073] In some cases, the local memory controller 265 may be configured to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During a read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify the target memory cell 205 on which a read operation will be performed. The local memory controller 265 may identify a target word line 210, a target digital line 215, and / or a target board line 220 that are electrically connected to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digital line 215, and / or the target board line 220 (e.g., by applying voltage to the word line 210, the digital line 215, or the board line 220) to access the target memory cell 205. Target memory cell 205 can transmit a signal to sensing component 250 in response to a bias access line. Sensing component 250 can amplify the signal. Local memory controller 265 can activate sensing component 250 (e.g., latching sensing component) and then compare the signal received from memory cell 205 with reference signal 255. Based on the comparison, sensing component 250 can determine the logic state stored in memory cell 205. As part of a read operation, local memory controller 265 can transmit the logic state stored in memory cell 205 to external memory controller 105 (or device memory controller).

[0074] In some memory architectures, accessing memory cell 205 may degrade or corrupt the logic state stored in memory cell 205. For example, a read operation performed on a ferroelectric memory cell may corrupt the logic state stored in a ferroelectric capacitor. In another instance, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. Local memory controller 265 may perform a rewrite or refresh operation to restore the memory cell to its original logic state. Local memory controller 265 may rewrite the logic state to the target memory cell after a read operation. In some cases, a rewrite operation may be considered part of a read operation. Additionally, activating a single access line (e.g., word line 210) may interfere with the state stored in some memory cells that are electrically connected to the access line. Therefore, a rewrite or refresh operation may be performed on one or more memory cells that may not have been accessed yet.

[0075] Figure 3 An example of a system 300 supporting an error-correcting memory device with fast data access as disclosed herein is shown. System 300 may include, as referenced... Figure 1 and 2The system 300 may include one or more components as described. The system 300 may include a memory device 310 coupled to multiple channels (e.g., C / A channel 386, CLK channel 388, control channel 392, or combinations thereof), which may be connected to an external memory controller (e.g., as referenced). Figure 1 (As described) communication. Memory device 310 may be a reference. Figure 1 and 2 Examples of the described memory device 110 and / or memory die 200; C / A channel 386, CLK channel 388 and control channel 392 may be as described in the references. Figure 1 Examples of the described C / A channel 186, CLK channel 188, and other channels 192; array 395 may be as described in the reference. Figure 1 Examples of one or more of the described memory arrays 170; memory controller 340 and register / fuse 360 ​​may include, as referenced Figure 1 and 2 The described aspects are memory controller 155 or local memory controller 165 or 265; row address decoder 320 may be a reference. Figure 2 The described row decoder 225 is an example; the column address decoder 325 may be a reference. Figure 2 The described example is the column decoder 230; the voltage reference supply 350 can be as a reference... Figure 2 The example of reference line 250 described; the sense amplifier 345 and I / O logic 385 may include, as in the reference... Figure 2 The described aspects of the sensing component 245; the ECC block 365 may be as referenced. Figure 2 The described instance of ECC block 270; and the I / O buffer 355 may be as referenced. Figure 2 An example of the described I / O 260. The memory device 310 may also include a clock input buffer 315, a control input buffer 330, a C / A input buffer 335, a subword driver 380, buffer logic 390, and self-refresh logic 370.

[0076] Memory device 310 can be coupled to multiple channels to communicate with an external memory controller (e.g., a host device). Signals transmitted via the channels can be received by interface 305 and stored in a buffer associated with the channel. Channels can be dedicated to transmitting specific types of information. For example, CLK channel 388 can be configured to transmit one or more common clock signals between the external memory controller and memory device 310. Memory device 310 can receive CLK signals via interface 305-a and perform clock stabilization and recovery at clock input buffer 315. In another example, control channel 392 can be configured to transmit control signals with the external memory controller. Control signals can be transmitted via interface 305-b and captured at control input buffer 330. In a third example, C / A channel can be configured to transmit commands between the external memory controller and memory device 310, including address information associated with the command. C / A signals can be received by interface 305-c and captured at C / A input buffer 335.

[0077] The memory controller 340 may receive information stored in an input buffer. For example, the memory controller 340 may receive and store control signals and / or C / A signals from the control input buffer 330 and the C / A input buffer 335, respectively. The memory device 310 may also include a register / fuse 360. Based on the information stored in the memory controller 340 or the register / fuse 360, the memory controller 340 may control the operation of the memory device 310 via various components (e.g., row address decoder 320, column address decoder 325, subword driver 380). The memory controller 340 may be configured to receive commands and / or data from the control input buffer 330 and the C / A input buffer 335, translate the commands and / or data into information usable by the memory device 310, perform one or more operations on the memory device 310, and, in response to performing the one or more operations, transfer data from the memory device to an external memory controller via the I / O buffer 355 and the interface 305-d.

[0078] The memory controller 340 can generate row and column address signals based on commands and / or data received from the memory device 310. The memory controller 340 can transmit the row address signals to the row address decoder 320 and the column address signals to the column address decoder 325. The row address decoder 320 can activate a word line at array 395 (or a portion of a word line can be activated by the sub-word driver 380). The column address decoder 325 can activate a digital line based on the received column address. Therefore, memory cells at the intersection of the word line and the digital line can be accessed. In some cases, the number of memory cells associated with the accessed word line can be based on the sub-word driver 380. That is, the sub-word driver 380 can access the entire word line or a portion of a word line based on the row address received from the memory controller 340. Memory cells of array 395 associated with the word line or a portion of the word line can be accessed.

[0079] The sense amplifier 345 can be configured to amplify the signal output from the array 395. The sense amplifier 345 can output the amplified signal to I / O logic 385. During a read operation, the sense amplifier 345 can be configured to detect a state (e.g., charge) stored at the array 395. For example, the sense amplifier 345 can compare a signal received from the array 395 with a voltage from a voltage reference supply 350. The sense amplifier 345 can determine the stored state of one or more memory cells based on the comparison. The sense amplifier 345 can output the detected logic state to I / O logic 385. During a write operation, I / O logic 385 can receive data from I / O buffer 355 via ECC block 365. The data can be stored at the array 395 based on digital lines and word lines activated by column address decoder 325 and row address decoder 320.

[0080] ECC block 365 can perform one or more error detection or correction operations on data received from an external memory controller or from I / O logic 385 (e.g., previously stored at array 395). During a write operation, ECC block 365 can generate error detection or correction information based on data received from an external memory controller (e.g., from I / O buffer 355). For example, parity check or Hamming code information can be generated based on the data. ECC block 365 can transmit the generated error detection or correction information to I / O logic 385 for storage along with the data at array 395. During a read operation, ECC block 365 can perform inline ECC. Here, ECC block 365 can receive data and error detection or correction information (e.g., associated with the data and stored at array 395) from I / O logic 385. ECC block 365 can also generate error detection or correction information based on data read from array 395 during a read operation. Furthermore, ECC block 365 can compare the received error detection or correction information with the generated error detection or correction information. If the received error detection or correction information does not match the generated error detection or correction information, ECC block 365 can detect an error.

[0081] Error detection operations performed by ECC block 365 can add latency to command execution. For example, an error detection operation may take several nanoseconds, or may add one or more clock cycles to the time it takes for data to be ready for output via I / O buffer 355. In some cases, the additional latency may be associated with a specific error detection operation (e.g., H matrix corrector generation, error decoding). Where an error detection operation occurs during each access command (e.g., for each read command, for each write command), there may be a corresponding latency in the operation of memory device 310. For example, if an error detection operation introduces a two (2) nanosecond latency into a read operation, then one thousand (1000) read operations will correspond to a two thousand (2000) nanosecond latency. If ECC block 365 detects an error (e.g., a unit error) in one thousand (1000) read operations, then the other 999 read operations will have performed unnecessary error detection operations and accumulated a latency of 1,998 nanoseconds.

[0082] In some examples, an alternative path between I / O logic 385 and I / O buffer 355 can be used to bypass ECC block 365 (thus eliminating the latency caused by error detection operations performed at ECC block 365). Here, data can be passed between I / O logic 385 and I / O buffer 355 while ECC block 365 performs error detection operations on data. If an error is detected by ECC block 365 during command execution, an indication of the detected error (and, in some cases, corrected data) can be traced back to the external memory controller. For example, during a read operation, when ECC block 365 performs error detection operations on data, data can be passed from I / O logic 385 to I / O buffer 355 (and subsequently to the external memory controller via interface 305-d). If ECC block 365 detects an error, it can indicate the error to the external memory controller during or after the original data (e.g., with the detected error) has been transmitted to the external memory controller. Here, if the error detection operation introduces a delay of two (2) nanoseconds into the read operation, and the ECC block 365 detects an error (e.g., a unit error) in one thousand read operations, the delay associated with the one thousand read operations may be equal to the burst length used to reread the corrected data from the read operation with the error.

[0083] Memory device 310 may include self-refresh logic 370. Self-refresh logic 370 enables memory device 310 to initiate a refresh operation. A self-refresh mode can be used in a low-power or standby state of memory device 310, wherein memory device 310 may not receive memory commands containing refresh commands. In self-refresh mode, register / fuse 360 ​​or self-refresh logic 370 may use an internal oscillator, internal counter, or other refresh array 395. Register / fuse 360 ​​or self-refresh logic 370 can determine the refresh rate.

[0084] The memory device may include a test mode 375. The test mode 375 provides an interface for test and diagnostic functions of the memory device 310.

[0085] Figure 4A An example of a system 400-a supporting an error-correcting memory device with fast data access as disclosed herein is shown. System 400-a may include, as referenced... Figure 1 , 2 And one or more components as described in 3. For example, system 400-a may include: array 490-a, which may be as described in reference Figure 2 and 3 Examples of one or more of the described memory arrays 170 or 395; a sense amplifier 445-a, which may include, as referenced Figure 2 and3 The aspects of the described sensing component 250 and sense amplifier 345; I / O logic 485-a, which may include as referenced Figure 3 The described aspects of I / O logic 385; ECC block 465-a, which may be as referenced Figure 2 and 3 Examples of ECC block 270 or ECC block 365 described; I / O buffer 455-a, which may be as referenced Figure 2 and 3 Examples of the described input / output 260 or I / O buffer 355; and interface 405, which may include, as referenced Figure 3 The interface 305 described herein. System 400-a may also include a first-in-first-out (FIFO) buffer 410 and a multiplexer (MUX) 425-a.

[0086] System 400-a can be configured to perform a read operation. System 400-a can receive a read command (e.g., from a host device). The read command can indicate data to be read from array 490-a (e.g., via the address of the read command). In some cases (e.g., if system 400-a is associated with an ECC memory device), array 490-a can store error detection or correction information for error detection and correction of the data. System 400-a can communicate with a memory controller (e.g., as referenced). Figure 1 and 2 (As described) In communication, the memory controller can instruct the sub-word driver 480-a to activate or select a word line or portion of a word line based on a received read command. Thus, the memory controller can instruct a portion of the array 490-a to be read. During the read operation, a sense amplifier 445-a can detect and amplify a signal output from the array 495-a. After amplifying the signal, the sense amplifier 445-a can output a signal to the I / O logic 485-a. This signal may correspond to data indicated by the read command and error detection or correction information (e.g., first error detection or correction information) associated with said data indicated by the read command.

[0087] Data output to I / O logic 485-a can be transferred to FIFO buffer 410-a and ECC block 465-a. Data output from I / O logic 485-a to FIFO buffer 410-a can correspond to first data. The first data can bypass the on-die ECC block 465-a. Therefore, the first data can correspond to data in which no correction occurs (e.g., raw data from array 490-a).

[0088] I / O logic 485-a can transmit data and associated error detection or correction information to ECC block 465-a. ECC block 465-a can perform error detection and correction operations on the data based on the associated error detection or correction information. That is, after receiving a read command for data, ECC block 465-a can generate new error detection or correction information (e.g., second error detection or correction information) based on the data retrieved by I / O logic 485-a from array 490-a using the same error correction code previously used to generate the first error detection or correction information. If the first and second error detection or correction information match, ECC block 465-a can determine that the data is not corrupted (e.g., no error exists). If the first and second error detection or correction information do not match, ECC block 465-a can determine that the data is corrupted (e.g., at least one error exists).

[0089] If ECC block 465-a determines that the data is corrupted, it can correct the data to produce a second, corrected version of the data read from array 490-a. Furthermore, ECC block 465-a can indicate an error to the host device. Specifically, ECC block 465-a can set an error flag 420-a to indicate the error. The host device can receive the error flag via interface 405-b. Interface 405-b (e.g., corresponding to error flag 420-a) can correspond to a pin dedicated to error flagging or a multi-function pin (e.g., a pin for a direct memory interface, a pin for decode status feedback).

[0090] If ECC block 465-a is a SEC ECC block 465-a, then ECC block 465-a can detect and correct unit errors. Here, the second data may contain corrected unit errors. Furthermore, error flag 420-a may indicate one or more of corrected unit errors, uncorrected errors, or incorrectly flipped bits (e.g., aliased bad bits) within the second data. Alternatively or concurrently, if ECC block 465-a is a SECDED ECC block 465-a, then ECC block 465-a can detect and correct unit errors and detect double-bit errors. Here, the second data may contain corrected unit errors. Furthermore, error flag 420-a may indicate one or more of corrected unit errors, detected double-bit errors, uncorrected errors, or incorrectly flipped bits (e.g., aliased bad bits) within the second data. In some other cases, ECC block 465-a may implement different ECC schemes (e.g., other than SEC or SECDED ECC). Here, the second data may be based on the type of error that can be detected or corrected by different ECC schemes.

[0091] ECC block 465-a may output second data to FIFO buffer 410-b. In some cases, ECC block 465-a may not output data to buffer 410-b when no error is detected or corrected. In other cases, ECC block 465-a may output second data to FIFO buffer 410-b during the execution of each read operation. That is, when a read operation is performed, ECC block 465-a replaces any existing data in buffer 410-b with data corresponding to the second data determined during the execution of the current read command. Depending on the input from mode register controller 415-a (e.g., from mode register controller 415-a to MUX 425-a), first data stored in FIFO buffer 410-a or second data stored in FIFO buffer 410-b may propagate from FIFO buffer 410 to I / O buffer 455-a. In other words, the mode register controller 415-a can adjust the MUX 425-a to select either the FIFO buffer 410-a or the FIFO buffer 410-b. Data transferred to the I / O buffer 455-a can be propagated from the FIFO buffer 410 via the MUX 425-a in a first-in, first-out (FIFO) order. Data within the I / O buffer 455-a can be transferred to the host device via the interface 405-a. Therefore, the system 400-a can transfer data stored in the array 490-a to the host device based on a read command received from the host device.

[0092] In the first mode, the mode register controller 415-a can instruct data from the FIFO buffer 410-a to be propagated to the I / O buffer 455-a via the MUX 425-a. In some cases, this can be a flow-through mode. That is, the first data associated with a read operation can bypass the ECC block 465-a by flowing directly from the I / O logic 485-a to the I / O buffer 455-a. By bypassing the ECC block 465-a, the first mode can bypass the latency associated with the ECC block 465-a. For example, error detection and correction operations can take approximately a few nanoseconds. Therefore, by bypassing this error detection and correction operation, the first mode can have lower latency. In this mode, the ECC block 465-a can perform error detection and correction operations on the first data in parallel with the transfer of the first data from the I / O logic 485-a to the I / O buffer 455-a.

[0093] In the second mode, the mode register controller 415-a can instruct data from the FIFO buffer 410-b to be propagated to the I / O buffer 455-a via the MUX 425-a. In some cases, this can be an ECC correction sub-mode. When operating in the second mode, data associated with a read command is propagated to the I / O buffer 455-a via the ECC block 465-a. That is, the system 400-a transmits data that has already undergone error detection and correction operations. In some cases, the mode register controller 415-a can be configured to operate according to this second mode. That is, some systems 400-a may not be able to utilize the first mode that bypasses the ECC block 465-a. For example, the system 400-a may use specific mode settings or register codes to utilize the first mode used to bypass the ECC block 465-a.

[0094] In some cases, the mode register controller 415-a may generate second data based on whether the ECC block 465-a detects and / or corrects errors in the first data. For example, the mode register controller 415-a may instruct the system 400-a to propagate the first data from the FIFO buffer 410-a to the I / O buffer 455-a. However, if the ECC block 465-a detects and / or corrects errors in the first data to generate second data, the mode register controller 415-a may instruct the system 400-a to propagate the second data from the FIFO buffer 410-b to the I / O buffer 455-a. In some cases, because the path from the FIFO buffer 410-a to the I / O buffer 455-a is faster (e.g., due to less latency caused by bypassing the ECC block 465-a), the mode register controller 415-a may retroactively instruct the propagation of the second data from the FIFO buffer 410-b to the I / O buffer 455-a. In other words, system 400-a can transmit all or part of the first data (e.g., by FIFO buffer 410-a) and the second data (e.g., by FIFO buffer 410-b) to the host device. In this way, the latency caused by error detection and correction operations can be minimized by bypassing ECC block 465-a when no error is detected. In some other cases, memory system 400-a may allow all data associated with a read command to bypass ECC block 465-a.

[0095] In a first instance, the mode register controller 415-a can automatically adjust the output of the MUX 425-a based on whether the ECC block 465-a detects and / or corrects errors in the first data to generate second data. This may be referred to as flow ECC automatic mode. Here, if the ECC block 465-a detects and / or corrects the data to generate second data, the system 400-a can flag the detected and / or corrected errors via error flag 420-a. Error flag 420-a may further include an indication that the system 400-a will transmit the second data after transmitting the first data. For example, the system 400-a can transmit all or part of the first data to the host device via I / O buffer 455-a by means of a first burst. The indication may indicate that the second data will immediately follow the first burst (e.g., a double burst of all or part of the first data is followed by the second data). The mode register controller 415-a may instruct the system 400-a to propagate the second data from the FIFO buffer 410-b to the I / O buffer 455-a in the next burst. For example, system 400-a can operate according to a first mode (e.g., bypassing ECC block 465-a). ECC block 465-a can detect unit errors (e.g., via SEC operation) and indicate via error flag 420-a that second data will be interrupted or immediately following a burst containing the first data.

[0096] Alternatively, the indication may indicate a delay for the second data. The mode register controller 415-a may instruct the system 400-a to propagate the second data from the FIFO buffer 410-b to the I / O buffer 455-a in a burst following the first burst, according to the indicated delay. The delay may correspond to a certain number of bursts. For example, the delay may indicate two (2) bursts, such that the second data can propagate from the FIFO buffer 410-b to the I / O buffer 455-a in a burst two (2) bursts after the completion of the first burst. In some cases, the delay for circulating ECC automatic mode may be approximately 2.5 nanoseconds. In these cases, the ECC block 465-a may generate the indication within 1.5 to two (2) nanoseconds. For example, the system 400-a may use an additional cycle (e.g., a READ clock corresponding to the burst length) to transmit the second data from the FIFO buffer 410-b to the host device after the first data has been transmitted from the FIFO buffer 410-a. The delay may support memory systems with low latency constraints.

[0097] In a second example, the mode register controller 415-a can adjust the output of MUX425-b based on an instruction received from the host device. This may be referred to as an ECC-dedicated mode. Here, the host device may receive an indication of detected and / or corrected errors (e.g., via error flag 420-a). When the host device receives the indication of detected and / or corrected errors, it may temporarily suspend the operation of system 400-a and instruct the mode register controller 415-a to set MUX425-a to propagate second data (e.g., generated by correcting at least one error in the first data) from FIFO buffer 410-b to I / O buffer 455-a. The host device may instruct the mode register controller 415-a to propagate the second data from FIFO buffer 410-b within a time limit (e.g., 1.5 nanoseconds). Thus, data can be guided via ECC block 465-a. Setting the mode register controller 415-a to guide data via ECC block 465-a may correspond to a deactivated circulation mode. The host device can repeat read commands (or multiple read commands) corresponding to indications of detected and / or corrected errors. Because the host device sets the mode register controller 415-a to disable circulation mode, data can be driven via ECC block 465-a when a reread (or multiple rereads) is performed. In some cases, a reread may involve system 400-a rewriting corrected data to array 490-a.

[0098] Alternatively, the host device may receive an indication of detected and / or corrected errors without initiating a reread. The host device may correct errors within the first data (e.g., received from system 400-a) at the host device. In some cases, this may prevent errors introduced by SEC operations at system 400-a (e.g., bits incorrectly flipped by ECC block 465-a). The host device may determine whether to continue operation in the first mode (e.g., bypassing ECC block 465-a) or switch the mode register controller 415-a to cause the system to operate according to a second mode (e.g., via ECC block 465-a).

[0099] The host device can determine whether system 400-a continues to propagate data via ECC block 465-a (e.g., according to the second mode) or switches back to bypassing ECC block 465-a (e.g., according to the first mode). In some cases, the host device can determine the mode based on a segment of array 490-a that is being accessed. For example, the host device can identify segments of array 490-a that are associated with a higher error rate (e.g., unit error) compared to other segments. The host device can determine to switch to the second mode when accessing (e.g., reading) these segments of array 490-a.

[0100] The method for adjusting the mode register controller 415-a (e.g., adjusting the mode register controller 415-a autonomously or based on instructions from the host device) can be non-programmable (e.g., hardwired or stored in read-only memory (ROM)) or one-time programmable (OTP) (e.g., stored in one or more fuses or antifuses or one or more OTP memories). In a second example, the method for adjusting the mode register controller 415-a can be programmed after assembly (e.g., by the host device or by the original equipment manufacturer).

[0101] Figure 4B An example of a system 400-b supporting an error-correcting memory device with fast data access as disclosed herein is shown. System 400-b may include, as referenced... Figures 1 to 4A One or more components as described. For example, system 400-b may include: array 490-b, which may be as described in the reference. Figure 1 , 3 Examples of one or more of the memory arrays 170 or 395 and 490-a described in 4A; and a sense amplifier 445-b, which may include, as referenced Figures 2 to 4A The described aspects include sensing component 245 and sense amplifiers 345 and 445-a; and I / O logic 485-b, which may include, as referenced... Figure 3 and 4A The described aspects of I / O logic 385 and 485-a; ECC block 465-b, which may be as referenced Figures 2 to 4A Examples of ECC blocks 270, 365, and 465-a described; I / O buffer 455-b, which may be as referenced. Figures 2 to 4A Examples of the described input / output 260 or I / O buffers 355 and 455-a; and interface 405, which may include, as referenced Figure 3 and 4A The described aspects of interfaces 305 and 405; and MUX 425-b, which may be as referenced. Figure 4A An example of the described MUX 425-a. System 400-b may also include a FIFO buffer 410-c.

[0102] System 400-b can be similar to the reference. Figure 4ASystem 400-a is described. However, system 400-b may utilize a different configuration for transferring data from I / O logic 485-b to the host device via I / O buffer 455-b. Specifically, system 400-b may utilize a single FIFO buffer 410-c instead of two (2) FIFO buffers 410-a and 410-b. In some cases, this may reduce the physical size of system 400-b (e.g., compared to system 400-a). Alternatively or concurrently, system 400-b may be associated with more latency compared to system 400-a. System 400-b may introduce latency when outputting corrected data (e.g., from ECC block 465-b) after outputting data from I / O logic 485-b. System 400-a may not introduce similar latency when reading corrected data from FIFO buffer 410-b after reading data from FIFO buffer 410-a.

[0103] Similar to system 400-a, system 400-b can be configured to perform read operations. System 400-b can receive read commands (e.g., from a host device). The read command can indicate data to be read from array 490-b (e.g., via the address of the read command). In some cases (e.g., if system 400-b is associated with an ECC memory device), array 490-b can store error detection or correction information for error detection and correction associated with the data. System 400-b can communicate with a memory controller (e.g., as referenced). Figure 1 and 2 (As described) In communication, the memory controller can instruct the sub-word driver 480-b to activate or select a word line or portion of a word line based on a received read command. Thus, the memory controller can instruct a portion of the array 490-b to be read. During the read operation, a sense amplifier 445-b can detect and amplify a signal output from the array 495-b. After amplifying the signal, the sense amplifier 445-b can output a signal to the I / O logic 485-b. This signal may correspond to data indicated by the read command and error detection or correction information (e.g., first error detection or correction information) associated with said data indicated by the read command.

[0104] Data output to I / O logic 485-b can be transmitted from I / O logic 485-b directly or via ECC block 465-b to MUX 425-b. Data output from I / O logic 485-b may correspond to first data. In some cases, the first data may bypass the on-die ECC block 465-b. I / O logic 485-b can transmit data and associated error detection or correction information to ECC block 465-b. ECC block 465-b can perform error detection and correction operations on the data based on the associated error detection or correction information. That is, after receiving a read command for data, ECC block 465-b can generate new error detection or correction information (e.g., second error detection or correction information) based on the data retrieved by I / O logic 485-b from array 490-b using the same error correction code previously used to generate the first error detection or correction information. If the first and second error detection or correction information match, ECC block 465-b can determine that the data is not corrupted (e.g., no errors exist). If the first and second error detection or correction information do not match, ECC block 465-b can determine that the data is corrupted (e.g., at least one error exists).

[0105] If ECC block 465-b determines that the data is corrupted, it can correct the data to generate a second set of corrected data corresponding to the data read from array 490-b. Furthermore, ECC block 465-b can indicate an error to the host device. Specifically, ECC block 465-b can set an error flag 420-b to indicate the error. The host device can receive the error flag via interface 405-d. Interface 405-d (e.g., corresponding to error flag 420-b) can correspond to a pin dedicated to error flagging or a multi-function pin (e.g., a pin for a direct memory interface, a pin for decode status feedback).

[0106] If ECC block 465-b is a SEC ECC block 465-b, then ECC block 465-b can detect and correct unit errors. Here, the second data may contain corrected unit errors. Furthermore, error flag 420-b may indicate one or more of corrected unit errors, uncorrected errors, or incorrectly flipped bits (e.g., aliased bad bits) within the second data. Alternatively or concurrently, if ECC block 465-b is a SECDED ECC block 465-b, then ECC block 465-b can detect and correct unit errors and detect double-bit errors. Here, the second data may contain corrected unit errors. Furthermore, error flag 420-b may indicate one or more of corrected unit errors, detected double-bit errors, uncorrected errors, or incorrectly flipped bits (e.g., aliased bad bits) within the second data.

[0107] ECC block 465-b can output second data to MUX 425-b. Depending on the input from mode register controller 415-b (e.g., from mode register controller to MUX 425-b), first data from I / O logic 485-b or second data from ECC block 465-b can be propagated to FIFO buffer 410-c. That is, mode register controller 415-b can instruct the propagation of first or second data. Data transferred to I / O buffer 455-b can be propagated from FIFO buffer 410-c according to first-in-first-out order. Data in I / O buffer 455-b can be transferred to the host device via interface 405-c. Therefore, system 400-b can transfer data stored in array 490-b to the host device based on a read command received from the host device.

[0108] In the first mode, the mode register controller 415-b can instruct the first data from I / O logic 485-b to be propagated to the FIFO buffer 410-c via MUX 425-b. In some cases, this can be a flow mode. That is, the first data associated with a read operation can bypass the ECC block 465-b by flowing directly from I / O logic 485-b to I / O buffer 455-b. By bypassing the ECC block 465-b, the first mode can bypass the latency associated with the ECC block 465-b. For example, error detection and correction operations can take approximately a few nanoseconds. Therefore, by bypassing this error detection and correction operation, the first mode can have lower latency. In this mode, the ECC block 465-b can perform error detection and correction operations on the first data in parallel with the transmission of the first data from I / O logic 485-b to I / O buffer 455-b.

[0109] In the second mode, the mode register controller 415-b can instruct data from ECC block 465-b to be propagated to FIFO buffer 410-c via MUX 425-b. In some cases, this can be an ECC correction sub-mode. When operating in the second mode, data associated with a read command is propagated to I / O buffer 455-b via ECC block 465-b. That is, system 400-b transmits data that has already undergone error detection and correction operations. In some cases, the mode register controller 415-b can be configured to operate according to this second mode. That is, some systems 400-b may not be able to utilize the first mode that bypasses ECC block 465-b. For example, system 400-b can use specific mode settings or register codes to utilize the first mode used to bypass ECC block 465-b.

[0110] In some cases, the mode register controller 415-b may generate second data based on whether the ECC block 465-b detects and / or corrects errors in the first data. For example, the mode register controller 415-b may instruct the system 400-b to propagate the first data from the I / O logic 485-b to the FIFO buffer 410-c. However, if the ECC block 465-b detects and / or corrects errors in the first data to generate second data, the mode register controller 415-b may instruct the system 400-b to propagate the second data from the ECC block 465-b to the FIFO buffer 410-c. In some cases, because the path from the I / O logic 485-b to the FIFO buffer 410-c is faster (e.g., due to less latency caused by bypassing the ECC block 465-b), the mode register controller 415-b may retroactively instruct the propagation of the second data from the ECC block 465-b to the FIFO buffer 410-c. In other words, system 400-b can transmit part or all of the first and second data to the host device. In this way, the latency caused by error detection and correction operations can be minimized by bypassing ECC block 465-b when no error is detected. In some other cases, memory system 400-b can allow all data associated with a read command to bypass ECC block 465-b.

[0111] In a first instance, the mode register controller 415-b may automatically adjust the input to the MUX 425-b based on whether the ECC block 465-b detects and / or corrects errors in the first data to generate second data. This may be referred to as flow ECC automatic mode. Here, if the ECC block 465-b detects and / or corrects the data to generate second data, the system 400-b may flag the detected and / or corrected errors via error flag 420-b. Error flag 420-b may further include an indication that the system 400-b will transmit the second data after transmitting the first data. For example, the system 400-b may transmit all or part of the first data to the host device via the I / O buffer 455-b using a first burst. The indication may indicate that the second data will immediately follow the first burst (e.g., a double burst of all or part of the first data is followed by the second data). The mode register controller 415-b may instruct the system 400-b to propagate the second data from the ECC block 465-b to the FIFO buffer 410-c in the next burst. For example, system 400-b can operate according to a first mode (e.g., bypassing ECC block 465-b). ECC block 465-b can detect unit errors (e.g., via SEC operation) and indicate via error flag 420-b that second data will be interrupted or immediately following a burst containing the first data.

[0112] Alternatively, the indication may indicate a delay for the second data. The mode register controller 415-b may instruct the system 400-b to propagate the second data from ECC block 465-b to FIFO buffer 410-c in a burst following the first burst, according to the indicated delay. The delay may correspond to a certain number of bursts. For example, the delay may indicate two (2) bursts, such that the second data can propagate from ECC block 465-b to FIFO buffer 410-c in a burst two (2) bursts after the completion of the first burst. In some cases, the delay for circulating the ECC automatic mode may be approximately 2.5 nanoseconds. In these cases, ECC block 465-b may generate the indication within 1.5 to two (2) nanoseconds. For example, the system 400-b may use an additional cycle (e.g., a READ clock corresponding to the burst length) to transmit the second data from ECC block 465-b to the host device after the first data has been transmitted from I / O logic 485-b. The delay may support memory systems with low latency constraints.

[0113] In a second example, the mode register controller 415-b may instruct the MUX 425-b to propagate data from I / O logic 485-b or ECC block 465-b based on an instruction received from the host device. This may be referred to as an ECC-specific mode. Here, the host device may receive an indication of detected and / or corrected errors (e.g., via error flag 420-b). When the host device receives an indication of detected and / or corrected errors, the host device may temporarily suspend operation of system 400-b and may instruct the mode register controller 415-b to set the MUX 425-b to propagate second data (e.g., generated by correcting at least one error in the first data) from ECC block 465-b to FIFO buffer 410-c. The host device may instruct the mode register controller 415-b to set the MUX 425-b to propagate the second data within a time limit (e.g., 1.5 nanoseconds). Thus, data may be guided via ECC block 465-b. Setting the mode register controller 415-b to boot data via ECC block 465-b corresponds to disabling circulation mode. The host device can repeat read commands (or multiple read commands) corresponding to indications of detected and / or corrected errors. Because the host device sets the mode register controller 415-b to disable circulation mode, data can be booted via ECC block 465-b when a reread (or multiple rereads) is performed. In some cases, a reread may involve system 400-b rewriting corrected data to array 490-b.

[0114] Alternatively, the host device may receive an indication of detected and / or corrected errors without initiating a reread. The host device may correct errors within the first data (e.g., received from system 400-b) at the host device. In some cases, this may prevent errors introduced by SEC operations at system 400-b (e.g., bits incorrectly flipped by ECC block 465-b). The host device may determine whether to continue operation in the first mode (e.g., bypassing ECC block 465-b) or switch the mode register controller 415-b to cause the system to operate according to a second mode (e.g., via ECC block 465-b).

[0115] The host device can determine whether system 400-b continues to propagate data via ECC block 465-b (e.g., according to the second mode) or switches back to bypassing ECC block 465-b (e.g., according to the first mode). In some cases, the host device can determine the mode based on a segment of array 490-b that is being accessed. For example, the host device can identify segments of array 490-b that are associated with a higher error rate (e.g., unit error) compared to other segments. The host device can determine to switch to the second mode when accessing (e.g., reading) these segments of array 490-b.

[0116] The method for adjusting the mode register controller 415-b (e.g., adjusting the mode register controller 415-b autonomously or based on instructions from the host device) can be non-programmable (e.g., hardwired or stored in ROM) or OTP (e.g., stored in one or more fuses or antifuses or one or more OTP memories). In a second example, the method for adjusting the mode register controller 415-b can be programmed after assembly (e.g., by the host device or by the original equipment manufacturer).

[0117] Figure 5 An example of a system 500 supporting an error-correcting memory device with fast data access as disclosed herein is shown. System 500 may include, as referenced... Figure 1 The system 500 may include one or more components as described in section 4. For example, system 500 may include: array 590, which may be as described in reference 4. Figure 1 and 3 Examples of one or more of the memory arrays 170 or 395 and 490 described in 4; a sense amplifier 545, which may include, as referenced Figure 2 and 3 The aspects of the sensing component 245 and the sense amplifiers 345 and 445 described in 4; and the I / O logic 585, which may include, as referenced Figures 3 to 5 The described aspects of I / O logic 385 and 485; ECC block 565, which may be as referenced. Figure 2Examples of ECC blocks 270, 365, and 465 as described in section 4; and I / O buffer 555, which may be as described in reference 4. Figure 2 Examples of the input / output 260 or I / O buffers 355 and 455 described in section 4. System 500 may also include a link ECC block 530, a FIFO buffer 510, and a MUX 525.

[0118] System 500 can be coupled to a host device via a first channel 505 and a second channel 520. System 500 can be configured to perform write operations. System 500 can receive a write command (e.g., from the host device) containing data at I / O buffer 555 via the first channel 505. The data can be transferred from I / O buffer 555 to FIFO buffer 510.

[0119] The write command may further include error detection or correction information received by the second channel 520. The second channel 520 may propagate the error detection or correction information to the link ECC block 530. The link ECC block 530 may be used to increase the reliability of data received by the channel 505. The second channel 520 may also propagate the error detection or correction information to the MUX 525-b. The error detection or correction information may include one or more SEC ECC bits, SECDED ECC bits, or some other type of ECC bit (e.g., other than SEC or SECDED ECC bits), depending on the mode of ECC operation. The link ECC block 530 may use the error detection or correction information to detect and correct individual bits, and in some cases detect and / or correct double-bit errors in data received through the first channel 505. The link ECC block 530 may transmit the corrected data to the I / O buffer 555. The link ECC block 530 may further transmit the error detection or correction information in a manipulated form (e.g., where a bit error is detected in the error detection or correction information) to the MUX 525-b.

[0120] I / O buffer 555 can propagate data to be stored via ECC block 565 to FIFO buffer 510. FIFO buffer 510 can then transfer data to be stored at array 590 to MUX 525-a. Mode register controller 515-a can determine, based on the operating mode of system 500, whether to propagate data via MUX 525-a to MUX 525-b (thus bypassing ECC block 565) or to ECC block 565. In some cases, performing error detection and correction operations at ECC block 565 can increase the latency of write operations. For example, error detection and correction operations may take several nanoseconds, which can result in write latency of one or more clock cycles. It may be necessary to reduce the latency associated with write operations. In one instance, system 500 can bypass ECC block 565 and store data indicated by a write operation without any corresponding error detection or correction information. However, not storing error detection or correction information may reduce system reliability. In another instance, system 500 can bypass ECC block 565 and store data generated by the host device and corresponding error correction and detection information. Here, the latency introduced by ECC block 565 can be bypassed while maintaining the reliability associated with storing error detection or correction information.

[0121] In the first operating mode, the mode register controller 515-a adjusts the output of the MUX 525-a to propagate data from the FIFO buffer 510 to the ECC block 565. The ECC block 565 can generate second error detection or correction information associated with the data to be stored at array 590. In some cases, the error detection or correction information may be based on the type of ECC operation performed by the ECC block 565. For example, if the ECC block 565 is performing SEC, the ECC block 565 can generate first error detection or correction information. In another instance, if the ECC block 565 is performing SECDED, the ECC block 565 can generate second error detection or correction information that differs from the first error detection or correction information. In yet another instance, the ECC block 565 is performing a different type of ECC operation (e.g., other than SEC or SECDED), and the second error detection or correction information is based on the type of ECC operation. The ECC block 565 can propagate the generated error detection or correction information to I / O logic 585.

[0122] In the second operating mode, the mode register controller 515-a adjusts the output of MUX 525-a to propagate data from FIFO buffer 510 to MUX 525-b. MUX 525-b can receive data from FIFO buffer 510 along with error detection or correction information. The error detection or correction information can be manipulated error detection information transmitted by link ECC block 530 (e.g., in an event where link ECC block 530 detects an error in data received from the host device) or error detection or correction information transmitted by channel 520 (e.g., if link ECC block 530 does not detect an error in data received from the host device). The mode register controller 515-b can control the operation of MUX 525-b to output either data and error detection or correction information, or manipulated error detection or correction information. Therefore, MUX 525-b can propagate data and error detection or correction information to I / O logic 585.

[0123] The second operating mode corresponds to the operating mode in which ECC block 565 is bypassed. Instead of generating error detection or correction information, system 500 can utilize error detection or correction information (e.g., link ECC information) generated by the host device. In some cases, performing error detection and correction operations at ECC block 565 can increase the latency of write operations. In the second operating mode, the latency introduced by ECC block 565 can be bypassed while still maintaining the reliability associated with storing error detection or correction information.

[0124] I / O logic 585 can transmit data and error detection or correction information to array 590 (e.g., via sense amplifier 545). Based on the location of array 590 indicated by a write command, subword driver 580 can activate the corresponding location of array 590 to store data and error detection or correction information at array 590.

[0125] Figure 6 An example of process flow 600 supporting an error-correcting memory device with fast data access as disclosed herein is shown. Process flow 600 may include operations performed by a host device 605, which may be as described in reference... Figure 1 An example of the described external memory controller 105. Process flow 600 may further include a memory device (e.g., referenced...) Figures 1 to 3 The memory device 110, memory die 160, memory die 200, or memory device 310 described herein, and others, or as shown in reference, are all memory devices. Figures 1 to 5 The operations performed by components of the memory device, such as the memory controller 155, local memory controller 165, local memory controller 265, system 400, or system 500, as described.

[0126] At 615, memory device 610 can receive read commands from host device 605. Memory device 610 may include a memory array.

[0127] At 620, memory device 610 can read first data from memory array based on a read command.

[0128] At 625, the memory device 610 can perform an error correction operation on the first data to obtain second data and an indicator of errors in the first data. The error correction operation may correspond to a SEC operation or a SECDED operation.

[0129] At 630, the memory device 610 can output the first data to the host device 605 in parallel with at least a portion of the error correction operation. That is, the memory device 610 can output the first data while performing the error correction operation on the data. Therefore, the memory device 610 can output the first data without the delay caused by the error correction operation.

[0130] If the error correction operation corresponds to the SEC operation, the error indication may include an indication of a corrected unit error in the second data, an indication of an uncorrected error in the second data, an indication of an incorrectly flipped bit in the second data, or a combination thereof. If the error correction operation corresponds to the SECDED operation, the error indication may include an indication of a corrected unit error in the second data, an indication of a detected double bit error in the second data, an indication of an uncorrected error in the second data, or an indication of an incorrectly flipped bit in the second data, or a combination thereof.

[0131] At 635, memory device 610 can output an error indicator to host device 605. In some cases, memory device 610 can output the error indicator in parallel with at least a portion of the error correction operation.

[0132] At 640, memory device 610 may optionally output second data to host device 605 based on errors in the first data. In some cases, memory device 610 may output the second data immediately after a determined time following the output of the first data, or at said determined time. For example, memory device 610 may indicate the determined time in an error indication (e.g., output by memory device at 610). In some other cases, memory device 610 may not output the second data. In this case, memory device 610 may receive a second read command from host device 605 indicating a reread of the memory array based on an output error indication (e.g., at 635). Memory device 610 may read third data from the memory array based on the second read command and perform a second error correction operation on the third data to obtain fourth data. Memory device 610 may output the fourth data to host device 605.

[0133] Figure 7 An example of process flow 700 supporting an error-correcting memory device with fast data access as disclosed herein is shown. Process flow 700 may include operations performed by a host device 705, which may be as described in reference... Figure 1 The external memory controller 105 described or as referenced Figure 6 An example of the described host device 605. Process flow 700 may further include a memory device (e.g., reference...) Figures 1 to 3 The memory device 110, memory die 160, memory die 200, memory device 310 or memory device 610 described in reference 6, and others) or, for example, as shown in reference 6 Figures 1 to 5 The operations performed by components of the memory device, such as the memory controller 155, local memory controller 165, local memory controller 265, system 400, or system 500, as described.

[0134] At 715, memory device 710 can receive write commands from host device 705. Memory device 710 may include a memory array.

[0135] At 720, the memory device may receive first data and error detection or correction information associated with the write command from the host device 705.

[0136] At 725, the memory device 710 can use the received error detection or correction information to perform an error correction operation on the first data to obtain the second data. In some cases, at 725, the memory device 710 may also adjust the error detection or correction information received from the host device 705 based on the performance of the error correction operation.

[0137] At 730, the memory device 710 may optionally generate error correction or detection information based on the second data.

[0138] At 735, memory device 710 may store second data and error detection or correction information. In some cases, the memory device may store the received error detection or correction information at the memory array based on a write command. Here, memory device 710 may not generate error correction or detection information. Therefore, memory device 710 may bypass the latency associated with error correction and detection operations corresponding to the generation of error correction or detection information. In some other cases, memory device 710 may store adjusted error detection or correction information. Here, memory device 710 may also bypass the latency associated with error correction and detection operations corresponding to the generation of error correction or detection information. In some other cases (e.g., if memory device 710 generates error correction or detection information at 730), memory device 710 may store the generated error correction or detection information. In some cases, memory device 710 may store error detection or correction information received during the execution of one write operation, error detection or correction information adjusted during the execution of another write operation, and error detection or correction information generated during the execution of a third write operation.

[0139] Figure 8 A block diagram 800 illustrates a memory device 805 that supports error-correcting memory devices with fast data access, according to the examples disclosed herein. The memory device 805 may be as shown in the reference... Figure 1 , 3 Examples of aspects of the memory device described in 6 and 7. Memory device 805 may include a read command receiver 810, a data read manager 815, an error correction component 820, an output manager 825, a write command receiver 830, a data receiver 835, a data storage manager 840, and an error message generator 845. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0140] At the memory device containing the memory array, the read command receiver 810 can receive read commands from the host device. The read command receiver 810 can also receive a second read command from the host device instructing a reread of the memory array based on an error indicator being output to the host device.

[0141] The data read manager 815 can read first data from the memory array based on a read command. In some instances, the data read manager 815 reads third data from the memory array based on a second read command.

[0142] Error correction component 820 can perform an error correction operation on first data to obtain second data and an indicator of errors in the first data. In some instances, error correction component 820 performs a second error correction operation on third data to obtain fourth data. In some cases, the error correction operation corresponds to the SEC operation. Here, the error indicator includes an indication of a corrected unit error in the second data, an indication of an uncorrected error in the second data, an indication of an incorrectly flipped bit in the second data, or a combination thereof. In some other cases, the error correction operation corresponds to the SECDED operation. Here, the error indicator includes an indication of a corrected unit error in the second data, an indication of a detected double-bit error in the second data, an indication of an uncorrected error in the second data, or an indication of an incorrectly flipped bit in the second data, or a combination thereof.

[0143] Output manager 825 can output first data and an error indicator to the host device in parallel with at least a portion of the error correction operation. In some instances, output manager 825 outputs second data at a time determined after the first data is output, based on an error in the first data. In some cases, output manager 825 outputs fourth data to the host device.

[0144] The write command receiver 830 may receive write commands (e.g., a first write command) from the host device at a memory device containing a memory array. In some instances, the write command receiver 830 may receive a second write command from the host device at a memory device.

[0145] The data receiver 835 may receive first data and error detection or correction information associated with the first write command from the host device. In some instances, the data receiver 835 may receive third data and second error correction and detection information based on the second write command from the host device.

[0146] Error correction component 820 can perform error correction operations using received error correction and detection information (e.g., associated with a first write command). In some cases, error correction component 820 adjusts error detection or correction information based on the performance of error correction operations. In some instances, error correction component 820 performs a second error correction operation on third data using second error correction and detection information (e.g., corresponding to a second write command) to obtain fourth data. Error correction component 820 can then generate third error correction and detection information at the memory device based on the fourth data.

[0147] The data storage manager 840 may store second data (e.g., obtained by performing an error correction operation on data associated with a first write command) and received error detection or correction information at the memory array based on a write command. In some instances, the data storage manager 840 may store fourth data (e.g., obtained by performing an error correction operation on data associated with a second write command) and third error correction and detection information at the memory array based on the generation. In some cases, the data storage manager 840 stores adjusted error detection or correction information at the memory array.

[0148] The read command receiver 810 can receive read commands from the host device at the memory device. The data read manager 815 can read second data and error detection or correction information from the memory array based on the read command. In some instances, the error correction component 820 uses the received error detection or correction information to perform error correction operations on the first data to obtain the second data.

[0149] Figure 9 The flowchart illustrates one or more methods 900 supporting an error-correcting memory device with fast data access as disclosed herein. The operation of method 900 can be performed by a memory device (e.g., as referenced). Figure 1 , 3 The method 900 may be implemented by the memory device 110, memory device 310, and memory device 610 disclosed in reference 6) and / or a system (e.g., system 500) or one or more components. For example, the operation of method 900 may be performed by, as described in reference 6. Figure 8 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0150] At 905, the memory device may receive a read command from the host device at a memory device comprising a memory array. The operation of 905 can be performed according to the method described herein. In some instances, aspects of the operation of 905 may be provided as referenced. Figure 8 The described read command is executed by the receiver.

[0151] At 910, the memory device can read first data from the memory array based on a read command. The operation of 910 can be performed according to the method described herein. In some instances, aspects of the operation of 910 can be derived from, as referenced... Figure 8 The described data read manager is executed.

[0152] At 915, the memory device can perform an error correction operation on the first data to obtain second data and an indicator of errors in the first data. The operation of 915 can be performed according to the method described herein. In some instances, aspects of the operation of 915 can be derived from, as referenced... Figure 8 The described error correction component is executed.

[0153] At 920, the memory device may output first data and an error indicator to the host device in parallel with at least a portion of the error correction operation. The operation at 920 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 8 The described output manager performs the 920 operation.

[0154] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a read command from a host device at a memory device comprising a memory array; reading first data from the memory array based on the read command; performing an error correction operation on the first data to obtain second data and an indicator of errors in the first data; and outputting the first data and the error indicator to the host device in parallel with at least a portion of performing the error correction operation.

[0155] Some instances of the method 900 and device described herein may further include operations, features, components, or instructions for outputting second data at a time determined after the first data is output, based on an error in the first data.

[0156] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: receiving a second read command from the host device instructing a reread of the memory array based on an error indicator being output to the host device; reading third data from the memory array based on the second read command; performing a second error correction operation on the third data to obtain fourth data; and outputting the fourth data to the host device.

[0157] In some instances of the method 900 and device described herein, the error correction operation corresponds to the SEC operation.

[0158] In some instances of the method 900 and apparatus described herein, the error indicator includes an indication of a corrected unit error in the second data, an indication of an uncorrected error in the second data, an indication of an incorrectly flipped bit in the second data, or a combination thereof.

[0159] In some instances of the method 900 and device described herein, the error correction operation corresponds to the SECDED operation.

[0160] In some instances of the method 900 and apparatus described herein, the error indicator includes an indication of a corrected unit error in the second data, an indication of a detected double bit error in the second data, an indication of an uncorrected error in the second data, or an indication of an incorrectly flipped bit in the second data, or a combination thereof.

[0161] Figure 10 A flowchart illustrating an example disclosed herein shows one or more methods 1000 supporting an error-correcting memory device with fast data access. Operation of method 1000 may be implemented by a memory device or its components as described herein. For example, operation of method 1000 may be performed as described in reference... Figure 8 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0162] At 1005, the memory device may receive a read command from the host device at a memory device comprising a memory array. The operation of 1005 may be performed according to the method described herein. In some instances, aspects of the operation of 1005 may be derived from, as referenced... Figure 8 The described read command is executed by the receiver.

[0163] At 1010, the memory device can read first data from the memory array based on a read command. The operation of 1010 can be performed according to the methods described herein. In some instances, aspects of the operation of 1010 can be derived from, as referenced... Figure 8 The described data read manager is executed.

[0164] At 1015, the memory device can perform an error correction operation on the first data to obtain second data and an indicator of errors in the first data. The operation of 1015 can be performed according to the methods described herein. In some instances, aspects of the operation of 1015 can be derived from, as referenced... Figure 8 The described error correction component is executed.

[0165] At 1020, the memory device may output first data and an error indicator to the host device in parallel with at least a portion of the error correction operation. The operation of 1020 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 8 The described output manager performs the 1020 operation.

[0166] At point 1025, the memory device can output second data at a time determined after the first data is output, based on an error in the first data. The operation of point 1025 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 8 The described output manager performs 1025 operations.

[0167] Figure 11 A flowchart illustrating an example disclosed herein shows one or more methods 1100 supporting an error-correcting memory device with fast data access. Operation of method 1100 may be implemented by a memory device or its components as described herein. For example, operation of method 1100 may be performed as described in reference... Figure 8 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0168] At 1105, the memory device may receive a write command from the host device at a memory device comprising a memory array. The operation of 1105 may be performed according to the method described herein. In some instances, aspects of the operation of 1105 may be derived from, as referenced... Figure 8 The described write command is executed by the receiver.

[0169] At 1110, the memory device may receive first data and error detection or correction information associated with a write command from the host device. The operation of 1110 may be performed according to the methods described herein. In some instances, aspects of the operation of 1110 may be as described in references... Figure 8 The described data receiver performs the operation.

[0170] At 1115, the memory device can perform an error correction operation on the first data using the received error detection or correction information to obtain the second data. The operation of 1115 can be performed according to the methods described herein. In some instances, aspects of the operation of 1115 can be as described in reference... Figure 8 The described error correction component is executed.

[0171] At 1120, the memory device can store second data and received error detection or correction information at the memory array based on a write command. The operation of 1120 can be performed according to the method described herein. In some instances, aspects of the operation of 1120 can be derived from, as referenced... Figure 8 The described data storage manager is executed.

[0172] In some instances, the device as described herein may perform one or more methods, such as method 1100. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a write command from a host device at a memory device comprising a memory array; receiving first data and error detection or correction information associated with the write command from the host device; performing an error correction operation on the first data using the received error detection or correction information to obtain second data; and storing the second data and the received error detection or correction information at the memory array based on the write command.

[0173] Some examples of the method 1100 and apparatus described herein may further include operations, features, components, or instructions for: receiving a read command from a host device at a memory device; reading second data and error detection or correction information from a memory array based on the read command; and performing a second error correction operation using the received error correction and detection information.

[0174] Some examples of the method 1100 and apparatus described herein may further include operations, features, components, or instructions for: receiving a second write command from a host device at a memory device; receiving third data and second error detection or correction information from the host device based on the second write command; performing a second error correction operation on the third data using the second error detection or correction information to obtain fourth data; generating third error detection or correction information based on the fourth data at a memory device; and storing the fourth data and the third error detection or correction information at a memory array based on the generation.

[0175] Some instances of the method 1100 and apparatus described herein may further include operations, features, components, or instructions for: adjusting error detection or correction information based on performing error correction operations; and storing the adjusted error detection or correction information at a memory array.

[0176] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two (2) or more aspects of the methods described may be combined.

[0177] In some instances, a device corresponding to an error-correcting memory device with fast data access may use general-purpose or special-purpose hardware to perform aspects of the functions described herein. The device may include: an array of memory cells, each including a capacitive storage element; an interface configured to receive a read command from a host device; a first circuit configured to read first data from the array based on the read command; and a second circuit coupled to the first circuit and configured to perform an error-correcting operation on the first data to obtain second data and an indicator of errors in the first data, wherein the interface is configured to transmit the first data and the indicator of errors in the first data to the host device.

[0178] In some instances, the second circuitry can be configured to perform error correction operations on the first data in parallel with the interface transmitting the first data to the host device.

[0179] In some cases, the device may further include: a first buffer coupled to a first circuit and configured to receive first data from the first circuit; a second buffer coupled to a second circuit and configured to receive second data from an error detection circuit; and a multiplexer coupled to the first buffer, the second buffer, and the interface, the multiplexer being configured to output the first data from the first buffer or the second data from the second buffer to the interface based on an error correction operation.

[0180] In some examples, the device may further include a buffer coupled to the interface and configured to receive first data or second data, store the first data or second data in the buffer, and serially output a subset of the stored first data or second data to the interface.

[0181] In some cases, the device may further include a register configured to indicate the output of first data or second data, wherein a buffer is configured to receive first data from a first circuit or second data from a second circuit based on a value stored in the register.

[0182] In some cases, the device may further include memory control configured to couple the buffer to the interface.

[0183] In some instances, the second circuit can be configured to perform a SEC operation or a SECDED operation.

[0184] In some examples, the interface can be configured to transmit first or second data via a first channel, and an error indicator via a second channel.

[0185] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0186] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Accordingly, the voltage of the virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" implies a connection to approximately 0V.

[0187] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be electronically connected (or electrically contacted, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any time. At any given time, the conductive path between components that are electronically connected (or electrically contacted, connected, or coupled) to each other can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0188] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via conductive paths, while in a closed-circuit relationship, signals can be transmitted between components via conductive paths. When a component, such as a controller, couples other components together, the components begin to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0189] The term "isolation" refers to a relationship between components in which signals are currently not allowed to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two (2) components are isolated from each other when the switch is open. When the controller isolates two (2) components from each other, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0190] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0191] The switching assembly or transistor discussed herein may represent a field-effect transistor (FET) and includes a three (3) terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “turned on” or “activated”. When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "disconnected" or "deactivated".

[0192] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0193] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a second reference numeral following the reference numeral with a strikethrough, distinguishing them from each other. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, but not to the second reference numeral.

[0194] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0195] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0196] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0197] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method implemented by a memory device, comprising: A read command is received from a host device outside the memory device at the memory device, which includes a memory array; At least in part, based on the read command, first data and an error control code corresponding to the first data are read from the memory array via a first data path to the error control circuit and via a second data path that bypasses the error control circuit to the buffer; The error is identified in the first data by the error control circuit based at least in part on performing an error correction operation on the first data using the error control code; The first data, corresponding to the error control code and including the error, is output to the host device in parallel with at least a portion of the error correction operation performed using the error control code; as well as The error indicator is output to the host device based at least in part on the error correction operation that identifies the error in the first data.

2. The method according to claim 1, further comprising: The second data is obtained at least in part based on performing the error correction operation on the first data; as well as The second data is output at a time determined after the first data is output, at least in part based on the error in the first data.

3. The method according to claim 1, further comprising: At least in part, based on outputting the error indicator to the host device and receiving a second read command from the host device instructing the memory array to be reread; Third data is read from the memory array, at least in part, based on the second read command; A second error correction operation is performed on the third data to obtain the fourth data; as well as The fourth data is output to the host device.

4. The method of claim 1, wherein the error correction operation corresponds to a single error correction (SEC) operation.

5. The method of claim 4, further comprising: The second data is obtained at least in part based on performing the error correction operation on the first data. The error indicator includes an indication of a corrected unit error in the second data, an indication of an uncorrected error in the second data, an indication of an incorrectly flipped bit in the second data, or a combination thereof.

6. The method of claim 1, wherein the error correction operation corresponds to a single error correction double error detection (SECDED) operation.

7. The method of claim 1, further comprising: The second data is obtained at least in part based on performing the error correction operation on the first data. The error indicator includes an indication of a corrected unit error in the second data, an indication of a detected double bit error in the second data, an indication of an uncorrected error in the second data, or an indication of an incorrectly flipped bit in the second data, or a combination thereof.

8. A memory device comprising: An array of memory cells in a memory device, each including a capacitor storage element; An interface configured to receive read commands from a host device external to the memory device; A first circuit is configured to read first data and an error control code corresponding to the first data from the array via a first data path to a second circuit and to a buffer via a second data path that bypasses the second circuit, at least in part based on the read command. as well as The second circuit, coupled to the first circuit and configured to identify errors in the first data based at least in part on performing an error correction operation on the first data using the error control code, The interface is further configured to: The first data corresponding to the error control code and including the error is transmitted to the host device in parallel with at least a portion of the error correction operation performed using the error control code via the buffer and the second circuit. as well as The error indicator is transmitted to the host device based at least in part on the error correction operation that identifies the error in the first data.

9. The memory device of claim 8, wherein the second circuitry is further configured to obtain the second data at least in part based on performing the error correction operation, the memory device further comprising: A first buffer, which is coupled to the first circuit and configured to receive the first data from the first circuit; A second buffer, which is coupled to the second circuit and configured to receive the second data from the second circuit; as well as A multiplexer coupled to the first buffer, the second buffer, and the interface, the multiplexer being configured to output the first data from the first buffer or the second data from the second buffer to the interface, at least in part based on the error correction operation.

10. The memory device of claim 8, wherein the second circuitry is further configured to obtain second data at least in part based on performing the error correction operation, the memory device further comprising a buffer coupled to the interface and configured to: Receive data including the first data or the second data; The received data is stored in the buffer; and A subset of the received data is serially output to the interface.

11. The memory device of claim 10, further comprising a register configured to indicate the output of the first data or the second data, wherein the buffer is configured to receive the first data from the first circuit or the second data from the second circuit based at least in part on a value stored in the register.

12. The memory device of claim 11, further comprising: A memory controller configured to change the value stored in the register based at least in part on the error in the first data.

13. The memory device of claim 10, further comprising: A multiplexer configured to couple the buffer to the interface.

14. The memory device of claim 8, wherein the second circuit is configured to perform a single error correction (SEC) operation or a single error correction double error detection (SECDED) operation.

15. The memory device according to claim 8, wherein: The second circuit is further configured to obtain the second data at least in part based on performing the error correction operation; and The interface is configured to transmit the first data or the second data via a first channel, and to transmit the error indicator via a second channel.

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