Method of resetting an integrated circuit and integrated circuit

Abstract

The present disclosure provides a method for resetting integrated circuits, comprising: in response to receiving a reset signal for a first data unit, generating a synchronous reset signal according to the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and in response to a first data signal output by the first data unit, generating a second data signal according to the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. The present disclosure also provides an integrated circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor integrated circuits, and in particular, to a method for resetting an integrated circuit and an integrated circuit. BACKGROUND

[0002] With the evolution of technology and accumulation of technology, integrated circuit (IC) design can integrate more and more complex functions onto a chip. Different IP cores integrated in a system on chip (SoC) are generally used to realize different functions of the chip, which also leads to the fact that multiple reset domains are usually covered in a chip.

[0003] Among them, reset is to initialize the sequential device that maintains the state in the circuit, so as to initialize the state of the circuit, IP core, and even the chip. The chip needs to correctly initialize the reset signal of the entire chip circuit to ensure that each part of the internal logic can be initialized when powered on, so that the circuit enters a certain state that can be stably operated. In addition to the global reset of the chip, different IP cores also need to have separate reset functions, which are generally realized by synchronous reset or asynchronous reset. However, asynchronous reset has the possibility of causing output signal metastability because the interval between the reset withdrawal time and the clock active edge is short and the reset recovery time is insufficient. At present, the asynchronous reset synchronous release mode is mostly used to reduce the probability of metastability occurring during reset release.

[0004] However, for two logic modules belonging to different reset domains and having data signal interaction, the data output by one of the logic modules may have metastability when the reset of the logic module takes effect, and there is a possibility of metastability propagation. This metastability propagation has a difficult-to-eliminate security risk and can harm the normal operation of the chip submodules. SUMMARY

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and proposes a method for resetting an integrated circuit and an integrated circuit.

[0006] To achieve the above-mentioned purpose, in a first aspect, an embodiment of the present disclosure provides a method for resetting an integrated circuit, comprising:

[0007] In response to receiving a reset signal of a first data unit, a synchronous reset signal is generated according to the reset signal, and the synchronous reset signal is output to the first data unit after at least one preset period, wherein the reset signal is used to reset the first data unit, and the synchronous reset signal is delayed by N preset periods compared with the reset signal, and N is greater than or equal to 2;

[0008] generate a second data signal according to the synchronous reset signal and the first data signal, and output to a second data unit, wherein the first data signal is received by the second data unit, and the first data unit and the second data unit belong to different reset domains.

[0009] In a second aspect, the embodiments of the present disclosure further provide an integrated circuit, comprising:

[0010] a first data unit;

[0011] a second data unit different from the first data unit in a reset domain;

[0012] a reset clamp unit configured to receive a reset signal received by the first data unit, generate a synchronous reset signal according to the reset signal, and output the synchronous reset signal to the first data unit after at least one preset period, wherein the reset signal is used to reset the first data unit, the synchronous reset signal is delayed by N preset periods compared with the reset signal, and N is greater than or equal to 2; receive a first data signal output by the first data unit, generate a second data signal according to the synchronous reset signal and the first data signal, and output to the second data unit, wherein the first data signal is received by the second data unit.

[0013] The present disclosure has the following beneficial effects:

[0014] The embodiments of the present disclosure provide a reset method of an integrated circuit and an integrated circuit, which can input a reset signal to a corresponding data unit after synchronous processing, process a data signal output by the data unit according to the synchronous reset signal, ensure that the data signal output by the data unit does not contain metastable state when the data unit is reset, and effectively reduce the metastable state transmission risk caused by reset operation across reset domains when a chip is locally reset, thereby improving the reliability of reset operation in different reset domains. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A flowchart of a reset method of an integrated circuit according to the embodiments of the present disclosure is provided.

[0016] Figure 2 A flowchart of another reset method of an integrated circuit according to the embodiments of the present disclosure is provided.

[0017] Figure 3 A structural schematic diagram of an integrated circuit according to the embodiments of the present disclosure is provided.

[0018] Figure 4 A structural schematic diagram of another integrated circuit according to the embodiments of the present disclosure is provided.

[0019] Figure 5 Another structure schematic diagram of an integrated circuit provided by the embodiment of the present disclosure is provided.

[0020] Figure 6 The signal timing diagram when resetting the first data unit in the integrated circuit shown in FIG. 1 is provided. Figure 5 The specific implementation The specific implementation

[0021] In order to enable a person skilled in the art to better understand the technical solutions of the present disclosure, a method for resetting an integrated circuit and an integrated circuit provided by the present disclosure are described in detail below with reference to the drawings.

[0022] In the following, example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to a person skilled in the art.

[0023] The terms used herein are only used to describe specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprise" and / or "consist of" are used in this specification, the specified features, integers, steps, operations, elements, and / or components are present, but that one or more other features, integers, steps, operations, elements, components, and / or groups thereof can also be present.

[0024] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element, and, similarly, a first component or a first module discussed below could be termed a second component or a second module, without departing from the teachings of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] The method and integrated circuit provided by the present disclosure can be used to input the reset signal to the corresponding data unit after synchronization processing, and output a data signal without metastability by the action of the synchronized reset signal and the data signal output by the data unit, thereby effectively reducing the metastability transmission risk caused by the reset operation across the reset domain when the chip performs local reset processing, and improving the reliability of the reset operation in different reset domains.

[0027] Figure 1 A flowchart of a method for resetting an integrated circuit is provided for the embodiments of the present disclosure. As shown in Figure 1 the method comprises:

[0028] Step S1, in response to the reset signal of the receiving object being the first data unit, generating a synchronized reset signal according to the reset signal, and outputting the synchronized reset signal to the first data unit after at least one preset period.

[0029] The reset signal is used to reset the first data unit, wherein the receiving object is the final destination initially designated by the sending end of the signal; the synchronized reset signal is delayed by N preset periods compared to the reset signal, and N is greater than or equal to 2. That is, the reset signal is synchronized for two or more levels to generate a synchronized reset signal, and the first data unit is reset based on the synchronized reset signal.

[0030] The first data unit can be any relatively independent logic unit in the chip for realizing a certain function.

[0031] Specifically, according to the calculation formula of the mean time between failures (MTBF), as follows:

[0032]

[0033] where t r is the longest time that metastability can last, τ and T0 are constants related to the electrical characteristics of the process, f in is the frequency of the input signal, and f clock is the frequency of the synchronization clock, i.e. the frequency of the synchronization clock signal. Generally, the synchronization clock signal is synchronized with the data clock. As can be seen, the mean time between failures is related to the frequency of the synchronization clock signal. In actual application, when the frequency of the synchronization clock signal used is low, two-level synchronization can ensure that the mean time between failures is as long as one hundred years.

[0034] Step S2, in response to the first data signal output by the first data unit, generating a second data signal according to the synchronized reset signal and the first data signal, and outputting the second data signal to the second data unit.

[0035] The first data signal is a signal of specific data generated or forwarded by the first data unit. Similarly to the first data unit, the second data unit can be any logical unit in the chip, which has data interaction with the first data unit, and the first data unit and the second data unit belong to different reset domains. Since local reset is adopted, the corresponding reset signal is different from that of the first data unit. In some embodiments, the first data unit and the second data unit also belong to different power domains or voltage domains.

[0036] The first data signal is a signal of specific data generated or forwarded by the first data unit. Similarly to the first data unit, the second data unit can be any logical unit in the chip, which has data interaction with the first data unit, and the first data unit and the second data unit belong to different reset domains. Since local reset is adopted, the corresponding reset signal is different from that of the first data unit. In some embodiments, the first data unit and the second data unit also belong to different power domains or voltage domains,

[0037] Thus, the method for resetting the integrated circuit provided in the embodiment makes the output signal of the first data unit zero when the first data unit is reset, thereby achieving the purpose of eliminating the metastable state transmission across the reset domains when the integrated circuit is locally reset.

[0038] Figure 2 Another flowchart of a method for resetting an integrated circuit is provided in the embodiments of the present disclosure. As shown in Figure 2 The method is a specific optional implementation of the method shown in Figure 1 Specifically, step S1 includes step S101 and step S102, and step S2 includes step S201. The steps S101, S102 and S201 are described in detail below.

[0039] Step S101 generates a synchronous reset signal according to the reset signal in response to the reset signal input to the reset signal synchronizer.

[0040] In some embodiments, the reset signal synchronizer is an N-stage register synchronizer, and each predetermined period is a period of a synchronous clock signal. In step S101, the step of generating the synchronous reset signal according to the reset signal includes delaying the starting time of the reset signal to a preset trigger edge after N periods of the synchronous clock signal to generate the synchronous reset signal.

[0041] In step S102, the synchronous reset signal is output to the clamp action device, and the synchronous reset signal is output to the first data unit through the flip-flop.

[0042] In some embodiments, in step S102, the step of outputting the synchronous reset signal to the first data unit through the flip-flop comprises: outputting the synchronous reset signal to the first data unit through the flip-flop after delaying a period of the synchronous clock signal.

[0043] In step S201, in response to the synchronous reset signal and the first data signal input to the clamp action device, a second data signal is generated according to the synchronous reset signal and the first data signal.

[0044] In some embodiments, in step S201, the step of generating the second data signal according to the synchronous reset signal and the first data signal comprises: inputting the synchronous reset signal and the first data signal to a clamp gate circuit in the clamp action device to generate the second data signal. The clamp gate circuit is an AND gate circuit suitable for single-bit signals.

[0045] For example, when the reset signal is low, the function of the clamp action device is to ensure that the second data signal is not metastable when sent to the second data unit when the reset signal is low, and remains low, thereby achieving clamping of the reset signal. If the reset signal is high, i.e., the first data unit is not reset, the first data signal output by the first data unit remains at the original level and is input to the second data unit, without affecting the original data path.

[0046] It should be noted that using an AND gate as a clamp gate circuit is only one optional implementation in the present disclosure, which does not limit the technical solutions of the present disclosure. The clamp action device is not limited to an AND gate.

[0047] The method for resetting an integrated circuit provided by the embodiments of the present disclosure can be used to input a reset signal to a corresponding data unit after synchronous processing, clamp the reset signal and a data signal output by the data unit, and ensure that the final output data signal does not contain metastable states when the data unit is reset, thereby effectively reducing the risk of metastable state transmission caused by reset operation across reset domains during local reset processing of a chip, and improving the reliability of reset operation in different reset domains. At the same time, the method is not only suitable for cross-reset-domain logic in a general case, but also suitable for scenarios of reset operation on IP cores in different reset domains. The method is suitable for data units in different power domains or different voltage domains. The method does not need to increase circuit modules, units and devices in a reset domain receiving data, and does not need to additionally control the reset signal, which is simple, efficient and widely applicable.

[0048] Figure 3 A structure diagram of an integrated circuit is provided for an embodiment of the present disclosure. As shown in the diagram, the integrated circuit comprises a first data unit, a reset clamp unit and a second data unit. Figure 3

[0049] The first data unit and the second data unit belong to different reset domains.

[0050] The reset clamp unit is configured to receive a reset signal with the first data unit as the receiving object, generate a synchronous reset signal according to the reset signal, and output the synchronous reset signal to the first data unit after at least one preset period. The reset signal is used to reset the first data unit, and the synchronous reset signal is delayed by N preset periods compared with the reset signal, where N is greater than or equal to 2. The reset clamp unit is also configured to receive a first data signal output by the first data unit, generate a second data signal according to the synchronous reset signal and the first data signal, and output the second data signal to the second data unit. The first data signal has the second data unit as the receiving object.

[0051] It should be noted that an integrated circuit can include multiple units, and any two units in different reset domains and requiring data signal transmission can be the first data unit and the second data unit in the present disclosure. In addition, each IP core integrated in a system-level chip can also be a data unit in the present disclosure. The above embodiment is only an optional implementation provided for the convenience of description, and it does not limit the technical solution of the present disclosure, nor the first data unit and the second data unit in the technical solution.

[0052] Figure 4 Another structure diagram of an integrated circuit is provided for an embodiment of the present disclosure. As shown in the diagram, the structure is based on Figure 4 Figure 3 As shown in the diagram, the structure is based on Figure 3 On the basis shown in the diagram, the reset clamp unit comprises a reset signal synchronizer and a clamp action device.

[0053] The reset signal synchronizer is configured to receive the reset signal and generate a synchronous reset signal according to the reset signal. The reset signal synchronizer is also configured to output the synchronous reset signal to the clamp action device, and output the synchronous reset signal to the first data unit through a flip-flop.

[0054] In some embodiments, the reset signal synchronizer is an N-stage register synchronizer. Each predetermined period is a period of a synchronous clock signal. The reset signal synchronizer is configured to delay the starting time of the reset signal to a preset trigger edge after N periods of the synchronous clock signal to generate the synchronous reset signal. The synchronous reset signal is output to the first data unit after being delayed by one period of the synchronous clock signal through the flip-flop. ​​

[0055] The clamp action device receives the synchronous reset signal and the first data signal, generates the second data signal according to the synchronous reset signal and the first data signal, and outputs to the second data unit.

[0056] In some embodiments, the clamp action device inputs the synchronous reset signal and the first data signal into a clamp gate circuit of the clamp action device to generate the second data signal.

[0057] In some embodiments, the reset clamp unit further comprises the above-mentioned patting device, or the above-mentioned patting device is disposed in the reset signal synchronizer.

[0058] The method of resetting the integrated circuit provided by the present disclosure is described in detail below in combination with actual applications.

[0059] Figure 5 Another structure diagram of an integrated circuit provided by an embodiment of the present disclosure is shown in FIG. 4. Figure 5 As shown in FIG. 4, the integrated circuit comprises a first data unit, a reset clamp unit, and a second data unit. The first data unit comprises three registers and a certain amount of combinational logic (not shown in the figure); the reset clamp unit comprises a reset signal synchronizer, a patting device, and a clamp action device, the reset signal synchronizer is composed of D flip-flops, the stage number N=2, the input bit width is 1 bit, the patting device, i.e. the patting register, is realized by a D flip-flop, and the clamp gate circuit in the clamp action device adopts an AND logic gate; the second data unit belongs to a different reset domain from the first data unit, and comprises a plurality of registers. Figure 5 Each rectangular block (D flip-flop) in the figure is a register, wherein CLK represents the entrance of a synchronous clock signal (CLK1), D represents a data signal input end, and Q represents a data signal output end.

[0060] Figure 6 A signal timing diagram when resetting the first data unit in the integrated circuit shown in FIG. 4 is shown in FIG. 5. Figure 5 As shown in FIG. 5, the first data unit is reset by the reset signal (RST1) and the synchronous reset signal (RST2). Figure 5 and Figure 6As shown, in the reset clamp unit, the reset signal synchronizer generates a synchronous reset signal (RST_A_0) by delaying the starting time of the reset signal to the rising edge of the synchronous clock signal after two periods in response to receiving a first reset signal (RST_A) of the first data unit, and outputs the synchronous reset signal to the pulser and the clamp actuator. It can be seen that the reset signal and the synchronous clock signal are in different clock domains, the reset signal changes from high to low at a certain time within the first period of the synchronous clock signal, and the reset signal is low valid. The synchronous reset signal is the reset signal after two levels of synchronization, which is output by the rising edge trigger in the third period of the synchronous clock signal. The pulser generates a second reset signal (RST_A_1) by delaying the synchronous reset signal for one period of the synchronous clock signal, and outputs the second reset signal to the first data unit. The second reset signal is output in the fourth period of the synchronous clock signal by the pulser for the second reset signal.

[0061] For the first data unit, the second reset signal is received and reset, and at the same time, the initial data signal (DATA0) of a single bit is output as the first data signal (DATA1) through three registers and a certain amount of combination logic. Since the reset of each register is asynchronous in the fourth period of the synchronous clock signal, the first data signal has a metastable state (X state). The first data unit outputs the first data signal to the clamp actuator, and the clamp actuator inputs the received synchronous reset signal and the first data signal into the clamp gate circuit to generate the second data signal (DATA2) and output it to the second data unit. The first data signal and the synchronous reset signal which is pulled low in the third period of the synchronous clock signal are processed by the AND logic gate, and the output second data signal does not have a metastable state.

[0062] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the apparatuses can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is common knowledge to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0063] Example embodiments have been disclosed herein and, although the use of specific terms is expressly used herein, they are intended in a generic sense only and, in no way, should be construed as limiting. In some instances, features, characteristics or elements described in connection with a particular embodiment can be used in conjunction with, or in place of, features, characteristics or elements described in connection with other embodiments, unless expressly stated otherwise. Accordingly, one of ordinary skill in the art will recognize that the various forms and details of the disclosure can be varied, without departing from the spirit or essential characteristics thereof.

Claims

1. A method for resetting an integrated circuit, wherein, include: In response to a reset signal received by a first data unit, a synchronous reset signal is generated based on the reset signal, and then output to the first data unit after at least one preset period. The reset signal is used to reset the first data unit, and the synchronous reset signal is delayed by N preset periods compared to the reset signal, where N is greater than or equal to 2. In response to the first data signal output by the first data unit, a second data signal is generated based on the synchronous reset signal and the first data signal, and output to the second data unit, wherein the receiving object of the first data signal is the second data unit, and the first data unit and the second data unit belong to different reset domains; The step of responding to a reset signal received by a first data unit, generating a synchronous reset signal based on the reset signal, and then outputting the synchronous reset signal to the first data unit after at least one preset period includes: In response to the reset signal input to the reset signal synchronizer, the synchronous reset signal is generated based on the reset signal; the synchronous reset signal is output to the clamping actuator, and the synchronous reset signal is output to the first data unit via the beater; The step of generating a second data signal based on the synchronization reset signal and the first data signal in response to the first data signal output by the first data unit, and outputting it to the second data unit, includes: In response to the synchronous reset signal and the first data signal input to the clamping actuator, the second data signal is generated based on the synchronous reset signal and the first data signal.

2. The method according to claim 1, wherein, The reset signal synchronizer is an N-stage register synchronizer; each predetermined period is the period of a synchronization clock signal; The step of generating the synchronous reset signal based on the reset signal includes: The start time of the reset signal is delayed to a preset trigger edge N cycles after the synchronous clock signal to generate the synchronous reset signal.

3. The method according to claim 1, wherein, The step of outputting the synchronous reset signal to the first data unit via the beater includes: The synchronous reset signal is delayed by one synchronous clock cycle by a beater and then output to the first data unit.

4. The method according to claim 1, wherein, The step of generating the second data signal based on the synchronous reset signal and the first data signal includes: The synchronous reset signal and the first data signal are input into the clamping gate circuit in the clamping actuator to generate the second data signal.

5. An integrated circuit, wherein, include: First data unit; A second data unit that belongs to a different reset domain from the first data unit; A reset clamping unit is configured to receive a reset signal whose receiving object is the first data unit, generate a synchronous reset signal based on the reset signal, and output the synchronous reset signal to the first data unit after at least one preset period, wherein the reset signal is used to reset the first data unit, and the synchronous reset signal is delayed by N preset periods compared to the reset signal, where N is greater than or equal to 2; receive a first data signal output by the first data unit, generate a second data signal based on the synchronous reset signal and the first data signal, and output it to the second data unit, wherein the receiving object of the first data signal is the second data unit; The reset clamping unit includes: a reset signal synchronizer and a clamping actuator; The reset signal synchronizer is used to receive the reset signal, generate the synchronized reset signal according to the reset signal, output the synchronized reset signal to the clamping actuator, and output the synchronized reset signal to the first data unit via the beater. The clamping actuator is used to receive the synchronous reset signal and the first data signal, generate the second data signal according to the synchronous reset signal and the first data signal, and output it to the second data unit.

6. The integrated circuit according to claim 5, wherein, The reset signal synchronizer is an N-stage register synchronizer; each predetermined period is the period of a synchronization clock signal; The reset signal synchronizer is used to delay the start time of the reset signal to a preset trigger edge N cycles after the synchronous clock signal in order to generate the synchronous reset signal.

7. The integrated circuit according to claim 5, wherein, The reset signal synchronizer is used to output the synchronous reset signal to the first data unit after delaying it by one synchronous clock signal period via a timer.

8. The integrated circuit according to claim 5, wherein, The clamping actuator is used to input the synchronous reset signal and the first data signal into its own clamping gate circuit to generate the second data signal.

Images