Pixel circuit, display device and driving method

Abstract

The embodiment of the invention provides a pixel circuit, a display device and a driving method. A driving transistor; the first control circuit is coupled with the first node and a set electrode of the driving transistor, responds to a signal of a first control signal end, and controls the first node to be conducted with the set electrode of the driving transistor; the set electrode is a grid electrode or a second electrode of the driving transistor; the data write-in circuit responds to a signal of a scanning signal end and provides a data voltage signal of a data signal end to a first node; the coupling control circuit is coupled with the first node and the grid electrode of the driving transistor, and couples a signal of the first node to the grid electrode of the driving transistor; the second control circuit is coupled with the grid electrode and the second electrode of the driving transistor, responds to a signal of a second control signal end, and controls the grid electrode and the second electrode of the driving transistor to be conducted; the first light-emitting control circuit responds to a signal of the first light-emitting control signal end, and the second electrode of the driving transistor is connected with the light-emitting device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to pixel circuits, display devices, and driving methods. Background Technology

[0002] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) are among the light-emitting devices that possess advantages such as self-illumination and low energy consumption, making them a hot topic in current display device application research. Generally, pixel circuits are used in display devices to drive the light-emitting devices to emit light. Summary of the Invention

[0003] The pixel circuit provided in this embodiment includes:

[0004] Light-emitting devices;

[0005] A driving transistor, coupled to the light-emitting device, is configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage signal;

[0006] A first control circuit, coupled to a first node and a set terminal of the driving transistor, is configured to control the first node and the set terminal of the driving transistor to conduct in response to a signal at a first control signal terminal; the set terminal is the gate of the driving transistor or the second terminal of the driving transistor.

[0007] The data writing circuit, coupled to the first node, is configured to provide the data voltage signal from the data signal terminal to the first node in response to a signal from the scan signal terminal.

[0008] A coupling control circuit, coupled to the first node and the gate of the driving transistor, is configured to couple a signal from the first node to the gate of the driving transistor.

[0009] The second control circuit, coupled to the gate and the second electrode of the driving transistor, is configured to control the gate of the driving transistor to conduct and the second electrode of the driving transistor in response to a signal at the second control signal terminal.

[0010] A first light-emitting control circuit, coupled to the second terminal of the driving transistor and the light-emitting device, is configured to conduct the second terminal of the driving transistor and the light-emitting device in response to a signal at the first light-emitting control signal terminal.

[0011] In some possible implementations, the first control circuit includes: a first transistor;

[0012] The gate of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the first node, and the second terminal of the first transistor is coupled to the set terminal of the driving transistor.

[0013] In some possible implementations, the active layer of the first transistor is made of low-temperature polycrystalline silicon.

[0014] In some possible implementations, the second control circuit includes: a second transistor;

[0015] The gate of the second transistor is coupled to the second control signal terminal, the first terminal of the second transistor is coupled to the gate of the driving transistor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor.

[0016] In some possible implementations, the active layer of the second transistor is made of a metal-oxide-semiconductor material.

[0017] In some possible implementations, the coupling control circuit includes:

[0018] A first coupling control circuit, coupled to the first node and the second node, is configured to couple the signal from the first node to the second node;

[0019] A second coupling control circuit, coupled to the second node and the gate of the driving transistor, is configured to couple a signal from the second node to the gate of the driving transistor.

[0020] In some possible implementations, the first coupling control circuit includes: a first capacitor;

[0021] The first electrode of the first capacitor is coupled to the first node, and the second electrode of the first capacitor is coupled to the second node.

[0022] In some possible implementations, the second coupling control circuit includes: a second capacitor;

[0023] The first electrode of the second capacitor is coupled to the second node, and the second electrode of the second capacitor is coupled to the gate of the driving transistor.

[0024] In some possible implementations, a third control circuit is also included;

[0025] The third control circuit is coupled to the second node and is configured to provide a signal from the reference voltage signal terminal to the second node in response to a signal from the third control signal terminal.

[0026] In some possible implementations, the third control circuit includes: a third transistor;

[0027] The gate of the third transistor is coupled to the third control signal terminal, the first terminal of the third transistor is coupled to the second node, and the second terminal of the third transistor is coupled to the reference voltage signal terminal.

[0028] In some possible implementations, the active layer of the third transistor is made of a metal-oxide-semiconductor material.

[0029] In some possible implementations, the data writing circuit includes a fourth transistor;

[0030] The gate of the fourth transistor is coupled to the scan signal terminal, the first terminal of the fourth transistor is coupled to the data signal terminal, and the second terminal of the fourth transistor is coupled to the first node.

[0031] In some possible implementations, the first light-emitting control circuit includes: a fifth transistor;

[0032] The gate of the fifth transistor is coupled to the first light-emitting control signal terminal, the first terminal of the fifth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth transistor is coupled to the light-emitting device.

[0033] In some possible implementations, it further includes: a first initialization circuit coupled to the first node, configured to provide a signal from the first initialization signal terminal to the first node in response to a signal from the first reset signal terminal.

[0034] In some possible implementations, the first initialization circuit includes: a sixth transistor;

[0035] The gate of the sixth transistor is coupled to the first reset signal terminal, the first terminal of the sixth transistor is coupled to the first node, and the second terminal of the sixth transistor is coupled to the first initialization signal terminal.

[0036] In some possible implementations, a second initialization circuit, coupled to the light-emitting device, is further included, configured to provide a signal from the second initialization signal terminal to the light-emitting device in response to a signal from the second reset signal terminal.

[0037] In some possible implementations, the second initialization circuit includes a seventh transistor;

[0038] The gate of the seventh transistor is coupled to the second reset signal terminal, the first terminal of the seventh transistor is coupled to the light-emitting device, and the second terminal of the seventh transistor is coupled to the second initialization signal terminal.

[0039] In some possible implementations, a third initialization circuit, coupled to the first terminal of the driving transistor, is further included, configured to provide a signal from the third initialization signal terminal to the first terminal of the driving transistor in response to a signal from the third reset signal terminal.

[0040] In some possible implementations, the third initialization circuit includes: an eighth transistor;

[0041] The gate of the eighth transistor is coupled to the third reset signal terminal, the first terminal of the eighth transistor is coupled to the first terminal of the driving transistor, and the second terminal of the eighth transistor is coupled to the third initialization signal terminal.

[0042] In some possible implementations, a second light-emitting control circuit is further included, coupled to the first terminal of the driving transistor, and configured to provide a signal from the first power supply terminal to the first terminal of the driving transistor in response to a signal from the second light-emitting control signal terminal.

[0043] In some possible implementations, the second light-emitting control circuit includes: a ninth transistor;

[0044] The gate of the ninth transistor is coupled to the second light-emitting control signal terminal, the first terminal of the ninth transistor is coupled to the first power supply terminal, and the second terminal of the ninth transistor is coupled to the first terminal of the driving transistor.

[0045] The display device provided in this disclosure includes the pixel circuit described above.

[0046] This disclosure provides a driving method for the above-described pixel circuit, including: an initialization phase, a threshold voltage compensation phase, a data writing phase, and a light emission phase;

[0047] During the initialization phase, the first control circuit responds to the signal at the first control signal terminal and controls the first node to be connected to the set terminal of the driving transistor; the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be connected to the second terminal of the driving transistor; the first light-emitting control circuit responds to the signal at the first light-emitting control signal terminal and connects the second terminal of the driving transistor to the light-emitting device.

[0048] During the threshold voltage compensation phase, the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be turned on with the second terminal of the driving transistor.

[0049] During the data writing phase, the data writing circuit responds to the signal at the scan signal terminal by providing the data voltage signal at the data signal terminal to the first node; the second control circuit responds to the signal at the second control signal terminal by controlling the gate of the driving transistor to be connected to the second terminal of the driving transistor; the coupling control circuit couples the signal of the first node to the gate of the driving transistor.

[0050] During the light-emitting phase, the first light-emitting control circuit responds to the signal at the first light-emitting control signal terminal by connecting the second terminal of the driving transistor to the light-emitting device. Attached Figure Description

[0051] Figure 1 Some schematic diagrams of pixel circuits provided in the embodiments of this disclosure;

[0052] Figure 2 These are some other schematic diagrams of the pixel circuit provided in the embodiments of this disclosure;

[0053] Figure 3 Further schematic diagrams of the pixel circuit provided in embodiments of this disclosure;

[0054] Figure 4 Some signal timing diagrams provided for embodiments of this disclosure;

[0055] Figure 5 A flowchart of a pixel circuit driving method provided in an embodiment of this disclosure;

[0056] Figure 6 Further schematic diagrams of the pixel circuit provided in embodiments of this disclosure;

[0057] Figure 7 Other signal timing diagrams provided for embodiments of this disclosure;

[0058] Figure 8 Further schematic diagrams of the pixel circuit provided in embodiments of this disclosure;

[0059] Figure 9 Further schematic diagrams of the pixel circuit provided in embodiments of this disclosure;

[0060] Figure 10 Further signal timing diagrams provided for embodiments of this disclosure;

[0061] Figure 11 Further schematic diagrams of the pixel circuit provided in embodiments of this disclosure;

[0062] Figure 12 Further signal timing diagrams are provided for embodiments of this disclosure. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0065] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0066] The display device provided in this disclosure includes: a display panel, wherein the display area of ​​the display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixels. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0067] In this embodiment, each sub-pixel includes a pixel circuit, which includes a driving transistor and a light-emitting device to control the light-emitting device to emit light, thereby enabling the display panel to display an image. Due to process technology and device aging, the threshold voltage Vth of the driving transistor that drives the light-emitting device to emit light may be non-uniform. This causes the current flowing through different light-emitting devices to vary, resulting in uneven display brightness and affecting the overall image display effect.

[0068] Components in a pixel circuit can generally be tested using an array test (AT). For example, the data signal terminal of the pixel circuit is connected to a detection device (e.g., a current sensor). By detecting the current at the data signal terminal, it can be determined whether the pixel circuit meets the requirements. If the detected current value is less than or equal to a preset value, then the requirements are met. The preset value can be selected based on the specific requirements. For example, if the pixel circuit has high requirements, the preset value can be smaller; if the pixel circuit has low requirements, the preset value can be larger.

[0069] In the prior art, for discrete pixel circuits, it is impossible to directly detect the gate of the driving transistor in the pixel circuit. As a result, it is impossible to determine whether there is an abnormality in the driving transistor, and thus it is impossible to repair the pixel circuit immediately. This may lead to the discovery that the pixel circuit is not working properly when the manufacturing process after the pixel circuit is completed (e.g., the manufacturing process of the light-emitting device), resulting in wasted costs and higher manufacturing costs for the display panel.

[0070] To address the aforementioned problems, the pixel circuit provided in this disclosure embodiment, such as... Figure 1 As shown, it includes:

[0071] Light-emitting devices;

[0072] The driving transistor T0 is coupled to the light-emitting device L and is configured to generate a driving current to drive the light-emitting device L to emit light according to the data voltage signal.

[0073] The first control circuit 10 is coupled to the first node N1 and the set terminal of the driving transistor T0, and is configured to control the first node N1 and the set terminal of the driving transistor T0 to be turned on in response to the signal of the first control signal terminal CS1; the set terminal is the second terminal of the driving transistor T0.

[0074] The data writing circuit 20, coupled to the first node N1, is configured to provide the data voltage signal of the data signal terminal DA to the first node N1 in response to the signal of the scan signal terminal SS1.

[0075] The coupling control circuit 30, coupled to the gate of the first node N1 and the driving transistor T0, is configured to couple the signal of the first node N1 to the gate of the driving transistor T0.

[0076] The second control circuit 40 is coupled to the gate and the second terminal of the driving transistor T0 and is configured to control the gate of the driving transistor T0 to be turned on and the second terminal of the driving transistor T0 in response to the signal of the second control signal terminal CS2.

[0077] The first light-emitting control circuit 50 is coupled to the second terminal of the driving transistor T0 and the light-emitting device L, and is configured to conduct the second terminal of the driving transistor T0 and the light-emitting device L in response to the signal of the first light-emitting control signal terminal EM1.

[0078] The embodiments disclosed herein can achieve direct detection of the gate of the driving transistor through the mutual cooperation of the first control circuit, the data writing circuit, the coupling control circuit, the second control circuit and the first light emission control circuit. That is, the gate of the driving transistor can be directly detected through array testing, and each component in the pixel circuit can also be tested through array testing, thereby achieving yield monitoring of the pixel circuit, reducing the risk of loss, avoiding cost waste, and thus reducing the impact of process fluctuations on display effect.

[0079] Furthermore, through the cooperation of the first control circuit, the data writing circuit, the coupling control circuit, the second control circuit, and the first light-emitting control circuit, the threshold voltage compensation of the driving transistor and the data voltage signal writing are performed separately. As a result, the threshold voltage compensation time of the driving transistor is not limited by the data voltage signal writing, and the threshold voltage compensation process can be carried out for a longer time, which is beneficial to the stability of the threshold voltage of the driving transistor. This enables high frame rate display and avoids the impact of threshold voltage drift of the driving transistor on the light emission of the light-emitting device, thereby improving the image quality of high frame rate display.

[0080] In some embodiments of this disclosure, such as Figure 1 As shown, the driving transistor T0 can be configured as a P-type transistor; its first terminal can be its source, and its second terminal can be its drain. When the driving transistor T0 is in saturation, current flows from its source to its drain. Of course, the driving transistor T0 can also be configured as an N-type transistor; this is not a limitation.

[0081] In the embodiments disclosed herein, such as Figure 1As shown, the first electrode of the light-emitting device L can be coupled to the second electrode of the driving transistor T0 through the first light-emitting control circuit 50. The second electrode of the light-emitting device L can be coupled to the second power supply terminal VSS. In some examples, the first electrode of the light-emitting device L can be its anode, and the second electrode can be its cathode. Exemplarily, the light-emitting device L can be an organic light-emitting diode. For example, the light-emitting device L can include at least one of: a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). Exemplarily, the light-emitting device L can include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In practical applications, the specific structure of the light-emitting device L can be designed and determined according to the actual application environment, and is not limited here.

[0082] In the embodiments disclosed herein, such as Figure 2 As shown, the coupling control circuit 30 includes: a first coupling control circuit 301 and a second coupling control circuit 302; wherein, the first coupling control circuit 301 is coupled to the first node N1 and the second node N2, and is configured to couple the signal of the first node N1 to the second node N2; the second coupling control circuit 302 is coupled to the second node N2 and the gate of the driving transistor T0, and is configured to couple the signal of the second node N2 to the gate of the driving transistor T0.

[0083] In the embodiments disclosed herein, such as Figure 3 As shown, the first coupling control circuit 301 includes: a first capacitor C1; wherein, the first electrode of the first capacitor C1 is coupled to the first node N1, and the second electrode of the first capacitor C1 is coupled to the second node N2.

[0084] In the embodiments disclosed herein, such as Figure 3 As shown, the second coupling control circuit 302 includes: a second capacitor C2; wherein, the first electrode of the second capacitor C2 is coupled to the second node N2, and the second electrode of the second capacitor C2 is coupled to the gate of the driving transistor T0.

[0085] In the embodiments disclosed herein, such as Figure 3 As shown, the first control circuit 10 includes: a first transistor T1; wherein, the gate of the first transistor T1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor T1 is coupled to the first node N1, and the second electrode of the first transistor T1 is coupled to the set electrode of the driving transistor T0.

[0086] For example, the first transistor T1 can be turned on under the control of the effective level of the first control signal transmitted at the first control signal terminal CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the first transistor T1 is set as a P-type transistor, then the effective level of the first control signal is low and the ineffective level of the first control signal is high. Alternatively, if the first transistor T1 is set as an N-type transistor, then the effective level of the first control signal is high and the ineffective level of the first control signal is low.

[0087] In this embodiment of the disclosure, the active layer of the first transistor T1 is made of low-temperature polycrystalline silicon.

[0088] It should be noted that transistors using low-temperature polysilicon (LTPS) as the active layer have high mobility and can be made thinner, smaller, and consume less power. In specific implementations, the active layer material of the first transistor T1 is set to low-temperature polysilicon. This allows the first transistor T1 to be configured as an LTPS type transistor, enabling the pixel circuit to achieve high mobility, thinner and smaller design, and lower power consumption.

[0089] In the embodiments disclosed herein, such as Figure 3 As shown, the second control circuit 20 includes: a second transistor T2; wherein the gate of the second transistor T2 is coupled to the second control signal terminal CS2, the first terminal of the second transistor T2 is coupled to the gate of the driving transistor T0, and the second terminal of the second transistor T2 is coupled to the second terminal of the driving transistor T0.

[0090] For example, the second transistor T2 can be turned on under the control of the effective level of the second control signal transmitted at the second control signal terminal CS2, and can be turned off under the control of the ineffective level of the second control signal. For example, if the second transistor T2 is set as a P-type transistor, then the effective level of the second control signal is low, and the ineffective level of the second control signal is high. Alternatively, if the second transistor T2 is set as an N-type transistor, then the effective level of the second control signal is high, and the ineffective level of the second control signal is low.

[0091] In this embodiment of the disclosure, the active layer of the second transistor T2 is made of metal oxide semiconductor material.

[0092] It should be noted that transistors with metal-oxide-semiconductor (MODS) materials as the active layer have relatively low leakage current. Therefore, in order to reduce leakage current, in some embodiments of this disclosure, the active layer material of the second transistor T2 may also include MODS materials, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials may also be used, and this is not limited here. This allows the second transistor T2 to be configured as an oxide thin-film transistor, thereby reducing the leakage current of the pixel circuit.

[0093] In the embodiments disclosed herein, such as Figure 3 As shown, it also includes: a third control circuit 60; wherein the third control circuit 60 is coupled to the second node N2 and is configured to provide the reference voltage signal Vref to the second node N2 in response to the signal of the third control signal terminal CS3.

[0094] In the embodiments disclosed herein, such as Figure 3 As shown, the third control circuit 60 includes: a third transistor T3; wherein, the gate of the third transistor T3 is coupled to the third control signal terminal CS3, the first terminal of the third transistor T3 is coupled to the second node N2, and the second terminal of the third transistor T3 is coupled to the reference voltage signal terminal Vref.

[0095] For example, the third transistor T3 can be turned on under the control of the effective level of the third control signal transmitted at the third control signal terminal CS3, and can be turned off under the control of the ineffective level of the third control signal. For example, if the third transistor T3 is set as a P-type transistor, then the effective level of the third control signal is low, and the ineffective level of the third control signal is high. Alternatively, if the third transistor T3 is set as an N-type transistor, then the effective level of the third control signal is high, and the ineffective level of the third control signal is low.

[0096] For example, the second control signal terminal CS2 and the third control signal terminal CS3 can be loaded with the same signal. This configuration simplifies the wiring layout, reduces the difficulty of wiring, and saves space.

[0097] For example, the reference voltage signal terminal Vref and the first power supply terminal VDD can be loaded with the same signal. This configuration simplifies the wiring layout, reduces the difficulty of wiring, and saves space.

[0098] In this embodiment of the disclosure, the active layer of the third transistor T3 is made of metal oxide semiconductor material.

[0099] It should be noted that transistors with metal-oxide-semiconductor (MODS) materials as active layers have relatively low leakage current. Therefore, in order to reduce leakage current, in some embodiments of this disclosure, the active layer material of the third transistor T3 may also include MODS materials, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials may also be used, and this is not limited here. This allows the third transistor T3 to be configured as an oxide thin-film transistor, thereby reducing the leakage current of the pixel circuit.

[0100] In the embodiments disclosed herein, such as Figure 3 As shown, the data writing circuit 20 includes: a fourth transistor T4; wherein, the gate of the fourth transistor T4 is coupled to the scan signal terminal SS1, the first terminal of the fourth transistor T4 is coupled to the data signal terminal DA, and the second terminal of the fourth transistor T4 is coupled to the first node N1.

[0101] For example, the fourth transistor T4 can be turned on under the control of the effective level of the scan signal transmitted at the scan signal terminal SS1, and can be turned off under the control of the ineffective level of the scan signal. For example, if the fourth transistor T4 is set as a P-type transistor, the effective level of the scan signal is low and the ineffective level of the scan signal is high. Alternatively, if the fourth transistor T4 is set as an N-type transistor, the effective level of the scan signal is high and the ineffective level of the scan signal is low.

[0102] In the embodiments disclosed herein, such as Figure 3 As shown, the first light-emitting control circuit 50 includes: a fifth transistor T5; wherein, the gate of the fifth transistor T5 is coupled to the first light-emitting control signal terminal EM1, the first terminal of the fifth transistor T5 is coupled to the second terminal of the driving transistor T0, and the second terminal of the fifth transistor T5 is coupled to the light-emitting device L.

[0103] For example, the fifth transistor T5 can be turned on under the control of the effective level of the first light-emitting control signal transmitted at the first light-emitting control signal terminal EM1, and can be turned off under the control of the ineffective level of the first light-emitting control signal. For example, if the fifth transistor T5 is set as a P-type transistor, then the effective level of the first light-emitting control signal is low, and the ineffective level of the first light-emitting control signal is high. Alternatively, if the fifth transistor T5 is set as an N-type transistor, then the effective level of the first light-emitting control signal is high, and the ineffective level of the first light-emitting control signal is low.

[0104] In the embodiments disclosed herein, such as Figure 3As shown, it also includes: a first initialization circuit 70, coupled to the first node N1, configured to provide the signal of the first initialization signal terminal Vinit1 to the first node N1 in response to the signal of the first reset signal terminal RE1.

[0105] In the embodiments disclosed herein, such as Figure 3 As shown, the first initialization circuit 70 includes: a sixth transistor T6; wherein, the gate of the sixth transistor T6 is coupled to the first reset signal terminal RE1, the first terminal of the sixth transistor T6 is coupled to the first node N1, and the second terminal of the sixth transistor T6 is coupled to the first initialization signal terminal Vinit1.

[0106] For example, the first reset signal terminal RE1 and the first light emission control signal terminal EM1 can be loaded with the same signal. This configuration simplifies the wiring layout, reduces the difficulty of wiring, and saves space.

[0107] For example, the sixth transistor T6 can be turned on under the control of the effective level of the first reset signal transmitted at the first reset signal terminal RE1, and can be turned off under the control of the ineffective level of the first reset signal. For example, if the sixth transistor T6 is set as a P-type transistor, then the effective level of the first reset signal is low, and the ineffective level of the first reset signal is high. Alternatively, if the sixth transistor T6 is set as an N-type transistor, then the effective level of the first reset signal is high, and the ineffective level of the first reset signal is low.

[0108] In the embodiments disclosed herein, such as Figure 3 As shown, it also includes: a second initialization circuit 80, coupled to the light-emitting device L, configured to provide the signal of the second initialization signal terminal Vinit2 to the light-emitting device L in response to the signal of the second reset signal terminal RE2.

[0109] In the embodiments disclosed herein, such as Figure 3 As shown, the second initialization circuit 80 includes: a seventh transistor T7; wherein, the gate of the seventh transistor T7 is coupled to the second reset signal terminal RE2, the first terminal of the seventh transistor T7 is coupled to the light-emitting device L, and the second terminal of the seventh transistor T7 is coupled to the second initialization signal terminal Vinit2.

[0110] For example, the seventh transistor T7 can be turned on under the control of the effective level of the second reset signal transmitted at the second reset signal terminal RE2, and can be turned off under the control of the ineffective level of the second reset signal. For example, if the seventh transistor T7 is set as a P-type transistor, then the effective level of the second reset signal is low, and the ineffective level of the second reset signal is high. Alternatively, if the seventh transistor T7 is set as an N-type transistor, then the effective level of the second reset signal is high, and the ineffective level of the second reset signal is low.

[0111] For example, the second transistor T2 and the third transistor T3 can be configured as oxide transistors, while the driving transistor T0, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be configured as LTPS transistors. By combining the processes of LTPS and oxide transistors in fabricating the LTPO pixel driving circuit, the leakage current of the gate of the driving transistor T0 can be reduced, resulting in lower power consumption.

[0112] In this embodiment, the first power supply terminal VDD can be configured to load a constant first power supply voltage vdd, and the first power supply voltage vdd is generally positive. Similarly, the second power supply terminal VSS can load a constant second power supply voltage vss, and the second power supply voltage vss is generally ground voltage or a negative value. In practical applications, the specific values ​​of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, and are not limited here.

[0113] In the embodiments disclosed herein, such as Figure 4 As shown, the driving method for the pixel circuit provided in this embodiment includes: an initialization stage F1, a threshold voltage compensation stage F2, a data writing stage F3, and a light emission stage F4.

[0114] like Figure 5 As shown, it may include the following steps:

[0115] S100. During the initialization phase, the first control circuit responds to the signal at the first control signal terminal and controls the first node to be connected to the set terminal of the driving transistor; the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be connected to the second terminal of the driving transistor; the first light-emitting control circuit responds to the signal at the first light-emitting control signal terminal and connects the second terminal of the driving transistor to the light-emitting device.

[0116] S200. During the threshold voltage compensation stage, the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be turned on with the second terminal of the driving transistor.

[0117] S300. During the data writing phase, the data writing circuit responds to the signal at the scan signal terminal and provides the data voltage signal at the data signal terminal to the first node; the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be turned on with the second terminal of the driving transistor; the coupling control circuit couples the signal of the first node to the gate of the driving transistor.

[0118] S400. During the light-emitting stage, the first light-emitting control circuit responds to the signal at the first light-emitting control signal terminal and connects the second electrode of the driving transistor to the light-emitting device.

[0119] For example, such as Figure 4 As shown, the driving method for the pixel circuit provided in this embodiment of the present disclosure further includes a reset stage F5 located between the threshold voltage compensation stage F2 and the light emission stage F4. In the reset stage F5, the second initialization circuit responds to the signal of the second reset signal terminal and provides the signal of the second initialization signal terminal to the light emission device.

[0120] The following is based on Figure 3 Taking the pixel circuit shown as an example, combined with Figure 4 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiments of this disclosure.

[0121] In the embodiments disclosed herein, such as Figure 4 As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, ss1 represents the scan signal of the scan signal terminal SS1, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, re1 represents the first reset signal of the first reset signal terminal RE1, and re2 represents the second reset signal of the second reset signal terminal RE2.

[0122] Furthermore, select the initialization phase F1, threshold voltage compensation phase F2, data writing phase F3, reset phase F5, and light emission phase F4 in a display frame 1H.

[0123] During the initialization phase F1, the first transistor T1 is turned on under the low level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light emission control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, and the seventh transistor T7 is turned off under the high level control of the second reset signal RE2. The sixth transistor T6, which is turned on, provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value of the first node VN1 = vini1, where vini1 represents the voltage value of the signal of the first initialization signal terminal Vinit1; the first transistor T1, which is turned on, controls the first node N1 to be connected to the second terminal of the driving transistor T0, so the voltage value of the second terminal of the driving transistor T0 is vini1; the second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0, so the voltage value of the gate of the driving transistor T0 is vini1; the fifth transistor T5, which is turned on, connects the second terminal of the driving transistor T0 to the light-emitting device L; the third transistor T3, which is turned on, provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value of the second node VN2 = vref, where vref represents the voltage value of the signal of the reference voltage signal terminal Vref.

[0124] During the threshold voltage compensation stage F2, the first transistor T1 is turned off under the high level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal Re1, and the seventh transistor T7 is turned on under the low level control of the second reset signal Re2. The turned-on second transistor T2 controls the gate and the second terminal of the driving transistor T0 to conduct; the turned-on third transistor T3 provides the signal of the reference voltage signal terminal Vref to the second node N2; then, the voltage values ​​of the gate and the second terminal of the driving transistor T0 are both Vdd + Vth, where Vdd represents the voltage value of the signal at the first power supply terminal, and Vth represents the threshold voltage of the driving transistor T0; the turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light-emitting device L.

[0125] During the data writing phase F3, the first transistor T1 is turned off under the high level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned on under the low level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, and the seventh transistor T7 is turned off under the high level control of the second reset signal RE2. The turned-on second transistor T2 controls the gate of the driving transistor T0 to conduct with the second terminal of the driving transistor T0; the turned-on third transistor T3 provides the reference voltage signal Vref to the second node N2; the turned-on fourth transistor T4 provides the data voltage signal DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0.

[0126] During the reset phase F5, the first transistor T1 is turned off under the high level control of the first control signal CS1, the second transistor T2 is turned off under the low level control of the second control signal CS2, the third transistor T3 is turned off under the low level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, and the seventh transistor T7 is turned on under the low level control of the second reset signal RE2. The turned-on seventh transistor T7 provides the signal from the second initialization signal terminal Vinit2 to the light-emitting device L.

[0127] During the light-emitting phase F4, the first transistor T1 is cut off under the high level control of the first control signal CS1, the second transistor T2 is cut off under the low level control of the second control signal CS2, the third transistor T3 is cut off under the low level control of the third control signal CS3, the fourth transistor T4 is cut off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light-emitting control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, and the seventh transistor T7 is cut off under the high level control of the second reset signal RE2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1; the turned-on fifth transistor T5 connects the second terminal of the driving transistor T0 with the light-emitting device L; the driving transistor T0 generates a driving current, which charges the anode of the light-emitting device L until the light-emitting device L emits light stably.

[0128] This disclosure provides other structural schematic diagrams of pixel driving circuits, such as... Figure 6 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; their general similarities will not be repeated here.

[0129] In the embodiments disclosed herein, such as Figure 6 As shown, the set electrode is the gate of the driving transistor T0; the second electrode of the first transistor T1 is coupled to the gate of the driving transistor T0.

[0130] In this embodiment of the disclosure, the active layer of the first transistor T1 is made of metal oxide semiconductor material.

[0131] It should be noted that transistors with metal-oxide-semiconductor (MODS) materials as active layers have relatively low leakage current. Therefore, to reduce leakage current, in this embodiment, the active layer of the first transistor T1 can also be made of MODS materials, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials can also be used, and this is not limited here. This allows the first transistor T1 to be configured as an oxide thin-film transistor, thereby reducing the leakage current of the pixel circuit.

[0132] For example, the first transistor T1, the second transistor T2, and the third transistor T3 can be configured as oxide transistors, while the driving transistor T0, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be configured as LTPS transistors. By combining the processes of LTPS and oxide transistors in fabricating the LTPO pixel driving circuit, the leakage current of the gate of the driving transistor T0 can be reduced, resulting in lower power consumption.

[0133] The following is based on Figure 6 Taking the pixel circuit shown as an example, combined with Figure 7 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiments of this disclosure.

[0134] In the embodiments disclosed herein, such as Figure 7As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, ss1 represents the scan signal of the scan signal terminal SS1, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, re1 represents the first reset signal of the first reset signal terminal RE1, and re2 represents the second reset signal of the second reset signal terminal RE2.

[0135] Furthermore, select the initialization phase F1, threshold voltage compensation phase F2, data writing phase F3, reset phase F5, and light emission phase F4 in a display frame 1H.

[0136] During the initialization phase F1, the first transistor T1 is turned on under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scan signal ss1, the fifth transistor T5 is turned on under the low level control of the first light emission control signal em1, the sixth transistor T6 is turned on under the low level control of the first reset signal re1, and the seventh transistor T7 is turned off under the high level control of the second reset signal re2. The sixth transistor T6, which is turned on, provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value of the first node VN1 = vini1; the first transistor T1, which is turned on, controls the first node N1 to be connected to the gate of the driving transistor T0, so the voltage value of the gate of the driving transistor T0 is vini1; the second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0, so the voltage value of the second terminal of the driving transistor T0 is vini1; the fifth transistor T5, which is turned on, connects the second terminal of the driving transistor T0 to the light-emitting device L; the third transistor T3, which is turned on, provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value of the second node VN2 = vref.

[0137] During the threshold voltage compensation stage F2, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal Re1, and the seventh transistor T7 is turned on under the low level control of the second reset signal Re2. The turned-on second transistor T2 controls the gate and the second terminal of the driving transistor T0 to conduct; the turned-on third transistor T3 provides the reference voltage signal Vref to the second node N2; therefore, the voltage values ​​of the gate and the second terminal of the driving transistor T0 are both Vdd + Vth; the turned-on seventh transistor T7 provides the second initialization signal Vinit2 to the light-emitting device L.

[0138] During the data writing phase F3, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned on under the low level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, and the seventh transistor T7 is turned off under the high level control of the second reset signal RE2. The turned-on second transistor T2 controls the gate of the driving transistor T0 to conduct with the second terminal of the driving transistor T0; the turned-on third transistor T3 provides the reference voltage signal Vref to the second node N2; the turned-on fourth transistor T4 provides the data voltage signal DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0.

[0139] During the reset phase F5, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned off under the low level control of the second control signal CS2, the third transistor T3 is turned off under the low level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, and the seventh transistor T7 is turned on under the low level control of the second reset signal RE2. The turned-on seventh transistor T7 provides the signal from the second initialization signal terminal Vinit2 to the light-emitting device L.

[0140] During the light-emitting phase F4, the first transistor T1 is cut off under the low level control of the first control signal CS1, the second transistor T2 is cut off under the low level control of the second control signal CS2, the third transistor T3 is cut off under the low level control of the third control signal CS3, the fourth transistor T4 is cut off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light-emitting control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, and the seventh transistor T7 is cut off under the high level control of the second reset signal RE2. The turned-on sixth transistor T6 provides the signal of the first initialization signal terminal Vinit1 to the first node N1; the turned-on fifth transistor T5 connects the second terminal of the driving transistor T0 with the light-emitting device L; the driving transistor T0 generates a driving current, which charges the anode of the light-emitting device L until the light-emitting device L emits light stably.

[0141] This disclosure provides some structural schematic diagrams of pixel driving circuits, such as... Figure 8 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; their general similarities will not be repeated here.

[0142] In the embodiments disclosed herein, such as Figure 8 As shown, it also includes: a third initialization circuit 90, coupled to the first terminal of the driving transistor T0, configured to provide the signal of the third initialization signal terminal Vinit3 to the first terminal of the driving transistor T0 in response to the signal of the third reset signal terminal RE3.

[0143] In the embodiments disclosed herein, such as Figure 9 As shown, the third initialization circuit 90 includes: an eighth transistor T8; wherein, the gate of the eighth transistor T8 is coupled to the third reset signal terminal RE3, the first terminal of the eighth transistor T8 is coupled to the first terminal of the driving transistor T0, and the second terminal of the eighth transistor T8 is coupled to the third initialization signal terminal Vinit3.

[0144] For example, the eighth transistor T8 can be turned on under the control of the effective level of the third reset signal transmitted at the third reset signal terminal RE3, and can be turned off under the control of the ineffective level of the third reset signal. For example, if the eighth transistor T8 is set as a P-type transistor, then the effective level of the third reset signal is low, and the ineffective level of the third reset signal is high. Alternatively, if the eighth transistor T8 is set as an N-type transistor, then the effective level of the third reset signal is high, and the ineffective level of the third reset signal is low.

[0145] For example, the second reset signal terminal RE2 and the third reset signal terminal RE3 can be loaded with the same signal. This configuration simplifies the wiring layout, reduces the difficulty of wiring, and saves space.

[0146] In the embodiments disclosed herein, such as Figure 8 As shown, it also includes: a second light-emitting control circuit 100, coupled to the first terminal of the driving transistor T0, configured to provide the signal of the first power supply terminal VDD to the first terminal of the driving transistor T0 in response to the signal of the second light-emitting control signal terminal EM2.

[0147] In the embodiments disclosed herein, such as Figure 9 As shown, the second light-emitting control circuit 100 includes: a ninth transistor T9; wherein, the gate of the ninth transistor T9 is coupled to the second light-emitting control signal terminal EM2, the first terminal of the ninth transistor T9 is coupled to the first power supply terminal VDD, and the second terminal of the ninth transistor T9 is coupled to the first terminal of the driving transistor T0.

[0148] For example, the ninth transistor T9 can be turned on under the control of the effective level of the second light-emitting control signal transmitted at the second light-emitting control signal terminal EM2, and can be turned off under the control of the ineffective level of the second light-emitting control signal. For example, if the ninth transistor T9 is set as a P-type transistor, then the effective level of the second light-emitting control signal is low, and the ineffective level of the second light-emitting control signal is high. Alternatively, if the ninth transistor T9 is set as an N-type transistor, then the effective level of the second light-emitting control signal is high, and the ineffective level of the second light-emitting control signal is low.

[0149] For example, the second transistor T2 and the third transistor T3 can be configured as oxide transistors, while the driving transistor T0, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be configured as LTPS transistors. By combining the processes of LTPS and oxide transistors in fabricating the LTPO pixel driving circuit, the leakage current of the gate of the driving transistor T0 can be reduced, and the power consumption can be lowered.

[0150] The following is based on Figure 9 Taking the pixel circuit shown as an example, combined with Figure 10 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiments of this disclosure.

[0151] In the embodiments disclosed herein, such as Figure 10As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, ss1 represents the scan signal of the scan signal terminal SS1, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, em2 represents the second light emission control signal of the second light emission control signal terminal EM2, re1 represents the first reset signal of the first reset signal terminal RE1, re2 represents the second reset signal of the second reset signal terminal RE2, and re3 represents the third reset signal of the third reset signal terminal RE3.

[0152] Furthermore, select the initialization phase F1, threshold voltage compensation phase F2, data writing phase F3, reset phase F5, and light emission phase F4 in a display frame 1H.

[0153] During the initialization phase F1, the first transistor T1 is turned on under the low level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light emission control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, the seventh transistor T7 is turned off under the high level control of the second reset signal RE2, the eighth transistor T8 is turned off under the high level control of the third reset signal RE3, and the ninth transistor T9 is turned off under the high level control of the second light emission control signal EM2. The sixth transistor T6, which is turned on, provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value of the first node VN1 = vini1; the first transistor T1, which is turned on, controls the first node N1 to be connected to the second terminal of the driving transistor T0, so the voltage value of the second terminal of the driving transistor T0 is vini1; the second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0, so the voltage value of the gate of the driving transistor T0 is vini1; the fifth transistor T5, which is turned on, connects the second terminal of the driving transistor T0 to the light-emitting device L; the third transistor T3, which is turned on, provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value of the second node VN2 = vref.

[0154] During the threshold voltage compensation stage F2, the first transistor T1 is turned off under the high level control of the first control signal cs1, the second transistor T2 is turned on under the high level control of the second control signal cs2, the third transistor T3 is turned on under the high level control of the third control signal cs3, the fourth transistor T4 is turned off under the high level control of the scan signal ss1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal em1, the sixth transistor T6 is turned off under the high level control of the first reset signal re1, the seventh transistor T7 is turned on under the low level control of the second reset signal re2, the eighth transistor T8 is turned on under the low level control of the third reset signal re3, and the ninth transistor T9 is turned on under the low level control of the second light emission control signal em2. The second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0; the third transistor T3, which is turned on, provides the reference voltage signal Vref to the second node N2; then, the voltage values ​​of the gate and the second terminal of the driving transistor T0 are both vdd+vth; the seventh transistor T7, which is turned on, provides the second initialization signal Vinit2 to the light-emitting device L; the eighth transistor T8, which is turned on, provides the third initialization signal Vinit3 to the first terminal of the driving transistor T0; the ninth transistor T9, which is turned on, provides the first power supply signal VDD to the first terminal of the driving transistor T0.

[0155] During the data writing phase F3, the first transistor T1 is turned off under the high level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned on under the low level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, the seventh transistor T7 is turned off under the high level control of the second reset signal RE2, the eighth transistor T8 is turned off under the high level control of the third reset signal RE3, and the ninth transistor T9 is turned on under the low level control of the second light emission control signal EM2. The second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0; the third transistor T3, which is turned on, provides the signal of the reference voltage signal terminal Vref to the second node N2; the fourth transistor T4, which is turned on, provides the data voltage signal of the data signal terminal DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0; the ninth transistor T9, which is turned on, provides the signal of the first power supply terminal VDD to the first terminal of the driving transistor T0.

[0156] During the reset phase F5, the first transistor T1 is turned off under the high level control of the first control signal CS1, the second transistor T2 is turned off under the low level control of the second control signal CS2, the third transistor T3 is turned off under the low level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, the seventh transistor T7 is turned on under the low level control of the second reset signal RE2, the eighth transistor T8 is turned on under the low level control of the third reset signal RE3, and the ninth transistor T9 is turned off under the high level control of the second light emission control signal EM2. The turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light-emitting device L; the turned-on eighth transistor T8 provides the signal of the third initialization signal terminal Vinit3 to the first terminal of the driving transistor T0.

[0157] During the light-emitting stage F4, the first transistor T1 is turned off under the high level control of the first control signal CS1, the second transistor T2 is turned off under the low level control of the second control signal CS2, the third transistor T3 is turned off under the low level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light-emitting control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, the seventh transistor T7 is turned off under the high level control of the second reset signal RE2, the eighth transistor T8 is turned off under the high level control of the third reset signal RE3, and the ninth transistor T9 is turned on under the low level control of the second light-emitting control signal EM2. The sixth transistor T6, which is turned on, provides the signal of the first initialization signal terminal Vinit1 to the first node N1; the ninth transistor T9, which is turned on, provides the signal of the first power supply terminal VDD to the first terminal of the driving transistor T0; the fifth transistor T5, which is turned on, connects the second terminal of the driving transistor T0 to the light-emitting device L; the driving transistor T0 generates a driving current, which charges the anode of the light-emitting device L until the light-emitting device L emits light stably.

[0158] This disclosure provides some structural schematic diagrams of pixel driving circuits, such as... Figure 11 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; their general similarities will not be repeated here.

[0159] In the embodiments disclosed herein, such as Figure 11 As shown, the set electrode is the gate of the driving transistor T0; the second electrode of the first transistor T1 is coupled to the gate of the driving transistor T0.

[0160] In this embodiment of the disclosure, the active layer of the first transistor T1 is made of metal oxide semiconductor material.

[0161] It should be noted that transistors with metal-oxide-semiconductor (MODS) materials as active layers have relatively low leakage current. Therefore, to reduce leakage current, in this embodiment, the active layer of the first transistor T1 can also be made of MODS materials, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials can also be used, and this is not limited here. This allows the first transistor T1 to be configured as an oxide thin-film transistor, thereby reducing the leakage current of the pixel circuit.

[0162] For example, the first transistor T1, the second transistor T2, and the third transistor T3 can be configured as oxide-type transistors, while the driving transistor T0, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be configured as LTPS-type transistors. By combining the processes of LTPS-type transistors and oxide-type transistors to fabricate the LTPO pixel driving circuit of low-temperature polycrystalline silicon oxide, the leakage current of the gate of the driving transistor T0 can be reduced, and the power consumption can be lowered.

[0163] The following is based on Figure 11 Taking the pixel circuit shown as an example, combined with Figure 12 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiments of this disclosure.

[0164] In the embodiments disclosed herein, such as Figure 12 As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, ss1 represents the scan signal of the scan signal terminal SS1, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, em2 represents the second light emission control signal of the second light emission control signal terminal EM2, re1 represents the first reset signal of the first reset signal terminal RE1, re2 represents the second reset signal of the second reset signal terminal RE2, and re3 represents the third reset signal of the third reset signal terminal RE3.

[0165] Furthermore, select the initialization phase F1, threshold voltage compensation phase F2, data writing phase F3, reset phase F5, and light emission phase F4 in a display frame 1H.

[0166] During the initialization phase F1, the first transistor T1 is turned on under the high level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light emission control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, the seventh transistor T7 is turned off under the high level control of the second reset signal RE2, the eighth transistor T8 is turned off under the high level control of the third reset signal RE3, and the ninth transistor T9 is turned off under the high level control of the second light emission control signal EM2. The sixth transistor T6, which is turned on, provides the signal of the first initialization signal terminal Vinit1 to the first node N1, so the voltage value of the first node VN1 = vini1; the first transistor T1, which is turned on, controls the first node N1 to be connected to the second terminal of the driving transistor T0, so the voltage value of the second terminal of the driving transistor T0 is vini1; the second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0, so the voltage value of the gate of the driving transistor T0 is vini1; the fifth transistor T5, which is turned on, connects the second terminal of the driving transistor T0 to the light-emitting device L; the third transistor T3, which is turned on, provides the signal of the reference voltage signal terminal Vref to the second node N2, so the voltage value of the second node VN2 = vref.

[0167] During the threshold voltage compensation stage F2, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, the seventh transistor T7 is turned on under the low level control of the second reset signal RE2, the eighth transistor T8 is turned on under the low level control of the third reset signal RE3, and the ninth transistor T9 is turned on under the low level control of the second light emission control signal EM2. The second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0; the third transistor T3, which is turned on, provides the reference voltage signal Vref to the second node N2; then, the voltage values ​​of the gate and the second terminal of the driving transistor T0 are both vdd+vth; the seventh transistor T7, which is turned on, provides the second initialization signal Vinit2 to the light-emitting device L; the eighth transistor T8, which is turned on, provides the third initialization signal Vinit3 to the first terminal of the driving transistor T0; the ninth transistor T9, which is turned on, provides the first power supply signal VDD to the first terminal of the driving transistor T0.

[0168] During the data writing phase F3, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned on under the high level control of the second control signal CS2, the third transistor T3 is turned on under the high level control of the third control signal CS3, the fourth transistor T4 is turned on under the low level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, the seventh transistor T7 is turned off under the high level control of the second reset signal RE2, the eighth transistor T8 is turned off under the high level control of the third reset signal RE3, and the ninth transistor T9 is turned on under the low level control of the second light emission control signal EM2. The second transistor T2, which is turned on, controls the gate of the driving transistor T0 to be connected to the second terminal of the driving transistor T0; the third transistor T3, which is turned on, provides the signal of the reference voltage signal terminal Vref to the second node N2; the fourth transistor T4, which is turned on, provides the data voltage signal of the data signal terminal DA to the first node N1; the first capacitor C1 couples the signal of the first node N1 to the second node N2, and the second capacitor C2 couples the signal of the second node N2 to the gate of the driving transistor T0; the ninth transistor T9, which is turned on, provides the signal of the first power supply terminal VDD to the first terminal of the driving transistor T0.

[0169] During the reset phase F5, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned off under the low level control of the second control signal CS2, the third transistor T3 is turned off under the low level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned off under the high level control of the first light emission control signal EM1, the sixth transistor T6 is turned off under the high level control of the first reset signal RE1, the seventh transistor T7 is turned on under the low level control of the second reset signal RE2, the eighth transistor T8 is turned on under the low level control of the third reset signal RE3, and the ninth transistor T9 is turned off under the high level control of the second light emission control signal EM2. The turned-on seventh transistor T7 provides the signal of the second initialization signal terminal Vinit2 to the light-emitting device L; the turned-on eighth transistor T8 provides the signal of the third initialization signal terminal Vinit3 to the first terminal of the driving transistor T0.

[0170] During the light-emitting stage F4, the first transistor T1 is turned off under the low level control of the first control signal CS1, the second transistor T2 is turned off under the low level control of the second control signal CS2, the third transistor T3 is turned off under the low level control of the third control signal CS3, the fourth transistor T4 is turned off under the high level control of the scan signal SS1, the fifth transistor T5 is turned on under the low level control of the first light-emitting control signal EM1, the sixth transistor T6 is turned on under the low level control of the first reset signal RE1, the seventh transistor T7 is turned off under the high level control of the second reset signal RE2, the eighth transistor T8 is turned off under the high level control of the third reset signal RE3, and the ninth transistor T9 is turned on under the low level control of the second light-emitting control signal EM2. The sixth transistor T6, which is turned on, provides the signal of the first initialization signal terminal Vinit1 to the first node N1; the ninth transistor T9, which is turned on, provides the signal of the first power supply terminal VDD to the first terminal of the driving transistor T0; the fifth transistor T5, which is turned on, connects the second terminal of the driving transistor T0 to the light-emitting device L; the driving transistor T0 generates a driving current, which charges the anode of the light-emitting device L until the light-emitting device L emits light stably.

[0171] The above are merely examples illustrating the specific structures of the various circuits in the pixel circuit provided in the embodiments of the present invention. In specific implementations, the specific structures of the circuits are not limited to those provided in the embodiments of the present invention, and may also be other structures known to those skilled in the art. These are all within the protection scope of the present invention, and are not specifically limited here.

[0172] Based on the same disclosed concept, this disclosure also provides a display device, including the display panel described above. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repetitions will not be repeated here.

[0173] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0174] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0175] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A pixel circuit, wherein, include: Light-emitting devices; A driving transistor, coupled to the light-emitting device, is configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage signal; A first control circuit, coupled to a first node and a set terminal of the driving transistor, is configured to control the first node and the set terminal of the driving transistor to be turned on in response to a signal at a first control signal terminal. The setting is the gate of the driving transistor or the second electrode of the driving transistor; The data writing circuit, coupled to the first node, is configured to provide the data voltage signal from the data signal terminal to the first node in response to a signal from the scan signal terminal. A coupling control circuit, coupled to the first node and the gate of the driving transistor, is configured to couple a signal from the first node to the gate of the driving transistor. The second control circuit, coupled to the gate and the second electrode of the driving transistor, is configured to control the gate of the driving transistor to conduct and the second electrode of the driving transistor in response to a signal at the second control signal terminal. A first light-emitting control circuit, coupled to the second terminal of the driving transistor and the light-emitting device, is configured to conduct the second terminal of the driving transistor and the light-emitting device in response to a signal at the first light-emitting control signal terminal.

2. The pixel circuit as described in claim 1, wherein, The first control circuit includes: a first transistor; The gate of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the first node, and the second terminal of the first transistor is coupled to the set terminal of the driving transistor.

3. The pixel circuit as described in claim 2, wherein, The active layer of the first transistor is made of low-temperature polycrystalline silicon.

4. The pixel circuit as described in claim 1, wherein, The second control circuit includes: a second transistor; The gate of the second transistor is coupled to the second control signal terminal, the first terminal of the second transistor is coupled to the gate of the driving transistor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor.

5. The pixel circuit as described in claim 4, wherein, The active layer of the second transistor is made of metal oxide semiconductor material.

6. The pixel circuit according to any one of claims 1-5, wherein, The coupling control circuit includes: A first coupling control circuit, coupled to the first node and the second node, is configured to couple the signal from the first node to the second node; A second coupling control circuit, coupled to the second node and the gate of the driving transistor, is configured to couple a signal from the second node to the gate of the driving transistor.

7. The pixel circuit as described in claim 6, wherein, The first coupling control circuit includes: a first capacitor; The first electrode of the first capacitor is coupled to the first node, and the second electrode of the first capacitor is coupled to the second node.

8. The pixel circuit as described in claim 6, wherein, The second coupling control circuit includes: a second capacitor; The first electrode of the second capacitor is coupled to the second node, and the second electrode of the second capacitor is coupled to the gate of the driving transistor.

9. The pixel circuit according to any one of claims 6-8, wherein, Also includes: Third control circuit; The third control circuit is coupled to the second node and is configured to provide a signal from the reference voltage signal terminal to the second node in response to a signal from the third control signal terminal.

10. The pixel circuit as claimed in claim 9, wherein, The third control circuit includes: a third transistor; The gate of the third transistor is coupled to the third control signal terminal, the first terminal of the third transistor is coupled to the second node, and the second terminal of the third transistor is coupled to the reference voltage signal terminal.

11. The pixel circuit as claimed in claim 10, wherein, The active layer of the third transistor is made of metal oxide semiconductor material.

12. The pixel circuit according to any one of claims 1-11, wherein, The data writing circuit includes: a fourth transistor; The gate of the fourth transistor is coupled to the scan signal terminal, the first terminal of the fourth transistor is coupled to the data signal terminal, and the second terminal of the fourth transistor is coupled to the first node.

13. The pixel circuit as claimed in claim 1, wherein, The first light-emitting control circuit includes: a fifth transistor; The gate of the fifth transistor is coupled to the first light-emitting control signal terminal, the first terminal of the fifth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth transistor is coupled to the light-emitting device.

14. The pixel circuit according to any one of claims 1-13, wherein, It also includes: a first initialization circuit, coupled to the first node, configured to provide a signal from the first initialization signal terminal to the first node in response to a signal from the first reset signal terminal.

15. The pixel circuit as claimed in claim 14, wherein, The first initialization circuit includes: a sixth transistor; The gate of the sixth transistor is coupled to the first reset signal terminal, the first terminal of the sixth transistor is coupled to the first node, and the second terminal of the sixth transistor is coupled to the first initialization signal terminal.

16. The pixel circuit according to any one of claims 1-15, wherein, It also includes: a second initialization circuit, coupled to the light-emitting device, configured to provide the signal of the second initialization signal terminal to the light-emitting device in response to a signal of the second reset signal terminal.

17. The pixel circuit of claim 16, wherein, The second initialization circuit includes: a seventh transistor; The gate of the seventh transistor is coupled to the second reset signal terminal, the first terminal of the seventh transistor is coupled to the light-emitting device, and the second terminal of the seventh transistor is coupled to the second initialization signal terminal.

18. The pixel circuit according to any one of claims 1-17, wherein, It also includes: a third initialization circuit, coupled to the first pole of the driving transistor, configured to provide a signal from the third initialization signal terminal to the first pole of the driving transistor in response to a signal from the third reset signal terminal.

19. The pixel circuit as claimed in claim 18, wherein, The third initialization circuit includes: an eighth transistor; The gate of the eighth transistor is coupled to the third reset signal terminal, the first terminal of the eighth transistor is coupled to the first terminal of the driving transistor, and the second terminal of the eighth transistor is coupled to the third initialization signal terminal.

20. The pixel circuit according to any one of claims 1-19, wherein, Also includes: The second light-emitting control circuit, coupled to the first terminal of the driving transistor, is configured to provide a signal from the first power supply terminal to the first terminal of the driving transistor in response to a signal from the second light-emitting control signal terminal.

21. The pixel circuit as claimed in claim 20, wherein, The second light-emitting control circuit includes: a ninth transistor; The gate of the ninth transistor is coupled to the second light-emitting control signal terminal, the first terminal of the ninth transistor is coupled to the first power supply terminal, and the second terminal of the ninth transistor is coupled to the first terminal of the driving transistor.

22. A display device, wherein, Includes the pixel circuit as described in any one of claims 1-21.

23. A driving method for a pixel circuit as described in any one of claims 1-21, wherein, include: The process includes the initialization phase, the threshold voltage compensation phase, the data writing phase, and the light emission phase. During the initialization phase, the first control circuit responds to the signal at the first control signal terminal and controls the first node to be connected to the set terminal of the driving transistor; the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be connected to the second terminal of the driving transistor; the first light-emitting control circuit responds to the signal at the first light-emitting control signal terminal and connects the second terminal of the driving transistor to the light-emitting device. During the threshold voltage compensation phase, the second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be turned on with the second terminal of the driving transistor. During the data writing phase, the data writing circuit responds to the signal at the scan signal terminal by providing the data voltage signal at the data signal terminal to the first node; The second control circuit responds to the signal at the second control signal terminal and controls the gate of the driving transistor to be turned on with the second terminal of the driving transistor; The coupling control circuit couples the signal from the first node to the gate of the driving transistor. During the light-emitting phase, the first light-emitting control circuit responds to the signal at the first light-emitting control signal terminal by connecting the second terminal of the driving transistor to the light-emitting device.

Images