Data drive and display device including data drive

Abstract

A data driver and a display device including the data driver are provided. The data driver includes a signal generator and a channel driver. The signal generator includes a stepped waveform grayscale voltage signal generator, which generates multiple stepped waveform grayscale voltage signals using a minimum gamma reference voltage, a maximum gamma reference voltage, and multiple gamma voltages having a magnitude between the minimum and maximum gamma reference voltages. The channel driver includes a decoder that outputs a stepped waveform grayscale voltage signal selected from the multiple stepped waveform grayscale voltage signals, an output circuit that outputs a grayscale voltage corresponding to the selected stepped waveform grayscale voltage signal, and a reset unit that supplies one of the multiple gamma voltages to the output circuit as a reset voltage.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2020-0100137, filed on August 10, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This invention relates to a data driver and a display device including a data driver. Background Technology

[0003] With the development of information technology, the importance of display devices, which serve as a connection medium between users and information, has increased. Therefore, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0004] The display device may include pixels connected to scan lines and data lines, a scan driver for driving scan lines, a data driver for driving data lines, a grayscale voltage generator for supplying grayscale voltage to the data driver, and a timing controller for supplying image data to the data driver.

[0005] The data driver can use grayscale voltages for each channel to generate data voltages corresponding to the input image data. In this case, each channel may include a decoder (or multiplexer) for selecting one grayscale voltage from multiple grayscale voltages that corresponds to the image data. The area occupied by the decoder in the channel can be increased proportionally to the number of grayscale levels to be represented.

[0006] To reduce the area occupied by the decoder in the channel, a method has been proposed to convert multiple grayscale voltages along the time axis to generate grouped stepped waveform grayscale voltage signals (hereinafter referred to as ramp signals) and supply the ramp signals to the decoder. Summary of the Invention

[0007] However, in methods of supplying the ramp signal of the packets to the decoder of the data driver, the operation of selecting and maintaining either of the ramp signal to generate the data voltage (or sample / hold operation) can be performed within a horizontal time unit. In this case, in the display device, when a large voltage difference occurs, for example, when the gray level changes from a high gray level (gray level of 255) to a low gray level (gray level of zero) or from a low gray level (gray level of zero) to a high gray level (gray level of 255) in each horizontal time unit, the current consumption of the sample / hold operation may increase.

[0008] Furthermore, in order to stably perform the sample / hold operation, it is desirable to reach the gray level corresponding to the selected ramp signal within at least 1 / 16 of the horizontal time period ((1 / 16)H), and the ramp signal is difficult to stabilize when the current consumption decreases. Therefore, the linearity of the ramp signal may be disrupted.

[0009] Embodiments of the present invention provide a data driver capable of reducing average current consumption during sample / hold operations by supplying the decoder with a smaller number of ramp signals than the number of grayscale voltages.

[0010] Another aspect of the invention provides a data driver capable of maintaining the linearity of the ramp signal during sample / hold operations by supplying the decoder with a ramp signal quantity smaller than the grayscale voltage quantity.

[0011] However, it should be understood that the aspects of the present invention are not limited to the foregoing, but can be extended in various ways without departing from the spirit and scope of the present invention.

[0012] To address the above problems, the data driver according to an embodiment of the present invention includes a signal generator and a channel driver. The signal generator includes a stepped waveform grayscale voltage signal generator, which generates multiple stepped waveform grayscale voltage signals using a minimum gamma reference voltage, a maximum gamma reference voltage, and multiple gamma voltages having a magnitude between the minimum and maximum gamma reference voltages. The channel driver includes a decoder that outputs a stepped waveform grayscale voltage signal selected from the multiple stepped waveform grayscale voltage signals, an output circuit that outputs a grayscale voltage corresponding to the selected stepped waveform grayscale voltage signal, and a reset unit that supplies one of the multiple gamma voltages to the output circuit as a reset voltage.

[0013] The decoder can select one stepped waveform grayscale voltage signal from multiple stepped waveform grayscale voltage signals in each horizontal time period.

[0014] The reset voltage can be one of a plurality of gamma voltages, corresponding to the intermediate value between the final grayscale voltage of a stepped waveform grayscale voltage signal selected in the previous horizontal time period and the initial grayscale voltage of a stepped waveform grayscale voltage signal selected in the current horizontal time period.

[0015] The reset unit can use the high bits of the image data supplied to the decoder to detect a stepped waveform grayscale voltage signal selected in the previous horizontal time period and a stepped waveform grayscale voltage signal selected in the current horizontal time period.

[0016] The reset unit can supply a reset voltage to the output circuit in each horizontal time period, and can supply the reset voltage to the output circuit before a stepped waveform grayscale voltage signal selected by the decoder is supplied to the output circuit.

[0017] Each of the multiple stepped waveform grayscale voltage signals with multiple grayscale voltages can be gradually increased in each horizontal time period.

[0018] Each of the multiple stepped waveform grayscale voltage signals with multiple grayscale voltages can be gradually increased and decreased alternately at every horizontal time interval.

[0019] The signal generator may also include a pulse width modulation (PWM) signal generation circuit, which generates multiple PWM signals based on digital codes generated from oscillating signals.

[0020] The PWM signal generation circuit may include an oscillator, a frequency divider, a code generator, and a PWM signal generator, wherein the oscillator generates an oscillating signal, the frequency divider divides the frequency of the oscillating signal with a constant division ratio and generates an oscillating signal with the divided frequency, the code generator counts the oscillating signal with the divided frequency and generates a digital code as the result of the count, and the PWM signal generator generates multiple PWM signals in response to the digital code.

[0021] The channel driver may also include a switch signal generation circuit that generates multiple switch signals using any one of a plurality of PWM signals selected in response to the low-order bits of the image data.

[0022] The switching signal generation circuit may include a selection circuit and a level shifter. The selection circuit outputs a PWM signal selected from multiple PWM signals in response to the low-order bits of the image data. The level shifter generates multiple switching signals by shifting the level of a PWM signal output from the selection circuit.

[0023] The output circuit may include a capacitor, multiple switches, and an operational amplifier. The capacitor and multiple switches respond to multiple switching signals to perform a sample-and-hold operation on the grayscale voltage corresponding to the selected stepped waveform grayscale voltage signal. The operational amplifier amplifies the voltage held in the capacitor by the sample-and-hold operation.

[0024] An operational amplifier may include a first input terminal for receiving a reference voltage, a second input terminal connected to a first terminal of a capacitor, and an output terminal. The capacitor may include a second terminal connected to a first node.

[0025] The multiple switches may include a first switch located between the reset unit and the first node, a second switch located between the second input terminal and the output terminal of the operational amplifier, a third switch located between the output terminal of the decoder and the first node, and a fourth switch located between the output terminal of the operational amplifier and the first node.

[0026] The first switch can be turned on before the third switch is turned on, and then the first switch can be turned off after the third switch is turned on.

[0027] A display device according to an embodiment of the present invention includes a pixel unit comprising a plurality of pixels connected to a data line and a data driver supplying data signals to the data line.

[0028] The data driver includes a signal generator and a channel driver. The signal generator includes a stepped waveform grayscale voltage signal generator, which generates multiple stepped waveform grayscale voltage signals using a minimum gamma reference voltage, a maximum gamma reference voltage, and multiple gamma voltages of magnitude between the minimum and maximum gamma reference voltages. The channel driver includes a decoder that outputs a stepped waveform grayscale voltage signal selected from the stepped waveform grayscale voltage signals, an output circuit that outputs the grayscale voltage corresponding to the selected stepped waveform grayscale voltage signal to the data line as a data signal, and a reset unit that supplies one of the multiple gamma voltages to the output circuit as a reset voltage.

[0029] The decoder can select one stepped waveform grayscale voltage signal from multiple stepped waveform grayscale voltage signals in each horizontal time period.

[0030] The reset voltage can be one of a plurality of gamma voltages, corresponding to the intermediate value between the final grayscale voltage of a stepped waveform grayscale voltage signal selected in the previous horizontal time period and the initial grayscale voltage of a stepped waveform grayscale voltage signal selected in the current horizontal time period.

[0031] The reset unit can use the high bits of the image data supplied to the decoder to detect a stepped waveform grayscale voltage signal selected in the previous horizontal time period and a stepped waveform grayscale voltage signal selected in the current horizontal time period.

[0032] The reset unit can supply a reset voltage to the output circuit in each horizontal time period, and can supply the reset voltage to the output circuit before a stepped waveform grayscale voltage signal selected by the decoder is supplied to the output circuit.

[0033] Each of the multiple stepped waveform grayscale voltage signals with multiple grayscale voltages can be gradually increased in each horizontal time period.

[0034] The display device may also include a gamma reference voltage supply unit that supplies a minimum gamma reference voltage, a maximum gamma reference voltage, and multiple gamma voltages to the data driver. Attached Figure Description

[0035] Figure 1 This is a schematic block diagram illustrating a display device according to an embodiment of the present invention.

[0036] Figure 2 It is shown Figure 1 The diagram shows an implementation of the pixels.

[0037] Figure 3 yes Figure 1 A schematic block diagram of a signal generator.

[0038] Figure 4 It is a graph used to describe the relationship between digital stepped waveform grayscale voltage signals and analog grayscale voltages.

[0039] Figure 5 yes Figure 1 A schematic block diagram of the channel driver.

[0040] Figure 6 It is a graph showing the tracking process of a pulse width modulation (PWM) signal.

[0041] Figure 7 A timing diagram of multiple switches during the sample / hold period is shown according to an embodiment.

[0042] Figure 8 A table showing 8-bit image data divided into high 4 bits and low 4 bits is presented.

[0043] Figure 9 It is shown in Figure 3 signal generator and Figure 5 A graph showing the gamma voltage level at a specific point in the channel driver.

[0044] Figure 10A and Figure 10B It is a graph used to describe the effect produced by the reset unit.

[0045] Figure 11 The illustration shows another embodiment of the invention. Figure 3 signal generator and Figure 5 A graph showing the gamma voltage level at a specific point in the channel driver.

[0046] Figure 12 It is used to describe according to Figure 11 The graph shows the effect of the implementation method. Detailed Implementation

[0047] In the following description, embodiments of the invention will be described in more detail with reference to the accompanying drawings. Throughout the description of the drawings, similar reference numerals refer to similar elements, and descriptions of identical components will not be repeated.

[0048] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first “element,” “component,” “area,” “layer,” or “part” discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings herein.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are also intended to include the plural forms, thereby including “at least one.” “At least one” shall not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including,” when used in this specification, indicate the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or clusters thereof.

[0050] Figure 1 This is a schematic block diagram illustrating a display device 1 according to an embodiment of the present invention.

[0051] Reference Figure 1 The display device 1 according to an embodiment of the present invention may include a timing controller 100, a gamma reference voltage supply unit 200, a data driver 300, a scan driver 400, and a pixel unit 500.

[0052] The timing controller 100 can receive image data as well as synchronization signals and clock signals for controlling the display of the image data. The timing controller 100 can correct externally input image data to suit the image display of the pixel unit 500, and can provide the corrected image data DATA to the data driver 300.

[0053] The timing controller 100 can output a data control signal DCS for controlling the operating timing of the data driver 300 and a scan control signal SCS for controlling the operating timing of the scan driver 400. Additionally, the timing controller 100 can output a voltage control signal VCS for controlling the operating timing of the gamma reference voltage supply unit 200 and the voltage level of the gamma reference voltage VREF.

[0054] The gamma reference voltage supply unit 200 can supply the gamma reference voltage VREF to the data driver 300. Here, the gamma reference voltage VREF may include the lowest gamma reference voltage VGMA_L corresponding to the lowest gray level value and the highest gamma reference voltage VGMA_H corresponding to the highest gray level value.

[0055] The data driver 300 can be connected to multiple data lines D1 to Dm and can supply data signals to the pixel unit 500 through the multiple data lines D1 to Dm. The data driver 300 can generate data signals (or data voltages) in response to the data control signal DCS and can supply the generated data signals to the multiple data lines D1 to Dm during a horizontal time period. Here, m is a natural number.

[0056] As an example, the data driver 300 can generate an analog data signal based on the gamma reference voltage VREF so that it has a voltage value corresponding to the bit value (or gray level value) of the image data DATA.

[0057] According to one implementation, the data driver 300 may include a signal generator 10 and multiple channel drivers 20. The signal generator 10 may generate multiple pulse width modulation (PWM) signals Track<0:15> and multiple stepped waveform grayscale voltage signals A1 to A16 (see [link to implementation details]) based on a digital code (4 bits) generated from an oscillating signal. Figure 3 Each of the multiple channel drivers 20 can supply a data signal generated in response to multiple PWM signals Track<0:15>, multiple stepped waveform grayscale voltage signals A1 to A16, and image data DATA to the pixel unit 500 via multiple data lines D1 to Dm.

[0058] The scan driver 400 can be connected to multiple scan lines S1 to Sn, and can provide scan signals to the pixel unit 500 through the multiple scan lines S1 to Sn. Specifically, the scan driver 400 can output a scan signal by shifting the level of the gate voltage in response to a scan control signal SCS received from the timing controller 100. In an embodiment, the scan driver 400 may be provided with multiple stages of circuitry, and can sequentially supply scan signals to the multiple scan lines S1 to Sn. Here, n is a natural number.

[0059] Pixel unit 500 can display an image in response to a data signal supplied from data driver 300 and a scan signal supplied from scan driver 400. Pixel unit 500 may include a plurality of pixels PX connected to a plurality of scan lines S1 to Sn and a plurality of data lines D1 to Dm.

[0060] Specifically, in response to a scan signal supplied to any one of the plurality of scan lines S1 to Sn, pixels PX are selected on a horizontal line-by-horizontal basis. In this case, each of the plurality of pixels PX selected by the scan signal can receive a data signal from any one of the plurality of data lines D1 to Dm connected thereto. Each of the plurality of pixels PX used to receive the data signal can emit light at a predetermined brightness corresponding to the data signal. Each of the plurality of pixels PX may include sub-pixels for emitting red light, green light, and blue light, respectively. However, the color light emitted by the sub-pixels according to the invention is not limited thereto. For example, each of the plurality of pixels PX may include sub-pixels for emitting red light, green light, blue light, and white light, respectively.

[0061] According to the embodiment, the data driver 300 can display a predetermined image in the pixel unit 500 by supplying a data signal corresponding to the image data DATA in each horizontal time period. The scan driver 400 can sequentially supply scan signals in each horizontal time period to select the pixel PX to be supplied with a data signal.

[0062] Figure 2 It is shown Figure 1 A diagram illustrating an implementation of pixel PX. Specifically, in Figure 2 For ease of description, the pixel connected to the nth scan line Sn (simply referred to as scan line Sn) and the mth data line Dm (simply referred to as data line Dm) is shown.

[0063] Reference Figure 2 Each pixel PX may include a light-emitting diode LD and a pixel circuit PXC connected to a data line Dm and a scan line Sn to control the light-emitting diode LD.

[0064] The anode of the light-emitting diode (LD) can be connected to the pixel circuit PXC, and the cathode of the light-emitting diode (LD) can be connected to the second voltage source VSS.

[0065] A light-emitting diode (LD) can generate light at a predetermined brightness in response to the current supplied from the pixel circuit (PXC).

[0066] Light-emitting diodes (LDs) can be provided as organic light-emitting diodes or inorganic light-emitting diodes such as micro light-emitting diodes (micro LEDs) or quantum dot light-emitting diodes. Furthermore, LDs can be light-emitting diodes made from a combination of organic and inorganic materials. Figure 2 In this illustration, pixel PX is shown as comprising a single light-emitting diode (LD), but in other embodiments, pixel PX may comprise multiple light-emitting diodes. The multiple light-emitting diodes may be connected in series, in parallel, or in a combination of series and parallel.

[0067] When a scan signal is supplied to scan line Sn, pixel circuit PXC controls the amount of current supplied to light-emitting diode LD in response to the data signal supplied to data line Dm. For this purpose, pixel circuit PXC includes a second transistor T2 connected between the first voltage source VDD and light-emitting diode LD, a first transistor T1 connected between the second transistor T2, data line Dm, and scan line Sn, and a storage capacitor Cst connected between the gate electrode of the second transistor T2 and the first electrode.

[0068] The gate electrode of the first transistor T1 is connected to the scan line Sn, and the first electrode of the first transistor T1 is connected to the data line Dm. The second electrode of the first transistor T1 is connected to a terminal of the storage capacitor Cst.

[0069] Here, the first electrode is set as one of the source electrode and the drain electrode, and the second electrode is set as the other of the source electrode and the drain electrode. For example, when the first electrode is set as the source electrode, the second electrode is set as the drain electrode.

[0070] When a scan signal is supplied from the scan line Sn, the first transistor T1, connected to the scan line Sn and the data line Dm, is turned on, thereby supplying the data signal from the data line Dm to the storage capacitor Cst. In this case, the storage capacitor Cst is charged with a voltage corresponding to the data signal.

[0071] The gate electrode of the second transistor T2 is connected to one terminal of the storage capacitor Cst, and the first electrode of the second transistor T2 is connected to the other terminal of the storage capacitor Cst and the first voltage source VDD. The second electrode of the second transistor T2 is connected to the anode of the light-emitting diode LD.

[0072] The second transistor T2, in response to the voltage value stored in the storage capacitor Cst, controls the amount of current flowing from the first voltage source VDD to the second voltage source VSS via the light-emitting diode LD. In this case, the light-emitting diode LD generates light corresponding to the amount of current supplied from the second transistor T2.

[0073] because Figure 2 The above-described structure of the pixel PX is merely an embodiment of the present invention, and therefore the pixel PX of the present invention is not limited to this pixel structure. In fact, the pixel circuit PXC may have a circuit structure capable of supplying current to the light-emitting diode LD, and may be selected from any of the various structures currently known in the art.

[0074] Figure 3 yes Figure 1 A schematic block diagram of the signal generator 10. Figure 4 It is a graph used to describe the relationship between digital stepped waveform grayscale voltage signals and analog grayscale voltages.

[0075] Reference Figure 3 The signal generator 10 may include a PWM signal generation circuit 11, a grayscale voltage generator 12, and a stepped waveform grayscale voltage signal generation circuit 13.

[0076] The PWM signal generation circuit 11 can generate multiple PWM signals Track<0:15> based on a digital code (4 bits) generated from the oscillation signal.

[0077] The PWM signal generation circuit 11 may include an oscillator 11-1, a frequency divider 11-2, a code generator 11-3, and a PWM signal generator 11-4.

[0078] Oscillator 11-1 can generate an oscillation signal with a frequency of, for example, about 2.0 MHz. Alternatively, oscillator 11-1 can generate an oscillation signal with a frequency of about 1.5 MHz to about 2.5 MHz. According to an embodiment, oscillator 11-1 can be implemented as a crystal oscillator.

[0079] Frequency divider 11-2 can divide the frequency of the oscillation signal generated by oscillator 11-1 with a constant division ratio, and can generate an oscillation signal with the divided frequency. For example, the division ratio can be a real number.

[0080] In an implementation example, when the frequency of the oscillation signal is 2MHz, a frequency divider 11-2 with a division ratio set to 1 can generate an oscillation signal with a period of 0.5 microseconds (μs), a frequency divider 11-2 with a division ratio set to 2 can generate an oscillation signal with a period of 1.0 μs, and a frequency divider 11-2 with a division ratio set to 4 can generate an oscillation signal with a period of 2.0 μs. As the division ratio increases, the power consumed by the data driver 300 (or signal generator 10) can be reduced.

[0081] Frequency divider 11-2 may include a register (not shown) for setting the division ratio. Furthermore, frequency divider 11-2 can generate an oscillating signal having frequencies divided according to the division ratio set in an external register (not shown).

[0082] The code generator 11-3, which can be implemented as a counter, can count an oscillating signal having a divided frequency generated by the frequency divider 11-2, and generate a digital code (e.g., 4 bits) as the counting result. For example, the code generator 11-3 can count the number of rising or falling edges of the oscillating signal and generate a K-bit digital code (e.g., 4 bits) corresponding to the counting result. Here, K is a natural number, and for the convenience of description in this specification, K is set to K = 4.

[0083] The PWM signal generator 11-4 can generate multiple PWM signals Track<0:15> in response to the 4-bit digital code generated by the code generator 11-3. For example, Figure 6 As shown, when the 4-digit code sequentially increases from 0000 to 1111, the PWM signal generator 11-4 can generate the following: Figure 6 The pulse width shown is increased periodically by a least significant bit (1 "LSB") for multiple PWM signals Track<0:15>.

[0084] The grayscale voltage generator 12 can generate multiple grayscale voltages V0 to V255. This specification shows a resistor string for generating 256 grayscale voltages V0 to V255. Here, the grayscale voltage generator 12 can use a resistor string connected between a first line VL1 for receiving the lowest gamma reference voltage VGMA_L and a second line VL2 for receiving the highest gamma reference voltage VGMA_H to generate 256 grayscale voltages V0 to V255. For example, the lowest gamma reference voltage VGMA_L can be 9 volts (V), and the highest gamma reference voltage VGMA_H can be 0V.

[0085] According to the implementation, the grayscale voltage generator 12 can receive from the gamma reference voltage supply unit 200 a plurality of gamma tap voltages VGMA_T having a size between the lowest gamma reference voltage VGMA_L and the highest gamma reference voltage VGMA_H.

[0086] Multiple gamma tap voltages VGMA_T may include a first gamma tap voltage VGMA_T1 to a fifteenth gamma tap voltage VGMA_T15 obtained by equally dividing the difference between the lowest gamma reference voltage VGMA_L and the highest gamma reference voltage VGMA_H into sixteen parts. For example, the first gamma tap voltage VGMA_T1 may have the final value of a first stepped waveform grayscale voltage signal A1 (i.e., the grayscale voltage corresponding to V15) or the initial value of a second stepped waveform grayscale voltage signal A2 (i.e., the grayscale voltage corresponding to V16).

[0087] The stepped waveform grayscale voltage signal generation circuit 13 can generate multiple stepped waveform grayscale voltage signals A1 to A16 according to the digital code (4 bits).

[0088] Multiple stepped waveform grayscale voltage signals A1 to A16 can respectively include multiple sets of grayscale voltages V0 to V255, namely V0 to V15, V16 to V31, V32 to V47, V48 to V63, V64 to V79, V80 to V95, V96 to V111, V112 to V127, V128 to V143, V144 to V159, V160 to V175, V176 to V191, V192 to V207, V208 to V223, V224 to V239, and V240 to V255. Multiple grayscale voltages V0 to V15, V16 to V31, V32 to V47, V48 to V63, V64 to V79, V80 to V95, V96 to V111, V112 to V127, V128 to V143, V144 to V159, V160 to V175, V176 to V191, V192 to V207, V208 to V223, V224 to V239, and V240 to V255 are decoded according to the digital code (4 bits) output from the PWM signal generation circuit 11.

[0089] In implementation methods, for example, such as Figure 4As shown, the first stepped waveform grayscale voltage signal A1 may include grayscale voltages V0 to V15 from the first group. The second stepped waveform grayscale voltage signal A2 may include grayscale voltages V16 to V31 from the second group. The third stepped waveform grayscale voltage signal A3 may include grayscale voltages V32 to V47 from the third group. The fourth stepped waveform grayscale voltage signal A4 may include grayscale voltages V48 to V63 from the fourth group. The fifth stepped waveform grayscale voltage signal A5 may include grayscale voltages V64 to V79 from the fifth group. The sixth stepped waveform grayscale voltage signal A6 may include grayscale voltages V80 to V95 from the sixth group. The seventh stepped waveform grayscale voltage signal A7 may include grayscale voltages V96 to V111 from the seventh group. The eighth stepped waveform grayscale voltage signal A8 may include grayscale voltages V112 to V127 from the eighth group. The ninth stepped waveform grayscale voltage signal A9 may include grayscale voltages V128 to V143 from the ninth group. The tenth-step waveform grayscale voltage signal A10 may include grayscale voltages V144 to V159 from the tenth group. The eleventh-step waveform grayscale voltage signal A11 may include grayscale voltages V160 to V175 from the eleventh group. The twelfth-step waveform grayscale voltage signal A12 may include grayscale voltages V176 to V191 from the twelfth group. The thirteenth-step waveform grayscale voltage signal A13 may include grayscale voltages V192 to V207 from the thirteenth group. The fourteenth-step waveform grayscale voltage signal A14 may include grayscale voltages V208 to V223 from the fourteenth group. The fifteenth-step waveform grayscale voltage signal A15 may include grayscale voltages V224 to V239 from the fifteenth group. The sixteenth-step waveform grayscale voltage signal A16 may include grayscale voltages V240 to V255 from the sixteenth group.

[0090] The stepped waveform grayscale voltage signal generation circuit 13 may include multiple decoders 13a-01, 13a-02, and 13a-03 to 13a-16, and multiple buffers 13b-01, 13b-02, and 13b-03 to 13b-16. The stepped waveform grayscale voltage signal generation circuit 13 may also include a delay circuit 13c for adjusting the delay time. The delay circuit 13c may also include a register (not shown) for storing an externally settable delay time.

[0091] Therefore, the delay circuit 13c can delay the signal corresponding to each bit of the 4-bit digital code by setting a delay time.

[0092] In an implementation, for example, the first decoder 13a-01 may receive a first group of grayscale voltages V0 to V15 from 256 grayscale voltages V0 to V255, and may output a first stepped waveform grayscale voltage signal A1 including the first group of grayscale voltages V0 to V15 decoded according to a 4-bit digital code or a 4-bit digital code delayed by the delay circuit 13c.

[0093] That is, such as Figure 4 As shown, when the 4-bit digital code increases sequentially from 0000 to 1111, the first decoder 13a-01 can output a first-step waveform grayscale voltage signal A1 whose grayscale voltage increases sequentially from grayscale voltage V15 to grayscale voltage V0.

[0094] In the same manner as in the first decoder 13a-01, when the 4-bit digital code increases sequentially from 0000 to 1111, the second decoder 13a-02 to the sixteenth decoder 13a-16 can respectively output the second-step waveform gray-scale voltage signal A2 to the sixteenth-step waveform gray-scale voltage signal A16, whose gray-scale voltage increases sequentially.

[0095] Multiple buffers 13b-01, 13b-02, and 13b-03 through 13b-16 can respectively buffer the first-step waveform grayscale voltage signals A1 through the sixteenth-step waveform grayscale voltage signals A16 output from multiple decoders 13a-01, 13a-02, and 13a-03 through 13a-16. Each of the multiple buffers 13b-01, 13b-02, and 13b-03 through 13b-16 can be implemented as a unity-gain buffer. Each of the multiple buffers 13b-01, 13b-02, and 13b-03 through 13b-16 can be implemented as an operational amplifier.

[0096] Multiple PWM signals Track<0:15> and multiple stepped waveform grayscale voltage signals A1 to A16 generated by signal generator 10 can be supplied to multiple channel drivers 20.

[0097] Figure 5 yes Figure 1 A schematic block diagram of the channel driver 20. Figure 6 It is a graph showing the tracking process of the PWM signal. Figure 7 A timing diagram of multiple switches during the sample / hold period is shown according to an embodiment. Figure 8 The table shows 8-bit image data DATA divided into high 4 bits and low 4 bits.

[0098] Reference Figure 5 The channel driver 20 may include a data latch 21, a switch signal generation circuit 22, a decoder 23, a reset unit 24, and an output circuit 25.

[0099] According to an embodiment of the present invention, the data latch 21 can receive and latch image data DATA from the timing controller 100, divide the latched image data DATA into high bits DU<7:4> and low bits DL<3:0>, and output the divided high bits DU<7:4> to the decoder 23, and output the divided low bits DL<3:0> to the switch signal generation circuit 22.

[0100] In an implementation, for example, when the image data DATA is 8 bits, the data latch 21 can divide the latched 8 bits of image data DATA into the high 4 bits DU<7:4> and the low 4 bits DL<3:0>.

[0101] The channel driver 20 may further include a first level shifter 26 connected between the data latch 21 and the decoder 23, which shifts the level of each of the high 4 bits DU<7:4>. That is, the first level shifter 26 can shift the level of each of the high 4 bits DU<7:4> to control the operation of each switch implemented in the decoder 23. Therefore, the decoder 23 can output any one of a plurality of stepped waveform grayscale voltage signals A1 to A16 in response to the level of the high 4 bits DU<7:4> shifted by the first level shifter 26.

[0102] Switch signal generation circuit 22 can be selected from PWM signal generators 11-4 in response to the lower 4 bits DL<3:0> (see PWM signal generator 11-4). Figure 3 The output of multiple PWM signals Track<0:15> can be used to generate multiple switching signals S1, S2 and S3 from any one of the PWM signals TP.

[0103] The switching signal generation circuit 22 may include a selection circuit 22-1 for selecting any one of the PWM signals TP from a plurality of PWM signals Track<0:15> in response to the lower 4 bits DL<3:0> of the image data DATA.

[0104] When the lower 4 bits DL<3:0> are input to the selection circuit 22-1, and then multiple PWM signals Track<0:15> are input to the selection circuit 22-1, the selection circuit 22-1 can selectively output any one of the multiple PWM signals Track<0:15> in response to the lower 4 bits DL<3:0>.

[0105] In implementation methods, for example, such as Figure 6 As shown, when the lower 4 bits DL<3:0> are "1010", the switch... <10> It can be turned on in response to "1010", and therefore, the selection circuit 22-1 can output the PWM signal Track. <10> .

[0106] In the same manner as described above, the lower 4 bits DL<3:0> of the image data DATA are “0000”, “0001”, “0010”, “0011”, “0100”, “0101”, “0110”, “0111”, “1000”, “1001”, “1011”, “1100”, “1101”, “1110”, and “1111”. The selection circuit 22-1 can output the PWM signal Track in response to each of the lower 4 bits DL<3:0>. <0> PWM signal Track <1> PWM signal Track <2> PWM signal Track <3> PWM signal Track <4> PWM signal Track <5> PWM signal Track <6> PWM signal Track <7> PWM signal Track <8> PWM signal Track <9> PWM signal Track <11> PWM signal Track <12> PWM signal Track <13> PWM signal Track <14> and PWM signal Track <15> .

[0107] After the level of any PWM signal TP output from the selection circuit 22-1 increases, the switch signal generation circuit 22 can generate multiple switch signals S1, S2 and S3 with the increased level.

[0108] That is, because the level of the PWM signal TP output from the selection circuit 22-1 is a logic level (e.g., 1.5V or less), a high voltage level (e.g., 4V to 6V) is required in order to control the switching operation of each switch implemented in the output circuit 25. Therefore, the switch signal generation circuit 22 may also include a second level shifter 22-2 for shifting the level of any PWM signal TP output from the selection circuit 22-1.

[0109] Decoder 23 can selectively output any one of a plurality of stepped waveform grayscale voltage signals A1 to A16 Vin in response to the high 4 bits DU<7:4>. Decoder 23 can selectively output the first stepped waveform grayscale voltage signal A1 to the sixteenth stepped waveform grayscale voltage signal A16 in response to the high 4 bits DU<7:4>.

[0110] In implementation methods, for example, such as Figure 4 and Figure 6 As shown, when the high 4 bits DU<7:4> of the image data DATA are “0000”, the decoder 23 can output the first step waveform grayscale voltage signal A1 to the output circuit 25.

[0111] In the same manner as described above, when the high 4 bits DU<7:4> are “0001”, “0010”, “0011”, “0100”, “0101”, “0110”, “0111”, “1000”, “1001”, “1010”, “1011”, “1100”, “1101”, “1110” and “1111”, the decoder 23 can output the second-step waveform grayscale voltage signal A2 to the sixteenth-step waveform grayscale voltage signal A16.

[0112] Before the first-step waveform grayscale voltage signal A1 to the sixteenth-step waveform grayscale voltage signal A16 selected by the decoder 23 are supplied to the output circuit 25, which will be described below, the reset unit 24 may use the gamma tap voltage VGMA_T (see [link to relevant documentation]). Figure 3 The reset unit 24 uses the high 4 bits of the image data DATA (DU<7:4>) to generate the reset voltage VRST and supplies the reset voltage VRST to the output circuit 25. For example, multiple stepped waveform grayscale voltage signals A1 to A16 can be sampled / held in each horizontal period. Therefore, the reset unit 24 can supply the reset voltage VRST to the output circuit 25 in each horizontal period.

[0113] According to the implementation, the reset unit 24 can convert the gamma tap voltage VGMA_T (see [reference]) to the intermediate value between the final value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the initial value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H. Figure 3 The voltage is supplied to the output circuit 25 as the reset voltage VRST.

[0114] The output circuit 25 can perform a sample-and-hold operation on the levels of a plurality of gray voltages V0 to V255 included in the stepped waveform gray voltage signal Vin output from the decoder 23, and can output the output voltage Vout to the pixel unit 500, wherein the output voltage Vout is obtained by amplifying a voltage held by means of the sample-and-hold operation using an operational amplifier AMP.

[0115] Output circuit 25 may include capacitor CH, multiple switches SW1, SW2, SW3 and SW4, and operational amplifier AMP. Output circuit 25 may use capacitor CH and the switching operation of each switch to perform a sample-and-hold operation on the levels of multiple grayscale voltages V0 to V255 included in the stepped waveform grayscale voltage signal Vin output from decoder 23, and may use operational amplifier AMP to amplify and output the voltage held in capacitor CH by the sample-and-hold operation.

[0116] That is, the output circuit 25 can respond to the timing of a plurality of switching signals S1, S2 and S3 in response to the selected PWM signal TP, thereby sampling and holding any one of the plurality of gray voltages V0 to V255 included in the selected stepped waveform gray voltage signal Vin.

[0117] Reference Figure 5 and Figure 7 When the first switch signal S0, used to control the on / off state of the first switch SW1, changes from a second level (e.g., low level) to a first level (e.g., high level), the first switch SW1 can be turned on. In this case, the voltage Va at the left terminal of the capacitor CH becomes the reset voltage VRST. According to an embodiment, the first switch signal S0 can be supplied from the timing controller 100.

[0118] Subsequently, when the second switch signal S1, used to control the on / off state of the second switch SW2, changes from a second level (e.g., low level) to a first level (e.g., high level), the second switch SW2 is turned on. In this case, the voltage Vb at the second input terminal (e.g., the inverting input terminal) of the operational amplifier AMP is set to the reference voltage Gvref. Here, the reference voltage Gvref can be set to half of the power supply voltage GVDD of the operational amplifier AMP. Subsequently, when the third switch signal S2, used to control the on / off state of the third switch SW3, changes from a second level to a first level, the third switch SW3 is turned on. In this case, while the third switch signal S2 maintains the first level, the left terminal of the capacitor CH is charged with the level of a specific grayscale voltage among the multiple grayscale voltages V0 to V255 in the stepped waveform grayscale voltage signal Vin, i.e., the level of the grayscale voltage to be sampled.

[0119] Therefore, capacitor CH is charged with a charge corresponding to the voltage difference (ΔVi = Vin - Vb), which corresponds to the difference between the level (Vin) of the grayscale voltage being sampled and the voltage Vb at the right terminal of capacitor CH.

[0120] After the second switch signal S1 and the third switch signal S2 transition from the first level to the second level, when the fourth switch signal S3 transitions from the second level to the first level, because the output voltage Vout of the operational amplifier AMP is "zero", the voltage Vb at the second input terminal of the operational amplifier AMP becomes -ΔVi. In this case, because the operational amplifier AMP is operating in differential mode, the operational amplifier AMP can amplify the voltage held in the capacitor CH.

[0121] like Figure 8As shown in the table, grayscale voltages V0 to V255 can be determined by combining the high-order bits DU<7:4> and low-order bits DL<3:0> of the image data DATA.

[0122] Figure 9 It is shown in Figure 3 Signal generator 10 and Figure 5 A graph showing the gamma voltage level at a specific point in the channel driver 20. Figure 10A and Figure 10B This is a graph used to describe the effect produced by the reset unit 24. Here, "GAMMA_TOP" means the maximum gamma voltage, "GAMMA_BOT" means the minimum gamma voltage, and "S / H" means sample / hold.

[0123] Reference Figure 3 , Figure 5 and Figure 9 The first curve G1 is a waveform diagram showing the gamma voltage level at the output terminal of the grayscale voltage generator 12; the second curve G2 is a waveform diagram showing the gamma voltage level at the output terminal of the stepped waveform grayscale voltage signal generation circuit 13; the third curve G3 is a waveform diagram showing the gamma voltage level at the first node N1 where the reset unit 24 and the output circuit 25 are connected; and the fourth curve G4 is a waveform diagram showing the gamma voltage level at the output terminal of the output circuit 25.

[0124] Referring to the first curve G1, at the output terminal of the grayscale voltage generator 12, the gamma voltage can correspond to each of a plurality of grayscale voltages V0 to V255, and can have 256 (256pcs) voltage levels, each of the 256 voltage levels maintaining the same level during a horizontal time period 1H.

[0125] Referring to the second curve G2, at the output terminal of the stepped waveform grayscale voltage signal generation circuit 13, the gamma voltage can be grouped into the first stepped waveform grayscale voltage signal A1 to the sixteenth stepped waveform grayscale voltage signal A16, and thus can have 16 (16pcs) voltage levels that gradually increase during a horizontal time period 1H. In this case, the gamma voltage level of each of the first stepped waveform grayscale voltage signals A1 to the sixteenth stepped waveform grayscale voltage signals A16 can gradually increase during a horizontal time period 1H.

[0126] Referring to the third curve G3, at the first node N1 where the reset unit 24 and the output circuit 25 are connected, the decoder 23 can select a step waveform gray voltage signal Vin from the first step waveform gray voltage signal A1 to the sixteenth step waveform gray voltage signal A16, and therefore the gamma voltage level can have a voltage level that gradually increases during a horizontal time period 1H.

[0127] According to the implementation, the reset unit 24 can supply the reset voltage VRST to the output circuit 25 during each horizontal time period 1H.

[0128] The reset unit 24 can use the high 4 bits DU<7:4> supplied from the decoder 23 to detect the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H. The reset unit 24 can select one of a plurality of gamma tap voltages VGMA_T, which corresponds to the intermediate value between the final grayscale value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the initial grayscale value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H, and the reset unit 24 can supply the selected gamma tap voltage VGMA_T to the output circuit 25 as the reset voltage VRST.

[0129] According to the implementation, the reset unit 24 can obtain an intermediate value by dividing the difference between the final gray value of the stepped waveform gray voltage signal selected in the previous horizontal time period (m-1)H and the initial gray value of the stepped waveform gray voltage signal selected in the current horizontal time period (m)H by 2, and can set the gamma tap voltage VGMA_T corresponding to the intermediate value as the reset voltage VRST.

[0130] In the implementation, for example, in the reset unit 24, when the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H is the first stepped waveform grayscale voltage signal A1 and the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H is the sixteenth stepped waveform grayscale voltage signal A16, the final grayscale value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H is V15, the initial grayscale value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H is V240, and the difference between the two values ​​is V225. Therefore, V225 divided by 2 is approximately V112. The grayscale voltage V112 corresponds to the grayscale voltages V112 to V127 of the eighth group, and the grayscale voltages V112 to V127 of the eighth group correspond to the eighth gamma tap voltage VGMA_T8. As a result, the reset unit 24 can select the eighth gamma tap voltage VGMA_T8 from multiple gamma tap voltages VGMA_T as the reset voltage VRST.

[0131] Simultaneously, for stable sample-and-hold operation, the voltage level corresponding to the selected stepped waveform grayscale voltage signal Vin must be reached within at least 1 / 16 of a horizontal time period ((1 / 16)H). Preferably, stable sample-and-hold operation is possible when the target value is reached within 1 / 32 of a horizontal time period ((1 / 32)H), which is half of the 1 / 16 horizontal time period ((1 / 16)H). For example, the current consumption I during the sample-and-hold operation can be calculated using the following Equation 1.

[0132] [Equation 1]

[0133]

[0134] Where CH refers to the capacitance of the capacitor in the output circuit 25, and ΔV refers to the difference between the final value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the initial value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H.

[0135] Reference Figure 10A When no reset voltage VRST is applied from the reset unit 24, since the final value of the first step waveform grayscale voltage signal A1 selected in the previous horizontal time period (m-1)H is approximately 9V, and the initial value of the sixteenth step waveform grayscale voltage signal A16 selected in the current horizontal time period (m)H is approximately 1V, it can be seen that the difference ΔV is 8V. Here, when calculated by Equation 1 above, the current consumption I is approximately 12 microamps (μA). However, in this case, as shown in Table 1 below, it is assumed that the capacitance of the capacitor in the output circuit 25 is 300 femtofarads (fF), and (1 / 32)H is 200 nanoseconds (ns).

[0136] [Table 1]

[0137]

[0138] On the other hand, according to an embodiment of the present invention, in order to stably perform the sampling / holding operation, the sampling / holding operation can be stabilized at the voltage level corresponding to the stepped waveform grayscale voltage signal Vin (or ramp signal) selected within the 1 / 17 level time period ((1 / 17)H).

[0139] In this case, the current consumption I during the sample / hold operation can be calculated using the following Equation 2.

[0140] [Equation 2]

[0141]

[0142] Where CH refers to the capacitance of the capacitor in the output circuit 25, and ΔV refers to the difference between the final value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the initial value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H.

[0143] Reference Figure 10B When the final value of the first-step waveform grayscale voltage signal A1 selected in the previous horizontal time period (m-1)H is approximately 9V, and the initial value of the sixteenth-step waveform grayscale voltage signal A16 selected in the current horizontal time period (m)H is approximately 1V, since the eighth gamma tap voltage VGMA_T8 of approximately 5V is applied from the reset unit 24 as the reset voltage VRST, it can be seen that ΔV is approximately 4V. Here, when calculated by Equation 2 above, the current consumption I during the sample / hold operation is approximately 6.38μA. However, in this case, as shown in Table 2 below, it is assumed that the capacitance of the capacitor of the output circuit 25 is 300fF, and (1 / 34)H is 188ns.

[0144] [Table 2]

[0145]

[0146] That is, according to the implementation, when the gamma tap voltage VGMA_T corresponding to the intermediate value between the final value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the initial value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H is supplied to the output circuit 25 as the reset voltage VRST, the current consumption I during the sampling / holding operation can be reduced by about 1 / 2 times compared to when the reset unit 24 does not supply the reset voltage VRST to the output circuit 25.

[0147] Refer again Figure 9 In the fourth curve G4, at the output terminal of the output circuit 25, the gamma voltage can have one of 16 voltage levels of a selected stepped waveform grayscale voltage signal Vin held by a sample / hold operation. A held voltage level means that the data signal can maintain the same level for a horizontal time period 1H. According to the embodiment, during the current horizontal time period (m)H, it is supplied to pixel unit 500 (see...). Figure 1 The data signal may have a voltage level held by a sample / hold operation during the previous horizontal time period (m-1)H. In this case, n refers to the resolution of the data driver 300, that is, the total number of bits of the image data DATA, and k refers to the number of high-order bits of the image data DATA.

[0148] Other embodiments will be described below. In the embodiments described below, the description of configurations that are the same as those of the previously described embodiments will be omitted or simplified, and the differences will be mainly described.

[0149] Figure 11 The illustration shows another embodiment according to the invention. Figure 3 Signal generator 10 and Figure 5 A graph showing the gamma voltage level at a specific point in the channel driver 20. Figure 12 It is used to describe according to Figure 11 The graph shows the effect of the implementation method. Here, "GAMMA_TOP" means the maximum gamma voltage, "GAMMA_BOT" means the minimum gamma voltage, and "S / H" means sample / hold.

[0150] because Figure 11 The first curve G1 and the fourth curve G4 shown are... Figure 9 The first curve G1 and the fourth curve G4 are basically the same, so redundant descriptions will be omitted, and the main description will be... Figure 11 The second curve G2' and the third curve G3' shown are... Figure 9 The difference between the second curve G2 and the third curve G3 shown in the figure.

[0151] Reference Figure 11 The second curve G2', the stepped waveform grayscale voltage signal generation circuit 13 in this embodiment and according to Figure 9 The difference between the stepped waveform grayscale voltage signal generation circuit 13 in this embodiment and the previous one is that the stepped waveform grayscale voltage signal generation circuit 13 in this embodiment outputs stepped waveform grayscale voltage signals A1 to A16, which alternately display 16 grayscale voltages in increasing and decreasing order at every horizontal time interval 1H, and according to... Figure 9 The stepped waveform grayscale voltage signal generation circuit 13 of the embodiment outputs stepped waveform grayscale voltage signals A1 to A16, which include 16 grayscale voltages in ascending order of voltage value, in each horizontal time period 1H.

[0152] Reference Figure 11 The third curve G3', at the first node N1 where the reset unit 24 and the output circuit 25 are connected (see... Figure 5 At point ), a stepped waveform grayscale voltage signal Vin can be selected, and can have a voltage level that alternately decreases or increases in each horizontal time period 1H.

[0153] Reference Figure 12 ,like Figure 11As shown, when the first-step waveform grayscale voltage signal A1 is selected in the previous horizontal time period (m-1)H and the sixteenth-step waveform grayscale voltage signal A16 is selected in the current horizontal time period (m)H, the final value of the first-step waveform grayscale voltage signal A1 can have the same voltage of about 9V because the first-step waveform grayscale voltage signal A1 has a gradually increasing voltage level. However, the initial value of the sixteenth-step waveform grayscale voltage signal A16 can change to about 1.5V because the seventh gamma tap voltage VGMA_T7 of about 5.25V is applied from the reset unit 24 as the reset voltage VRST, so ΔV can be seen to be about 3.75V. Here, when calculated by Equation 2 above, the current consumption I during the sample / hold operation is about 5.98μA. However, in this case, as shown in Table 3 below, it is assumed that the capacitance of the capacitor of the output circuit 25 is 300fF and (1 / 34)H is 188ns.

[0154] [Table 3]

[0155]

[0156] The difference ΔV between the final value of the stepped waveform grayscale voltage signal selected in the previous horizontal time period (m-1)H and the initial value of the stepped waveform grayscale voltage signal selected in the current horizontal time period (m)H is reduced, thereby further reducing the current consumption I during the sample / hold operation.

[0157] In a method of supplying a ramp signal to the decoder in quantities less than the number of grayscale voltages, the data driver according to an embodiment of the invention uses a gamma tap voltage to apply a reset voltage in response to the start point of the ramp signal, thereby reducing the average current consumption during sample / hold operations.

[0158] In a method of supplying a ramp signal to the decoder in quantities less than the number of grayscale voltages, the data driver according to an embodiment of the invention uses a gamma tap voltage to apply a reset voltage in response to the start of the ramp signal, thereby maintaining linear operation of the ramp signal during the sample / hold period.

[0159] However, the effects of the present invention are not limited to those described above, but various modifications can be made without departing from the spirit and scope of the present invention.

[0160] Although the invention has been described with reference to embodiments, those skilled in the art will appreciate that various modifications and variations can be made to the invention without departing from the spirit or scope of the invention as described in the appended claims.

Claims

1. A data driver, comprising: A signal generator, comprising a stepped waveform grayscale voltage signal generator, wherein the stepped waveform grayscale voltage signal generator uses a minimum gamma reference voltage, a maximum gamma reference voltage, and a plurality of gamma voltages having a magnitude between the minimum gamma reference voltage and the maximum gamma reference voltage to generate a plurality of stepped waveform grayscale voltage signals. as well as A channel driver, comprising a decoder that outputs a selected grayscale voltage signal from a plurality of stepped waveform grayscale voltage signals, an output circuit that outputs a grayscale voltage corresponding to the selected grayscale voltage signal, and a reset unit that supplies one of the plurality of gamma voltages to the output circuit as a reset voltage. Specifically, the decoder selects one stepped waveform grayscale voltage signal from the plurality of stepped waveform grayscale voltage signals in each horizontal time period. The reset voltage among the plurality of gamma voltages is the gamma voltage corresponding to the intermediate value between the final grayscale voltage of a stepped waveform grayscale voltage signal selected in the previous horizontal time period and the initial grayscale voltage of a stepped waveform grayscale voltage signal selected in the current horizontal time period.

2. The data driver according to claim 1, wherein, The reset unit uses the high bits of the image data supplied to the decoder to detect the stepped waveform grayscale voltage signal selected in the previous horizontal time period and the stepped waveform grayscale voltage signal selected in the current horizontal time period.

3. The data driver according to claim 1, wherein, The reset unit supplies the reset voltage to the output circuit during each horizontal time period, and supplies the reset voltage to the output circuit before the stepped waveform grayscale voltage signal selected by the decoder is supplied to the output circuit.

4. The data driver according to claim 1, wherein, Each of the plurality of stepped waveform grayscale voltage signals having multiple grayscale voltages increases progressively in each horizontal time period.

5. The data driver according to claim 1, wherein, Each of the plurality of stepped waveform grayscale voltage signals having multiple grayscale voltages alternately increases and decreases gradually at every other horizontal time interval.

6. The data driver according to claim 1, wherein, The signal generator further includes a pulse width modulation (PWM) signal generation circuit, which generates multiple PWM signals based on digital codes generated from oscillation signals. The pulse width modulation signal generation circuit includes: An oscillator that generates the oscillation signal; A frequency divider divides the frequency of the oscillation signal at a constant division ratio and generates an oscillation signal with the divided frequencies. A code generator that counts the oscillating signals having the divided frequencies and generates the digital code as a result of the counting; and A pulse width modulation signal generator that generates the plurality of pulse width modulation signals in response to the digital code.

7. The data driver according to claim 6, wherein, The channel driver further includes a switch signal generation circuit that generates a plurality of switch signals using any one of the plurality of pulse width modulation signals selected in response to the low-order bits of the image data. The switching signal generation circuit includes: A selection circuit, which responds to the low-order bits of the image data by outputting the one pulse width modulation signal selected from the plurality of pulse width modulation signals; and A level shifter generates the plurality of switching signals by level shifting the pulse width modulation signal output from the selection circuit.

8. The data driver according to claim 7, wherein, The output circuit includes: A capacitor and a plurality of switches, the capacitor and the plurality of switches responding to the plurality of switch signals to perform a sample / hold operation on the grayscale voltage corresponding to the selected stepped waveform grayscale voltage signal; and An operational amplifier that amplifies the voltage held in the capacitor by the sample / hold operation.

9. The data driver according to claim 8, wherein, The operational amplifier includes a first input terminal for receiving a reference voltage, a second input terminal connected to the first terminal of the capacitor, and an output terminal. The capacitor includes a second terminal connected to the first node, and The plurality of switches includes a first switch located between the reset unit and the first node, a second switch located between the second input terminal of the operational amplifier and the output terminal of the operational amplifier, a third switch located between the output terminal of the decoder and the first node, and a fourth switch located between the output terminal of the operational amplifier and the first node.

10. The data driver according to claim 9, wherein, The first switch is turned on before the third switch is turned on, and then the first switch is turned off after the third switch is turned on.

11. A display device, comprising: A pixel unit, the pixel unit comprising a plurality of pixels connected to a plurality of scan lines and a plurality of data lines; A data driver that supplies one stepped waveform grayscale voltage signal selected from multiple stepped waveform grayscale voltage signals to the pixel unit via the data line in each horizontal time period; as well as A scan driver that sequentially supplies scan signals to the pixel units via the plurality of scan lines in each horizontal time interval. The data driver outputs a reset voltage between the previous horizontal time period and the current horizontal time period. The multiple stepped waveform grayscale voltage signals are generated using a minimum gamma reference voltage, a maximum gamma reference voltage, and multiple gamma voltages having a value between the minimum and maximum gamma reference voltages. The reset voltage is a gamma voltage among the plurality of gamma voltages that corresponds to the intermediate value between the final grayscale voltage of a stepped waveform grayscale voltage signal selected in the previous horizontal time period and the initial grayscale voltage of a stepped waveform grayscale voltage signal selected in the current horizontal time period.

12. The display device according to claim 11, wherein, Each of the plurality of stepped waveform grayscale voltage signals having multiple grayscale voltages increases progressively in each horizontal time period.

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