Semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device, which includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer, and an electric field modulation structure. The electrode structure includes a gate structure and source and drain structures on both sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is between the gate structure and the drain structure, and the electric connection structure is electrically connected to the source and drain structures. The semiconductor device provided by embodiments of the present application can change the electric field distribution, reduce the risk of the gate structure being subjected to a high electric field, and improve the operation stability and reliability of the semiconductor device.

Description

Technical Field

[0001] This application relates to a semiconductor device, and more particularly to a semiconductor device having an electric field modulation structure. Background Technology

[0002] Gallium nitride (GaN)-based semiconductor materials possess many excellent material properties, such as high heat resistance, wide bandgap, and high electron saturation velocity. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light-emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

[0003] While existing high electron mobility transistor (HEM) package structures largely meet their intended applications, they do not completely fulfill all requirements. For example, the gate structure in current devices remains susceptible to high electric fields, which negatively impacts device reliability. Therefore, developing structures and manufacturing methods that further improve the performance and reliability of HEM devices remains a key research focus in the industry. Summary of the Invention

[0004] This invention provides a semiconductor device comprising a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer, and an electric field modulation structure on the epitaxial layer. The electrode structure includes a gate structure and source and drain structures located on opposite sides of the gate structure. The electric field modulation structure includes an electrical connection structure and a conductive layer connecting the electrical connection structure. The conductive layer is located between the gate and drain structures, and the electrical connection structure electrically connects the source and drain structures. The length direction of the source structure is a first direction, and the direction from the source structure to the drain structure is a second direction, wherein the first direction is perpendicular to the second direction.

[0005] To make the features of this application clear and easy to understand, embodiments are provided below in conjunction with the accompanying drawings for detailed explanation. For other precautions, please refer to the technical field. Attached Figure Description

[0006] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0007] Figure 1 The present invention provides some embodiments thereof, which illustrate a partial perspective view of an exemplary semiconductor device.

[0008] Figure 2 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 The diagram shows a cross-sectional view of the semiconductor device along line segment A-A'.

[0009] Figure 3 According to some embodiments of the present invention, the diagram is illustrated by... Figure 1 The image shows a top view of some components in a semiconductor device.

[0010] Figure 4 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 Top view of the semiconductor device shown.

[0011] Figure 5 This is a top view of a semiconductor device according to another embodiment of the present invention.

[0012] Figure 6 This is a top view of a semiconductor device according to another embodiment of the present invention.

[0013] Figure 7 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention.

[0014] Figure 8 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention.

[0015] Figure 9 According to other embodiments of the present invention, the diagrams corresponding to Figure 8 The diagram shows a cross-sectional view of the semiconductor device along line segment B-B'.

[0016] Figure 10 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention.

[0017] Figure 11 According to other embodiments of the present invention, the diagrams corresponding to Figure 10 The diagram shows a cross-sectional view of the semiconductor device along line segment C-C'.

[0018] Figures 12 to 14 This is a partial perspective view of an exemplary semiconductor device according to some other embodiments of the present invention.

[0019] Figure 15 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention.

[0020] Figure 16 According to other embodiments of the present invention, the diagrams corresponding to Figure 15 Top view of the semiconductor device shown.

[0021] Figure 17 According to other embodiments of the present invention, the diagram is drawn from... Figure 15 The diagram shows a projection of some components of a semiconductor device onto the XY plane along the +Z axis.

[0022] Figure 18 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention.

[0023] Figure 19 According to other embodiments of the present invention, the diagrams corresponding to Figure 18 Top view of the semiconductor device shown.

[0024] Figure 20 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention.

[0025] Figure 21 According to other embodiments of the present invention, the diagrams corresponding to Figure 20 Top view of the semiconductor device shown.

[0026] [Symbol Explanation]

[0027] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000: Semiconductor devices;

[0028] 102:Substrate;

[0029] 104: Seed layer;

[0030] 110: Epitaxial layer;

[0031] 112: Buffer layer;

[0032] 114: Channel layer;

[0033] 116: Barrier layer;

[0034] 120: Dielectric layer;

[0035] 122: First dielectric layer;

[0036] 124: Second dielectric layer;

[0037] 126: Third dielectric layer;

[0038] 130: Source structure;

[0039] 132: Source electrode;

[0040] 134: Source contact;

[0041] 136: Source metal layer;

[0042] 138: Source metal layer;

[0043] 140: Drain structure;

[0044] 142: Drain electrode;

[0045] 144: Drain contact;

[0046] 146: Drain metal layer;

[0047] 148: Drain metal layer;

[0048] 150: Gate structure;

[0049] 152: Gate electrode;

[0050] 154: Gate metal layer;

[0051] 156: Doped compound semiconductor layer;

[0052] 160: Electrode structure;

[0053] 170: Electric field modulation structure;

[0054] 172: Electrical connection structure;

[0055] 1721, 1722: Electrical connection structure;

[0056] 174: Conductive layer;

[0057] 1741, 1742, 1743: Conductive layer;

[0058] 176: First contact element;

[0059] 1761, 1762, 1763, 1764: First contact element;

[0060] 177a: Second contact element;

[0061] 177a1, 177a2: Second contact element;

[0062] 177b: Second contact element;

[0063] 177b1, 177b2: Second contact element;

[0064] 180: Access Area;

[0065] L: Length;

[0066] A-A', B-B', C-C': line segments. Detailed Implementation

[0067] Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description refers to a first component being formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may use repeated component symbols in many examples. These repetitions are for simplification and clarity only and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0068] Furthermore, spatial terms such as "above," "below," "above," "below," and similar terms encompass not only the orientation shown in the diagram but also the different orientations of the device in use or operation. When the device is turned to another orientation (rotated 90 degrees or to another orientation), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation.

[0069] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0070] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this application, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this application.

[0071] The semiconductor device with an electric field modulation structure provided in this invention can change the electric field distribution and reduce the risk of the gate structure being subjected to high electric fields. Furthermore, when the device is turned off, the electric field modulation structure can form a conduction path to guide carriers (e.g., charges) out of the device, thereby improving the performance of the semiconductor device. In addition, the semiconductor device provided in this invention is particularly suitable for high electron mobility transistors (HEMTs).

[0072] Please refer to the following first. Figure 1 . Figure 1This is a partial perspective view of an exemplary semiconductor device 100 according to some embodiments of the present invention. Figure 1 As shown, the semiconductor device 100 includes a substrate 102, a seed layer 104 on the substrate 102, an epitaxial layer 110 on the seed layer 104, a dielectric layer 120 on the epitaxial layer 110, and an electrode structure 160 and an electric field modulation structure 170 in the dielectric layer 120. It should be noted that, to highlight the features of the electrode structure 160 and the electric field modulation structure 170, the film layers located therebetween and beneath them are indicated by "dashed lines" in this and subsequent perspective views. Furthermore, it should be noted that although these features are indicated by dashed lines, they are still part of the embodiments of the present invention.

[0073] First, please refer to Figure 1 A substrate 102 is provided. In some embodiments, the substrate 102 may be a silicon on insulator (SOI) substrate. In some embodiments, the substrate 102 may also include a ceramic substrate and a pair of barrier layers (not shown) respectively disposed on the upper and lower surfaces of the ceramic substrate.

[0074] In some embodiments, the ceramic substrate comprises a ceramic material. The ceramic material comprises a metallic inorganic material. In some embodiments, the ceramic substrate may comprise silicon carbide, aluminum nitride (AlN), a sapphire substrate, or other suitable materials. The sapphire substrate may be alumina.

[0075] In some embodiments, the barrier layer located on the upper and lower surfaces of the ceramic substrate may comprise a single or multiple layers of insulating material and / or other suitable material layers, such as semiconductor layers. The insulating material layers may be oxides, nitrides, oxynitrides, or other suitable insulating materials. The semiconductor layers may be polycrystalline silicon. The barrier layer prevents diffusion in the ceramic substrate and also prevents the ceramic substrate from interacting with other film layers or process equipment. In some embodiments, the barrier layer may also encapsulate the ceramic substrate. In this case, the barrier layer covers not only the upper and lower surfaces but also the two side surfaces.

[0076] Next, continue to refer to Figure 1, a seed layer 104 is formed on the substrate 102. In some embodiments, the seed layer 104 may be formed of silicon (Si), aluminum nitride (AlN), or other suitable materials. In some embodiments, the method of forming the seed layer 104 may include a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process, a molecular beam epitaxy (MBE) process, a solid-phase epitaxial recrystallization (SPER) step after depositing a doped amorphous semiconductor (such as Si), a method of directly transferring a seed crystal, or other suitable processes. The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, or other suitable processes.

[0077] Next, continue to refer to Figure 1 , an epitaxial layer 110 is formed on the seed layer 104. In some embodiments, the epitaxial layer 110 includes a buffer layer 112 on the seed layer 104, a channel layer 114 on the buffer layer 112, and a blocking layer 116 on the channel layer 114.

[0078] In some embodiments, an epitaxial growth is performed on the seed layer 104 to form the buffer layer 112. The buffer layer 112 can help reduce the strain of a subsequent channel layer 114 formed on the buffer layer 112 and prevent defects from forming in the channel layer 114. In some embodiments, the material of the buffer layer 112 is AlN, GaN, Al x Ga 1-x N (1 < x < 1), the foregoing combinations, or similar materials. In some embodiments, the buffer layer 112 may be formed by a hydride vapor phase epitaxy (HVPE) method, a molecular beam epitaxy (MBE) method, a metalorganic chemical vapor deposition (MOCVD) method, a combination of the foregoing methods, or a similar method. Although in the embodiment shown in Figure 1 , the buffer layer 112 is a single-layer structure, in some other embodiments, the buffer layer 112 may also be a multi-layer structure.

[0079] Next, a channel layer 114 is epitaxially formed on the buffer layer 112. In some embodiments, the channel layer 114 comprises an undoped III-V semiconductor material. For example, the channel layer 114 may be formed of undoped gallium nitride (GaN), but the present invention is not limited thereto. In some other embodiments, the channel layer 114 comprises AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination thereof. In some embodiments, the channel layer 114 may be formed using molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metalorganic chemical vapor deposition (MOCVD), other suitable methods, or a combination of the above methods.

[0080] After that, a barrier layer 116 is epitaxially formed on the channel layer 114. In some embodiments, the barrier layer 116 comprises an undoped III-V semiconductor material. For example, the barrier layer 116 is formed of undoped aluminum gallium nitride (Al x Ga 1-x N, where 0 < x < 1), but the present invention is not limited thereto. In some other embodiments, the barrier layer 116 may also comprise GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination thereof. For example, the barrier layer 116 may be formed on the channel layer 114 using molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or a combination of the above methods.

[0081] In some embodiments, the channel layer 114 and the barrier layer 116 comprise different materials to form a heterojunction interface between the channel layer 114 and the barrier layer 116. Through the band gap difference of the heterojunction materials, a two-dimensional electron gas (2DEG) (not shown) can be formed on this heterojunction interface. For a semiconductor structure formed according to some embodiments, such as a high electron mobility transistor (HEMT), the two-dimensional electron gas can be utilized as the conductive carrier. In some embodiments, the channel layer 114 may be a gallium nitride (GaN) layer, and the barrier layer 116 formed on the channel layer 114 may be an aluminum gallium nitride (AlGaN) layer, where the gallium nitride layer and the aluminum gallium nitride layer may have dopants (such as n-type dopants or p-type dopants) or may not have dopants.

[0082] In some embodiments, the epitaxial layer 110 is a group III-V composite layer, but this application is not limited thereto. Furthermore, in addition to the aforementioned buffer layer 112, channel layer 114, and barrier layer 116, the epitaxial layer 110 may also contain other layers. For example, in some other embodiments, a carbon-doped layer may be formed between the buffer layer 112 and the channel layer 114 to improve the breakdown voltage of the semiconductor structure.

[0083] Next, continue to refer to Figure 1 A dielectric layer 120 is formed on the epitaxial layer 110, and an electrode structure 160 and an electric field modulation structure 170 are formed in the dielectric layer. In some embodiments, the electrode structure 160 and the underlying epitaxial layer 110 may be a high electron mobility transistor (HEMT).

[0084] In some embodiments, dielectric layer 120 comprises a first dielectric layer 122, a second dielectric layer 124, and a third dielectric layer 126, which may each comprise one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials. Low dielectric constant dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide.

[0085] In some embodiments, the dielectric material described above may be deposited on the epitaxial layer 110 (e.g., barrier layer 116) using spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), other suitable methods, or combinations thereof to form the first dielectric layer 122, the second dielectric layer 124, and the third dielectric layer 126.

[0086] In some embodiments, transistor 160 includes a source structure 130, a drain structure 140, and a gate structure 150. The source structure 130 and the drain structure 140 are formed on opposite sides of the gate structure 150.

[0087] In some embodiments, the gate structure 150 includes a gate electrode 152 and a gate metal layer 154 electrically connected to each other, wherein the gate electrode 152 is formed on the barrier layer 116, and the gate metal layer 154 is formed directly on the gate electrode 152 and electrically connected thereto.

[0088] In some embodiments, the gate metal layer 154 serves as a gate field plate, reducing the electric field strength of the gate on the drain side. For example, the gate metal layer 154 completely covers the gate electrode 152 to reduce the risk of the gate electrode 152 being subjected to a high electric field. Furthermore, in some embodiments, the gate metal layer 154 extends into the drain structure 140 and beyond the gate electrode 152 to further improve the electric field distribution.

[0089] In some embodiments, the gate electrode 152 may be made of a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or multiple layers thereof. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The aforementioned conductive material may be formed on the barrier layer 116 by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods, and then the gate electrode 152 may be formed by a patterning process.

[0090] In other embodiments, an optional doped compound semiconductor layer 156 may be included between the gate electrode 152 and the barrier layer 116.

[0091] Specifically, before forming the gate electrode 152, a doped compound semiconductor layer 156 can be formed on the barrier layer 116, and then the gate electrode 152 can be formed on the doped compound semiconductor layer 156. By forming the doped compound semiconductor layer 156 between the gate electrode 152 and the barrier layer 116, the generation of two-dimensional electron gas (2DEG) below the gate electrode 152 can be suppressed to achieve the normally off state of the semiconductor structure. In some embodiments, the material of the doped compound semiconductor layer 156 can be gallium nitride (GaN) doped with p-type or n-type. The step of forming the doped compound semiconductor layer 156 may include depositing the doped compound semiconductor layer (not shown) on the barrier layer 116 by an epitaxial growth process and performing a patterning process thereon to form the doped compound semiconductor layer 156 corresponding to the predetermined location for forming the gate electrode 152.

[0092] In some embodiments, the source structure 130 includes a source electrode 132, a source contact 134, and a source metal layer 136 electrically connected to each other, while the drain structure 140 includes a drain electrode 142, a drain contact 144, and a drain metal layer 146 electrically connected to each other. In some embodiments, the source electrode 132 and the drain electrode 142 located on both sides of the gate electrode 152 pass through the barrier layer 116 and contact the channel layer 114.

[0093] In some embodiments, the source electrode 132 and drain electrode 142 formed on both sides of the gate electrode 152 may contain the same material as the gate electrode 152 and may be formed in the same deposition process, so they will not be described in detail here.

[0094] In some embodiments, the gate metal layer 154, source contact 134, source metal layer 136, drain contact 144, and drain metal layer 146 may be formed by deposition and patterning processes, and their materials include conductive materials such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or combinations thereof.

[0095] In some embodiments, you may first refer to Figure 2 The gate electrode 152 is formed in the first dielectric layer 122 on the barrier layer 116, and the gate metal layer 154 is formed on the first dielectric layer 122 and buried in the second dielectric layer 124 on the first dielectric layer 122. Furthermore, the source contact 134 and drain contact 144 located on both sides of the gate electrode 152 pass through the second dielectric layer 124 and the third dielectric layer 126 on the epitaxial layer 110 and contact the source electrode 132 and drain electrode 142 respectively. The source metal layer 136 and drain metal layer 146 are formed on the third dielectric layer 126 and are electrically connected to the source contact 134 and drain contact 144 respectively.

[0096] Please return Figure 1 In some embodiments of the present invention, the extending direction of the source structure 130 is defined as the first direction (X direction), the direction from the source structure 130 toward the drain structure 140 is defined as the second direction (Y direction), and the direction from the source electrode 132 toward the source metal layer 136 is defined as the third direction (Z direction). Here, the X direction, Y direction, and Z direction are perpendicular to each other.

[0097] In some embodiments, the electric field modulation structure 170 includes an electrical connection structure 172, a conductive layer 174, a first contact 176, and a pair of second contacts 177a and 177b.

[0098] In some embodiments, the electrical connection structure 172 is electrically connected to the conductive layer 174. In some embodiments, the conductive layer 174 is located between the source structure 150 and the drain structure 140, and the electrical connection structure 172 is electrically connected to the source structure 130 and the drain structure 140.

[0099] exist Figure 1 In this embodiment, the electrical connection structure 172 is electrically connected to the conductive layer 174 via the first contact 176. Furthermore, one end of the electrical connection structure 172 is electrically connected to the source structure 130 via the second contact 177a, while the other end of the electrical connection structure 172 is electrically connected to the drain structure 140 via the second contact 177b. That is, one end of the electrical connection structure 172 has the same potential as the source structure 130, and the other end of the electrical connection structure 172 has the same potential as the drain structure 140.

[0100] Because the electrical connection structure 172 has a resistance value, the central region of the electrical connection structure 172 can have a potential different from that of its two ends. In other words, as long as the position where the first contact 176 and the conductive layer 174 are connected to the electrical connection structure 172 is different from the position where the source structure 130 and the drain structure 140 are connected to the electrical connection structure 172, the potential of the first contact 176 and the conductive layer 174 can be different from the potential of the source structure 130 and the drain structure 140.

[0101] In some embodiments, the potential of the first contact 176 and the conductive layer 174 located between the source structure 130 and the drain structure 140 is also between the potential of the source structure 130 and the potential of the drain structure 140.

[0102] The electric field distribution can be optimized by setting the first contact 176 and the conductive layer 174 with different potentials than the source structure 130 and the drain structure 140.

[0103] In addition, Figure 1 In this embodiment, the first contact 176 and the conductive layer 174 are disposed between the gate structure 150 and the drain structure 140. This allows the gate structure 150 to be protected from high electric fields, thereby improving semiconductor performance.

[0104] In some embodiments, the materials of the first contact 176 and the second contact 177a / 177b may be similar to the materials of the source contact 134 and the drain contact 144, and may be formed in the same deposition process, which will not be described in detail here.

[0105] In some embodiments, the materials of the electrical connection structure 172 and the conductive layer 174 include semiconductor materials or metallic materials.

[0106] The aforementioned metallic materials include metals and metal silicides, etc. Metals may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), aluminum-copper (AlCu), similar materials, combinations thereof, or multilayers thereof. Metal silicides may be nickel silicide (SiNi), titanium silicide (SiTi2), cobalt silicide (SiCo), similar materials, combinations thereof, or multilayers thereof. The aforementioned semiconductor materials may be doped or undoped amorphous silicon, polycrystalline silicon, polycrystalline germanium or gallium nitride (GaN), similar materials, combinations thereof, or multilayers thereof.

[0107] In some embodiments, the electrical connection structure 172 is made of a semiconductor material and the conductive layer 174 is made of a metallic material, which can further achieve the effect of saving energy. Specifically, when the electrical connection structure 172 is made of undoped polycrystalline silicon and the conductive layer 174 is made of copper (Cu), a potential different from that of the source and drain structures can be effectively generated without significant leakage.

[0108] In some embodiments, the resistance of the electrical connection structure 172 is 10 ohms. 6 Ω-10 8 Ω. Within this range, semiconductor devices can achieve a more optimized electric field distribution while saving energy.

[0109] In some embodiments, the electrical connection structure 172, the conductive layer 174, the first contact 176, and the second contact 177a / 177b can be formed by deposition and patterning processes, with details similar to those described above, and will not be repeated here.

[0110] Next, please refer to Figure 2 . Figure 2 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 The diagram shows a cross-sectional view of the semiconductor device 100 along line A-A'. It should be noted that the gate structure 150 is located on the -X direction side of line A-A', but to highlight the relative positions of the gate structure 150 with other components, the gate structure 150 is represented by a dashed line here.

[0111] exist Figure 2 In this embodiment, the electrical connection structure 172 directly contacts the barrier layer 116 and is embedded in the first dielectric layer 122, and the two ends of the electrical connection structure 172 are close to but do not contact the source electrode 132 and the drain electrode 142. That is, the electrical connection structure 172 separates the source electrode 132 and the drain electrode 142 through the first dielectric layer 122. In addition, the top surface of the electrical connection structure 172, the top surface of the source electrode 132, and the top surface of the drain electrode 142 are substantially flush with the first dielectric layer 122.

[0112] In addition, Figure 2 In one embodiment, the first contact 176 and the second contact 177a / 177b are approximately at the same height as the source contact 134 and the drain contact 144, such that the source metal layer 136, the drain metal layer 146 and the conductive layer 174 are all located at the same level.

[0113] In addition, Figure 2In one embodiment, in the second direction (Y direction), the length L of the electrical connection structure 172 may be greater than the distance between the source metal layer 136 and the drain metal layer 146, but the length L is less than the distance between the source electrode 132 and the drain electrode 142.

[0114] In addition, Figure 2 In one embodiment, the source electrode 132 and the drain electrode 142 are electrically connected to the electrical connection structure 172 via contacts (e.g., source contact 134 and drain contact 144), the metal layer above them (e.g., source metal layer 136 and drain metal layer 146), and contacts (e.g., second contacts 177a and 177b) to ensure the formation of an ohmic contact.

[0115] exist Figure 2 In one embodiment, in the second direction (Y direction), the source structure 130, the gate structure 150, the conductive layer 174 and the drain structure 140 are arranged in that order.

[0116] Furthermore, in the second direction (Y direction), the conductive layer 174 may or may not overlap with the gate structure 150, as long as it does not affect the operation of the device.

[0117] Furthermore, the gate electrode 152, the doped compound semiconductor layer 156, and the electrical connection structure 172 are disposed at the same level, while the gate metal layer 154 and the electrical connection structure 172 are disposed at different levels. That is, in the third direction (Z direction), the gate metal layer 154 and the electrical connection structure 172 are disposed at different positions.

[0118] In addition, the gate metal layer 154 is disposed between the first contact 176 and the second contact 177a, and is spaced apart from the first contact 176 and the second contact 177a by the second dielectric layer 124 to avoid short circuit.

[0119] Next, please refer to Figure 3 . Figure 3 According to some embodiments of the present invention, the diagram is illustrated by... Figure 1 The image shows a top view of some components in a semiconductor device. More specifically, Figure 3 Only the source electrode 132, gate electrode 152, drain electrode 142, electrical connection structure 172, and conductive layer 174 are projected onto the XY plane to facilitate the description of their respective locations. Here, the electrical connection structure 172, which overlaps with and is located beneath the conductive layer 174, is shown as a dashed line.

[0120] exist Figure 3In one embodiment, the two ends of the gate electrode 152 extend in the second direction (Y direction) to the area defined by the drain electrode 142 (as shown by the dashed line in the figure) to form the access region 180, which is generally used to increase the device breakdown voltage, and the longer its length in the second direction, the higher the withstand voltage.

[0121] exist Figure 3 In this embodiment, the conductive layer 174 spans over the access region 180, while the electrical connection structure 172 is located outside the access region 180. Thus, the electrical connection structure 172 can optimize the electric field distribution through the conductive layer 174 without affecting device operation, thereby reducing the electric field strength of the gate structure 150 on the drain structure 140 side (+Y direction).

[0122] Next, please refer to Figure 4 . Figure 4 According to some embodiments of the present invention, the diagrams corresponding to Figure 1 The diagram shows a top view of the semiconductor device. It should be noted that, to simplify the illustration and highlight the relative positions of other components, the dielectric layer 120 located between these features is not shown here. In this and subsequent top views, the gate metal layer 154, which overlaps with and is located beneath the source metal layer 136, and the electrical connection structure 172, which overlaps with and is located beneath the source metal layer 136, gate metal layer 154, or conductive layer 174, are shown in dashed lines.

[0123] exist Figure 4 In the embodiment, the source metal layer 136, the gate metal layer 154, the conductive layer 174, and the drain metal layer 146 all extend along a first direction (X direction), while the electrical connection structure 172 extends along a second direction (Y direction).

[0124] Furthermore, in the second direction (Y direction), the source metal layer 136, the conductive layer 174, and the drain metal layer 146 are all overlapped on the electrical connection structure 172. Furthermore, in the first direction (X direction), the electrical connection structure 172 overlaps with the source metal layer 136.

[0125] Next, please match Figures 4 to 6 This is to facilitate the description of the shape of the electrical connection structure 172 and the potential relationship between the conductive layer 174 of the electrical connection structure 172. Figure 5 This is a top view of a semiconductor device according to another embodiment of the present invention. Figure 6 This is a top view of a semiconductor device according to another embodiment of the present invention.

[0126] exist Figure 4In the embodiment, the length of the electrical connection structure 172 is fixed in the first direction (X direction), and in the second direction (Y direction), the electrical connection structure 172 is linear between the source structure 130 and the drain structure 140. Therefore, the potential of the conductive layer 174 of the electrical connection structure 172 has a linear relationship with its position in the second direction (Y direction).

[0127] For example, when the source structure 130 and the drain structure 140 are electrically connected at both ends of the electrical connection structure 172, the potential of the drain structure 140 is 600V, the potential of the source structure 130 is 0V (grounded), and the potential at the center of the electrical connection structure 172 is 300V. Therefore, the potential of the first contact 176 and the conductive layer 174 at the center of the electrical connection structure 172 is also 300V.

[0128] In other words, Figure 4 In one embodiment, the potential of the first contact 176 and the conductive layer 174 can be determined by the position (node) at which the first contact 176 is connected to the electrical connection structure 172.

[0129] In other embodiments, for example Figure 5 and Figure 6 In some embodiments, when the electrical connection structure 172 is asymmetrical with respect to the midline between the source structure 130 and the drain structure 140, the potential of the conductive layer 174 of the electrical connection structure 172 may exhibit a nonlinear relationship with its position in the second direction (Y direction).

[0130] Specifically, in Figure 5 In one embodiment, the electrical connection structure 172 has a length that gradually decreases along the second direction (+Y direction) in the first direction (X direction), thus exhibiting a trapezoidal shape. Figure 6 In this embodiment, the position of the electrical connection structure 172 in the first direction (X direction) varies with the second direction, thus exhibiting a curved shape. Meanwhile, the potential of the conductive layer 174 of the electrical connection structure 172 is non-linear.

[0131] In this embodiment of the invention, a parallel electrical connection structure 172 is connected at both ends of the drain structure 140 and the source structure 130, and the conductive layer of the electrical connection structure 172 is disposed between the drain structure 140 and the source structure 130. This can modulate the electric field, raise the electric field on the surface of the access region 180, and reduce the surface electric field near the gate structure 150 and the source structure 130.

[0132] Furthermore, the embodiments of the present invention form an additional conduction path through the electric field modulation structure 170, which can prevent carriers (e.g., charges) from being trapped (e.g., in the dielectric) when the device is turned off, further avoiding the generation of thermal carriers, thereby improving semiconductor performance.

[0133] Figure 7 A partial perspective view of an exemplary semiconductor device 200 is shown in accordance with other embodiments of the present invention. Figure 7 Semiconductor device 200 and Figure 1 The difference in the semiconductor device 100 is that the source structure 130 completely covers the gate structure 150. Specifically, the source metal layer 136 can serve as a source field plate, extending along the +Y direction and beyond the gate structure 150. This further reduces the electric field strength of the gate structure 150 on the drain structure 140 (+Y direction) side.

[0134] Please refer to the matching instructions. Figures 8 to 9 . Figure 8 A partial perspective view of an exemplary semiconductor device 300 is shown in accordance with other embodiments of the present invention. Figure 9 According to other embodiments of the present invention, the diagrams corresponding to Figure 8 The diagram shows a cross-sectional view of the semiconductor device along line segment B-B'.

[0135] It should be noted that the gate structure 150 is omitted in this and subsequent diagrams to simplify the diagrams and highlight the relative relationships of other components.

[0136] Figure 8 Semiconductor device 300 and Figure 1 The difference in the semiconductor device 100 is that the electrical connection structure 172 is embedded in the second dielectric layer 124. That is, the electrical connection structure 172 is separated from the epitaxial layer 110 by the first dielectric layer 122, and is located at a different level from the source electrode 132 and the drain electrode 142. By placing the electrical connection structure 172 in a region with higher voltage resistance (e.g., away from the epitaxial layer 110), impact ionization can be reduced, thereby improving the device's breakdown voltage and reliability.

[0137] exist Figure 8 In some embodiments, the material of the electrical connection structure 172 may be a semiconductor material, while the material of the conductive layer 174 may be a metallic material. In some embodiments, the electrical connection structure 172 is polycrystalline silicon, and the conductive layer 174 is copper (Cu). In this embodiment, the first dielectric layer 122 prevents the electrical connection structure 172 from directly contacting the epitaxial layer 110, thus preventing the electrical connection structure 172 from affecting the operation of the underlying epitaxial layer 110.

[0138] Next, please continue to refer to Figure 9 .exist Figure 9 In this embodiment, the bottom surface of the electrical connection structure 172 is flush with the upper surfaces of the source electrode 132, the drain electrode 142, and the first dielectric layer 122. Furthermore, in the third direction (Z direction), the electrical connection structure 172 is located between the source electrode 132 and the source metal layer 136. Therefore, in the third direction (Z direction), the heights of the first contact 176 and the second contacts 177a / 177b are both less than the heights of the source contact 134 and the drain contact 144.

[0139] Please refer to the matching instructions. Figures 10 to 11 . Figure 10 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention. Figure 11 According to other embodiments of the present invention, the diagrams corresponding to Figure 10 The diagram shows a cross-sectional view of the semiconductor device along line segment C-C'.

[0140] Figure 10 Semiconductor device 400 and Figure 1 The difference in the semiconductor device 100 lies in that the first and second contacts 176 / 177a / 177b extend further through the first dielectric layer 122 and the barrier layer 116 and contact the channel layer 114, and the two-dimensional electron gas (2DEG) located at the interface between the barrier layer 116 and the channel layer 114 serves as the electrical connection structure 172. Specifically, the first and second contacts 176 / 177a / 177b contact the two-dimensional electron gas (2DEG), such that the two-dimensional electron gas, located at a different position than the drain structure 140 and the source structure 130, can generate a potential different from that of the drain structure 140 and the source structure 130, thereby increasing the field plate effect to improve the performance of the semiconductor device.

[0141] Next, please continue to refer to Figure 11 When energized, a two-dimensional electron gas (2DEG) flows between the source electrode 132 and the drain electrode 142. The two-dimensional electron gas (2DEG) between the second contacts 177a and 177b serves as an electrical connection structure 172, which can provide a potential different from that of the source electrode 132 and the drain electrode 142 while reducing complexity.

[0142] Figure 12 This is a partial perspective view of an exemplary semiconductor device 500, illustrated according to some other embodiments of the present invention. It should be noted that the various film layers (e.g., dielectric layer 120, epitaxial layer 110, etc.) between and below the electrode structure 160 and the electric field modulation structure 170 are omitted here and thereafter to simplify the diagram and highlight the relative relationships of other components.

[0143] Figure 12 Semiconductor device 500 and Figure 1 The difference in the semiconductor device 100 is that the electrical connection structure 172 is not disposed between the source electrode 132 and the drain electrode 142. Specifically, in the first direction (X direction), the electrical connection structure 172 does not overlap with the source contact 134 and the source electrode 132. That is, in the first direction (X direction), the electrical connection structure 172 separates the source electrode 132 and the source contact 134 through a dielectric layer (not shown). On the other hand, in the first direction (X direction), the electrical connection structure 172 overlaps with a portion of the source metal layer 136.

[0144] Furthermore, since the electrical connection structure 172 is not disposed between the source electrode 132 and the drain electrode 142, the length L of the electrical connection structure 172 in the second direction (Y direction) can be greater than the distance between the source electrode 132 and the drain electrode 142. That is, the electrical connection structure 172 extends beyond the +Y direction side of the drain structure 140 and also beyond the -Y direction side of the source structure 130. Therefore, the length of the electrical connection structure can be adjusted according to actual needs to facilitate component fabrication.

[0145] Figure 13 A partial perspective view of an exemplary semiconductor device 600 is shown, according to some other embodiments of the present invention. Figure 13 Semiconductor device 600 and Figure 1 The difference in the semiconductor device 100 is that another source metal layer 138 and another drain metal layer 148 are formed on the source metal layer 136 and the drain metal layer 146, and are electrically connected to the source electrode 132 and the drain electrode 142 through the source contact 134 and the drain contact 144, and are electrically connected to the electrical connection structure 172 through the second contact 177a / 177b.

[0146] In this embodiment, another source metal layer 138 extends in the +Y direction and extends beyond the source metal layer 136. That is, in the top view (not shown), the other source metal layer 138 can completely cover the source metal layer 136. This increases the field plate effect, thereby reducing the impact of high electric fields on the source structure.

[0147] In this embodiment, both second contacts 177a and 177b extend beyond the source metal layer 136 and drain metal layer 146 in a third direction (+Z direction) to contact another source metal layer 138 and another drain metal layer 148. Furthermore, the second contacts 177a / 177b do not directly contact the source metal layer 136 and drain metal layer 146 (e.g., by a spacer dielectric layer).

[0148] Furthermore, the first contact 176 extends along the third direction (+Z direction) and contacts the conductive layer 174. That is, the two ends of the first contact 176 connect the conductive layer 174 and the electrical connection structure 172.

[0149] In this embodiment, the conductive layer 174, another source metal layer 138, and another drain metal layer 148 are located on the same layer. Therefore, the electric field distribution of the device can be changed without affecting its operation.

[0150] Figure 14 A partial perspective view of an exemplary semiconductor device 700 is shown, according to some other embodiments of the present invention. Figure 14 Semiconductor device 700 and Figure 1 The difference in the semiconductor device 100 is that another source metal layer 138 and another drain metal layer 148 are formed on the source metal layer 136 and the drain metal layer 146, and the conductive layer 174 includes three conductive layers 1741 / 1742 / 1743, and is electrically connected to the electrical connection structure 172.

[0151] In detail, conductive layers 1741 and 1742 are disposed on the same layer as the source metal layer 136 and the drain metal layer 146, while conductive layer 1743 is disposed on the same layer as another source metal layer 138 and another drain metal layer 148. This allows for a significant reduction in the electric field near the gate structure (not shown) and an optimized electric field distribution away from the gate structure 150 (not shown), thereby increasing semiconductor performance.

[0152] In this embodiment, the first contact 176 includes a plurality of first contacts 1761 / 1762 / 1763, which are electrically connected to a plurality of conductive layers 1741 / 1742 / 1743 respectively. Alternatively, one contact corresponds to one conductive layer. The materials and forming methods of the respective first contacts 1761 / 1762 / 1763 are similar to those previously described, and the materials and forming methods of the respective conductive layers 1741 / 1742 / 1743 are also similar to those previously described, and will not be repeated here.

[0153] In this embodiment, the electric field of the source structure can be further reduced by extending another source metal layer 138 in the second direction (+Y direction).

[0154] Please refer to the matching instructions. Figures 15 to 17 . Figure 15 A partial perspective view of an exemplary semiconductor device is shown according to another embodiment of the present invention. Figure 16 According to other embodiments of the present invention, the diagrams corresponding to Figure 15 Top view of the semiconductor device shown. Figure 17 According to other embodiments of the present invention, the diagram is drawn from... Figure 15 The diagram shows a projection of some components of a semiconductor device onto the XY plane along the +Z axis.

[0155] Figure 15 Semiconductor device 800 and Figure 1 The difference in the semiconductor device 100 is that the electrical connection structure 172 includes two electrical connection structures 1721 / 1722, the first contact 176 includes two first contacts 1761 / 1762, and the second contacts 177a / 177b include two pairs of second contacts 177a1 / 177a2 / 177b1 / 177b2. Specifically, the electrical connection structure 1722 (or another electrical connection structure 1722) is located in the -X direction of the electrical connection structure 1721.

[0156] exist Figure 15 In this embodiment, one end of the electrical connection structures 1721 and 1722 (near the -Y direction side) is electrically connected to the source electrode 132 via second contacts 177a1 and 177a2, the source metal layer 136, and the source contact 134. The other end of the electrical connection structures 1721 and 1722 (near the +Y direction side) is electrically connected to the drain electrode 142 via second contacts 177b1 and 177b2, the drain metal layer 146, and the drain contact 144.

[0157] Furthermore, the central regions of electrical connection structures 1721 and 1722 are connected to both ends of conductive layer 174 via first contacts 1761 and 1762, respectively. In the second direction (Y direction), the first contacts 1761 and 1762 completely overlap to provide the conductive layer 174 with the same potential.

[0158] By connecting multiple electrical connection structures in parallel and electrically connecting conductive layers on them, multiple potential values ​​can be provided when the circuit is turned on, and multiple conduction paths for carriers (such as charges) can be provided when the circuit is turned off. This not only optimizes the electric field distribution but also prevents carriers from accumulating between film layers, thereby increasing semiconductor performance.

[0159] Next, please refer to Figure 16 .exist Figure 16 In this embodiment, electrical connection structures 1721 and 1722 both extend along the second direction (Y direction), while source metal layer 136 and drain metal layer 146 both extend along the first direction (X direction), thus forming a square shape. Furthermore, conductive layer 174 also extends along the first direction (X direction), and intersects with the electrical connection structures 1721 and 1722 extending along the second direction (Y direction) at two points.

[0160] In this embodiment, the source metal layer 136, the conductive layer 174, the drain metal layer 146, and the electrical connection structures 1721 / 1722 will form the shape of the number "8".

[0161] Next, please refer to Figure 17 . Figure 17 Only the source contact 134, drain contact 144, electrical connection structures 1721 / 1722, two first contacts 1761 / 1762, and two pairs of second contacts 177a1 / 177a2 / 177b1 / 177b2 in the semiconductor device 800 are projected onto the plane of the source metal layer 136, conductive layer 174, and drain metal layer 146 to highlight the relevant locations of the features. Furthermore, to emphasize the relevant locations of the first and second contacts, the electrical connection structures 1721 / 1722 are represented by dashed lines and drawn below the first and second contacts in this projection diagram.

[0162] In this embodiment, the second contacts 177a1 / 177a2 near the source structure 130 and the second contacts 177b1 / 177b2 near the drain structure 140 are laterally spaced from the first contacts 1761 / 1762. Specifically, the two second contacts 177a1 and 177a2, which are also close to the source structure 130, are not in direct contact with each other, but are electrically connected through the source metal layer 136. Similarly, the first contact 1761 and the second contacts 177a1 and 177b1, which are electrically connected to the electrical connection structure 1721, are also not in direct contact with each other.

[0163] Please refer to the matching instructions. Figures 18 to 19 . Figure 18 A partial perspective view of an exemplary semiconductor device 900 is shown in accordance with another embodiment of the present invention. Figure 19 According to other embodiments of the present invention, the diagrams corresponding to Figure 18 The top view of the semiconductor device 900 shown.

[0164] Figure 18 Semiconductor device 900 and Figure 15 The difference in the semiconductor device 800 is that the conductive layer 174 includes two conductive layers 1741 / 1742 and the first contacts include four first contacts 1761 / 1762 / 1763 / 1764. In this embodiment, one conductive layer corresponds to two first contacts; for example, conductive layer 1742 is electrically connected to electrical connection structures 1721 and 1722 via first contacts 1764 and 1763, respectively.

[0165] In addition, Figure 18 In this embodiment, in the second direction (Y direction), the first contacts 1761 and 1763 do not overlap, and the first contacts 1762 and 1764 do not overlap either; therefore, the conductive layers 1741 and 1742 do not overlap. That is, the conductive layers 1741 and 1742 can have different potentials.

[0166] By using multiple conductive layers, the potential of the source structure and the drain structure can be divided into multiple potentials between the source structure and the drain structure, so as to effectively improve the electric field distribution in the semiconductor device and reduce the electric field of the components (e.g., source structure 130 and gate structure (not shown)) on the -Y side.

[0167] Next, please refer to Figure 19 . Figure 19 The embodiments are similar to Figure 16 The embodiment differs in that the two conductive layers 1741 / 1742 extend along the first direction (X direction) and intersect with the electrical connection structure 1721 / 1722 extending in the second direction (Y direction) at four points.

[0168] Please refer to the matching instructions. Figures 20 to 21 . Figure 20 A partial perspective view of an exemplary semiconductor device 1000 is shown in another embodiment of the present invention. Figure 21 According to other embodiments of the present invention, the diagrams corresponding to Figure 20 The top view of the semiconductor device 1000 shown.

[0169] Figure 20 Semiconductor device 1000 and Figure 15 The difference in the semiconductor device 800 is that the conductive layer 174 does not extend along the first direction, but rather forms an angle with the first direction. Specifically, in the second direction (Y direction), the first contacts 1761 and 1762 are not located at the same position. In other words, in the second direction (Y direction), they are flush or have a gap between them. Therefore, the potentials at the two ends of the conductive layer 174 connected to the first contacts 1761 and 1762 are not the same.

[0170] Next, please refer to Figure 21 . Figure 21 The embodiments are similar to Figure 16 In this embodiment, the difference lies in that the conductive layer 174 does not extend along the first direction (X direction), but rather along a direction having an angle with the first direction. Therefore, in Figure 21 In one embodiment, the conductive layer 174 cuts the square shape surrounded by the source metal layer 136, the drain metal layer 146, and the electrical connection structures 1721 / 1722 into two trapezoids. This makes the layout of the electric field modulation structure 170 more flexible.

[0171] In summary, the electric field modulation structure provided by the embodiments of the present invention can generate a potential different from that of the source and drain structures, thereby altering the electric field distribution and reducing the surface electric field. Furthermore, when the device is turned off, carriers can be guided outside the device through the conduction path to reduce electrical changes in the device. In other words, the embodiments of the present invention can improve the operational stability and reliability of semiconductor devices through the aforementioned features.

[0172] The foregoing outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A seed crystal layer is located on the substrate; An epitaxial layer is located on the seed crystal layer; An electrode structure is located on the epitaxial layer, wherein the electrode structure includes a gate structure and a source structure and a drain structure located on both sides of the gate structure; and An electric field modulation structure includes an electrical connection structure and a conductive layer electrically connected to the electrical connection structure, wherein the conductive layer is located between the source structure and the drain structure, and the electrical connection structure electrically connects the source structure and the drain structure, wherein the length direction of the source structure is a first direction, and the direction from the source structure to the drain structure is a second direction, wherein the first direction is perpendicular to the second direction, and wherein the potential of the conductive layer is different from the potential of the drain structure and different from the potential of the source structure.

2. The semiconductor device according to claim 1, characterized in that, The potential of the conductive layer is between the potential of the drain structure and the potential of the source structure.

3. The semiconductor device according to claim 1, characterized in that, The electrical connection structure extends along the second direction and the conductive layer extends along the first direction.

4. The semiconductor device according to claim 1, characterized in that, The electric field modulation structure further includes a contact element that electrically connects the electrical connection structure to the conductive layer.

5. The semiconductor device according to claim 1, characterized in that, The electric field modulation structure further includes a pair of contacts that electrically connect the electrical connection structure to the source structure and the electrical connection structure to the drain structure, respectively.

6. The semiconductor device according to claim 1, characterized in that, The electrical connection structure is a two-dimensional electron gas in the epitaxial layer.

7. The semiconductor device according to claim 1, characterized in that, The gate structure and the drain structure define an access region, wherein the electrical connection structure is located outside the access region, and the conductive layer spans over the access region.

8. The semiconductor device according to claim 1, characterized in that, The length of the electrical connection structure is greater than the distance between a source electrode of the source structure and a drain electrode of the drain structure.

9. The semiconductor device according to claim 1, characterized in that, The electrical connection structure is in direct contact with the epitaxial layer.

10. The semiconductor device according to claim 1, characterized in that, The electrical connection structure is separated from the epitaxial layer by a dielectric layer.

11. The semiconductor device according to claim 1, characterized in that, In the source structure, one source electrode is electrically connected to the electrical connection structure through a source metal layer, and in the drain structure, one drain electrode is electrically connected to the electrical connection structure through a drain metal layer.

12. The semiconductor device according to claim 1, characterized in that, The electrical connection structure and the source structure are arranged to overlap in the first direction.

13. The semiconductor device according to claim 1, characterized in that, The source structure completely covers the gate structure.

14. The semiconductor device according to claim 1, characterized in that, The electric field modulation structure further includes another electrical connection structure that electrically connects the conductive layer.

15. The semiconductor device according to claim 14, characterized in that, The two ends of the conductive layer of the electrical connection structure have the same potential.

16. The semiconductor device according to claim 14, characterized in that, The two ends of the electrical connection structure and the other electrical connection structure are respectively electrically connected to the source structure and the drain structure.

17. The semiconductor device according to claim 14, characterized in that, The electric field modulation structure further includes another conductive layer electrically connected to the electrical connection structure.

18. The semiconductor device according to claim 1, characterized in that, The electrical connection structure includes metallic or semiconductor materials.

19. The semiconductor device according to claim 1, characterized in that, The resistance of the electrical connection structure is 10. 6 Ω-10 8 Ω.

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