FPGA-based DDR2 SRAM interface circuit and its phase adjustment method

Abstract

The present invention discloses a DDR2SRAM interface circuit based on an FPGA and a phase adjustment method thereof. The circuit includes: a control module for issuing control commands and a clock signal; the clock signal is phy_clk; an SRAM module connected to the control module; a data read / write module for writing data to or reading data from the SRAM module according to the control command based on the clock domain of phy_clk; and a phase adjustment module connected to the read / write module for finding a phase window for the read / write data and determining an intermediate value. The technical solution of the present invention allows DDR2SRAM write and read data to operate in the same clock domain, eliminating the need for cross-clock processing of read-return data.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to a DDR2 SRAM interface circuit based on FPGA and a phase adjustment method thereof. Background Art

[0002] The existing technology generates SRAM read and write clocks based on clock resources such as MMCM; however, when there are many SRAM chips in the system, the phase of the accompanying clock of each SRAM chip is adjusted by the MMCM, which will occupy more clock resources. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present invention is to provide a DDR2 SRAM interface circuit based on FPGA and its phase adjustment.

[0004] In order to solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0005] A DDR2 SRAM interface circuit based on FPGA, comprising:

[0006] A control module, the control module is used to issue control commands and clock signals; the clock signal is phy_clk;

[0007] An SRAM module, wherein the SRAM module is connected to the control module;

[0008] A data read / write module, which writes data into the SRAM module or reads data from the SRAM module according to the control command based on the clock domain of the phy_clk;

[0009] A phase adjustment module is connected to the read / write module and is used to adjust the write phase and the read phase.

[0010] Optionally, the phase adjustment module includes a write phase adjustment unit and a read phase adjustment unit; the write phase adjustment unit and the read phase adjustment unit are both connected to the read / write data module. Optionally, the read / write data module includes a write data unit, a read data unit, and an IOBUF unit;

[0011] The data writing unit and the data reading unit are both connected to the IOBUF unit.

[0012] Optionally, the data reading unit includes an IDDR unit and an IDELAY2 unit;

[0013] The data to be read from the SRAM module passes through the IOBUF unit, the IDELAY2 unit and the IDDR unit in sequence and enters the control module;

[0014] The IDELAY2 unit is connected to the read phase adjustment unit.

[0015] Optionally, the data writing unit includes an ODDR unit;

[0016] The data to be written output by the control module passes through the ODDR unit and the IOBUF unit in sequence and is written into the SRAM module.

[0017] Optionally, a clock module is further included, wherein the clock module includes an ODDR unit, an ODELAY2 unit, and an OBUFDS unit;

[0018] The ODELAY2 unit delays the offset clock signal sent by the ODDR unit to obtain a delayed clock;

[0019] The ODELAY2 unit sends the delayed clock to the SRAM module through the OBUFDS unit;

[0020] The ODELAY2 unit is connected to the read phase adjustment unit.

[0021] An embodiment of the present invention further provides a phase adjustment method for a DDR2 SRAM interface circuit based on an FPGA, based on the circuit described above, comprising:

[0022] After the read command is issued, the read data valid flag is generated immediately, and the read data valid flag is delayed, and the fixed delay beat number is set to P;

[0023] The initial values ​​of Odelay_tap_count and idelay_tap_count are preset to M=0 and N=0 respectively;

[0024] Determine the correct set of combinations for reading and writing;

[0025] Determining a tap value of a target write phase according to the combination set;

[0026] The target read phase tap value is determined according to the target write phase tap value.

[0027] Optionally, determining a correct read-write combination set includes:

[0028] Traverse the idelay_tap_count range 0-31;

[0029] Each time the value of idelay_tap_count is adjusted, multiple random reads and writes are performed to obtain the read and write results;

[0030] If the reading and writing results are correct, the corresponding combination value (L, M, N) is recorded;

[0031] A plurality of the combination values ​​(L, M, N) constitute the combination set.

[0032] Optionally, determining a tap value of a target write phase according to the combination set includes:

[0033] After traversing all values ​​of idelay_tap_count, the value of Odelay_tap_count is N=N+1, until Odelay_tap_count traverses to N=31;

[0034] Get the maximum continuous window of Odelay_tap_count;

[0035] Determine the value of Odelay_tap_mid according to the maximum continuous window of Odelay_tap_count;

[0036] According to the value of Odelay_tap_mid, the tap value of the target write phase is determined.

[0037] Optionally, determining the target read phase tap value according to the target write phase tap value includes:

[0038] Determine a maximum continuous window of idelay_tap_count based on the tap value of the target write phase;

[0039] Determine the value of idelay_tap_mid according to the maximum continuous window of idelay_tap_count;

[0040] According to the value of Odelay_tap_mid, the tap value of the target read phase is determined.

[0041] The embodiments of the present invention have the following technical effects:

[0042] The above technical solution of the present invention: 1) DDR2 SRAM write data and read data are in the same clock domain, and there is no need to perform cross-clock processing on the read return data.

[0043] 2) When there are multiple SRAM chips in the system and they are in different clock areas in the FPGA, the same interface clock phy_clk can be used to reduce the FPGA clock resource usage.

[0044] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of the read and write data path structure of the FPGA-based DDR2 SRAM interface circuit provided by an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of a write timing sequence provided by an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of a structure for generating a read / write command signal according to an embodiment of the present invention;

[0048] Figure 4 1 is a flow chart of a phase adjustment method for a DDR2 SRAM interface circuit based on an FPGA provided by an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the principle of finding the maximum continuous window of Odelay_tap_count according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0051] The present invention mentions, FPGA: field programmable gate array; SRAM: static random access memory (SRAM); tap: delay unit adjusts the count value; DQ: data line; IO interface: input and output interface; IDELAY2: input delay unit, which can realize the delay of data or clock; ODELAY2: output delay unit, which can realize the delay of data or clock; ODELAY2 and IDELAY2 primitives are high-precision, circular delay adjustment units with a tap value range of 0-31, which can realize the delay adjustment of output and input data; ODDR: can realize FPGA IO dual-edge data output; IDDR: can realize dual-edge data acquisition of FPGA IO input; OBUF: output buffer; IOBUF: input buffer; OBUFDS: output buffer; MMCM: mixed mode clock manager, used to generate clock and adjust phase.

[0052] Combine Figure 1, an embodiment of the present invention provides a DDR2 SRAM interface circuit based on FPGA, comprising:

[0053] A control module, the control module is used to issue control commands and clock signals; the clock signal is phy_clk;

[0054] An SRAM module, wherein the SRAM module is connected to the control module;

[0055] A data read / write module, which writes data into the SRAM module or reads data from the SRAM module according to the control command based on the clock domain of the phy_clk;

[0056] A phase adjustment module is connected to the read / write module and is used to adjust the write phase and the read phase.

[0057] In this embodiment of the present invention, DDR2 SRAM write data and read data are in the same clock domain, eliminating the need for cross-clock processing of read return data. When there are multiple SRAM modules in the system and they are in different clock domains in the FPGA, the same interface clock phy_clk can be used, reducing the FPGA clock resource usage.

[0058] In an optional embodiment of the present invention, the phase adjustment module includes a write phase adjustment unit and a read phase adjustment unit; the write phase adjustment unit and the read phase adjustment unit are both connected to the data read and write module.

[0059] This embodiment of the present invention realizes adjustment of the read phase and the write phase by providing a phase adjustment module, thereby achieving correct reading and writing.

[0060] In an optional embodiment of the present invention, the data reading and writing module includes a data writing unit, a data reading unit and an IOBUF unit;

[0061] The data writing unit and the data reading unit are both connected to the IOBUF unit.

[0062] Specifically, the signal definitions of the user interface when reading and writing data are shown in Table 1 below:

[0063] Table 1

[0064] Combine Figure 2 , which determines the timing of the above signals in the data writing process.

[0065]

[0066] In the embodiment of the present invention, by providing a data reading unit and a data writing unit, it is possible to write data into the SRAM module or read data from the SRAM module according to a control command of a control module.

[0067] In an optional embodiment of the present invention, the data reading unit includes an IDDR unit and an IDELAY2 unit;

[0068] The data to be read from the SRAM module passes through the IOBUF unit, the IDELAY2 unit, and the IDDR unit in sequence and enters the control module;

[0069] The IDELAY2 unit is connected to the read phase adjustment unit.

[0070] Specifically, the IDELAY2 unit is provided with a C port for obtaining phy_clk;

[0071] The IDDR unit includes a C port, a D port, a Q1 port, and a Q2 port; the D port is used to receive the data to be read sent by the IDELAY2 unit, the C port of the IDDR unit is used to obtain phy_clk, and the Q1 port and the Q2 port are used to output the data to be read to the user interface of the control module.

[0072] Specifically, the control module generates a read data command; the generating of the read data command includes:

[0073] like Figure 3 As shown, the user interface issues a read data command, determines the access address, and simultaneously pulls down the cmd_load signal and pulls up the cmd_rw signal;

[0074] Combine Figure 2 The read data command, access address, cmd_load and cmd_rw signals are all synchronized with the phy_clk.

[0075] The write data command signal is sent to the R / W interface through the OBUF unit.

[0076] When the read data command is valid, the corresponding read data valid flag (rd_vld) is generated. The read data valid flag is synchronized with the phy_clk clock and is fixedly delayed by a configurable P phy_clk clock cycles.

[0077] The user interface can obtain valid data to be read according to the read data valid identifier.

[0078] When reading data, the control signal T of the IOBUF unit remains at a high level, and the data to be read on the DQ line enters the IDELAY2 unit after passing through the IOBUF unit. The IDELAY2 unit can adjust the phase relationship between the data to be read and phy_clk. After port D receives the dual-edge data, it is sampled in the phy_clk clock domain of port C of the IDDR unit. When the data to be read meets the phase relationship with phy_clk, it can be correctly sampled and output in parallel from ports Q1 and Q2 to the user interface.

[0079] This embodiment of the present invention collects data from the dual edges of the IDDR unit FGPA IO input and writes data based on the same clock domain, thereby saving resources.

[0080] In an optional embodiment of the present invention, the data writing unit includes an ODDR unit;

[0081] The data to be written output by the control module passes through the ODDR unit and the IOBUF unit in sequence and is written into the SRAM module.

[0082] Specifically, the ODDR unit includes a C port, a Q port, a D1 port, and a D2 port; wherein the D port is used to send the data to be written to the DQ line of the SRAM module, the C port of the ODDR unit is used to obtain phy_clk, and the D1 port and the D2 port are used to obtain the data to be written issued by the control module.

[0083] The control module generates a write data command; the generating of the write data command includes:

[0084] like Figure 3 As shown, the user interface issues a write data command, determines the access address and write data mask signal, and pulls down the cmd_load and cmd_rw signals;

[0085] Combine Figure 2 The write data command, access address, write data mask, cmd_load and cmd_rw signals are all synchronized with the phy_clk.

[0086] Send the write data command signal to the R / W interface through the OBUF unit;

[0087] Send the cmd_load signal to the LD# interface through the OBUF unit;

[0088] Send the access address signal to the A interface through the OBUF unit;

[0089] Send the write data mask signal to the BW interface through the OBUF unit;

[0090] Among them, the IO interface includes R / W interface, LD# interface, A interface and BW interface.

[0091] When writing data, the control module sends wr_data[35:0] to the ODDR unit through the D1 and D2 lines under the clock domain of phy_clk; after the ODDR unit samples the data to be written obtained through the D1 and D2 ports, it outputs the sampled dual-edge data to be written from the Q port, and outputs the data to be written from the D1 port from the Q port on the rising edge of the clock, and outputs the data to be written from the D2 port from the Q port on the falling edge of the clock; when writing data, the T control signal of the IOBUF unit is pulled low, and the data to be written is sent to the DQ line through the IOBUF unit.

[0092] This embodiment of the present invention implements FGPA IO dual-edge data output through the ODDR unit, and simultaneously reads data based on the same clock domain, eliminating the need for cross-clock processing of read return data, thereby saving resources.

[0093] An optional embodiment of the present invention further includes a clock module, wherein the clock module includes an ODDR unit, an ODELAY2 unit, and an OBUFDS unit;

[0094] The ODELAY2 unit delays the offset clock signal sent by the ODDR unit to obtain a delayed clock;

[0095] The ODELAY2 unit sends the delayed clock to the SRAM module through the OBUFDS unit;

[0096] The ODELAY2 unit is connected to the read phase adjustment unit.

[0097] Specifically, the control module uses the phy_clk input through the user interface as the input clock of the C port of the ODDR unit (input value setting D1=1, D2=0), and the Q port outputs an offset clock with a phase shift of 90° from phy_clk; the offset clock passes through the ODELAY2 unit and the OBUFDS unit in turn to generate the differential clock signal required by the SRAM module.

[0098] Among them, the ODELAY2 unit can adjust the K clock phase and generate the K# clock for correcting the K clock phase.

[0099] This embodiment of the present invention generates the differential clock signal required by the SRAM module and corrects the K clock phase.

[0100] like Figure 4 As shown, an embodiment of the present invention further provides a phase adjustment method for a DDR2 SRAM interface circuit based on FPGA, comprising:

[0101] Step S1: After the read command is issued, a read data valid flag is generated immediately, and a delay is applied to the read data valid flag, with a fixed delay number being set to P;

[0102] Step S2: Preset the initial values ​​of Odelay_tap_count and idelay_tap_count to M=0 and N=0 respectively;

[0103] Step S3: Determine the correct combination set of reading and writing;

[0104] Step S4: determining the tap value of the target write phase according to the combination set;

[0105] Step S5: Determine the target read phase tap value according to the target write phase tap value.

[0106] In this embodiment of the present invention, by adjusting the phase, it is possible to find a suitable phase between write data and write clock, and a suitable phase between read data and read clock, thereby achieving correct writing and reading of data.

[0107] In an optional embodiment of the present invention, in step S3, determining a correct read / write combination set includes:

[0108] Step S31: traverse the idelay_tap_count range 0-31;

[0109] Specifically, the value range of Odelay_tap_count and idelay_tap_count is 0-31.

[0110] Step S32: performing multiple random reads and writes each time the value of idelay_tap_count is adjusted to obtain read and write results;

[0111] Step S33: If the read / write result is correct, the corresponding combination value (L, M, N) is recorded.

[0112] Step S34: A plurality of the combination values ​​(L, M, N) form the combination set.

[0113] This embodiment of the present invention determines the combination value corresponding to the correct read and write result, so as to obtain the correct combination set.

[0114] In an optional embodiment of the present invention, in step S4, determining the tap value of the target write phase according to the combination set includes:

[0115] Step S41: After traversing all values ​​of idelay_tap_count, the value of Odelay_tap_count is N=N+1, until Odelay_tap_count traverses to N=31;

[0116] Step S42: Obtain the maximum continuous window of Odelay_tap_count;

[0117] Step S43: determining the value of Odelay_tap_mid according to the continuous maximum window of Odelay_tap_count;

[0118] Step S44: Determine the tap value of the target write phase according to the value of Odelay_tap_mid.

[0119] This embodiment of the present invention achieves acquisition of the correct write phase and clock phase, so as to correctly write data.

[0120] In an optional embodiment of the present invention, in step S5, determining the target read phase tap value according to the target write phase tap value includes:

[0121] Step S51: determining a maximum continuous window of idelay_tap_count based on the tap value of the target write phase;

[0122] Step S52: determining the value of idelay_tap_mid according to the continuous maximum window of idelay_tap_count;

[0123] Step S53: Determine the tap value of the target read phase according to the value of Odelay_tap_mid.

[0124] This embodiment of the present invention achieves acquisition of the correct read phase and clock phase, so as to correctly read data.

[0125] Table 2 below shows the definition of user interface signals during the phase adjustment process:

[0126] Table 2

[0127] Specifically, the ODELAY2 unit is used to adjust the write phase; the IDELAY2 unit is used to adjust the read phase; wherein,

[0128]

[0129] Read_data_valid_delay is the read data valid signal delay count with a maximum count value of P, which can realize the effective delay selection of rd_vld.

[0130] Combine Figure 5 , the effective delay selection of rd_vld can be achieved in the following way:

[0131] 1) The default value of P is 20;

[0132] 2) Set the initial value of Read_data_valid_delay to L=0, the initial value of Delay_tap_count to M=0, and the initial value of Delay_tap_count to N=0.

[0133] 3) Traverse the idelay_tap_count range of 0-31; perform 10,000 random reads and writes each time the idelay value is adjusted; if the random read and write is correct, record the current combination value (L, M, N) and obtain a combination set containing multiple combination values ​​(L, M, N).

[0134] 4) After one round of traversal of Odelay_tap_count, Odelay_tap_count value N=N+1, until Odelay_tap_count traverses to N=31.

[0135] 5) After Odelay_tap_count has traversed one cycle, the value of Read_data_valid_delay is L=L+1. Then, steps 3), 4), and 5) are repeated until Read_data_valid_delay reaches the set value P.

[0136] 6) Find the maximum continuous window of odelay_tap_count in the combined values ​​recorded in step 3) and calculate the middle value odelay_tap_mid; set the middle value of odelay_tap_mid as the final adjustment value of the write phase;

[0137] 7) Traverse the idelay_tap_count value again, find the maximum continuous window of idelay_tap_count, and calculate the middle value idelay_tap_mid, and set this idelay_tap_mid as the final tap value of the read phase.

[0138] In addition, other structures and functions of the circuits in the embodiments of the present invention are known to those skilled in the art and are not described here in detail to reduce redundancy.

[0139] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0140] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0141] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0142] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0143] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0144] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0145] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0146] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A DDR2 SRAM interface circuit based on FPGA, characterized in that: include: A control module, the control module is used to issue control commands and clock signals; the clock signal is phy_clk; An SRAM module, wherein the SRAM module is connected to the control module; A data read / write module, which is based on the clock domain of the phy_clk and writes data into the SRAM module or reads data from the SRAM module according to the control command, wherein the reading and writing of data are performed based on the same clock domain; A phase adjustment module, connected to the data reading and writing module, and configured to adjust a write phase and a read phase; The control module is further configured to generate a read data valid flag when the read data command is valid, beat delay the read data valid flag, and set a fixed delay beat number P, where P is equal to the phy_clk; The phase adjustment module is further configured to preset the initial values ​​of Odelay_tap_count and idelay_tap_count to M=0 and N=0 respectively, and then determine the tap value of the target write phase according to the correct read and write combination set, and determine the tap value of the target read phase according to the tap value of the target write phase.

2. The circuit according to claim 1, wherein: The phase adjustment module includes a write phase adjustment unit and a read phase adjustment unit; the write phase adjustment unit and the read phase adjustment unit are both connected to the read and write data module.

3. The circuit according to claim 2, characterized in that The data reading and writing module includes a data writing unit, a data reading unit and an IOBUF unit; The data writing unit and the data reading unit are both connected to the IOBUF unit.

4. The circuit according to claim 3, characterized in that The data reading unit includes an IDDR unit and an IDELAY2 unit; The data to be read from the SRAM module passes through the IOBUF unit, the IDELAY2 unit, and the IDDR unit in sequence and enters the control module; The IDELAY2 unit is connected to the read phase adjustment unit.

5. The circuit according to claim 4, characterized in that The data writing unit includes an ODDR unit; The data to be written output by the control module passes through the ODDR unit and the IOBUF unit in sequence and is written into the SRAM module.

6. The circuit according to claim 5, characterized in that Also included is a clock module, the clock module including an ODDR unit, an ODELAY2 unit, and an OBUFDS unit; The ODELAY2 unit delays the offset clock signal sent by the ODDR unit to obtain a delayed clock; The ODELAY2 unit sends the delayed clock to the SRAM module through the OBUFDS unit; The ODELAY2 unit is connected to the read phase adjustment unit.

7. A phase adjustment method for a DDR2 SRAM interface circuit based on FPGA, characterized in that: Based on the circuit according to any one of claims 1 to 6, comprising: After the read command is issued, the read data valid flag is generated immediately, and the read data valid flag is delayed, and the fixed delay beat number is set to P; The initial values ​​of Odelay_tap_count and idelay_tap_count are preset to M=0 and N=0 respectively; Determine the correct set of combinations for reading and writing; Determining a tap value of a target write phase according to the combination set; A target read phase tap value is determined according to the target write phase tap value.

8. The method according to claim 7, characterized in that Determining the correct read and write combination set includes: Traverse the idelay_tap_count range 0-31; Each time the value of idelay_tap_count is adjusted, multiple random reads and writes are performed to obtain the read and write results; If the reading and writing results are correct, the corresponding combination value (L, M, N) is recorded; A plurality of the combination values ​​(L, M, N) constitute the combination set.

9. The method according to claim 8, characterized in that Determining a tap value of a target write phase according to the combination set includes: After traversing all values ​​of idelay_tap_count, the value of Odelay_tap_count is N=N+1, until Odelay_tap_count reaches N=31; Get the maximum continuous window of Odelay_tap_count; Determine the value of Odelay_tap_mid according to the maximum continuous window of Odelay_tap_count; According to the value of Odelay_tap_mid, the tap value of the target write phase is determined.

10. The method according to claim 9, characterized in that Determining the target read phase tap value according to the target write phase tap value includes: Determine a maximum continuous window of idelay_tap_count based on the tap value of the target write phase; Determine the value of idelay_tap_mid according to the maximum continuous window of idelay_tap_count; According to the value of Odelay_tap_mid, the tap value of the target read phase is determined.

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