Method, System, Device, and Storage Medium for Post-Silicon Testing

Abstract

The present disclosure provides a method, a system, a device, and a storage medium for post-silicon testing. The method includes: obtaining random configuration information according to a chip to be tested; obtaining a test instruction stream according to the random configuration information; obtaining instruction-level random test cases according to the test instruction stream; and running the instruction-level random test cases on the chip to verify the chip. The post-silicon testing method of the present disclosure can hit as many scenarios as possible through large-scale regression testing even in the post-silicon stage by generating and running instruction-level random test cases, so that more scenarios can be tested, the testing is more complete, the testing cost is lower, and defects of the chip can be found before the chip is launched into the market.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method, system, device, and storage medium for post-silicon testing. Background Art

[0002] The design and manufacturing process of a typical very large scale integrated circuit can generally be divided into: function partitioning, logic design and verification, synthesis, placement and routing, manufacturing, and testing. Since an integrated circuit is built on a wafer made of silicon as the raw material, the steps before manufacturing have no physical entity, so they can be called pre-silicon, and the steps after manufacturing are called post-silicon.

[0003] For example, a processor is a typical very large scale integrated circuit. As the complexity of the processor increases, sufficient verification is beneficial to discover potential problems in advance and reduce defects in the final product. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a method for post-silicon testing, including: obtaining random configuration information according to a chip to be tested; obtaining a test instruction stream according to the random configuration information; obtaining instruction-level random test cases according to the test instruction stream; and running the instruction-level random test cases on the chip to verify the chip.

[0005] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, the random configuration information includes one or more of the following: a first type of configuration configured not to affect the instruction execution result; a second type of configuration configured to affect the instruction execution result; and test case configuration.

[0006] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, obtaining random configuration information according to a chip to be tested includes: obtaining a plurality of target configurations according to the architecture and microarchitecture of the chip; and obtaining at least one of the first type of configuration and at least one of the second type of configuration of the random configuration information at least partially randomly from a configuration library, where the configuration library includes configuration items and configuration values of each target configuration in the plurality of target configurations.

[0007] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, obtaining at least one of the first type of configuration and at least one of the second type of configuration of the random configuration information at least partially randomly from the configuration library includes: randomly obtaining configuration values of the target configurations in the configuration library, and / or randomly pairing the target configurations with different configuration items in the configuration library to obtain at least one of the first type of configuration and at least one of the second type of configuration of the random configuration information.

[0008] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, the test instruction stream includes at least one first instruction stream configured to test a target function, or the test instruction stream includes at least one second instruction stream configured to be completely random.

[0009] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, obtaining the test instruction stream according to the random configuration information includes: providing at least one first test template according to the random configuration information, and respectively replacing the instruction parameters of each of the at least one first test template with first options to obtain the at least one first instruction stream; or providing at least one second test template according to the instruction format of the instruction set, and respectively replacing the instruction parameters of each of the at least one second test template with second options to obtain the at least one second instruction stream.

[0010] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, the test instruction stream includes at least one first instruction stream configured to test a target function and at least one second instruction stream configured to be completely random.

[0011] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, obtaining the test instruction stream according to the random configuration information includes: providing at least one first test template according to the random configuration information, and respectively replacing the instruction parameters of each of the at least one first test template with first options to obtain the at least one first instruction stream; and providing at least one second test template according to the instruction format of the instruction set, and respectively replacing the instruction parameters of each of the at least one second test template with second options to obtain the at least one second instruction stream.

[0012] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, obtaining the instruction-level random test cases according to the test instruction stream includes: initializing to determine the operating environment of the post-silicon testing; obtaining at least one instruction-level random initial test case according to the test instruction stream; and verifying the at least one instruction-level random initial test case to obtain the corresponding at least one instruction-level random test case with verification.

[0013] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, in response to the test instruction stream including the at least one first instruction stream and the at least one second instruction stream, obtaining at least one random initial test case according to the test instruction stream includes: randomly mixing each of the at least one first instruction stream and each of the at least one second instruction stream to obtain the at least one random initial test case.

[0014] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, verifying the at least one initial test case to obtain the corresponding at least one instruction-level random test case with verification includes: obtaining a reference model; performing a verification operation on each of the at least one initial test case on the reference model to obtain the corresponding reference verification value; associating the reference verification value with the corresponding initial test case to obtain the corresponding instruction-level random test case with verification.

[0015] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, the reference verification value is a cyclic redundancy check value.

[0016] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, running the instruction-level random test case on the chip to verify the chip includes: providing N instruction-level random test cases with verification; in response to running M threads on the chip, randomly selecting M from the N instruction-level random test cases with verification, where N and M are positive integers and N is greater than or equal to M; each of the M instruction-level random test cases with verification is configured to run on the corresponding thread of the chip to obtain the corresponding verification result; comparing the verification result of each of the M instruction-level random test cases with verification with the corresponding reference verification value to verify the chip.

[0017] For example, in a method for post-silicon testing provided by at least one embodiment of the present disclosure, comparing the verification result of each of the M instruction-level random test cases with verification with the corresponding reference verification value to verify the chip includes: in response to at least one of the verification results corresponding to the M instruction-level random test cases with verification being inconsistent with the corresponding reference verification value, the chip test fails; in response to the verification result of each of the M instruction-level random test cases with verification being consistent with the corresponding reference verification value, each of the remaining N - M instruction-level random test cases with verification out of the N instruction-level random test cases with verification is randomly selected to run on the corresponding thread of the chip to obtain the corresponding verification result, where N - M > 0;

[0018] In response to at least one of the verification results corresponding to the remaining N - M instruction-level random test cases with verification being inconsistent with the corresponding reference verification value, the chip test fails;

[0019] In response to the verification result of each of the remaining N - M instruction-level random test cases with verification being consistent with the corresponding reference verification value, the chip test passes.

[0020] At least one embodiment of the present disclosure provides a post-silicon test system, including: a configuration information acquisition module configured to acquire random configuration information according to a chip to be tested; an instruction stream acquisition module configured to acquire a test instruction stream according to the random configuration information; a test case acquisition module configured to acquire randomly generated test cases at the instruction level according to the test instruction stream; and a test case execution module configured to execute the randomly generated test cases at the instruction level on the chip to verify the chip.

[0021] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the method for post-silicon testing as described in any one of the above is implemented.

[0022] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the method for post-silicon testing as described in any one of the above examples is implemented. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a flowchart of a method for post-silicon testing provided by some embodiments of the present disclosure;

[0025] Figure 2 It is a simplified schematic diagram of random configuration information provided by some embodiments of the present disclosure;

[0026] Figure 3 Provided by some embodiments of the present disclosure Figure 1 The flowchart of step S1 in

[0027] Figure 4A It is a simplified diagram of a first test template provided by some embodiments of the present disclosure;

[0028] Figure 4B It is a simplified diagram of a second test template provided by some embodiments of the present disclosure;

[0029] Figure 5 Provided by some embodiments of the present disclosure Figure 1 The flowchart of step S3 in

[0030] Figure 6Schematic diagram of the initial test case provided for some embodiments of the present disclosure;

[0031] Figure 7 Provided for some embodiments of the present disclosure Figure 5 Flowchart of step S33 in

[0032] Figure 8 Provided for some embodiments of the present disclosure Figure 1 Flowchart of step S4 in

[0033] Figure 9 Flowchart for verifying a chip by running an instruction-level random test case on the chip provided for some embodiments of the present disclosure;

[0034] Figure 10 Block diagram of a post-silicon test system provided for some embodiments of the present disclosure; and

[0035] Figure 11 Block diagram of an electronic device provided for some embodiments of the present disclosure. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present disclosure.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the related art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the embodiments of the present disclosure.

[0038] In the embodiments of the present disclosure, the terms "first", "second" and similar terms do not denote any order, quantity or importance, but are only used to distinguish different components. Similar terms such as "a", "an" or "the" do not denote a quantity limitation either, but mean that there is at least one. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily have to be carried out precisely in order. On the contrary, they can be carried out in reverse order or various steps can be processed simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0039] Generally, silicon pre-simulation is to simulate the behavior of a circuit on a computer using simulation software provided by EDA (Electronic Design Automation) manufacturers. Usually, stimuli are injected into the modules or the top layer of the circuit, and the logical function correctness of the circuit is judged by checking whether certain signals in the middle of the circuit or the output signals meet the expectations.

[0040] There are generally two ways to generate stimuli in simulation. One is that the verification personnel write directed test cases to verify specific functions, and the other is to randomly generate test cases according to specific constraints.

[0041] The inventors of the present disclosure have found that through the above-mentioned silicon pre-simulation, most of the logical problems can be verified, but there are also some defects in silicon pre-simulation. For example, the simulation is to simulate the circuit under ideal conditions, but the actual operation of the chip is more complex than the verified situation. Another example is that for a processor, the circuit frequency in the simulation is often about seven orders of magnitude different from the operating frequency of the actual circuit, making it difficult to simulate the circuit behavior for a long time.

[0042] The inventors of the present disclosure have also found that FPGA or hardware provided by EDA manufacturers can be used to accelerate the RTL (Register Transfer Level) simulation to achieve silicon pre-simulation. However, because the hardware of FPGA or EDA manufacturers is very expensive, the cost of large-scale testing is very high, and the speed is still very different from that of the actual processor.

[0043] In response to this, at least one embodiment of the present disclosure provides a post-silicon testing method, including: obtaining configuration information for a chip to be tested; obtaining a test instruction stream according to the configuration information; obtaining instruction-level random test cases according to the test instruction stream; and running the instruction-level random test cases on the chip to verify the chip.

[0044] The post-silicon testing method of the above embodiments of the present disclosure generates and runs instruction-level random test cases, enabling post-silicon to also undergo large-scale regression testing to encounter as many scenarios as possible, thereby being able to test more scenarios, with more complete testing and lower testing costs. It overcomes the deficiencies of the above pre-silicon testing and can detect chip defects before the chip is launched into the market.

[0045] Figure 1 It is a flowchart of a post-silicon testing method provided by some embodiments of the present disclosure.

[0046] For example, as Figure 1 shown, the post-silicon testing method provided by at least one embodiment of the present disclosure includes steps S1 to S4.

[0047] Step S1: Obtain random configuration information according to the chip to be tested.

[0048] Step S2: Obtain a test instruction stream according to the random configuration information.

[0049] Step S3: Obtain instruction-level random test cases according to the test instruction stream.

[0050] Step S4: Run the instruction-level random test cases on the chip to verify the chip.

[0051] Thus, the post-silicon testing method of the above embodiments of the present disclosure generates and runs instruction-level random test cases, enabling post-silicon to also undergo large-scale regression testing to encounter as many scenarios as possible, thereby being able to test more scenarios, with more complete testing and lower testing costs, and being able to detect chip defects before the chip (such as a processor) is launched into the market.

[0052] The inventors of the present disclosure found that although some technical solutions involve post-silicon verification of, for example, a processor, they generally only aim to enable the processor to run correctly and enter the operating system (commonly known as "booting up"), and then some benchmark tests will be run. However, these steps are only running application programs, and the main purpose is not to find processor defects. At the same time, application programs are some code segments with specific purposes and can only verify some specific scenarios. Moreover, whether these application programs run correctly can only be verified by adding specific data self-checks in the program, and there is no general method for checking the running results.

[0053] In some examples, the chip to be tested includes a processor. For example, during the design process of the processor, generally multiple configurations are allowed, and these configurations specify the operating state of the processor and also include requirements for test cases.

[0054] In some examples, the random configuration information is the configuration information provided randomly, and the random configuration information includes one or more of the following: at least one first - type configuration provided randomly, at least one second - type configuration provided randomly, and at least one test - case configuration provided randomly.

[0055] In some examples, the first - type configuration refers to the configuration that does not affect the instruction execution result, and the second - type configuration refers to the configuration that affects the instruction execution result.

[0056] In some examples, the test - case configuration refers to the configuration of the limitations of the test case itself, such as the number of test cases in the generated test - case set, the number of instructions in each test case, the proportion of a certain type of instruction in each test case, etc. There is no need to list and elaborate here one by one.

[0057] Thus, the embodiments of the present disclosure can randomly provide a set of configuration information. For this set of configuration information, it can be randomly one type or randomly multiple types, and the embodiments of the present disclosure do not limit this. Moreover, in the case of randomly providing more types of configurations, the test method of the embodiments of the present disclosure can test more scenarios and the test is more complete.

[0058] Figure 2 It is a simplified schematic diagram of the random configuration information provided for some embodiments of the present disclosure.

[0059] For example, as Figure 2 shown, the first - type configuration includes EnablePrefetch, and EnablePrefetch indicates whether to turn on instruction pre - fetching. Whether to turn on instruction pre - fetching affects the execution efficiency of the instruction, but does not affect the instruction execution result. Therefore, EnablePrefetch belongs to the first - type configuration that does not affect the instruction execution result.

[0060] For example, as Figure 2 shown, the second - type configuration includes EnableEncryption, and EnableEncryption indicates whether to allow encryption instructions. Since running a test case containing encryption instructions on a processor that does not allow the execution of encryption instructions will cause the processor to enter an abnormal state, EnableEncryption belongs to the second - type configuration that affects the instruction execution result.

[0061] For example, as Figure 2As shown, the test case configuration includes TestcaseNum. TestcaseNum represents the number of test cases to be generated. Therefore, TestcaseNum belongs to the configuration that restricts the test cases themselves.

[0062] It should be noted that the various configurations of the random configuration information in the embodiments of the present disclosure are not limited to the above examples, and can also be other reasonable configurations. For example, the first type of configuration can include Enablex2Apic, and Enablex2Apic means to turn on the x2apic mode. Another example is that the second type of configuration can include EnableSVM, and EnableSVM means that SVM-related instructions can be issued only after it is turned on. Another example is that the test case configuration can include EncryptionRatio, and EncryptionRatio represents the ratio of controlling encryption instructions. The embodiments of the present disclosure do not limit this, and do not make an exhaustive list and elaboration.

[0063] Figure 3 For some embodiments provided by the present disclosure Figure 1 The flowchart of step S1 in

[0064] For example, as Figure 3 shown, for step S1, obtaining random configuration information according to the chip to be tested includes step S11 and step S12.

[0065] Step S11: Obtain a plurality of target configurations according to the architecture and microarchitecture of the chip.

[0066] Step S12: Randomly obtain at least one first type of configuration and at least one second type of configuration of the random configuration information from at least part of the configuration library, where the configuration library includes configuration items and configuration values of each target configuration in the plurality of target configurations.

[0067] Thus, the embodiments of the present disclosure randomly select the first type of configuration and the second type of configuration in the configuration library, so that the post-silicon test method can test more scenarios and the test is more complete.

[0068] For step S11, in some examples, when designing, for example, a processor, a design specification is given, and all register information is provided according to this design specification. Thus, all possible target configurations can be found according to the architecture and microarchitecture of the processor.

[0069] For step S12, in some examples, all configuration items and configuration values of the target configuration are placed in a configuration library, and are completely randomly or randomly according to constraints in the configuration library to obtain the first type of configuration and the second type of configuration of the random configuration information. For example, randomness in the configuration library can be randomness in two aspects. For example, on the one hand, it is randomness of the configuration value, and on the other hand, it is random pairing of the configurations of different configuration items. This is only exemplary and is not a limitation of the present disclosure.

[0070] For example, for step S12, obtaining the first type of configuration and the second type of configuration of the random configuration information from the configuration library at least partially randomly includes: completely randomly or randomly according to constraints obtaining the configuration values of the target configuration in the configuration library, and / or completely randomly or randomly according to constraints randomly pairing the target configurations with different configuration items in the configuration library to obtain the first type of configuration and the second type of configuration of the random configuration information. In this way, the post-silicon test method of the embodiments of the present disclosure can test more scenarios, can meet the test requirements, and the test is more complete.

[0071] In some examples, the test instruction stream refers to the instruction stream of the post-silicon test, abbreviated as the test instruction stream. The test instruction stream includes at least one first instruction stream and / or at least one second instruction stream. The first instruction stream is configured to test a target function (such as a specific function), and the second instruction stream is configured to be completely random.

[0072] It should be noted that the embodiments of the present disclosure can generate any one of the first instruction stream and the second instruction stream according to the random configuration information. For example, in the case of only generating the first instruction stream, the post-silicon test method of the embodiments of the present disclosure has a high test efficiency, but only covers a part of the instructions and has a slightly poor coverage. Another example is that in the case of only generating the second instruction stream, the post-silicon test method of the embodiments of the present disclosure can cover all instructions, but has a low test efficiency. In addition, the embodiments of the present disclosure can generate both the first instruction stream and the second instruction stream according to the random configuration information. In this way, the post-silicon test method of the embodiments of the present disclosure not only has a good test efficiency, but also has a good coverage, making the test more complete.

[0073] In some examples, the first instruction stream for testing a specific function comes from a test template given by a tester according to the characteristics of the chip under test (such as the processor under test), and the random second instruction stream comes from the instruction format provided by the instruction set.

[0074] Figure 4A Schematic diagram of the first test template provided by some embodiments of the present disclosure. Figure 4B Schematic diagram of the second test template provided by some embodiments of the present disclosure.

[0075] For example, as Figure 4AAs shown, the functions corresponding to the first test template A1 are: placing a memory address into the first register; placing a number into the second register; writing the above number into the above memory address; reading the value from the above memory address and putting it into the third register, and comparing the values in the second register and the third register; if they are not equal, then jump to the test failure program.

[0076] For example, as Figure 4B shown, the second test template A2 is a purely random test template.

[0077] For example, for step S2, when the test instruction stream obtained according to the random configuration information includes the first instruction stream, step S2 includes: providing at least one first test template according to the random configuration information, and respectively replacing the instruction parameters of each first test template with first options to obtain the corresponding first instruction stream.

[0078] Thus, the embodiments of the present disclosure can give test templates according to the characteristics of the chip to be tested, and replace them with corresponding options according to the special meanings of each instruction parameter to form the first instruction stream, so as to verify code segments in specific scenarios, and the test efficiency is relatively high.

[0079] Another example, for step S2, when the test instruction stream obtained according to the random configuration information includes the second instruction stream, step S2 includes: providing at least one second test template according to the instruction format of the instruction set, and respectively replacing the instruction parameters of each second test template with second options to obtain the corresponding second instruction stream.

[0080] Thus, the implementation of the present disclosure can provide a completely random test template according to the instruction format of the instruction set, and replace it with corresponding options according to the special meanings of each instruction parameter to form the second instruction stream, so as to test more scenarios and the test is more complete.

[0081] For example, in Figure 4A the example, the format (such as instruction parameters) of the first test template A1 is replaced with specific content (such as options) to obtain the corresponding first instruction stream. For example, in Figure 4B the example, the format (such as instruction parameters) of the second test template A2 is replaced with specific content (such as options) to obtain the corresponding second instruction stream. For example, reg_1, reg_2, reg_3 are replaced with 3 different registers, reg is replaced with a random register, mem is replaced with a legal memory address, and imm is replaced with a random number. This is only exemplary and not a limitation of the present disclosure.

[0082] Figure 5 For some embodiments of the present disclosure Figure 1 is the flowchart of step S3.Figure 6 Schematic diagram of an initial test case provided for some embodiments of the present disclosure.

[0083] For example, as Figure 5 shown, for step S3, obtaining a test case with instruction-level randomness according to a test instruction stream includes steps S31 to S33.

[0084] Step S31, initialization, to determine the operating environment for post-silicon testing.

[0085] Step S32, obtain at least one initial test case with instruction-level randomness according to the test instruction stream.

[0086] Step S33, verify at least one initial test case with instruction-level randomness to obtain the corresponding at least one verified test case with instruction-level randomness.

[0087] Thus, the test cases of the embodiments of the present disclosure have self-verification, enabling the chip to quickly detect possible problems at an extremely fast operating speed, achieving scientific and efficient post-silicon testing.

[0088] For example, for step S31, in some examples, initialization can make the environment for each run of the test case consistent, so that the test results are also consistent. The embodiments of the present disclosure do not limit the method of initialization. For example, initialization can be achieved by writing registers in assembly language, which will not be elaborated here.

[0089] For example, for step S31, in some examples, multiple instruction streams included in the test instruction stream are randomly mixed to generate a test case. For example, when the test instruction stream includes a first instruction stream and a second instruction stream, the first instruction stream and the second instruction stream are randomly mixed to generate an initial test case with instruction-level randomness. Thus, the embodiments of the present disclosure generate an initial test case with instruction-level randomness by mixing a first instruction stream for testing a specific function and a random second instruction stream, which not only has good test efficiency but also good coverage.

[0090] For example, in Figure 6 the example, the initial test case B with instruction-level randomness is formed by Figure 4A the first instruction stream corresponding to the example and Figure 4B the second instruction stream corresponding to the example being mixed. This is merely exemplary and not a limitation of the present disclosure.

[0091] It should be noted that the above-mentioned randomly mixing the first instruction stream and the second instruction stream can be mixing one first instruction stream and one second instruction stream. In this way, more random test cases can be obtained, more scenarios can be tested, the test is more complete, and the actual operation is simpler. Of course, it can also be mixing one first instruction stream and multiple second instruction streams, or mixing multiple first instruction streams and one second instruction stream, or mixing multiple first instruction streams and multiple second instruction streams. The embodiments of the present disclosure do not limit this and can be freely adjusted according to actual situations.

[0092] Figure 7 For some embodiments provided by the present disclosure Figure 5 The flowchart of step S33 in

[0093] For example, as Figure 7 shown, for step S33, verifying at least one initial test case and obtaining the corresponding at least one instruction-level random test case with verification includes steps S331 to S333.

[0094] Step S331: Obtain a reference model.

[0095] Step S332: Perform verification operations on each of the at least one initial test cases on the reference model respectively to obtain the corresponding reference verification values.

[0096] Step S333: Associate the reference verification values with the corresponding initial test cases to obtain the corresponding instruction-level random test cases with verification.

[0097] Thus, the embodiments of the present disclosure add real-time verification for registers during the test process to generate instruction-level random test cases with verification. Therefore, there is no need to compare the register values one by one, avoiding low efficiency caused by excessive time consumption. The embodiments of the present disclosure can directly know the expected verification values (i.e., reference verification values) of the registers after a section of instruction stream is executed through the instruction-level random test cases with verification, and use them to compare with the verification results obtained by the registers after the test cases are run on the chip to be tested. The efficiency is relatively high, thus realizing scientific and efficient post-silicon testing.

[0098] For example, for step S331, in some examples, the reference model refers to a chip with the same instruction set that can be obtained in the market (such as a processor of AMD or Intel). Therefore, the reference model has been fully verified before being put on the market, avoiding repeated labor; in other examples, the reference model can also be other existing chips with the same instruction set, etc.

[0099] For example, for step S332, in some examples, the reference check value may be a cyclic redundancy check value, that is, the reference check value is a CRC (Cyclic Redundancy Check) reference check value. Thus, the embodiments of the present disclosure can generate instruction-level random test cases with checks using CRC checks. It should be noted that the embodiments of the present disclosure are not limited to CRC checks, and other check methods can also be used, such as parity checks, longitudinal redundancy checks (LRC), checksums, etc. The embodiments of the present disclosure are not limited thereto, as long as a reference check value that can be associated with the initial test case is obtained through the check, which will not be elaborated here.

[0100] In some examples, when generating instruction-level random test cases with CRC checks, step S33 includes steps one to three, as follows.

[0101] Step one: Obtain a reference model.

[0102] Step two: Perform CRC check operations on each of at least one initial test case on the reference model to obtain the corresponding CRC reference check value.

[0103] Step three: Write the CRC reference check value back to the corresponding initial test case to obtain the corresponding instruction-level random test case with CRC checks respectively.

[0104] Thus, the embodiments of the present disclosure can detect the results of any code segment by adding real-time CRC checks for registers during the test process, generate instruction-level random test cases with CRC checks, with relatively high efficiency, strong error detection ability, and high reliability.

[0105] It should be noted that for step S333, the reference check value associated with the corresponding initial test case can be added to the original data frame in the form of a data frame to obtain a new data frame. For example, if the original data frame becomes 101100110000, dividing it by the divisor 11001 using modulo 2 division gives a remainder of 0100, which is the CRC check code. Then the data frame after addition is 101100110100. However, the embodiments of the present disclosure are not limited thereto, and can be adjusted accordingly according to the actual check method used, as long as the check value that the register should have after the execution of an instruction stream can be directly obtained from the instruction-level random test case with checks, all are within the protection scope of the present disclosure, which will not be elaborated here.

[0106] Figure 8 For some embodiments of the present disclosure Figure 1 The flowchart of step S4.

[0107] For example, as Figure 8 shown, for step S4, test cases with instruction-level randomness are run on the chip to verify that the chip includes steps S41 to S44.

[0108] Step S41, schedule N test cases with instruction-level randomness and checksums.

[0109] Step S42, in response to M threads running on the chip, randomly select M from the N test cases with instruction-level randomness and checksums, where N and M are positive integers and N is greater than or equal to M.

[0110] Step S43, each of the M test cases with instruction-level randomness and checksums is configured to run on the corresponding thread of the chip, and obtain the corresponding checksum results.

[0111] Step S44, compare the checksum result of each of the M test cases with instruction-level randomness and checksums with the corresponding reference checksum value to verify the chip.

[0112] Thus, embodiments of the present disclosure verify the chip by comparing the reference checksum value in the test cases with instruction-level randomness and checksums with the checksum results obtained after running the test cases on the chip to be tested, to check whether the result of the instruction stream running on the chip to be tested is correct. For example, if the checksum result obtained by running on the chip to be tested is consistent with the reference checksum value obtained by running on the reference model, the chip to be tested passes the test; otherwise, the chip to be tested fails the test.

[0113] Figure 9 It is a flowchart of running test cases with instruction-level randomness on the chip to verify the chip provided by some embodiments of the present disclosure.

[0114] For example, as Figure 9 shown, running test cases with instruction-level randomness on the chip to verify the chip includes steps T41 to T47.

[0115] Step T41, schedule N test cases with instruction-level randomness and checksums.

[0116] Step T42, randomly select from the N test cases with instruction-level randomness and checksums, for example, randomly select M test cases with instruction-level randomness and checksums, where N and M are positive integers and N is greater than or equal to M.

[0117] Step T43, each of the M test cases with instruction-level randomness and checksums is configured to run on the corresponding thread among the M threads of the chip, and obtain the corresponding checksum results.

[0118] Step T44: Compare the verification result of each of the M randomly selected test cases with instruction-level verification with the corresponding reference verification value.

[0119] Step T45: Determine whether the verification result is consistent with the corresponding verification value. If not, directly go to Step T47 and end the test, that is, when the verification result corresponding to at least one of the M randomly selected test cases with instruction-level verification is inconsistent with the corresponding verification value, the chip test ends and the chip test is determined to be failed; if so, that is, when the verification result corresponding to each of the M randomly selected test cases with instruction-level verification is consistent with the corresponding reference verification value, then continue to execute Step T46.

[0120] Step T46: Determine whether the number of times of running the randomly selected test cases with instruction-level verification on the chip reaches N times, that is, determine whether all of the N randomly selected test cases with instruction-level verification that are scheduled have been completely run and verified. If not, go to Step T42, randomly select another one from the remaining N - M (N - M > 0) randomly selected test cases with instruction-level verification and run it on the corresponding thread, obtain the corresponding verification result, and repeat the above Steps T43 to T46 until the test ends; if so, go to Step T47 and end the test.

[0121] Thus, the post-silicon test method of the embodiments of the present disclosure can select randomly selected test cases with instruction-level verification according to the threads of the chip, which can not only effectively and qualitatively test the chip, but also ensure a certain test pressure and improve the execution speed.

[0122] In some examples, when the verification result corresponding to at least one of the remaining N - M randomly selected test cases with instruction-level verification is inconsistent with the corresponding reference verification value, the chip test is failed, and at this time, the reason for the error needs to be found. When the verification result corresponding to each of the remaining N - M randomly selected test cases with instruction-level verification is consistent with the corresponding reference verification value, the chip test is passed.

[0123] For example, for Step T41, in some examples, multiple randomly selected test cases with instruction-level verification are scheduled by using the C language. This is only exemplary and not a limitation of the present disclosure.

[0124] For example, for Step T46, in some examples, after the M randomly selected test cases with instruction-level verification are run on the corresponding threads, after each test case is run, a new test case is randomly selected to fill the vacancy until N test cases are run. In this way, the post-silicon test method of the embodiments of the present disclosure can ensure the test pressure.

[0125] Figure 10 It is a block diagram of a post-silicon test system provided for some embodiments of the present disclosure.

[0126] For example, as Figure 10 shown, the post-silicon test system 100 provided by at least one embodiment of the present disclosure includes a configuration information acquisition module 101, an instruction stream acquisition module 102, a test case acquisition module 103, and a test case execution module 104. The configuration information acquisition module 101 is configured to acquire random configuration information according to the chip to be tested. The instruction stream acquisition module 102 is configured to acquire a test instruction stream according to the random configuration information. The test case acquisition module 103 is configured to acquire instruction-level random test cases according to the test instruction stream. The test case execution module 104 is configured to execute the instruction-level random test cases on the chip to verify the chip.

[0127] It should be noted that, in the embodiments of the present disclosure, the post-silicon test system 100 may include more or fewer modules, and the connection relationships between the various modules are not limited and may be determined according to actual requirements. The specific composition manners of the various modules are not limited. For the technical effects of the post-silicon test system 100, reference may be made to the technical effects of the post-silicon test method provided in the above embodiments of the present disclosure, which will not be elaborated here.

[0128] Each of the above modules in the embodiments may be respectively configured as software, hardware, firmware, or any combination of the above items for performing specific functions. For example, these modules may correspond to dedicated integrated circuits, may also correspond to pure software codes, or may also correspond to modules combining software and hardware.

[0129] It should be noted that although the post-silicon test system is divided into modules for respectively performing corresponding processes above, however, those skilled in the art are aware that the processes executed by each module may also be executed when the post-silicon test system does not perform any specific module division or there is no clear demarcation between the modules.

[0130] Figure 11 It is a schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 11 The shown electronic device is merely an example and should not bring any limitation to the functions and usage scopes of the embodiments of the present disclosure.

[0131] For example, as Figure 11As shown, in some examples, the electronic device 200 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) 201, which can perform the post-silicon testing as described above according to a program stored in a read-only memory (ROM) 202 or a program loaded from a storage device 208 into a random access memory (RAM) 203. In the RAM 203, various programs and data required for the operation of the computer system are also stored. The processing device 201, the ROM 202, and the RAM 203 are connected to each other through a bus 204. An input / output (I / O) interface 205 is also connected to the bus 204.

[0132] For example, the following components can be connected to the I / O interface 205: an input device 206 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 207 including, such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 208 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 209 including a network interface card such as a LAN card, a modem, etc. The communication device 209 can allow the electronic device 200 to communicate with other devices wirelessly or wiredly to exchange data and perform communication processing via a network such as the Internet. A driver 310 is also connected to the I / O interface 205 as needed. A removable medium 311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the driver 310 as needed so that a computer program read from it can be installed into the storage device 209 as needed. Although Figure 11 an electronic device 200 including various devices is shown, it should be understood that it is not required to implement or include all the shown devices. More or fewer devices can be alternatively implemented or included.

[0133] For example, the electronic device 200 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 209 can communicate with the network and other devices through wireless communication. The network can be, for example, the Internet, an intranet, and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any one of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on the IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), WiMAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0134] For example, the electronic device can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or can be any combination of an electronic device and hardware. The embodiments of the present disclosure are not limited thereto.

[0135] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium. The computer program contains program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 209, or installed from the storage device 208, or installed from the ROM 202. When the computer program is executed by the processing device 201, the above-mentioned post-silicon test function defined in the method of the embodiment of the present disclosure is executed.

[0136] It should be noted that the computer-readable medium described above in the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in conjunction with an instruction execution system, apparatus, or device. In an embodiment of the present disclosure, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0137] In some embodiments, the client and the server may communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LANs"), wide area networks ("WANs"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0138] The above computer-readable medium may be included in the above electronic device; or it may exist separately without being assembled into the electronic device.

[0139] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 200 may refer to the description of the method for post-silicon testing in the above text, and will not be elaborated here.

[0140] The following points need to be noted:

[0141] (1) The attached drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0142] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0143] As described above, it is only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A method for post - silicon testing, comprising: Obtaining random configuration information according to the chip to be tested; Obtaining a test instruction stream according to the random configuration information; Obtaining instruction - level random test cases according to the test instruction stream; Running the instruction - level random test cases on the chip to verify the chip; Wherein, obtaining the instruction - level random test cases according to the test instruction stream includes: Initializing to determine the operating environment of the post - silicon testing; Obtaining at least one instruction - level random initial test case according to the test instruction stream; Verifying the at least one instruction - level random initial test case to obtain the corresponding at least one verified instruction - level random test case.

2. The method for post - silicon testing according to claim 1, wherein, The random configuration information includes one or more of the following: The first type of configuration configured not to affect the instruction execution result; The second type of configuration configured to affect the instruction execution result; Test case configuration.

3. The method for post-silicon testing according to claim 2, wherein, Obtaining the random configuration information according to the chip to be tested includes: Obtaining a plurality of target configurations according to the architecture and micro - architecture of the chip; Obtaining at least one of the first type of configuration and at least one of the second type of configuration of the random configuration information at least partially randomly from a configuration library, wherein the configuration library includes configuration items and configuration values of each target configuration among the plurality of target configurations.

4. The method for post-silicon testing according to claim 3, wherein, Obtaining at least one of the first type of configuration and at least one of the second type of configuration of the random configuration information at least partially randomly from the configuration library includes: Randomly obtaining the configuration values of the target configurations in the configuration library, and / or randomly pairing the target configurations with different configuration items in the configuration library to obtain at least one of the first type of configuration and at least one of the second type of configuration of the random configuration information.

5. The method for post - silicon testing according to claim 1, wherein, The test instruction stream includes at least one first instruction stream configured to test a target function; Or, the test instruction stream includes at least one second instruction stream configured to be completely random.

6. The method for post-silicon testing as claimed in claim 5, wherein, Obtaining the test instruction stream according to the random configuration information includes: Providing at least one first test template according to the random configuration information and respectively replacing the instruction parameters in each of the at least one first test template with first options to obtain the at least one first instruction stream; or, Providing at least one second test template according to the instruction format of the instruction set and respectively replacing the instruction parameters in each of the at least one second test template with second options to obtain the at least one second instruction stream.

7. The method for post - silicon testing according to claim 1, wherein, The test instruction stream includes at least one first instruction stream configured to test a target function and at least one second instruction stream configured to be completely random.

8. The method for post-silicon testing according to claim 7, wherein, Obtaining the test instruction stream according to the random configuration information includes: Providing at least one first test template according to the random configuration information and respectively replacing the instruction parameters in each of the at least one first test template with first options to obtain the at least one first instruction stream; and, Provide at least one second test template according to the instruction format of the instruction set, and replace the instruction parameters of each of the at least one second test template with second options respectively to obtain the at least one second instruction stream.

9. The method for post-silicon testing according to any one of claims 5 to 8, wherein In response to the test instruction stream including the at least one first instruction stream and the at least one second instruction stream, obtaining at least one random initial test case according to the test instruction stream includes: Randomly mix each of the at least one first instruction stream and each of the at least one second instruction stream to obtain the at least one random initial test case.

10. The method of post-silicon testing according to any one of claims 5 to 8, wherein, Verify the at least one initial test case to obtain the corresponding at least one instruction-level random test case with verification, including: Obtain a reference model; Perform verification operations on each of the at least one initial test case on the reference model respectively to obtain the corresponding reference verification values; Associate the reference verification values with the corresponding initial test cases to obtain the corresponding instruction-level random test cases with verification.

11. The method for post-silicon testing according to claim 10, wherein, The reference verification value is a cyclic redundancy check value.

12. The method for post-silicon testing according to claim 10, wherein, Running the instruction-level random test cases on the chip to verify the chip includes: Provide N of the instruction-level random test cases with verification; In response to running M threads on the chip, randomly select M from the N instruction-level random test cases with verification, where N and M are positive integers and N is greater than or equal to M; Each of the M instruction-level random test cases with verification is configured to run on the corresponding thread of the chip respectively to obtain the corresponding verification results; Compare the verification result of each of the M instruction-level random test cases with verification with the corresponding reference verification value to verify the chip.

13. The method for post-silicon testing according to claim 12, wherein, Comparing the verification result of each of the M instruction-level random test cases with verification with the corresponding reference verification value to verify the chip includes: In response to at least one of the verification results corresponding to the M instruction-level random test cases with verification being inconsistent with the corresponding reference verification value, the chip test fails; In response to the verification result of each of the M instruction-level random test cases with verification being consistent with the corresponding reference verification value, each of the remaining N - M instruction-level random test cases with verification among the N instruction-level random test cases with verification excluding the M instruction-level random test cases with verification is randomly selected to run on the corresponding thread of the chip to obtain the corresponding verification results, where N - M > 0; In response to at least one of the verification results corresponding to the remaining N - M instruction-level random test cases with verification being inconsistent with the corresponding reference verification value, the chip test fails; In response to the verification result of each of the remaining N - M instruction-level random test cases with verification being consistent with the corresponding reference verification value, the chip test passes.

14. A post-silicon testing system, including: A configuration information acquisition module, configured to acquire random configuration information according to a chip to be tested; An instruction stream acquisition module, configured to acquire a test instruction stream according to the random configuration information; A test case acquisition module, configured to acquire randomly generated instruction-level test cases according to the test instruction stream; A test case execution module, configured to execute the randomly generated instruction-level test cases on the chip to verify the chip; Wherein, acquiring the randomly generated instruction-level test cases according to the test instruction stream includes: Initializing to determine the operating environment for post-silicon testing; Acquiring at least one randomly generated initial test case at the instruction level according to the test instruction stream; Verifying the at least one randomly generated initial test case at the instruction level to obtain the corresponding at least one verified test case at the instruction level.

15. An electronic device, comprising: A processor and a memory, Wherein, a computer program is stored on the memory, and when the computer program is executed by the processor, the method for post-silicon testing according to any one of claims 1 to 13 is implemented.

16. A computer-readable storage medium, wherein, A computer program is stored in the storage medium, and when the computer program is executed by a processor, the method for post-silicon testing according to any one of claims 1 to 13 is implemented.

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