Method of manufacturing a semiconductor device

Abstract

Embodiments of the present disclosure disclose a method for manufacturing a semiconductor device. The method comprises: providing a pseudo stack structure; wherein the pseudo stack structure comprises: insulating layers and gaps arranged alternately in a stack, and a recess passing through the pseudo stack structure, the recess being in communication with the gaps; depositing a dielectric material conformally along the recess and the gaps to form a dielectric layer covering side walls of the recess, surfaces of the gaps, and a bottom of the recess; performing a doping process on the dielectric layer covering the side walls of the recess and the bottom of the recess to form a first doped region; and removing the first doped region by using an etchant; wherein a chemical reaction between the etchant and the dielectric layer covering the surfaces of the gaps is an inert reaction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and more particularly to a method for manufacturing a semiconductor device. Background Technology

[0002] With the development of technology, people are using more and more portable electronic devices in their lives, such as digital cameras, MP3 players, tablets, and smartphones. As a result, the memory market has also grown rapidly, leading to a gradual increase in the integration and bit density of memory.

[0003] However, with the increasing integration and bit density of memory, the feature size of vias or trenches used to deposit thin films to form related functional structures in memory is becoming smaller and smaller, leading to increased difficulty and reduced uniformity in thin film deposition. Therefore, how to reduce the difficulty of thin film deposition and improve its uniformity while ensuring high integration and bit density of memory has become an urgent problem to be solved. Summary of the Invention

[0004] In view of the above, this disclosure provides a method for fabricating a semiconductor device, the method comprising:

[0005] A pseudo-stacked structure is provided; wherein the pseudo-stacked structure includes: an insulating layer and a gap that are alternately stacked, and a groove that penetrates the pseudo-stacked structure, the groove communicating with the gap;

[0006] A dielectric material is conformally deposited along the groove and the gap to form a dielectric layer covering the sidewalls of the groove, the surface of the gap, and the bottom of the groove;

[0007] The dielectric layer covering the sidewalls of the groove and the bottom of the groove is doped to form a first doped region;

[0008] The first doped region is removed using an etchant; wherein the chemical reaction between the etchant and the dielectric layer covering the gap surface is an inert reaction.

[0009] In some embodiments, doping the dielectric layer covering the sidewalls of the groove and the bottom of the groove to form a first doped region includes:

[0010] Ion implantation is performed on the dielectric layer covering the sidewalls of the groove and the bottom of the groove to introduce defects in the dielectric layer covering the sidewalls of the groove and the bottom of the groove.

[0011] In some embodiments, the ratio of the reaction rate between the etchant and the first doped region to the reaction rate between the etchant and the dielectric layer covering the gap surface is greater than 25.

[0012] In some embodiments, the constituent materials of the dielectric layer include: a dielectric material with a dielectric constant greater than 3.9;

[0013] The doped particles in the first doped region include: boron, phosphorus, argon, germanium, indium, carbon, or nitrogen;

[0014] The etching agent comprises a mixture of dilute sulfuric acid and hydrogen peroxide, or hydrofluoric acid.

[0015] In some embodiments, the dielectric layer is composed of materials such as aluminum oxide, hafnium oxide, or titanium dioxide.

[0016] In some embodiments, providing the pseudo-stacked structure includes:

[0017] A stacked structure is formed on a substrate; wherein the stacked structure includes: an insulating layer and a sacrificial layer that are alternately stacked, and a support pillar that penetrates the stacked structure;

[0018] The groove is formed through the stacked structure;

[0019] The sacrificial layer is removed to form the gap, wherein the gap exposes the sidewall of the support column.

[0020] In some embodiments, the substrate surface includes: a first region and a second region; wherein the stacked structure is located in the first region;

[0021] The method further includes:

[0022] While conformally depositing the dielectric material along the groove and the gap, the dielectric material covering the second region is formed;

[0023] When the dielectric layer covering the sidewalls of the groove and the bottom of the groove is doped, the dielectric material covering the second region is also doped to form a second doped region in the second region.

[0024] When removing the first doped region using the etchant, the second doped region is also removed using the etchant.

[0025] In some embodiments, the method further includes:

[0026] After removing the first doped region using the etchant, a barrier layer and a gate layer covering the dielectric layer of the gap surface are formed sequentially.

[0027] In some embodiments, the method is applied to the manufacture of a three-dimensional memory.

[0028] In some embodiments, the three-dimensional memory includes: 3D NAND memory.

[0029] Compared to directly depositing thin film materials in a groove covered with a dielectric layer on the sidewalls and bottom, in this embodiment of the present disclosure, by doping the dielectric layer covering the sidewalls and bottom of the groove, a first doped region can be formed in the dielectric layer. The first doped region can be removed by using an etchant, which can increase the process window for subsequent deposition of thin film materials and help reduce the process difficulty of thin film deposition.

[0030] Furthermore, the increased process window ensures that the thickness of the films deposited at the top and bottom of the pseudo-stacked structure is more uniform, which is beneficial to improving the reliability of semiconductor devices.

[0031] Furthermore, since the chemical reaction between the etchant and the dielectric layer covering the gap surface is an inert reaction, while increasing the subsequent process window, the dielectric layer covering the gap surface can be retained, preventing particles from entering the gap and revealing other functional structures (e.g., support pillars) during the subsequent thin film deposition process. Attached Figure Description

[0032] Figures 1a to 1d This is a schematic diagram illustrating a method for fabricating a semiconductor device based on relevant technologies;

[0033] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0034] Figures 3a to 3f This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0035] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0036] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0037] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0038] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0039] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0040] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0041] Figures 1a to 1d This is a schematic diagram illustrating a method for fabricating a semiconductor device 100 according to related technologies. (Refer to...) Figure 1a As shown, the fabrication of semiconductor device 100 includes at least the following steps:

[0042] Step 1: Form a stacked structure 120 on the substrate 110; wherein the stacked structure 120 includes: an insulating layer 121 and a sacrificial layer (not shown) that are alternately stacked;

[0043] Step 2: Form the support column 130 through the stacked structure 120;

[0044] For example, refer to Figure 1a As shown, the support pillar 130 includes: a barrier layer 131, a storage layer 132, a tunneling layer 133, a channel layer 134, and an insulating pillar 135. The support pillar 130 can be a storage pillar for storing information, or it can be a virtual pillar for supporting a stacked structure. When the support pillar is a virtual pillar, it can be filled only with insulating material.

[0045] Step 3: Form a trench 150 that penetrates the stacked structure 120 and the dielectric layer 140;

[0046] Step 4: Remove the sacrificial layer along the sidewall of the trench 150 to form a gap between adjacent insulating layers 121; wherein one end of the gap exposes the sidewall of the support post, and the other end of the gap communicates with the trench 150.

[0047] Step 5: Conformally deposit dielectric material based on trench 150 and gap to form dielectric layer 151 covering the sidewalls of trench 150, the surface of gap and the bottom of trench 150;

[0048] Step 6: Sequentially deposit the metal barrier material and the gate material covering the dielectric layer 151, etch back part of the metal barrier material and part of the gate material along the direction close to the support pillar 130, and the remaining metal barrier material and the remaining gate material form the metal barrier layer 152 and the gate layer 153, respectively.

[0049] Taking aluminum oxide (AlO) as the dielectric material, titanium nitride (TiN) as the metal barrier material, and tungsten (W) as the gate material as an example, in related technologies, the selectivity of H4 (a mixed solution of phosphoric acid, nitric acid, acetic acid, and water) for tungsten, titanium nitride, and aluminum oxide can be used to etch back part of the metal barrier material and part of the gate material, forming a structure like... Figure 1a The structure shown, Figure 1b It shows Figure 1a The magnified view within the dashed box shows that H4 has a low selectivity for AlO (i.e., etching rate).

[0050] It should be noted that in steps five and six above, sub-trenches can be formed in trench 150 based on dielectric layer 151. Combined with... Figure 1c and Figure 1d As shown, the characteristic dimension W1 (Critical Dimension, CD) of the sub-groove is smaller than the characteristic dimension W2 of the trench.

[0051] After forming the metal barrier layer and the gate layer, other functional structures (e.g., common source) can be formed in the sub-trench by filling it with insulating and / or conductive materials.

[0052] In related technologies, to increase the process window for filling insulating and / or conductive materials, the temperature of rapid thermal annealing (RTA) of the dielectric material is lowered during dielectric material deposition. This increases the etching rate of the etchant on the dielectric material during the etch-back process of the metal barrier and gate materials in step six, removing the dielectric layer covering the trench sidewalls and bottom, thus forming a layer such as... Figure 1d The structure is shown. However, lowering the rapid thermal annealing temperature affects the crystallinity of the dielectric layer covering the gap surface, leading to a decrease in the electrical performance of the semiconductor device.

[0053] Furthermore, as the integration and bit density of semiconductor devices increase, the feature size of trenches becomes smaller and smaller. Correspondingly, the feature size of sub-trenches formed after the deposition of dielectric layers also becomes smaller and smaller. This increases the difficulty of depositing metal barrier materials and gate materials based on the sub-trench process window in step six above.

[0054] Furthermore, as the integration density and bit density of semiconductor devices increase, the number of layers in the stacked structure gradually increases. Correspondingly, the depth of the trenches penetrating the stacked structure also continuously increases, reducing the uniformity of the deposited metal barrier material and gate material in step six above. For example, the thickness of the top metal barrier layer is greater than the thickness of the bottom metal barrier layer, and the thickness of the top gate layer is less than the thickness of the bottom gate layer.

[0055] In view of this, the present disclosure provides a method for manufacturing a semiconductor device.

[0056] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure. (Refer to...) Figure 2 As shown, the method includes the following steps:

[0057] S110: Provides a pseudo-stacked structure; wherein the pseudo-stacked structure includes: an insulating layer and a gap arranged in alternating stacks and a groove penetrating the pseudo-stacked structure, the groove communicating with the gap;

[0058] S120: Conformally deposit dielectric material along the grooves and gaps to form a dielectric layer covering the sidewalls of the grooves, the surface of the gaps, and the bottom of the grooves;

[0059] S130: The dielectric layer covering the sidewalls and bottom of the covered groove is doped to form the first doped region;

[0060] S140: Remove the first doped region using an etchant; wherein the chemical reaction between the etchant and the dielectric layer covering the gap surface is an inert reaction.

[0061] Compared to directly depositing thin film materials in a groove covered with a dielectric layer on the sidewalls and bottom, in this embodiment of the present disclosure, by doping the dielectric layer covering the sidewalls and bottom of the groove, a first doped region can be formed in the dielectric layer. The first doped region can be removed by using an etchant, which can increase the process window for subsequent deposition of thin film materials and help reduce the process difficulty of thin film deposition.

[0062] Furthermore, the increased process window ensures that the thickness of the films deposited at the top and bottom of the pseudo-stacked structure is more uniform, which is beneficial to improving the reliability of semiconductor devices.

[0063] Furthermore, since the chemical reaction between the etchant and the dielectric layer covering the gap surface is an inert reaction, while increasing the subsequent process window, the dielectric layer covering the gap surface can be retained, preventing particles from entering the gap and revealing other functional structures (e.g., support pillars) during the subsequent thin film deposition process.

[0064] Compared to related technologies that involve reducing the temperature of rapid thermal annealing of dielectric materials to remove the dielectric layer covering the sidewalls and bottom of the trench, the present disclosure embodiment performs doping treatment on the dielectric layer covering the sidewalls and bottom of the trench, which has less impact on the dielectric layer on the surface of the gap, thus helping to maintain the electrical performance of the semiconductor device.

[0065] Figures 3a to 3f This is a schematic diagram illustrating a method for fabricating a semiconductor device 200 according to an embodiment of this disclosure. The following will be combined with... Figure 2 , Figures 3a to 3f This disclosure will be further explained in more detail.

[0066] First, refer to Figure 3b As shown, step S110 is performed: a pseudo-stacked structure 220' is provided, wherein the pseudo-stacked structure 220' includes: an insulating layer 221 and a gap 241 that are alternately stacked, and a groove 240 that penetrates the pseudo-stacked structure 220', the groove 240 communicating with the gap 241.

[0067] The insulating layer 221 is composed of oxides, such as silicon oxide or silicon oxynitride.

[0068] In some embodiments, combined with Figure 3a and Figure 3b As shown, the pseudo-stacked structure 220' provided above includes:

[0069] A stacked structure 220 is formed on a substrate 210; wherein the stacked structure 220 includes: an insulating layer 221 and a sacrificial layer 222 that are alternately stacked, and a support pillar 230 that penetrates the stacked structure 220.

[0070] A groove 240 is formed that penetrates the stacked structure 220;

[0071] The sacrificial layer 222 is removed to form a gap 241, wherein the gap 241 exposes the sidewall of the support column 230.

[0072] For example, an insulating layer 221 and a sacrificial layer 222 may be alternately deposited on a substrate 210 in a direction perpendicular to the plane of the substrate using a thin film deposition process. The thin film deposition process includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0073] For example, the stacked structure 220 can be etched downwards along a direction perpendicular to the substrate plane by an etching process to form a channel hole through the stacked structure. The bottom of the channel hole exposes the surface of the substrate 210. An epitaxial layer can be formed at the bottom of the channel hole by selective epitaxial growth to fill the channel hole with the epitaxial layer to form a support pillar 230.

[0074] For example, the stacked structure 220 can be etched downwards along a direction perpendicular to the substrate plane using an etching process to form a groove 240 between two adjacent support pillars 230. It will be understood that the sidewalls of the groove 240 expose the insulating layer 221 and the sacrificial layer 222.

[0075] Etching processes include: dry etching, wet etching, or a combination thereof.

[0076] By way of example, wet etching can be used to remove the sacrificial layer 222 through the groove 240, forming a gap 241 between two adjacent insulating layers 221. (Refer to...) Figure 3b As shown, the side wall of the support column is exposed at the end of the gap 241 that is relatively far away from the groove, and the end of the gap 241 that is relatively close to the groove is connected to the groove 240.

[0077] It is understood that the pseudo-stacked structure 220' refers to the structure after the sacrificial layer 222 in the stacked structure 220 is removed through the groove 240. Along the direction perpendicular to the substrate plane, adjacent insulating layers 221 are separated by a gap 241. In actual production, after wet etching to remove the sacrificial layer, a cleaning and drying process can be performed to remove residual wet etchant or etching solution, thus forming the pseudo-stacked structure 220'. In subsequent processes, the gaps 241 in the pseudo-stacked structure 220' can be filled with a conductive material (e.g., tungsten metal) to form a gate stacked structure. The gate stacked structure includes alternately stacked insulating layers 221 and conductive layers, and the conductive layers can be used as the control gate or word line of the memory.

[0078] In some embodiments, refer to Figure 3a As shown, the support column 230 includes a barrier layer 231, a storage layer 232, a tunneling layer 233, a channel layer 234, and an insulating column 235, which are stacked sequentially in the radial direction inward along the channel hole. The support column 230 is used to support the stacked structure and prevent it from collapsing during the removal of the sacrificial layer 222.

[0079] The barrier layer 231, tunneling layer 233, and insulating pillar 235 are composed of oxides, such as silicon oxide or silicon dioxide. The materials of any two of the barrier layer 231, tunneling layer 233, and insulating pillar 235 may be the same or different, and this disclosure does not impose any limitations.

[0080] The constituent materials of the storage layer 232 include nitrides, such as silicon nitride.

[0081] The channel layer 234 is composed of semiconductor materials, such as polysilicon or doped polysilicon.

[0082] Then, refer to Figure 3c As shown, step S120 is performed: dielectric material is conformally deposited along the groove 240 and the gap 241 to form a dielectric layer 250 covering the sidewalls of the groove, the surface of the gap and the bottom of the groove.

[0083] For example, refer to Figure 3c As shown, dielectric materials can be conformally deposited by physical vapor deposition, chemical vapor deposition and / or atomic layer deposition to form a first sub-dielectric layer 250a covering the sidewalls of the groove 240, a second sub-dielectric layer 250b covering the surface of the gap 241 and a third sub-dielectric layer 250c covering the bottom of the groove 240.

[0084] It should be noted that the first sub-dielectric layer 250a, the second sub-dielectric layer 250b, and the third sub-dielectric layer 250c all refer to dielectric layer 250. The different reference numerals are only used to distinguish the differences in the positions of the first sub-dielectric layer 250a, the second sub-dielectric layer 250b, and the third sub-dielectric layer 250c, and are not used to indicate a specific order.

[0085] In some embodiments, the constituent materials of the dielectric layer 250 include dielectric materials with a dielectric constant greater than 3.9.

[0086] In some embodiments, the dielectric layer 250 is composed of materials such as aluminum oxide, hafnium oxide, or titanium dioxide.

[0087] Next, step S130 is performed: the dielectric layer covering the sidewalls of the covered groove and the bottom of the covered groove is doped to form a first doped region.

[0088] For example, combined Figure 3c and Figure 3d As shown, by doping the first sub-dielectric layer 250a, a first sub-doped region 251 covering the sidewall of the groove can be formed. By doping the third sub-dielectric layer 250c, a second sub-doped region 252 covering the bottom of the groove can be formed. The first doped region includes the first sub-doped region 251 and the second sub-doped region 252.

[0089] In some embodiments, the first sub-dielectric layer 250a and the third sub-dielectric layer 250c may be doped simultaneously, or the first sub-dielectric layer 250a and the third sub-dielectric layer 250c may be doped sequentially. This disclosure does not impose any limitations.

[0090] In some embodiments, the above-described doping treatment of the dielectric layer covering the sidewalls of the trench and the bottom of the trench to form a first doped region includes:

[0091] Ion implantation is performed on the dielectric layer covering the sidewalls and bottom of the covered groove to introduce defects into the dielectric layer covering the sidewalls and bottom of the covered groove.

[0092] For example, refer to Figure 3d As shown, a sub-groove can be formed in the groove 240 based on the dielectric layer 250. The sidewalls of the sub-groove expose the first sub-dielectric layer 250a, and the bottom of the sub-groove exposes the third sub-dielectric layer 250c. Through the sub-groove, an ion implantation process is performed along a direction perpendicular to the substrate plane to implant dopant particles into the first sub-dielectric layer 250a and the third sub-dielectric layer 250c to form a first sub-doped region 251 and a second sub-doped region 252, i.e., to form the first doped region.

[0093] It should be noted that, since ion implantation is directional (i.e., perpendicular to the direction of the substrate plane), doped particles can be introduced into the first sub-dielectric layer 250a and the third sub-dielectric layer 250c to form defects, while having little effect on the second sub-dielectric layer 250b.

[0094] In some embodiments, the doping particles in the first doped region include boron (B), phosphorus (P), argon (Ar), germanium (Ge), indium (In), carbon (C), or nitrogen (N), etc.

[0095] In some embodiments, the defect concentration of the first doped region is controlled by controlling parameters of the ion implantation process, such as concentration, time, and implantation energy, thereby controlling the etching rate of the first doped region, i.e., controlling its etching selectivity.

[0096] Finally, step S140 is performed: the first doped region is removed using an etchant; wherein the chemical reaction between the etchant and the dielectric layer covering the gap surface is an inert reaction.

[0097] In some embodiments, the inert reaction includes: no chemical reaction occurs between the etchant and the dielectric layer covering the gap surface; or, the rate of chemical reaction between the etchant and the first doped region and the second doped region is much higher than the rate of chemical reaction between the etchant and the dielectric layer covering the gap surface, such that the chemical reaction between the etchant and the dielectric layer covering the gap surface can be ignored.

[0098] It is understandable that removing the first doped region with an etchant can increase the process window for subsequent deposition of other thin films through the trench. At the same time, compared with the first doped region, the etchant has a lower selectivity for etching the undoped dielectric layer (i.e., the third sub-dielectric layer 250c), which can preserve the third sub-dielectric layer 250c. The third sub-dielectric layer 250c covers the sidewalls of the support pillar and the surface of the insulating layer (including the upper and lower surfaces), which helps to reduce the possibility of leakage current in the semiconductor device.

[0099] In some embodiments, the etchant comprises a mixture of dilute sulfuric acid and hydrogen peroxide, or hydrofluoric acid.

[0100] In some embodiments, the ratio of the reaction rate between the etchant and the first doped region to the reaction rate between the etchant and the dielectric layer covering the surface of the gap 241 is greater than 25.

[0101] Figure 3f The difference in etching rates between the two etchants for undoped and doped dielectric layers is shown, with reference to... Figure 3f As shown, the etching rate of the undoped dielectric layer with etchant pair one is between 1.0 and 1.1, and the etching rate of the doped dielectric layer with etchant pair one is approximately 30.0. The etching rate of the undoped dielectric layer with etchant pair two is between 1.1 and 1.2, and the etching rate of the doped dielectric layer with etchant pair two is approximately 30.0. Preferably, etchant one can be a DSP solution (a mixture of dilute sulfuric acid and hydrogen peroxide), and etchant two can be an HF solution (hydrofluoric acid solution).

[0102] It is understandable that, compared to the doped dielectric layer, the etching rates of etchant one and etchant two for the undoped dielectric layer are both lower. Therefore, it can be ensured that the dielectric layer covering the gap surface is retained when the first doped region is removed.

[0103] It should be noted that etchant one and etchant two are merely examples used to convey this disclosure to those skilled in the art; however, this disclosure is not limited thereto. In the actual fabrication of semiconductor devices, those skilled in the art can rationally select appropriate doping particles and suitable etchants based on the composition of the dielectric layer.

[0104] In some embodiments, the surface of the substrate 210 includes: a first region and a second region; wherein the stacked structure 220 is located in the first region; the method further includes:

[0105] While conformally depositing dielectric material along groove 240 and gap 241, dielectric material covering the second region is formed;

[0106] When doping the dielectric layer covering the sidewalls and bottom of the covered groove 240, the dielectric material covering the second region is doped to form a second doped region in the second region.

[0107] When removing the first doped region using an etchant, the second doped region is removed using an etchant.

[0108] The first region includes the functional region. Here, the functional region refers to the area on the substrate surface used to support the stacked structure.

[0109] The second region includes: blank areas. Here, blank areas refer to regions on the substrate surface where no functional structures are provided, such as cut areas or edge areas of the substrate surface.

[0110] It is understandable that while the dielectric material is deposited in the first region, the dielectric material will also cover the second region. When doping a portion of the dielectric layer in the first region, the dielectric material covering the second region can be doped at the same time to form a second doped region covering the second region. When the first doped region is removed using an etchant, the second doped region can be removed at the same time.

[0111] Compared to related technologies that employ an additional dry etching process to remove the dielectric material covering the second region, this embodiment of the present disclosure can remove the second doped region simultaneously with the removal of the first doped region, which helps to save processes and reduce the manufacturing cost of semiconductor devices.

[0112] In some embodiments, the above method further includes:

[0113] After removing the first doped region using an etchant, a barrier layer and a gate layer covering the gap surface of the dielectric layer are formed sequentially.

[0114] For example, refer to Figure 3e As shown, barrier material and gate material can be deposited sequentially based on the groove window formed after removing the first doped region to form a barrier layer and a gate layer covering the dielectric layer 250b.

[0115] The barrier layer is composed of metal nitrides, such as tungsten nitride or titanium nitride.

[0116] The gate layer is composed of conductive materials, such as tungsten or polysilicon.

[0117] In this embodiment, forming the barrier layer and gate layer after removing the first doped region increases the process window for depositing the barrier and gate materials, reducing the process difficulty of depositing the barrier and gate materials. Furthermore, due to the increased process window, the thickness of the barrier and gate layers formed in the top and bottom gaps of the pseudo-stacked structure is more uniform.

[0118] In some embodiments, the above method is applied to the manufacture of a three-dimensional memory.

[0119] In some embodiments, the three-dimensional memory includes: 3D NAND memory.

[0120] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A pseudo-stacked structure is provided; wherein the pseudo-stacked structure includes: an insulating layer and a gap that are alternately stacked, and a groove that penetrates the pseudo-stacked structure, the groove communicating with the gap; A dielectric material is conformally deposited along the groove and the gap to form a dielectric layer covering the sidewalls of the groove, the surface of the gap, and the bottom of the groove; The dielectric layer covering the sidewalls of the groove and the bottom of the groove is doped to form a first doped region; The first doped region is removed using an etchant; wherein the chemical reaction between the etchant and the dielectric layer covering the gap surface is an inert reaction; The provision of the pseudo-stacked structure includes: forming a stacked structure on a substrate, wherein the substrate surface includes a first region and a second region, and the stacked structure is located in the first region; The method further includes: While conformally depositing the dielectric material along the groove and the gap, the dielectric material covering the second region is formed; When the dielectric layer covering the sidewalls of the groove and the bottom of the groove is doped, the dielectric material covering the second region is doped to form a second doped region in the second region; when the first doped region is removed using the etchant, the second doped region is removed using the etchant.

2. The method according to claim 1, characterized in that, The step of doping the dielectric layer covering the sidewalls of the groove and the bottom of the groove to form a first doped region includes: Ion implantation is performed on the dielectric layer covering the sidewalls of the groove and the bottom of the groove to introduce defects in the dielectric layer covering the sidewalls of the groove and the bottom of the groove.

3. The method according to claim 1, characterized in that, The ratio of the reaction rate between the etchant and the first doped region to the reaction rate between the etchant and the dielectric layer covering the gap surface is greater than 25.

4. The method according to claim 1, characterized in that, The dielectric layer is composed of dielectric materials with a dielectric constant greater than 3.9; The doped particles in the first doped region include: boron, phosphorus, argon, germanium, indium, carbon, or nitrogen; The etching agent comprises a mixture of dilute sulfuric acid and hydrogen peroxide, or hydrofluoric acid.

5. The method according to claim 4, characterized in that, The dielectric layer is composed of materials including aluminum oxide, hafnium oxide, or titanium dioxide.

6. The method according to claim 1, characterized in that, The stacked structure includes: alternatingly stacked insulating layers and sacrificial layers, and support pillars penetrating the stacked structure; providing the pseudo-stacked structure further includes: The groove is formed through the stacked structure; The sacrificial layer is removed to form the gap, wherein the gap exposes the sidewall of the support column.

7. The method according to claim 1, characterized in that, The method further includes: After removing the first doped region using the etchant, a barrier layer and a gate layer covering the dielectric layer of the gap surface are formed sequentially.

8. The method according to any one of claims 1 to 7, characterized in that, The method is applied to the manufacture of three-dimensional memory.

9. The method according to claim 8, characterized in that, The three-dimensional memory includes: 3D NAND memory.

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