Multiphase Switch Mode Power Supplies

Abstract

A multi-phase switch mode power supply includes first and second interleaved phase circuits coupled between input terminals and output terminals. The first phase circuit includes a first inductor coupled to a first switch, and the second phase circuit includes a second inductor coupled to a second switch. A control circuit is configured to output first and second PWM signals to the first and second switches. The on-time of the second PWM signal is equal to the on-time of the first PWM signal plus a fixed offset time period. The control circuit is configured to determine a period between rising edges of the first PWM signal to determine a disconnect trigger PWM signal, and when the second PWM signal has a logic high value, when a falling edge of the disconnect trigger PWM signal occurs, change the second PWM signal to a logic low value.

Description

Technical Field

[0001] The present disclosure relates to multi-phase switch mode power supplies, and more particularly to critical discontinuous multi-phase switch mode power supplies. Background Art

[0002] This section provides background information related to the present disclosure which is not necessarily prior art.

[0003] Many customers require power supplies with titanium-rated efficiency or higher, so the use of soft-switching power supply topologies has become increasingly popular, such as critical discontinuous mode in front-end power factor correction (PFC) circuits. To reduce the high peak currents that limit the maximum output power, interleaved multiphase operation is used.

[0004] Interleaved operation provides good ripple cancellation in the output voltage, but interleaving critical discontinuous mode circuits is difficult because the difference in switching frequency between phases inhibits synchronization due to the zero current detection function of the critical discontinuous mode of operation. Summary of the invention

[0005] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0006] According to one aspect of the present disclosure, a multi-phase switch mode power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for providing a direct current (DC) voltage output to a load, and a first phase circuit coupled between the pair of input terminals and the pair of output terminals. The first phase circuit includes a first inductor coupled to a first switch. The power supply also includes a second phase circuit interleaved with the first phase circuit between the pair of input terminals and the pair of output terminals. The second phase circuit includes a second inductor coupled to a second switch. The power supply also includes a control circuit configured to output a first PWM signal to the first switch and a second PWM signal to the second switch. The on-time of the second PWM signal is equal to the on-time of the first PWM signal plus a fixed offset time period. The control circuit is configured to: determine a period between at least two rising edges of the first PWM signal, determine a disconnection trigger PWM signal based on the determined period, and when the second PWM signal has a logic high value, when a falling edge of the disconnection trigger PWM signal occurs, change the second PWM signal to a logic low value.

[0007] According to another aspect of the present disclosure, a method for controlling a multi-phase power supply is disclosed. The power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for providing a direct current (DC) voltage output to a load, a first phase circuit coupled between the pair of input terminals and the pair of output terminals and including a first inductor coupled to a first switch, and a second phase circuit interleaved with the first phase circuit and including a second inductor coupled to a second switch between the pair of input terminals and the pair of output terminals. The method includes outputting a first PWM signal to the first switch and outputting a second PWM signal to the second switch. The on-time of the second PWM signal is equal to the on-time of the first PWM signal plus a fixed offset time period. The method also includes: determining a period between at least two rising edges of the first PWM signal; determining a disconnection trigger PWM signal based on the determined period; and when the second PWM signal has a logic high value, when a falling edge of the disconnection trigger PWM signal occurs, changing the second PWM signal to a logic low value.

[0008] Other aspects and areas of applicability will become apparent from the description provided herein. It should be understood that the various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended only for illustrative purposes and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0010] Figure 1 is a circuit diagram of a multi-phase switch-mode power supply according to an example embodiment of the present disclosure.

[0011] Figure 2 is used for Figure 1 A circuit diagram of an example of a power supply control circuit wiring.

[0012] Figure 3 is used for Figure 1 A block diagram of example control circuit components of a power supply.

[0013] Figure 4 The example shows Figure 1 Example PWM control signal and inductor current waveform of a power supply.

[0014] Figure 5 The example shows Figure 1 An example of a power disconnect trigger waveform of the PWM signal.

[0015] Figure 6 The example shows Figure 1 Example PWM control signal, inductor current and disconnect trigger PWM signal waveforms for multiple cycles of a power supply.

[0016] Figure 7 The example shows Figure 1 Example input and output voltage and current waveforms of a power supply.

[0017] Figure 8 The example shows that during one cycle Figure 1 Example input and output voltage and current waveforms of a power supply.

[0018] Fig. 9 Waveforms showing example PWM control signals and inductor current for a three-phase switch mode power supply according to another example embodiment of the present disclosure are illustrated.

[0019] Corresponding reference numerals indicate corresponding parts or features throughout the several views of the drawings. DETAILED DESCRIPTION

[0020] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0021] Example embodiments are provided so that the present disclosure will be thorough and will fully convey the scope to those skilled in the art. Many specific details, such as embodiments of specific parts, devices and methods, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, and that example embodiments may be embodied in many different forms and should not be construed as limiting the scope of the present disclosure. In some example embodiments, well-known processes, well-known device structures and well-known techniques are not described in detail.

[0022] The terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" may also be intended to include plural forms unless the context clearly indicates otherwise. The terms "comprises", "comprising", "including", and "having" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof. The method steps, processes, and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or illustrated, unless explicitly identified as an execution order. It should also be understood that additional steps or alternative steps may be adopted.

[0023] Although the term first, second, third etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or part from another region, layer or part. Terms such as "first", "second" and other numerical terms do not imply an order or sequence when used in this article, unless the context clearly indicates. Therefore, without departing from the teaching of the example embodiment, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0024] For ease of description, spatially relative terms such as "inside", "outside", "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of an element or feature to another element or feature as illustrated in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms may be intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the elements described as being "below" or "below" other elements or features will be oriented to be "above" the other elements or features. Therefore, the example term "below" may include both an orientation of "above" and an orientation of "below". The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein may be interpreted accordingly.

[0025] A multiphase switch mode power supply is exemplified in Figure 11 and is generally indicated by reference numeral 100. The system 100 includes a pair of input terminals 102 and 104 for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source V1, and a pair of input terminals 102 and 104 for supplying power to a load ( Figure 1 A pair of output terminals (not shown) of bulk+ and bulk- provide a direct current (DC) voltage output. Figure 1 An AC voltage input of 180V is illustrated, but other embodiments may receive a DC voltage input, an AC voltage input having a smaller or larger voltage, etc.

[0026] The power supply 100 includes a first phase circuit coupled between a pair of input terminals 102, 104 and a pair of output terminals BULK+, BULK-. The first phase circuit includes an inductor L1 coupled to a switch Q1.

[0027] The power supply 100 further includes a second phase circuit interleaved with the first phase circuit between a pair of input terminals 102, 104 and a pair of output terminals BULK+, BULK-. The second phase circuit includes an inductor L2 coupled to a switch Q2.

[0028] The control circuit 106 is configured to output a PWM signal DRV1 to the first switch Q1 and output a PWM signal DRV2 to the switch Q2. The on-time of the PWM signal DRV2 is equal to the on-time of the PWM signal DRV1 plus a fixed offset period.

[0029] As further explained below, the control circuit 106 is configured to determine a period between at least two rising edges of the PWM signal DRV1, determine a disconnect trigger PWM signal based on the determined period, and when the PWM signal DRV2 has a logic high value, change the PWM signal DRV2 to a logic low value when a falling edge of the disconnect trigger PWM signal occurs.

[0030] Figure 2 An example wiring diagram of a portion of the control circuit 106 is illustrated. Figure 2 As shown in , the digital controller 208 includes a zero current detection input ZCD1 coupled to the inductor L1 to detect a zero current crossing at the inductor L1 , and a zero current detection input ZCD2 coupled to the inductor L2 to detect a zero current crossing at the inductor L2 . Figure 1 A resistor R4 coupled between the inductor L1 and the digital controller 208 to generate the signal ZCD1 , and a resistor R3 coupled between the inductor L2 and the digital controller 208 to generate the signal ZCD1 are illustrated.

[0031] The digital controller 208 includes an AC line input AC_L and an AC neutral input AC_N. Figure 1 and Figure 2As shown in FIG. 1 , a voltage divider including resistors R12, R10, R9, and R11 is coupled between the AC line input AC_L of the digital controller 208 and the line terminal 102 of the AC voltage input V1. A voltage divider including resistors R16, R15, R13, and R14 is coupled between the AC neutral input AC_N of the digital controller 208 and the neutral terminal 104 of the AC voltage input V1. A diode D6 is coupled between the AC neutral input ACN of the digital controller 208 and circuit ground, and a diode D7 is coupled between the AC line input AC_L of the digital controller 208 and circuit ground.

[0032] The current sense input CS of the digital controller is coupled to receive a signal from amplifier X1, which amplifies the sensed differential currents Csense+ and Csense- to determine the current through Figure 1 The current of the current sense resistor Rsense shown in .

[0033] The controller 208 includes a feedback input FB for receiving the voltage output of the power supply 100. Figure 2 As shown in , a voltage divider including resistors R5, R6, R7 and R8 is coupled between the output terminal BODY+ and the feedback input FB. Figure 1 and Figure 2 The example resistor values ​​illustrated in are for illustration purposes only, and other embodiments may use other suitable resistor values, may have more or fewer resistors, may have resistors coupled in other circuit arrangements, etc.

[0034] Digital controller 208 also includes a control signal output DRVA for providing a PWM signal DRV1 to switch Q1, a control signal output DRVB for providing a PWM signal DRV2 to switch Q2, and a ground input coupled to circuit ground. Figure 2 One specific connection interface between the digital controller 208 and other elements of the power supply 100 is illustrated, but other embodiments may use different connection arrangements when implementing the example control methods described herein.

[0035] Figure 3 A block diagram showing example components of control circuit 106 is illustrated. Figure 3 As shown in FIG. 1 , control circuit 106 includes a pulse width modulation (PWM) generator circuit 310 for generating a PWM signal PWMA, and a PWM generator circuit 312 for generating a PWM signal PWMB. Signal PWMA may define a signal DRV1 provided to switch Q1, and signal PWMB may define a signal provided to switch Q2.

[0036] The control circuit 106 includes a fixed offset circuit 314 coupled to an input of the PWM generator circuit 310 to add a fixed offset time period to the on-time of the signal PWMB. For example, the control circuit 106 includes a voltage error amplifier 316 coupled to compare the DC voltage output (bulk voltage) with a voltage reference (bulk voltage reference). The fixed offset circuit 314 is coupled to receive (via a multiplier circuit 318) a combined signal of an equivalent root mean square (RMS) voltage derived from the output of the voltage error amplifier 316 and the AC voltage input. The fixed offset time period can be a constant value that only requires a one-time time fine-tuning depending on the speed of the phase adjustment. In some embodiments, the fixed offset circuit 314 can include a hardware delay that replicates the functionality of adding the additional on-time via software.

[0037] like Figure 3 As shown in , the frequency capture circuit 320 is coupled to determine the period between at least two rising edges of the signal PWMA. The frequency capture circuit 320 may include a digital timer or an analog voltage ramp for measuring the instantaneous voltage of the signal PWMA. In some embodiments, the frequency capture circuit 320 may determine the period between at least two rising edges of the signal PWMA by measuring an average value of multiple periods of the signal PWMA, by predicting the next period of the signal PWMA based on the voltage input, the voltage output, and the latest duty cycle of the signal PWMA, etc.

[0038] The control circuit 106 also includes a disconnection trigger generator circuit 322 coupled between the frequency capture circuit 320 and the PWM generator circuit 312. The disconnection trigger generator circuit 322 can be configured to generate a disconnection trigger PWM signal having a 180-degree phase shift with the signal PWMA by using half of a determined period between at least two rising edges of the signal PWMA, half of a measured average value of multiple periods of the signal PWMA, half of a predicted next period of the signal PWMA, etc. In some embodiments, the on-time of the disconnection trigger PWM signal can be equal to the on-time of the signal PWMA.

[0039] like Figure 3 As shown in FIG, the control circuit 106 includes a zero current detector (ZCD) circuit 324 coupled to the PWM generator circuit 310 for detecting a zero current crossing at the inductor L1. The ZCD circuit 326 is coupled to the PWM generator circuit 312 to detect a zero current crossing at the inductor L2. Figure 3A specific arrangement of components outside of the prominent portion of the control circuit 106 (e.g., the fixed offset circuit 314, the frequency capture circuit 320, and the disconnect trigger generator circuit 322) for performing the example control method described herein is illustrated, but in other embodiments, the components may be arranged differently when the prominent portion of the control circuit 106 performs the example control method described herein.

[0040] The example control methods described herein (e.g., as performed by the control circuit 106, etc.) can use zero current detection for each inductor L1 and L2 (e.g., each PFC choke) to allow the inductor to reset itself. Each inductor L1 and L2 will reset at a different time depending on the inductance, gate drive delay, instantaneous input voltage, and instantaneous output voltage. Due to the different reset timing, the switching frequency of each phase may be different.

[0041] Some prior art control methods that detect only one phase and force the second phase to be out of phase at a certain phase angle based on the number of phases (e.g., for two-phase operation, the second phase is forced to be 180 degrees out of phase) may not allow the second phase to achieve valley switching or complete reset, especially when the inductance is large (e.g., the power supply operates primarily at low frequencies). Some prior art control methods that use ZCD detection for each inductor measure the frequencies of the two phases to keep them equal by adjusting the on-time of one or both phases, and the control method sets the phase shift of the other phase. In contrast, the example control method described herein can measure only the switching period of the main phase and provide a fixed turn-off point for the second phase (e.g., based on the on-time and period of the main phase).

[0042] In addition, the example control method described herein can add a fixed additional on-time to the other phases to allow the current reset point to move to the right by operating at a lower frequency. The second phase is allowed to slowly move to the correct phase angle on its own until the turn-off trigger point is reached to fix the second phase in place. In order to fix the second phase in place, the on-time is cut due to the turn-off trigger (e.g., from the disconnect trigger generator circuit 322, etc.), which reduces the switching cycle until the two frequencies are the same (e.g., the switching frequency of each switch Q1 and Q2 is equal). In view of the above, phase control may not require any complex calculations, such as implementing error calculations, etc. Each phase of the power supply 100 can adjust its phase by itself.

[0043] Some prior art control methods use the rising or falling edge of the PWM signal, averaged over multiple cycles, and comparing the average to a fixed reference to control the phase angle shift. This places higher processing requirements on the controller, especially for multi-phase operation where complex calculations are performed to provide phase control for each individual phase. In contrast, the example control method described herein may not require any complex calculations for multi-phase operation. As described above, a fixed turn-off trigger (e.g., based on the period of the main phase) is generated and applied to each individual phase. Therefore, each phase of the power supply can adjust its timing by itself, which reduces the hardware requirements for the controller.

[0044] Reference again Figure 1 , the power supply 100 optionally includes a power factor correction (PFC) circuit coupled between a pair of input terminals 102, 104 and the first and second phase circuits. The PFC circuit includes an electromagnetic interference (EMI) filter circuit 105. The EMI filter circuit 105 may include two inductors L3 and L4, two capacitors C3 and C4, more or fewer inductors, more or fewer capacitors, etc. The PFC circuit also includes a bridge circuit D1 including four diodes.

[0045] although Figure 1 The power supply 100 is illustrated as including an AC voltage input and a PFC circuit having an EMI filter circuit 105 and a bridge circuit D1 for AC-DC power conversion, but other embodiments may include other suitable PFC circuits, other embodiments may be a DC-DC converter receiving a DC voltage input, etc. For example, the power supply 100 may use any suitable AC-DC or DC-DC converter topology, such as a buck converter topology, a boost converter topology, or a forward converter topology, etc. The power supply 100 may use variable frequency operation, interleaved operation, etc.

[0046] In some embodiments, the power supply 100 may include more than two interleaved phase circuits (e.g., three phases, four phases, etc.). Each phase circuit may include its own inductor and switch, and the control circuit 106 may generate a PWM signal for each switch, as well as a separate disconnect trigger PWM signal for each switch except the switch of the first phase circuit.

[0047] like Figure 1As shown in , the power supply 100 may include an output capacitor C2 coupled between a pair of output terminals BODY+ and BODY-, a diode D3 coupled between an inductor L1 and the output terminal BODY+, a diode D2 coupled between an inductor L2 and the output terminal BODY+, and a capacitor C1 coupled with the inductors L1 and L2. In other embodiments, the power supply 100 may include more or fewer capacitors and diodes, capacitors and diodes coupled in other arrangements, etc. The terminals 102, 104, BODY+ and BODY- may include any suitable electrical terminals, wires, circuit traces, etc. for receiving a voltage input from a voltage source or providing a voltage output to a load.

[0048] The control circuit 106 may be configured to control the switching operation of the switches Q1 and Q2 to operate the power supply 100 in any suitable operating mode, such as a quasi-resonant operating mode, a critical discontinuous operating mode, or the like.

[0049] The control circuit 106 and the digital controller 208 may include any suitable microprocessor, microcontroller, integrated circuit, digital signal processor, etc., which may include memory. The control circuit 106 and the digital controller 208 may be configured to perform (e.g., be operable to perform, etc.) any of the example processes described herein using any suitable hardware and / or software implementation. For example, as described above, the control circuit 106 and the digital controller 208 may execute computer-executable instructions stored in a memory, which may include one or more logic gates, control circuits, etc.

[0050] Figure 4 An example waveform 400 showing control signals PWMA and PWMB and inductor current A and inductor current B during multiple switching cycles of power supply 100 is illustrated. For example, control signal PWMA may be provided to Figure 1 The switch Q1, and the control signal PWMB can be provided to Figure 1 The inductor current A may represent the current through the inductor L1, and the inductor current B may represent the current through the inductor L2.

[0051] like Figure 4 As shown in FIG, control signal PWMA has an on-time Ton, and control signal PWMB has an on-time equal to Ton plus a fixed offset for the additional on-time. At time T0, both control signals PWMA and PWMB jump to a logic high value, and inductor currents A and B rise. Because control signal PWMB has a longer on-time than control signal PWMA due to the fixed offset, inductor current B rises to a higher value than inductor current A before control signal PWMB transitions to a logic low value. Although Figure 4While the example of adding the additional on-time to the control signal PWMB is described, in other embodiments, the control method may be implemented by reducing the on-time of the control signal PWMA.

[0052] At time T1, the inductor current A reaches zero value, and the control signal PWMA jumps to a logic high value again (eg, due to the ZCD1 signal triggering Figure 3 The inductor current B is not yet zero at time T1, so the control signal PWMB does not jump to a logic high value until time T2 (e.g., based on the ZCD2 signal triggering the PWM generator 312 when the inductor current B reaches zero at time T2, etc.).

[0053] The process continues again at time T3, at which the control signal PWMA jumps to a logic high value due to the zero current state of the inductor current A, while the control signal PWMB does not jump to a logic high value until time T4 when the inductor current B reaches the zero current state. Figure 4 As shown in , due to the offset value added to the on-time of the control signal PWMB, the delay between time T3 and T4 is greater than the delay between time T2 and T1.

[0054] At times T5 and T6, the delay between the rising edges of control signals PWMA and PWMB increases further. Again, the offset value added to control signal PWMB continues to cause inductor current B to rise above inductor current A, and thus each cycle increasingly prolongs the time that inductor current B reaches relative to inductor current A.

[0055] Figure 5 An example waveform 500 is illustrated showing how to determine the disconnect trigger PWM signal based on the control signal PWMA and the inductor current A. Figure 5 As shown in , first determine the period between the rising edges of the control signal PWMA. For example, period 3 identifies the period between the rising edges of the pulse Ton3 at time T0 and the pulse Ton2 at time T2, period 2 identifies the period between the rising edges of the pulse Ton2 at time T2 and the pulse Ton1 at time T4, and period 1 identifies the period between the rising edges of the pulse Ton1 at time T4 and the pulse Ton0 at time T6.

[0056] like Figure 5 As shown in , each pulse of the off-trigger PWM signal starts at a 180 degree opposite phase of the pulse of the control signal PWMA. For example, each pulse of the off-trigger PWM signal may start midway through a determined cycle between pulses of the control signal PWMA.

[0057] Figure 5The rising edge of the pulse Ton3 of the disconnect trigger PWM signal is illustrated starting at time T1, which is the midpoint of the determined time period cycle 3 between the pulses of the control signal PWMA. Similarly, the rising edge of the pulse Ton2 of the disconnect trigger PWM signal occurs at T3, which is a delay of time T2 plus the previous time period cycle 3 divided by 2. The rising edge of the pulse Ton1 of the disconnect trigger PWM signal occurs at T5, which is a delay of time T4 plus the previous time period cycle 2 divided by 2. The rising edge of the pulse Ton0 of the disconnect trigger PWM signal occurs at T7, which is a delay of time T6 plus the previous time period cycle 1 divided by 2.

[0058] The on-time of each pulse of the off-trigger PWM signal may be equal to the on-time of each pulse of the control signal PWMA. Figure 5 Also illustrated is the falling edge of the pulse that turns off the trigger PWM signal, which can be used to turn off the control signal PWMB early as described further below.

[0059] Figure 6 An example waveform 600 showing the interaction of the off-trigger PWM signal with the control signals PWMA and PWMB and the inductor currents A and B is illustrated. Figure 6 As shown in FIG. 1 , at time T0 , pulses of both control signals PWMA and PWMB start simultaneously.

[0060] At time T1, the falling edge of the disconnect trigger PWM signal occurs. Because the control signal PWMB is at a logic low value at time T1, the control signal PWMB is not affected. At time T2, in response to the zero current state of the inductor current A, the control signal PWMA jumps to a logic high value, while the control signal PWMB does not jump to a logic high value until time T3 (e.g., because due to the offset added to the on-time of the control signal PWMB, the inductor current B does not reach the zero current state until time T3, etc.).

[0061] At time T4, the falling edge of the disconnect trigger PWM signal occurs again. Because the control signal PWMB is at a logic low value at time T4, the control signal PWMB is not affected. At time T5, in response to the zero current state of the inductor current A, the control signal PWMA jumps to a logic high value, while the control signal PWMB does not jump to a logic high value until time T6 (e.g., because the inductor current B does not reach the zero current state until time T6 due to the offset added to the on-time of the control signal PWMB, etc.).

[0062] The falling edge of the disconnect trigger PWM signal occurs at time T7, while the control signal PWMB is at a logic high level. This causes the control signal PWMB to transition to a logic low level early at the same time T7 as the falling edge of the disconnect trigger PWM signal, rather than the control signal PWMB remaining at a logic high value until its normal period TonB (e.g., TonA plus an offset) ends.

[0063] The shortened on-time of the control signal PWMB at time T7 reduces the ramp-up of the inductor current B, which results in a steady-state state in which the inductor currents A and B are equal and opposite in phase. For example, at time T8, the control signal PWMA jumps to a logic high value, and at time T9, both the disconnection trigger PWM signal and the control signal PWMB jump to a logic high value. The falling edge of the disconnection trigger PWM signal at time T10 again cuts off the control signal PWMB to maintain the steady-state operation of the inductor currents A and B.

[0064] In view of the above, the offset value and the disconnection trigger PWM signal allow the power supply 100 to start with the control signals PWMA and PWMB starting at the same time, while the control signal PWMB is continuously adjusted during the subsequent cycle according to the disconnection trigger PWM signal to achieve and maintain a steady-state operation with the inductor currents A and B balanced and in opposite phases to each other. Similarly, if the timing or the inductor currents A and B are disturbed during the operation of the power supply 100, the control signal PWMB can be adjusted during the subsequent cycle according to the disconnection trigger PWM signal again to achieve and maintain a steady-state operation with the inductor currents A and B balanced and in opposite phases to each other again.

[0065] In some embodiments, the inductance of inductor L1 can be lower (or higher) than the inductance of inductor L2. For DC input, the switching frequency of switches Q1 and Q2 may be the same. However, when fast PFC average mode control is used with inductor L1 having a lower inductance, the switching frequency may be different, with the second phase operating at a lower frequency. This may result in Figure 6 , and adds a disconnect trigger signal to provide phase control for different phases.

[0066] As another option, the switching frequency may again be different when peak current mode control is used where inductor L1 has a lower inductance than inductor L2, with the second phase operating at a lower frequency. Peak current control may compare the sensed inductor current to the output of the compensator for PFC operation. This may result in Figure 6 , and adds a disconnect trigger signal to provide phase control for different phases.

[0067] Figure 7Example waveforms 700 showing current and voltage of different components of power supply 100 during four different load conditions are illustrated. Specifically, Figure 7 An AC voltage input VinAC, an input current Iac, a current Ichoke1 through an inductor L1, a current Ichoke2 through an inductor L2, a voltage output Vbulk, and an output current Iout are illustrated.

[0068] A first load condition is illustrated from 0 milliseconds to 200 milliseconds, at an output current of approximately 2 amps. A second load condition is illustrated from 200 milliseconds to 400 milliseconds, at an output current of approximately 4 amps, a third load condition is illustrated from 400 milliseconds to 600 milliseconds, at an output current of approximately 5.5 amps, and a fourth load condition is illustrated from 600 milliseconds to 800 milliseconds, at an output current of approximately 7.5 amps.

[0069] Figure 8 An example waveform 800 showing the current and voltage of different components of the power supply 100 based on a 100% load condition for a half cycle of the AC voltage input is illustrated. Figure 8 As shown in , ripple cancellation is most effective when the current through inductor L1 is 180 degrees out of phase with respect to the current through inductor L2. Figure 7 and Figure 8 The effectiveness of using the phase control technique described herein for different step load conditions is also illustrated. Fig. 9 Example waveforms 900 showing PWM control signals and inductor currents for a three-phase power supply are illustrated. For example, control signal PWMA is provided to switches of a first phase circuit of the power supply, where current A corresponds to a current through an inductor of the first phase circuit.

[0070] The control signal PWMB is provided to the switch of the second phase circuit of the power supply, wherein the current B corresponds to the current through the inductor of the second phase circuit. The control signal PWMC is provided to the switch of the third phase circuit of the power supply, wherein the current C corresponds to the current through the inductor of the third phase circuit.

[0071] like Fig. 9 As shown in , the control signal DummyPWM has a frequency equal to twice the frequency of the previous cycle of the control signal PWMA. The control signal DummyPWM has a duty cycle of 10%. Each of the control signals PWMB and PWMC has an on-time equal to the on-time of the control signal PWMA plus a fixed offset.

[0072] The disconnect trigger of each phase PWMB and PWMC will have different movement. For example, Fig. 9The pseudocode illustrated in describes the disconnection trigger of signal PWMB as adding 33% of the previous cycle of control signal PWMA to the start of a pulse of control signal PWMA, and describes the disconnection trigger of signal PWMC as adding 66% of the previous cycle of control signal PWMA to the start of a pulse of control signal PWMA.

[0073] like Fig. 9 As shown in , the three-phase inductor currents A, B, and C reach a steady-state equilibrium after a plurality of cycles. The control signals PWMB and PWMC start with a phase difference of 90 degrees relative to the control signal PWMA at time T0, although in other embodiments, the control signals may all start at the same time, may start with different phase offsets, etc.

[0074] In another example embodiment, a method of controlling a multi-phase power supply is disclosed. The power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for providing a direct current (DC) voltage output to a load, a first phase circuit coupled between the pair of input terminals and the pair of output terminals and including a first inductor coupled to a first switch, and a second phase circuit interleaved with the first phase circuit between the pair of input terminals and the pair of output terminals and including a second inductor coupled to a second switch.

[0075] The method includes outputting a first PWM signal to a first switch and outputting a second PWM signal to a second switch. The on-time of the second PWM signal is equal to the on-time of the first PWM signal plus a fixed offset time period. The method also includes: determining a period between at least two rising edges of the first PWM signal; determining a disconnection trigger PWM signal according to the determined period; and when the second PWM signal has a logic high value, when a falling edge of the disconnection trigger PWM signal occurs, changing the second PWM signal to a logic low value.

[0076] Determining the period between at least two rising edges of the first PWM signal may include measuring the period using a digital timer or an analog voltage ramp for measuring an instantaneous voltage of the first PWM signal. Generating a disconnect trigger PWM signal may include generating a disconnect trigger PWM signal having a 180 degree phase shift with the first PWM signal by using half of the determined period between the two rising edges of the first PWM signal.

[0077] In some embodiments, determining the period between at least two rising edges of the first PWM signal may include measuring an average of a plurality of periods of the first PWM signal, or by predicting a next period of the first PWM signal based on the voltage input, the voltage output, and a latest duty cycle of the first PWM signal. Generating the disconnect trigger PWM signal may include generating a disconnect trigger PWM signal having a 180 degree phase shift with the first PWM signal by using half of the measured average of a plurality of periods of the first PWM signal or half of the predicted next period of the first PWM signal. The on-time of the disconnect trigger PWM signal is equal to the on-time of the first PWM signal.

[0078] The method may include simultaneously starting the first PWM signal and the second PWM signal during startup of the power supply, and continuously changing the second PWM signal until the switching period of the first PWM signal is equal to the switching period of the second PWM signal. The method may include, in response to the switching periods of the first PWM signal and the second PWM signal being disturbed and becoming unequal, continuously changing the second PWM signal until the switching period of the first PWM signal is again equal to the switching period of the second PWM signal.

[0079] The example embodiments described herein may provide one or more of the following advantages (or none of the following advantages): simplicity of control circuit design and phase control method, lower processing requirements for phase control when implemented using more than two phases (e.g., four-phase converters, etc.), use of cheaper controllers, ease of implementation since compensation for phase control is not required (especially for applications with more than two phases). For example, in a four-phase converter, each phase may require independent compensation that may affect the stability of the entire converter.

[0080] The foregoing description of the embodiments has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure. The individual elements or features of a specific embodiment are generally not limited to that specific embodiment, but are interchangeable where applicable and can be used in a selected embodiment, even if not specifically shown or described. It can also be varied in a variety of ways. Such variations should not be considered as departing from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. A multi-phase switch mode power supply, the power supply comprising: a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source; a pair of output terminals, the pair of output terminals being used to provide a direct current (DC) voltage output to a load; a first phase circuit coupled between the pair of input terminals and the pair of output terminals, the first phase circuit comprising a first inductor coupled to a first switch; a second phase circuit interleaved with the first phase circuit, between the pair of input terminals and the pair of output terminals, the second phase circuit comprising a second inductor coupled to a second switch; as well as A control circuit, the control circuit being configured to: outputting a first PWM signal to the first switch; outputting a second PWM signal to the second switch, wherein an on-time of the second PWM signal is equal to an on-time of the first PWM signal plus a fixed offset time period; determining a period between at least two rising edges of the first PWM signal; Determine disconnection trigger PWM signal according to the determined period; as well as When the second PWM signal has a logic high value, the second PWM signal is changed to a logic low value when a falling edge of the disconnection triggering PWM signal occurs.

2. The power supply of claim 1, wherein: The control circuit includes a first PWM generator circuit to generate the first PWM signal; The control circuit includes a second PWM generator circuit to generate the second PWM signal; and The control circuit includes a fixed offset circuit coupled to an input of the second PWM generator circuit to add the fixed offset period to the on-time of the second PWM signal.

3. The power supply according to claim 2, wherein: The control circuit includes a voltage error amplifier coupled to compare the DC voltage output with a voltage reference, and the voltage input received from the input power source is an AC voltage input, and the fixed offset circuit is coupled to receive a combined signal derived from an equivalent root mean square (RMS) voltage of the output of the voltage error amplifier and the AC voltage input.

4. The power supply according to claim 2, wherein: The control circuit includes a frequency capture circuit to determine the period between the at least two rising edges of the first PWM signal, and the frequency capture circuit includes a digital timer or an analog voltage ramp for measuring an instantaneous voltage of the first PWM signal.

5. The power supply according to claim 4, wherein: The control circuit includes a disconnection trigger generator circuit coupled between the frequency capture circuit and the second PWM generator circuit, and the disconnection trigger generator circuit is configured to generate the disconnection trigger PWM signal having a 180 degree phase shift from the first PWM signal by using half of the determined period between the at least two rising edges of the first PWM signal.

6. The power supply of claim 4, wherein: The frequency capture circuit is configured to determine the period between the at least two rising edges of the first PWM signal by measuring an average value of a plurality of periods of the first PWM signal or by predicting a next period of the first PWM signal based on the voltage input, the voltage output and a latest duty cycle of the first PWM signal; The control circuit includes a disconnect trigger generator circuit coupled between the frequency capture circuit and the second PWM generator circuit; and The turn-off trigger generator circuit is configured to generate the turn-off trigger PWM signal having a 180 degree phase shift from the first PWM signal by using half of a measured average value of the plurality of cycles of the first PWM signal or half of a predicted next cycle of the first PWM signal.

7. The power supply according to claim 1, wherein: The on-time of the disconnection triggering PWM signal is equal to the on-time of the first PWM signal.

8. The power supply according to claim 2, wherein: The control circuit includes a first zero current detector (ZCD) circuit coupled between the first inductor and the first PWM generator circuit to detect a zero current crossing at the first inductor, and a second ZCD circuit coupled between the second inductor and the second PWM generator circuit to detect a zero current crossing at the second inductor.

9. The power supply of claim 1 further comprising a third phase circuit interleaved with the first phase circuit and the second phase circuit between the pair of input terminals and the pair of output terminals, the third phase circuit comprising a third inductor coupled to a third switch.

10. The power supply of claim 1, further comprising a power factor correction (PFC) circuit coupled between the pair of input terminals and the first phase circuit and the second phase circuit, the PFC circuit comprising: An electromagnetic interference (EMI) filtering circuit includes at least two capacitors and at least two inductors, and a bridge circuit includes at least four diodes.

11. The power supply of claim 1 , further comprising an output capacitor coupled between the pair of output terminals, a first diode coupled between the first phase circuit and a first output terminal of the pair of output terminals, and a second diode coupled between the second phase circuit and the first output terminal of the pair of output terminals.

12. A method of controlling a multi-phase power supply, the power supply comprising a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for providing a direct current (DC) voltage output to a load, a first phase circuit coupled between the pair of input terminals and the pair of output terminals and comprising a first inductor coupled to a first switch, and a second phase circuit interleaved with the first phase circuit between the pair of input terminals and the pair of output terminals and comprising a second inductor coupled to a second switch, the method comprising: outputting a first PWM signal to the first switch; outputting a second PWM signal to the second switch, wherein an on-time of the second PWM signal is equal to an on-time of the first PWM signal plus a fixed offset time period; determining a period between at least two rising edges of the first PWM signal; Determine disconnection trigger PWM signal according to the determined period; as well as When the second PWM signal has a logic high value, the second PWM signal is changed to a logic low value when a falling edge of the disconnection triggering PWM signal occurs.

13. The method according to claim 12, wherein: Determining the period between the at least two rising edges of the first PWM signal includes measuring the period using a digital timer or an analog voltage ramp for measuring an instantaneous voltage of the first PWM signal.

14. The method according to claim 13, wherein: Generating the turn-off triggering PWM signal includes generating the turn-off triggering PWM signal having a 180-degree phase shift from the first PWM signal by using a half of the determined period between the two rising edges of the first PWM signal.

15. The method of claim 13, wherein: Determining the period between the at least two rising edges of the first PWM signal comprises: measuring an average of a plurality of periods of the first PWM signal, or by predicting a next period of the first PWM signal based on the voltage input, the voltage output, and a latest duty cycle of the first PWM signal; and Generating the turn-off trigger PWM signal includes generating the turn-off trigger PWM signal having a 180 degree phase shift from the first PWM signal by using half of a measured average value of the plurality of cycles of the first PWM signal or half of a predicted next cycle of the first PWM signal.

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