Transmitter and receiver, and storage system including the same

Abstract

A transmitter and a receiver, as well as a storage system including the transmitter and the receiver, are provided. The transmitter includes a multiplexer, control logic, and a voltage-mode driver. The multiplexer generates multiple time-interleaved data signals based on multiple input data signals and a multi-phase clock signal. The multiple input data signals are input in parallel. Each of the multiple input data signals is a binary signal and has two different voltage levels. The control logic generates at least one pull-down control signal and multiple pull-up control signals based on the multiple time-interleaved data signals. The voltage level of each of the multiple pull-up control signals is temporarily boosted. The voltage-mode driver generates an output data signal based on the at least one pull-down control signal and the multiple pull-up control signals. The output data signal is a duobinary signal and has three different voltage levels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0107701 filed on August 26, 2020, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to semiconductor integrated circuits, and more particularly to a transmitter and a receiver for low-power input / output, and a memory system including the transmitter and the receiver. Background Art

[0004] Storage-intensive applications can leverage storage bandwidth for high-performance computing (HPC), such as artificial intelligence (AI) and / or graphics processing units (GPUs). Bandwidth expansion can be driven by innovations in process technology. Advances in process technology have already created higher density in integrated circuits (ICs). Three-dimensional (3D) integration offers the potential to further expand IC density.

[0005] Research has been conducted on high-bandwidth memory (HBM) using through-silicon vias (TSVs). If multiple TSVs are used as channels, signal transitions on one channel may propagate or shift to adjacent channels as noise due to parasitic capacitance formed by the material properties of the TSVs. This noise may delay data or increase jitter, potentially degrading receiver performance. Summary of the Invention

[0006] At least one embodiment of the present disclosure provides a transmitter that generates a duobinary data signal using a time interleaving scheme for low power input / output.

[0007] At least one embodiment of the present disclosure provides a receiver for receiving a duobinary data signal.

[0008] At least one embodiment of the present disclosure provides a storage system including a transmitter and a receiver.

[0009] According to an embodiment, a transmitter includes: a multiplexer configured to generate a plurality of time-interleaved data signals based on a plurality of input data signals and a multi-phase clock signal, the plurality of input data signals being input in parallel, each of the plurality of input data signals having at least two voltage levels different from one another; control logic configured to generate a plurality of control signals based on the plurality of time-interleaved data signals, at least one of the plurality of control signals having a temporarily boosted voltage level; and a voltage-mode driver configured to generate an output data signal based on the plurality of control signals, the output data signal having at least three voltage levels different from one another.

[0010] According to an embodiment, a transmitter includes a multiplexer, control logic, and a voltage-mode driver. The multiplexer generates multiple time-interleaved data signals based on multiple input data signals and a multi-phase clock signal. The multiple input data signals are input in parallel. Each of the multiple input data signals is a binary signal and has two different voltage levels. The control logic generates at least one pull-down control signal and multiple pull-up control signals based on the multiple time-interleaved data signals. The voltage level of each of the multiple pull-up control signals is temporarily boosted. The voltage-mode driver generates an output data signal based on the at least one pull-down control signal and the multiple pull-up control signals. The output data signal is a duobinary signal and has three different voltage levels.

[0011] According to an embodiment, a receiver includes: a first trigger, the first trigger being configured to receive an input data signal having at least three voltage levels different from each other, a first clock signal, a first reference voltage and a first selection signal, forming a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal, generating a first output data signal based on the input data signal, the first clock signal, the first reference voltage and the first selection signal, and providing the first output data signal as a second selection signal, the first output data signal being a signal having at least two voltage levels different from each other; and a second trigger, the second trigger being configured to receive the input data signal, a second clock signal different from the first clock signal, the first reference voltage and the second selection signal, generating a second output data signal based on the input data signal, the second clock signal, the first reference voltage and the second selection signal, and providing the second output data signal as the first selection signal, the second output data signal being a signal having at least two voltage levels different from each other.

[0012] According to an embodiment, a receiver includes a first flip-flop and a second flip-flop. The first flip-flop receives an input data signal and generates a first output data signal based on the input data signal, a first clock signal, a first reference voltage, and a first select signal. The input data signal is a duobinary signal having three different voltage levels. The first output data signal is a binary signal having two different voltage levels. The second flip-flop receives the input data signal and generates a second output data signal based on the input data signal, a second clock signal, the first reference voltage, and a second select signal. The second output data signal is a binary signal having two different voltage levels. The second clock signal is different from the first clock signal. The second output data signal is provided as the first select signal, and the first output data signal is provided as the second select signal. A second reference voltage different from the first reference voltage is formed in the first flip-flop based on the first reference voltage and the first select signal.

[0013] According to an embodiment, a storage system includes: a transmitter configured to output write data to be stored in a storage device or read data to be retrieved from the storage device; a channel configured to transmit the write data or the read data; and a receiver configured to receive the write data or the read data, wherein the transmitter includes: a multiplexer configured to generate a plurality of time-interleaved data signals based on a plurality of input data signals and a multi-phase clock signal, the plurality of input data signals being input in parallel, each of the plurality of input data signals having at least two voltage levels different from each other; control logic configured to generate a plurality of control signals based on the plurality of time-interleaved data signals, at least one of the plurality of control signals having a temporarily boosted voltage level; and a voltage-mode driver configured to generate an output data signal based on the plurality of control signals, the output data signal having at least three voltage levels different from each other, wherein the receiver includes: a first flip-flop configured to receive the output data signal, a first clock signal, a first reference voltage and a first selection signal, forming a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal, generating a first data signal based on the output data signal, the first clock signal, the first reference voltage and the first selection signal, and providing the first data signal as the second selection signal, the first data signal being at least one input data signal among the multiple input data signals having at least two voltage levels different from each other; and a second trigger, the second trigger being configured to receive the output data signal, the second clock signal, the first reference voltage and the second selection signal, generating a second data signal based on the output data signal, the second clock signal, the first reference voltage and the second selection signal, and providing the second data signal as the first selection signal, the second data signal being at least one input data signal among the multiple input data signals having at least two voltage levels different from each other, the second clock signal being different from the first clock signal, wherein the multiple input data signals, the output data signal, and the first data signal and the second data signal correspond to the write data or the read data.

[0014] According to an embodiment, a storage system includes a transmitter, a channel, and a receiver. The transmitter outputs write data to be stored in a storage device or read data to be retrieved from the storage device. The channel transmits the write data or the read data. The receiver receives the write data or the read data. The transmitter includes a multiplexer, control logic, and a voltage-mode driver. The multiplexer generates multiple time-interleaved data signals based on multiple input data signals and a multi-phase clock signal. The multiple input data signals are input in parallel. Each of the multiple input data signals is a binary signal and has two different voltage levels. The control logic generates at least one pull-down control signal and multiple pull-up control signals based on the multiple time-interleaved data signals. Each of the multiple pull-up control signals has a temporarily boosted voltage level. The voltage-mode driver generates an output data signal based on the at least one pull-down control signal and the multiple pull-up control signals. The output data signal is a duobinary signal and has three different voltage levels. The receiver includes a first flip-flop and a second flip-flop. The first flip-flop receives the output data signal and generates a first data signal based on the output data signal, a first clock signal, a first reference voltage, and a first select signal. The first data signal is a binary signal. The second flip-flop receives the output data signal and generates a second data signal based on the output data signal, a second clock signal, the first reference voltage, and a second select signal. The second data signal is a binary signal. The second clock signal is different from the first clock signal. The second data signal is provided as the first select signal, and the first data signal is provided as the second select signal. A second reference voltage different from the first reference voltage is formed in the first flip-flop based on the first reference voltage and the first select signal. The multiple input data signals, the output data signal, and the first and second data signals correspond to the write data or the read data.

[0015] The transmitter and receiver according to the embodiment may have a structure for low-power input / output. For example, the transmitter may generate an output data signal as a duobinary signal based on a time interleaving scheme, may have a structure for minimizing or reducing static power consumption, and may have a structure for improving operating speed and power efficiency. For example, the receiver may have an optimized structure by reducing the number of reference voltages used to sense the input data signal as a duobinary signal, may have a structure for enhancing input offset, and may have a structure for reducing output delay variation.

[0016] A storage system according to embodiments including the transmitter and / or receiver according to embodiments may exhibit enhanced signal characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0018] Figure 1 is a block diagram illustrating a transmitter and a receiver according to an embodiment.

[0019] Figure 2 is a block diagram illustrating a transmitter according to an embodiment.

[0020] Figure 3 It shows Figure 2 An example circuit diagram of a transmitter.

[0021] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D and Figure 4E is shown as input to Figure 3 The transmitter or Figure 3 A signal diagram of an example of a signal output by a transmitter.

[0022] Figure 5 It is shown that the Figure 3 A circuit diagram of an example of a first boost circuit in a transmitter.

[0023] Figure 6 It shows the input to Figure 5 The first boost circuit or from Figure 5 A signal diagram of an example of a signal output by the first boost circuit.

[0024] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D It shows Figure 3 Signal diagram of the transmitter's performance.

[0025] Figure 8 is a block diagram illustrating a receiver according to an embodiment.

[0026] Figure 9 It is shown that the Figure 8 A circuit diagram of an example of a first flip-flop in a receiver.

[0027] Figure 10A and Figure 10B is shown as input to Figure 9 The first trigger or Figure 9 A signal diagram of an example of a signal output by the first flip-flop.

[0028] Figure 11A and Figure 11B It shows Figure 8 and Figure 9 A graphical diagram of the receiver's performance.

[0029] Figure 12 is a block diagram illustrating a storage system according to an embodiment.

[0030] Figure 13 It shows Figure 12 A block diagram of an example of a storage system.

[0031] Figure 14A and Figure 14B It is shown that Figure 12 and Figure 13 A cross-sectional view of an example of a semiconductor package of a memory system. DETAILED DESCRIPTION

[0032] Various embodiments will be described more fully with reference to the accompanying drawings that illustrate embodiments. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Throughout this application, like reference numerals may refer to like elements.

[0033] Figure 1 A transmitter and a receiver according to an embodiment are shown.

[0034] Reference Figure 1 , the transmitter (TX) 10 and the receiver (RX) 20 are connected to each other through a channel 30. For example, as will be referred to Figure 14A and Figure 14B As depicted, channel 30 may include at least one through-silicon via (TSV).

[0035] Transmitter 10 generates an output data signal TX_OUT based on input data signal TX_IN. Output data signal TX_OUT is transmitted to receiver 20 via channel 30. Receiver 20 generates an output data signal RX_OUT based on input data signal RX_IN. Each of input data signal TX_IN and output data signal RX_OUT can be implemented or formed based on a binary scheme and can be referred to as a binary signal. Each of output data signal TX_OUT and input data signal RX_IN can be implemented or formed based on a duobinary scheme and can be referred to as a duobinary signal.

[0036] In a duobinary scheme, a data signal may have three voltage levels that are different from one another. For example, each of the output data signal TX_OUT and the input data signal RX_IN may have one of three voltage levels during one unit interval (UI). Duobinary signals may also be referred to as three-level signals and / or multi-level signals. For example, a value (or data) included in the output data signal TX_OUT as a duobinary signal may represent the sum of two adjacent values (or bits) included in the input data signal TX_IN (e.g., the sum of the previous value and the current value).

[0037] For example, the three voltage levels of the output data signal TX_OUT may include a first voltage level VL1, a second voltage level VL2 higher than the first voltage level VL1, and a third voltage level VL3 higher than the second voltage level VL2. The first voltage level VL1, the second voltage level VL2, and the third voltage level VL3 may be referred to as a low level, a middle (or intermediate) level, and a high level, respectively. For example, the first voltage level VL1 may be approximately 0V, the second voltage level VL2 may be approximately 0.3V, and the third voltage level VL3 may be approximately 0.6V.

[0038] In a binary scheme, a data signal may have two different voltage levels. For example, each of the input data signal TX_IN and the output data signal RX_OUT may have one of two voltage levels during a unit interval. A binary signal may also be referred to as a two-level signal. For example, a value (or data) included in the output data signal RX_OUT, which is a binary signal, may represent a value (or bit) included in the input data signal TX_IN.

[0039] For example, the two voltage levels of the output data signal RX_OUT may include a first voltage level VL1 (but not limited thereto) and a fourth voltage level VL4 that is higher than the first voltage level VL1. The first voltage level VL1 and the fourth voltage level VL4 may be referred to as a low level and a high level, respectively. For example, the fourth voltage level VL4 may be higher than the third voltage level VL3 and may be approximately 1.2V. In other words, the swing width of the output data signal RX_OUT (e.g., the voltage difference between the low level and the high level) may be greater than the swing width of the output data signal TX_OUT.

[0040] For example, the input data signal TX_IN as a binary signal may also have two different voltage levels. For example, the low level of the input data signal TX_IN may be substantially equal to the first voltage level VL1, but is not limited thereto, and the high level of the input data signal TX_IN may be substantially equal to the third voltage level VL3, but is not limited thereto.

[0041] The transmitter 10 and the receiver 20 according to the embodiment may have a structure for low-power input / output. For example, the transmitter 10 may generate an output data signal TX_OUT as a duobinary signal based on a time interleaving scheme, may have a structure for minimizing or reducing static power consumption, and may have a structure for improving operating speed and power efficiency. For example, the receiver 20 may have a structure for reducing the number of reference voltages for reading out the input data signal RX_IN as a duobinary signal, may have a structure for enhancing input offset, and may have a structure for reducing output delay variation. The detailed configuration and operation of the transmitter 10 will be referred to Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 5 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D The detailed configuration and operation of the receiver 20 will be described in detail. Figure 8 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B Provide a description.

[0042] Figure 2 A transmitter according to an embodiment is shown.

[0043] Reference Figure 2 , the transmitter 100 includes a multiplexer 110 , a control logic 120 and a voltage-mode driver 130 .

[0044] The multiplexer 110 can generate a plurality of time-interleaved data signals TID based on a plurality of input data signals TX_IN and a multi-phase clock signal MPCK. The plurality of input data signals TX_IN can be input in parallel. Figure 1 As described, each of the plurality of input data signals TX_IN is a binary signal and has two voltage levels different from each other. The multi-phase clock signal MPCK may include clock signals whose phases partially overlap. The multiplexer 110 may serialize the plurality of input data signals TX_IN.

[0045] For example, the number of the plurality of input data signals TX_IN and the number of clock signals included in the multi-phase clock signal MPCK may be substantially equal to each other, and one clock signal may correspond to one input data signal. In addition, one time-interleaved data signal may be generated by temporally interleaving two or more input data signals, and thus the number of the plurality of time-interleaved data signals TID may be smaller than the number of the plurality of input data signals TX_IN.

[0046] The control logic 120 may generate at least one pull-down control signal PDS and multiple pull-up control signals PUS based on the multiple time-interleaved data signals TID. Each of the multiple pull-up control signals PUS has a temporarily boosted voltage level. Since the transmitter 100 operates or is driven based on the pull-up control signals PUS having the temporarily boosted voltage level, the transition of the output data signal TX_OUT may be enhanced, thereby improving the operating speed and power efficiency of the transmitter 100. In an alternative embodiment, the control logic 120 may generate at least one pull-up control signal PUS and multiple pull-down control signals PDS based on the multiple time-interleaved data signals TID.

[0047] The voltage mode driver 130 generates an output data signal TX_OUT based on at least one pull-down control signal PDS and a plurality of pull-up control signals PUS. Figure 1 As described, the output data signal TX_OUT is a dual binary signal and has three voltage levels that are different from each other. Figure 3 As depicted, the voltage-mode driver 130 may be a dual source driver. In alternative embodiments, the duobinary signal may have more than three voltage levels that are different from each other.

[0048] The transmitter 100 according to an embodiment may include a voltage-mode driver 130 having relatively low quiescent power consumption, rather than a current-mode logic (CML) driver or a current-mode driver having relatively high quiescent power consumption. The transmitter 100 according to an embodiment may include control logic 120 for generating a duobinary signal (e.g., a three-level signal) for the voltage-mode driver 130.

[0049] Figure 3 Shown Figure 2 Example of a transmitter. Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D and Figure 4E Shows the input to Figure 3 The transmitter or Figure 3 Example of the signal output by the transmitter.

[0050] Reference Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D and Figure 4E , the transmitter 100a includes a multiplexer 110a, a control logic 120a, and a voltage-mode driver 130a. The transmitter 100a may also include an output node or output terminal 140.

[0051] exist Figure 3 In the operation example, Figure 2 The plurality of input data signals TX_IN in the embodiment may include a first input data signal D0, a second input data signal D1, a third input data signal D2, and a fourth input data signal D3 which are input in parallel. Figure 2 The multi-phase clock signal MPCK in may include a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4, the phases of which partially overlap. Figure 2 The multiple time-interleaved data signals TID in may include a first time-interleaved data signal X and a second time-interleaved data signal Y. Figure 2 The at least one pull-down control signal PDS may include a first pull-down control signal PD. Figure 2 The plurality of pull-up control signals PUS may include a first pull-up control signal PUMID and a second pull-up control signal PUHIGH. Figure 2 The output data signal TX_OUT can correspond to Figure 3 The output data signal TOUT in.

[0052] The multiplexer 110a may include a first transistor MN11, a second transistor MN12, a third transistor MN13, and a fourth transistor MN14. The first transistor MN11 may be connected between a first input node N11 receiving a first input data signal D0 and a first output node N15 providing a first time-interleaved data signal X, and may have a gate electrode receiving a first clock signal CK1. The second transistor MN12 may be connected between a second input node N12 receiving a second input data signal D1 and a second output node N16 providing a second time-interleaved data signal Y, and may have a gate electrode receiving a second clock signal CK2. The third transistor MN13 may be connected between a third input node N13 receiving a third input data signal D2 and the first output node N15, and may have a gate electrode receiving a third clock signal CK3. The fourth transistor MN14 may be connected between a fourth input node N14 receiving a fourth input data signal D3 and the second output node N16, and may have a gate electrode receiving a fourth clock signal CK4.

[0053] When the time interval for representing a value of the output data signal TOUT is defined as Figure 4E When one unit interval (1UI) is shown, the time interval for representing a value of each of the first input data signal D0, the second input data signal D1, the third input data signal D2, and the fourth input data signal D3 may correspond to the following example: Figure 4A The four unit intervals (4UI) shown in FIG. 1 and the period of each of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 may correspond to the period of FIG. Figure 4B The four unit intervals shown. For example, the first data rate of the first input data signal D0, the second input data signal D1, the third input data signal D2, and the fourth input data signal D3 may be approximately 1 Gb / s, and the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 may be approximately 0.5 GHz. The first input data signal D0, the second input data signal D1, the third input data signal D2, and the fourth input data signal D3 may have values "a," "b," "c," and "d," respectively. For example, "a" and "b" may be "0," respectively, and "c" and "d" may be "1," respectively.

[0054] As described above, multiplexer 110a can serialize the first input data signal D0, the second input data signal D1, the third input data signal D2, and the fourth input data signal D3, and can output a first time-interleaved data signal X and a second time-interleaved data signal Y by temporally interleaving the first input data signal D0, the second input data signal D1, the third input data signal D2, and the fourth input data signal D3. For example, the first time-interleaved data signal X can be generated by temporally interleaving the first input data signal D0 and the third input data signal D2, and the second time-interleaved data signal Y can be generated by temporally interleaving the second input data signal D1 and the fourth input data signal D3. The second data rate of the first time-interleaved data signal X and the second time-interleaved data signal Y can be higher than the first data rate. For example, the second data rate can be approximately twice the first data rate and can be approximately 2 Gb / s.

[0055] For example, Figure 4A 、 Figure 4B and Figure 4CAs shown, at time t1, the first input data signal D0 can be output as the first time-interleaved data signal X based on the first clock signal CK1, the first time-interleaved data signal X can have a value of "0" corresponding to the first input data signal D0, and the second time-interleaved data signal Y can have a value of "0" as an initial value. At time t2, the second input data signal D1 can be output as the second time-interleaved data signal Y based on the second clock signal CK2, the second time-interleaved data signal Y can have a value of "0" corresponding to the second input data signal D1, and the first time-interleaved data signal X can have a value of "0" whose value is maintained at time t1. Similarly, at time t3, the third input data signal D2 can be output as the first time-interleaved data signal X based on the third clock signal CK3, the first time-interleaved data signal X can have a value of "1" corresponding to the third input data signal D2, and the second time-interleaved data signal Y can have a value of "0" whose value is maintained at time t2. At time t4, the fourth input data signal D3 can be output as the second time-interleaved data signal Y based on the fourth clock signal CK4, the second time-interleaved data signal Y can have a value of "1" corresponding to the fourth input data signal D3, and the first time-interleaved data signal X can have a value of "1" whose value is maintained at time t3.

[0056] The control logic 120 a may include a first NAND gate 121 , a NOR gate 122 , an inverter 123 , a second NAND gate 124 , a first boosting circuit 125 , and a second boosting circuit 126 .

[0057] The first NAND gate 121 can perform a NAND operation on the first time-interleaved data signal X and the second time-interleaved data signal Y. The NOR gate 122 can generate a first pull-down control signal PD by performing a NOR operation on the first time-interleaved data signal X and the second time-interleaved data signal Y. The inverter 123 can invert the output of the NOR gate 122 (for example, it can invert the first pull-down control signal PD). The second NAND gate 124 can perform a NAND operation on the output of the first NAND gate 121 and the output of the inverter 123. The first boost circuit 125 can generate a first pull-up control signal PUMID having a temporarily boosted voltage level based on the output of the first NAND gate 121. The second boost circuit 126 can generate a second pull-up control signal PUHIGH having a temporarily boosted voltage level based on the output of the second NAND gate 124.

[0058] The value of the first pull-down control signal PD and the value of the first pull-up control signal PUMID and the value of the second pull-up control signal PUHIGH can be determined based on the value of the first time-interleaved data signal X and the value of the second time-interleaved data signal Y. The third data rate of the first pull-down control signal PD and the first pull-up control signal PUMID and the second pull-up control signal PUHIGH can be higher than the second data rate. For example, the third data rate can be approximately twice the second data rate and can be approximately 4 Gb / s.

[0059] For example, Figure 4C and Figure 4D As shown, when the first time-interleaved data signal X and the second time-interleaved data signal Y have a value of "0" at time t1 and time t2, the first pull-down control signal PD may have a value of "1", and the first pull-up control signal PUMID and the second pull-up control signal PUHIGH may have a value of "0". When the first time-interleaved data signal X has a value of "1" and the second time-interleaved data signal Y has a value of "0" at time t3, the first pull-up control signal PUMID may have a value of "1", and the first pull-down control signal PD and the second pull-up control signal PUHIGH may have a value of "0". When the first time-interleaved data signal X and the second time-interleaved data signal Y have a value of "1" at time t4, the second pull-up control signal PUHIGH may have a value of "1", and the first pull-down control signal PD and the first pull-up control signal PUMID may have a value of "0". An asterisk (*) preceding the value '1' of the first pull-up control signal PUMID at time t3 and the value '1' of the second pull-up control signal PUHIGH at time t4 may indicate that the first and second pull-up control signals PUMID and PUHIGH have a boosted high level.

[0060] The voltage mode driver 130 a may include a first transistor MN15 , a second transistor MN16 , and a third transistor MN17 .

[0061] The first transistor MN15 can be connected between the output node 140 providing the output data signal TOUT and the ground voltage having the first voltage level VL1, and can have a gate electrode that receives the first pull-down control signal PD. The second transistor MN16 can be connected between the first power supply voltage VDDL1 having the third voltage level VL3 and the output node 140, and can have a gate electrode that receives the second pull-up control signal PUHIGH. The third transistor MN17 can be connected between the second power supply voltage VDDL2 having the second voltage level VL2 and the output node 140, and can have a gate electrode that receives the first pull-up control signal PUMID. For example, the second voltage level VL2 can be approximately half of the third voltage level VL3 (e.g., 2*VL2=VL3 or 2*VDDL2=VDDL1). For example, the first transistor MN15 can be a pull-down transistor, and each of the second transistor MN16 and the third transistor MN17 can be a pull-up transistor.

[0062] The output data signal TOUT may have a voltage level corresponding to the sum of two adjacent input data signals among the first input data signal D0, the second input data signal D1, the third input data signal D2, and the fourth input data signal D3. For example, based on the value of the first pull-down control signal PD, the value of the first pull-up control signal PUMID, and the value of the second pull-up control signal PUHIGH, one of the first transistor MN15, the second transistor MN16, and the third transistor MN17 may be turned on, and the voltage level of the output data signal TOUT may be determined based on the turned-on transistor. The output data signal TOUT may have a third data rate.

[0063] For example, Figure 4C 、 Figure 4D and Figure 4EAs shown, when the first pull-down control signal PD has a value of "1" at time t2, the first transistor MN15 may be turned on, and the output data signal TOUT may have a first voltage level VL1 based on the ground voltage. The first voltage level VL1 may correspond to a value "a+b" (e.g., "0"), which is the sum of the first input data signal D0 and the second input data signal D1. Similarly, when the first pull-up control signal PUMID has a value of "1" at time t3, the third transistor MN17 may be turned on, and the output data signal TOUT may have a second voltage level VL2 based on the second power supply voltage VDDL2. The second voltage level VL2 may correspond to a value "b+c" (e.g., "1"), which is the sum of the second input data signal D1 and the third input data signal D2. When the second pull-up control signal PUHIGH has a value of "1" at time t4, the second transistor MN16 may be turned on, and the output data signal TOUT may have a third voltage level VL3 based on the first power supply voltage VDDL1. The third voltage level VL3 may correspond to a value "c+d" (eg, "2") which is the sum of the third input data signal D2 and the fourth input data signal D3. Figure 4E Not shown, but at time t1 , the first transistor MN15 may be turned on as at time t2 , and the output data signal TOUT may have the first voltage level VL1 .

[0064] In an embodiment, each of the transistors MN11 , MN12 , MN13 , MN14 , MN15 , MN16 , and MN17 may be an n-type metal oxide semiconductor (NMOS) transistor.

[0065] Figure 5 It is shown that the Figure 3 A circuit diagram of an example of a first boost circuit in a transmitter. Figure 6 is shown as input to Figure 5 The first boost circuit or from Figure 5 FIG2 is a diagram of an example of a signal output by the first boosting circuit.

[0066] Reference Figure 5 and Figure 6 , the first boosting circuit 125 may include a pulse generator 128 , a first transistor MP21 , a capacitor C21 , a second transistor MP22 , and a third transistor MN23 .

[0067] The pulse generator 128 may be connected to an input node N21 that receives the output of the first NAND gate 121 and may generate a pulse signal PUL based on the output of the first NAND gate 121, for example, when the output of the first NAND gate 121 transitions from a high voltage level, such as VL3, to a low voltage level, such as VL1. The first transistor MP21 may be connected between the first power supply voltage VDDL1 and the node N22 and may have a gate electrode that receives the pulse signal PUL. The capacitor C21 may be connected between the gate electrode of the first transistor MP21 and the node N22. The second transistor MP22 may be connected between the node N22 and an output node N23 that provides the first pull-up control signal PUMID and may have a gate electrode connected to the input node N21. The third transistor MN23 may be connected between the output node N23 and the ground voltage and may have a gate electrode connected to the input node N21.

[0068] In an embodiment, each of the transistors MP21 and MP22 may be a p-type metal oxide semiconductor (PMOS) transistor, and the transistor MN23 may be an NMOS transistor.

[0069] The control logic 120a included in the transmitter 100a according to the embodiment may include a pulse generator 128 for generating a delay of a predetermined time interval, thereby improving the operating speed and power efficiency of the transmitter 100a. The level of the pulse signal PUL provided through the output node N23 and the level of the first pull-up control signal PUMID may be determined based on the output of the first NAND gate 121 received from the input node N21.

[0070] For example, in Figure 6In FIG, "IN1" represents the output of the first NAND gate 121 (e.g., X and NOR Y), such as the voltage at the input node N21, and "OUT1" represents the first pull-up control signal PUMID provided by the output node N23, such as the voltage at the output node N23. When the voltage IN1 at the input node N21 is at a high level (e.g., the third voltage level VL3 or "1"), each of the pulse signal PUL and the voltage OUT1 at the output node N23 may be at a low level (e.g., the first voltage level VL1 or "0"). When both the pulse signal PUL and the voltage OUT1 at the output node N23 are at a low level, the first transistor MP21, referred to as the head PMOS transistor, may be turned on to provide a sufficient precharge time, and the capacitor C21 may be precharged based on the first power supply voltage VDDL1. Thereafter, when the voltage IN1 at the input node N21 transitions from a high level to a low level, the pulse signal PUL may transition from a low level to a high level, may remain at a high level for a predetermined time interval, and may then transition from a high level to a low level again. During a predetermined time interval in which the pulse signal PUL has a high level, the first transistor MP21 may be turned off, and based on the charge pre-charged in the capacitor C21, the output node N23 may be boosted and the voltage OUT1 at the output node N23 may have a boosted high level (e.g., voltage level "VL3+α"). When the pulse signal PUL has a low level after the predetermined time interval in which the pulse signal PUL has a high level, the first transistor MP21 may be turned on, and the output node N23 may return to a previous state and the voltage OUT1 at the output node N23 may have an original high level (e.g., third voltage level VL3). As a result, the first pull-up control signal PUMID may have a temporarily boosted voltage level, e.g., Figure 6 The voltage OUT1 at the output node N23 is shown in FIG.

[0071] Although alternative embodiments may differ, the configuration and operation of the second boost circuit 126 may be similar to that of the reference embodiment. Figure 5 and Figure 6 The configuration and operation of the first boosting circuit 125 described are substantially the same, and repeated descriptions may be omitted.

[0072] In the voltage-mode driver 130a, which is the final stage, the transition from the first voltage level VL1 to the second voltage level VL2 and the transition from the second voltage level VL2 to the third voltage level VL3 can be strengthened based on the output of the control logic 120a (e.g., the first pull-up control signal PUMID and the second pull-up control signal PUHIGH) that is temporarily boosted to the voltage level "VL3+α". In other words, the pull-up transistor in the output driver can be temporarily driven more strongly. In addition, even if the transition from the second voltage level VL2 to the third voltage level VL3 occurs, the high level of the boost can ensure that the operating area is a linear area, so even if there are process voltage temperature (PVT) variations, the voltage-mode driver 130a can operate reliably.

[0073] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D Shown Figure 3 In particular, Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D Shown Figure 3 Simulation results of the transmitter.

[0074] Reference Figure 7A , shows the results of a Monte Carlo simulation of approximately 1,000 simulation runs for a transmitter 100a according to an example under theoretical ideal conditions (e.g., VDD, TT angle, and room temperature). The transmitter 100a operates with sufficient margin, as indicated by a sufficient eye area including a lower opening eye width and eye height corresponding to a transition from a first voltage level VL1 to a second voltage level VL2, and a sufficient eye area including an upper opening eye width and eye height corresponding to a transition from a second voltage level VL2 to a third voltage level VL3.

[0075] Reference Figure 7B , shows variations in the boosted voltage high level and rise time of the output of control logic 120a included in transmitter 100a, depending on PVT variations, according to an embodiment. The boosted voltage high level can be referred to as the peak voltage, and the rise time can be referred to as the duty cycle or time interval during which the boosted voltage high level is maintained. It can be seen that even with fluctuations of approximately ±10% in the boosted voltage high level, the eye diagram performance and power variation remain within approximately ±2%. Furthermore, it can be seen that even with variations in the rise time of up to approximately 40%, the overall performance variation remains within approximately 4%.

[0076] Reference Figure 7C , shows that based on Figure 7BThe results of PVT variation analysis using eye diagram performance at 20 corners (e.g., process corners: TT, SS, FF, FS, SF; power supply voltage: HVDD, LVDD; temperature: cold, hot) were analyzed. Analyzing the performance of "SS / LVDD / Hot," one of the corners with the largest variation, revealed performance variations of approximately 21% to approximately 6%. Analyzing the performance of "FF / HVDD / Cold," another of the corners with the largest variation, revealed performance variations of approximately 12% to approximately 21%.

[0077] Reference Figure 7D , shows the power consumption of the transmitter 100a according to the embodiment. Figure 7D In the figure, the left graph shows the power consumption of a related art transmitter using a current-mode driver (e.g., a CML driver), and the right graph shows the power consumption of a transmitter according to an embodiment of the present disclosure using a voltage-mode driver (e.g., a dual-source driver). It can be seen that the power consumption of the transmitter according to the embodiment is reduced by approximately 59% compared to the related art transmitter. Furthermore, it can be seen that the power consumption of the transmitter according to the embodiment is reduced by approximately 41% compared to a transmitter without a time interleaving scheme, and the power consumption of serialization is reduced by approximately 26%.

[0078] Figure 8 FIG. 1 shows a receiver according to an embodiment. Figure 8 , the receiver 200 includes a first flip-flop ( FF1 ) 210 and a second flip-flop ( FF2 ) 220 .

[0079] The first flip-flop 210 receives an input data signal RX_IN and generates a first output data signal RX_OUT1 based on the input data signal RX_IN, a first clock signal CKE, a first reference voltage VH, and a first selection signal SEL1. The second flip-flop 220 receives an input data signal RX_IN and generates a second output data signal RX_OUT2 based on the input data signal RX_IN, a second clock signal CKO different from the first clock signal CKE, the first reference voltage VH, and a second selection signal SEL2.

[0080] As reference Figure 1 As described, the input data signal RX_IN is a duobinary signal and has three different voltage levels, and the first output data signal RX_OUT1 and the second output data signal RX_OUT2 are both binary signals and have two different voltage levels. One of the first output data signal RX_OUT1 and the second output data signal RX_OUT2 (for example, the first output data signal RX_OUT1) may correspond to Figure 1 The output data signal RX_OUT in.

[0081] Each of the first flip-flop 210 and the second flip-flop 220 may include a first input terminal D receiving an input data signal RX_IN, a clock terminal receiving a corresponding one of clock signals CKE and CKO, an output terminal Q outputting a corresponding one of output data signals RX_OUT1 and RX_OUT2, a reference voltage terminal VREF receiving a first reference voltage VH, and a select terminal SEL receiving a corresponding one of select signals SEL1 and SEL2. The second output data signal RX_OUT2 of the second flip-flop 220 may be provided to the first flip-flop 210 as the first select signal SEL1, and the first output data signal RX_OUT1 of the first flip-flop 210 may be provided to the second flip-flop 210 as the second select signal SEL2.

[0082] A second reference voltage (e.g., VL) different from the first reference voltage VH can be formed or generated in the first flip-flop 210 based on the first reference voltage VH and the first selection signal SEL1. Similarly, a second reference voltage VL can be formed or generated in the second flip-flop 220 based on the first reference voltage VH and the second selection signal SEL2. In other words, substantially the same operation and / or effect as using two different reference voltages VH and VL can be obtained by using only one reference voltage VH.

[0083] The first flip-flop 210 and the second flip-flop 220 may be referred to as an even flip-flop and an odd flip-flop, respectively. The first clock signal CKE and the second clock signal CKO may be referred to as an even clock signal and an odd clock signal, respectively. For example, the first clock signal CKE and the second clock signal CKO may have opposite phases to each other. The receiver 200 may operate at approximately half the frequency using clock signals having opposite phases.

[0084] The receiver 200 according to the embodiment may receive and read out the input data signal RX_IN as a duo-binary signal having three voltage levels using only one reference voltage VH.

[0085] Figure 9 Shown included in Figure 8 Example of the first trigger in the receiver. Figure 10A and Figure 10B Shows the input to Figure 9 The first trigger or Figure 9 Example of the signal output by the first flip-flop.

[0086] Reference Figure 9 、 Figure 10A and Figure 10B , the first flip-flop 210a may include a first circuit 230, a second circuit 240 and an output circuit 250. Figure 9In the example, Figure 8 The input data signal RX_IN in may correspond to the input data signal DIN, and Figure 8 The first output data signal RX_OUT1 in may correspond to the output data signal RDE.

[0087] The first circuit 230 may generate a first data signal DA and a second data signal DREF based on a power supply voltage VDDH, an input data signal DIN, a first clock signal CKE, a first reference voltage VH, and a first selection signal SEL1. The first circuit 230 may include a first structure for forming or generating a second reference voltage VL, and a second structure for boosting the first data signal DA and the second data signal DREF.

[0088] like Figure 10A As shown, the input data signal DIN can have Figure 4E The waveform of the output data signal TOUT is substantially the same as the waveform of the output data signal TOUT, and may have a first voltage level VL1, a second voltage level VL2, and a third voltage level VL3. The first reference voltage VH may have a voltage level VLH between the second voltage level VL2 and the third voltage level VL3, and the second reference voltage VL may have a voltage level VLL between the first voltage level VL1 and the second voltage level VL2. For example, the voltage level VLH of the first reference voltage VH may be approximately 0.45V, and the voltage level VLL of the second reference voltage VL may be approximately 0.15V.

[0089] The first circuit 230 may include a first transistor MP31 , a second transistor MP32 , a third transistor MP33 , a fourth transistor MP34 , a fifth transistor MP35 , a sixth transistor MP36 , a seventh transistor MP37 , an eighth transistor MN38 , and a ninth transistor MN39 .

[0090] A first transistor MP31, a second transistor MP32, and a third transistor MP33 may be connected in parallel between a node N31 and a first data node N32 providing a first data signal DA. The first transistor MP31 may have a gate electrode that receives a power supply voltage VDDH. The second transistor MP32 may have a gate electrode that receives an input data signal DIN. The third transistor MP33 may have a gate electrode connected to a second data node N33 providing a second data signal DREF. A fourth transistor MP34, a fifth transistor MP35, and a sixth transistor MP36 may be connected in parallel between the node N31 and the second data node N33. The fourth transistor MP34 may have a gate electrode connected to the first data node N32. The fifth transistor MP35 may have a gate electrode that receives a first reference voltage VH. The sixth transistor MP36 may have a gate electrode that receives a first select signal SEL1. The seventh transistor MP37 may be connected between the power supply voltage VDDH and the node N31 and may have a gate electrode that receives a first clock signal CKE. The eighth transistor MN38 may be connected between the first data node N32 and the ground voltage and may have a gate electrode receiving the first clock signal CKE. The ninth transistor MN39 may be connected between the second data node N33 and the ground voltage and may have a gate electrode receiving the first clock signal CKE.

[0091] In an embodiment, the sixth transistor MP36 may correspond to the first structure for forming the second reference voltage VL. For example, when the first select signal SEL1, which is the second output data signal RX_OUT2 of the second flip-flop 220 (e.g., the previous data output of the second flip-flop 220), has a high level (e.g., "1"), the sixth transistor MP36 may be turned off, and the first circuit 230 may generate the first data signal DA and the second data signal DREF by comparing the input data signal DIN with the first reference voltage VH. When the first select signal SEL1 has a low level (e.g., "0"), the sixth transistor MP36 may be turned on, and additional current may flow to the second data node N33 through the turned-on sixth transistor MP36, thereby providing the second data node N33 with a current substantially the same as when the second reference voltage VL is applied to the fifth transistor MP35. In other words, when the first selection signal SEL1 has a low level, a driving current corresponding to the second reference voltage VL can be provided or applied to the second data node N33 based on the first reference voltage VH, the first selection signal SEL1, and the fifth transistor MP35 and the sixth transistor MP36, and the first circuit 230 can generate the first data signal DA and the second data signal DREF by comparing the input data signal DIN with the second reference voltage VL.

[0092] In an embodiment, the third transistor MP33 and the fourth transistor MP34 may correspond to a second structure for boosting the first data signal DA and the second data signal DREF. For example, during the evaluation timing, the current flowing to the first data node N32 and the second data node N33 may be temporarily boosted by the third transistor MP33 and the fourth transistor MP34. When an input having a relatively large amount of current flowing through a first voltage level (e.g., approximately 0V) is applied, the effect of the boosted current may be relatively small. When an input having a relatively small amount of current flowing through a third voltage level (e.g., approximately 0.6V) is applied, the effect of the boosted current may be relatively large. Therefore, the variation in output delay depending on the input level or situation may be reduced.

[0093] The second circuit 240 may generate a third data signal SB and a fourth data signal RB based on the power supply voltage VDDH, the first and second data signals DA and DREF, and the first clock signal CKE. The second circuit 240 may include a third structure for enhancing input offset.

[0094] The second circuit 240 may include a first inverter 242, a second inverter 244, a first transistor MP41, a second transistor MN42, a third transistor MN43, a fourth transistor MP44, a fifth transistor MN45, a sixth transistor MN46, and a seventh transistor MP47. In alternative embodiments, the first and second inverters 242 and 244 may be omitted, and the second and sixth N-type transistors MN42 and MN46 may be replaced with P-type transistors MP42 and MP46.

[0095] The first inverter 242 may receive the first data signal DA. The second inverter 244 may receive the second data signal DREF. The first transistor MP41 may have a gate electrode connected to a third data node N42 providing the third data signal SB and may be connected between the node N41 and a fourth data node N43 providing the fourth data signal RB. The second transistor MN42 and the third transistor MN43 may be connected in parallel between the fourth data node N43 and a ground voltage. The second transistor MN42 may have a gate electrode connected to the output of the first inverter 242. The third transistor MN43 may have a gate electrode connected to the third data node N42. The fourth transistor MP44 may be connected between the node N41 and the third data node N42 and may have a gate electrode connected to the fourth data node N43. The fifth transistor MN45 and the sixth transistor MN46 may be connected in parallel between the third data node N42 and a ground voltage. The fifth transistor MN45 may have a gate electrode connected to the fourth data node N43. The sixth transistor MN46 may have a gate electrode connected to the output of the second inverter 244. The seventh transistor MP47 may be connected between the power supply voltage VDDH and the node N41 and may have a gate electrode receiving the first clock signal CKE.

[0096] In an embodiment, the first inverter 242 and the second inverter 244 may correspond to a third structure for enhancing input offset. For example, by adding the first inverter 242 and the second inverter 244, the input offset occurring in the related art structure may be enhanced.

[0097] The output circuit 250 may generate an output data signal RDE and an inverted output data signal RDBE based on the third data signal SB and the fourth data signal RB.

[0098] Output circuit 250 may include a first inverter 252, a second inverter 254, and an SR NAND latch 256. First inverter 252 may receive third data signal SB. Second inverter 254 may receive fourth data signal RB. SR NAND latch 256 may generate an output data signal RDE and an inverted output data signal RDBE based on the outputs of first inverter 252 and second inverter 254.

[0099] The supply voltage VDDH can be different from Figure 3 The first power supply voltage VDDL1 and the second power supply voltage VDDL2 in the embodiment of the present invention may have a fourth voltage level VL4. Figure 10B As shown, the two voltage levels of the output data signal RDE generated based on the power supply voltage VDDH may include a first voltage level VL1 and a fourth voltage level VL4. In addition, the output data signal RDE may be generated such that Figure 4AThe values “a”, “b”, “c” and “d” of the input data signals D0, D1, D2 and D3 of the transmitter 100a are arranged in sequence.

[0100] In an embodiment, each of transistors MP31, MP32, MP33, MP34, MP35, MP36, MP37, MP41, MP44, and MP47 may be a PMOS transistor, and each of transistors MN38, MN39, MN42, MN43, MN45, and MN46 may be an NMOS transistor.

[0101] Although the exemplary embodiment is described based on an example using one reference voltage VH, the embodiment is not limited thereto. For example, one reference voltage VL may be used to generate an output data signal.

[0102] Figure 11A and Figure 11B Shown Figure 8 and Figure 9 In particular, Figure 11A and Figure 11B Shown Figure 8 and Figure 9 Simulation results of the receiver.

[0103] Reference Figure 11A , shows the current generated by the receiver 200 according to the embodiment. Figure 11A In the figure, the left graph shows the drive current Iconv generated by the second reference voltage VL in a related art receiver operating based on two reference voltages VH and VL, and the right graph shows the drive current Ipro generated by the first reference voltage VH and the first selection signal SEL1 in a receiver 200 according to an embodiment operating only based on the first reference voltage VH. In the related art receiver, it can be seen that the average value or mean of the drive current Iconv is approximately 2.53f, the standard deviation or sigma of the drive current Iconv is approximately 99.2a, and the mean of the sigma of the drive current Iconv is approximately 0.039. In the receiver 200 according to an embodiment, it can be seen that the average value of the drive current Ipro is approximately 2.54f, the standard deviation of the drive current Ipro is approximately 98.3a, and the mean of the sigma of the drive current Ipro is also approximately 0.039. Therefore, it can be seen that the drive current Iconv and the drive current Ipro are comparable to each other.

[0104] Reference Figure 11B , shows the performance of the receiver 200 according to the embodiment. Figure 11BIn FIG. 1 , the table on the left shows the performance of a receiver of the related art, and the table on the right shows the performance of the receiver 200 according to the embodiment. Figure 11B In the example, "Case 1" represents an input of approximately 0V and a reference voltage of approximately 0.15V, "Case 2" represents an input of approximately 0.3V and a reference voltage of approximately 0.15V, "Case 3" represents an input of approximately 0.3V and a reference voltage of approximately 0.45V, and "Case 4" represents an input of approximately 0.6V and a reference voltage of approximately 0.45V. As a result of examining the delays of "Case 1," "Case 2," "Case 3," and "Case 4," it can be seen that the delay in "Case 2" is reduced by approximately 1%, and the delay in "Case 4" is reduced by approximately 27%. In addition, it can be seen that the delay variation of each input case is improved by approximately 50% relative to the median (from approximately ±20% to ±10%).

[0105] Figure 12 A storage system according to an embodiment is shown. Figure 12 , the memory system 300 includes a memory controller 310 and a memory device 320. The memory system 300 may further include a plurality of signal lines 330 electrically connecting the memory controller 310 and the memory device 320.

[0106] The memory device 320 is controlled by the memory controller 310. For example, based on a request from a host, the memory controller 310 may store (e.g., write or program) data in the memory device 320, or may retrieve (e.g., read or read out) data from the memory device 320. For example, the memory device 320 may include a high-bandwidth memory (HBM) device.

[0107] The plurality of signal lines 330 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 310 may transmit commands CMD, addresses ADDR, and control signals CTRL to the memory device 320 via the command lines, address lines, and control lines, may exchange data signals MLDAT with the memory device 320 via the data I / O lines, and may transmit power supply voltage PWR to the memory device 320 via the power lines. For example, the control signal CTRL may include a chip enable signal (CE), a write enable signal (WE), a read enable signal (RE), a command latch enable signal (CLE), an address latch enable signal (ALE), and the like. For example, the data signal MLDAT may be a multi-level signal and may be a duobinary signal generated by a transmitter according to an embodiment and received by a receiver according to an embodiment.

[0108] In an embodiment, the plurality of signal lines 330 may further include a data strobe (DQS) signal line for transmitting a DQS signal. The DQS signal may be a signal for providing a reference time point for determining a logic value of the data signal MLDAT exchanged between the memory controller 310 and the memory device 320.

[0109] In an embodiment, at least a portion of the plurality of signal lines 330 may be referred to as a channel. The term "channel" as used herein may refer to a signal line including a data I / O line for transmitting a data signal MLDAT. However, embodiments are not limited thereto, and the channel may further include a command line for transmitting a command CMD and / or an address line for transmitting an address ADDR. For example, the channel may include at least one through-silicon via (TSV).

[0110] Figure 13 Shown Figure 12 An example of a storage system. Figure 13 , the storage system 302 includes a storage controller 312 , a storage device 322 , and a channel 332 .

[0111] The memory controller 312 includes a first transmitter 314 and a first receiver 316. The memory device 322 includes a second transmitter 324 and a second receiver 326. The first transmitter 314 and the first receiver 316 are connected to the second transmitter 324 and the second receiver 326 via a channel 332. In an embodiment, each of the memory controller 312 and the memory device 322 may include multiple transmitters and multiple receivers, and the memory system 302 may include multiple channels for connecting the multiple transmitters with the multiple receivers.

[0112] Transmitters 314 and 324 output write data to be stored in storage device 322 or read data to be retrieved from storage device 322, respectively. Channel 332 transmits the write data or read data. Receivers 326 and 316 receive the write data or read data, respectively. For example, during a data write operation, transmitter 314 may generate a data signal corresponding to the write data and may output the data signal via channel 332. Receiver 326 may receive the data signal, and a data write operation may be performed based on the received data signal. During a data read operation, transmitter 324 may generate a data signal corresponding to the read data and may output the data signal via channel 332. Receiver 316 may receive the data signal, and a data read operation may be performed based on the received data.

[0113] Each of transmitter 314 and transmitter 324 may be a transmitter according to an embodiment and may generate a duobinary signal according to an embodiment. Each of receiver 316 and receiver 326 may be a receiver according to an embodiment and may receive a duobinary signal according to an embodiment.

[0114] Figure 14A and Figure 14B is included Figure 12 and Figure 13 A cross-sectional view of an example of a semiconductor package of a memory system.

[0115] Reference Figure 14A The semiconductor package 400 includes a package substrate 401 , a first semiconductor device ( SD1 ) 410 , a second semiconductor device ( SD2 ) 420 , and an interposer 430 . The semiconductor package 400 may further include a sealing member 440 .

[0116] The semiconductor package 400 may be a memory package having a stacked chip structure in which a plurality of dies (or chips) are stacked. For example, the semiconductor package 400 may be implemented in a 2.5-dimensional (2.5D) structure and may include a semiconductor device and a memory device having a 2.5D chip structure. For example, the first semiconductor device 410 may include a logic semiconductor device, and the second semiconductor device 420 may include a memory device. For example, the logic semiconductor device may operate as a host or a memory controller and may include a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application-specific integrated circuit (ASIC), etc. For example, the memory device may include a high-bandwidth memory (HBM) device.

[0117] The package substrate 401 may have an upper surface and a lower surface facing each other. For example, the package substrate 401 may be a printed circuit board (PCB). The PCB may be a multilayer circuit board including pathways and various circuits.

[0118] Interposer 430 may be disposed on package substrate 401. Interposer 430 may be mounted on package substrate 401 via solder bumps 435. For example, solder bumps 435 may be C4 bumps. For example, the planar area of interposer 430 may be smaller than the planar area of package substrate 401. In other words, in a top view, interposer 430 may be disposed within the area of package substrate 401.

[0119] The interposer 430 may include a plurality of connection wirings 431 and a plurality of through electrodes 433. For example, the interposer 430 may be a silicon interposer including a silicon substrate as a semiconductor substrate, and the plurality of through electrodes 433 may be through silicon vias (TSVs) penetrating the silicon substrate.

[0120] The first semiconductor device 410 and the second semiconductor device 420 may be connected to each other through a plurality of connection wirings 431 and / or may be electrically connected to the package substrate 401 through a plurality of through-electrodes (e.g., through-silicon vias) 433 and solder bumps (e.g., C4 bumps) 435. A silicon interposer may provide high-density interconnection between the first semiconductor device 410 and the second semiconductor device 420.

[0121] The first semiconductor device 410 and the second semiconductor device 420 may be disposed on the interposer 430. The first semiconductor device 410 and the second semiconductor device 420 may be mounted on the interposer 430 using a flip-chip bonding scheme. For example, the first semiconductor device 410 and the second semiconductor device 420 may be mounted on the interposer 430 such that active surfaces of the first semiconductor device 410 and the second semiconductor device 420, on which die pads are disposed, face the interposer 430. The die pads of the first semiconductor device 410 and the second semiconductor device 420 may be electrically connected to connection pads of the interposer 430 via solder bumps 437, which are conductive bumps. For example, the solder bumps 437 may be microbumps.

[0122] although Figure 14A The semiconductor package 400 is shown to include a first semiconductor device 410 and a second semiconductor device 420, but the embodiment is not limited thereto. For example, the second semiconductor device 420 may include a buffer die and a plurality of memory dies (or chips) stacked on the buffer die. The buffer die and the plurality of memory dies may be electrically connected to each other via TSVs.

[0123] The first semiconductor device 410 , the second semiconductor device 420 , and the interposer 430 may be fixed by a sealing member 440 .

[0124] In an embodiment, the semiconductor package 400 may further include a first adhesive underfilling between the interposer 430 and the package substrate 401, a second adhesive underfilling between the first semiconductor device 410 and the interposer 430, and / or a third adhesive underfilling between the second semiconductor device 420 and the interposer 430. For example, the first adhesive, the second adhesive, and the third adhesive may include an epoxy material to fill the gap between the interposer 430 and the package substrate 401 and the gap between the interposer 430 and each of the first semiconductor device 410 and the second semiconductor device 420.

[0125] External connection pads may be provided on the lower surface of the package substrate 401, and external connectors 403 for electrically connecting to external devices may be provided on the external connection pads. For example, the external connectors 403 may be solder balls (e.g., a ball grid array (BGA)). The semiconductor package 400 may be mounted on a module substrate (e.g., a board substrate) (not shown) via the external connectors 403, thereby forming a memory module.

[0126] The first semiconductor device 410 may include an interface (IF) 411 for communicating with the outside of the semiconductor package 400. For example, the interface 411 may include at least one of various serial interfaces. The first semiconductor device 410 may include an interface 413 for communicating with the second semiconductor device 420, and the second semiconductor device 420 may include an interface 421 for communicating with the first semiconductor device 410. For example, each of the interface 413 and the interface 421 may include an HBM physical layer (PHY) unit for a storage interface.

[0127] exist Figure 14A In the example of FIG. 1 , the semiconductor substrate (eg, silicon substrate), the plurality of connection wirings 431, and the plurality of through electrodes 433 (eg, through silicon vias) included in the interposer 430 may be the same as those in FIG. 1 . Figure 12 and Figure 13 According to an embodiment, the interface 411, the interface 413, and the interface 421 may include a transmitter and a receiver.

[0128] Reference Figure 14B The semiconductor package 500 includes a package substrate 501 , a first semiconductor device 510 , and a second semiconductor device 520 . The semiconductor package 500 may further include a sealing member 540 .

[0129] Except for omitting Figure 14A The interposer 430, the first semiconductor device 510 and the second semiconductor device 520 are stacked in a vertical direction, and the through-electrodes and the connection wiring are included in the first semiconductor device 510 and the second semiconductor device 520 instead of the interposer 430. The semiconductor package 500 may be similar to Figure 14A A semiconductor package 400 is provided.

[0130] The semiconductor package 500 may be a memory package having a stacked chip structure in which a plurality of dies (or chips) are stacked. For example, the semiconductor package 500 may be implemented in a three-dimensional (3D) structure and may include a semiconductor device and a memory device having a 3D chip structure. For example, the first semiconductor device 510 may include a logic semiconductor device, and the second semiconductor device 520 may include a memory device.

[0131] The package substrate 501, the external connector 503 and the sealing member 540 may be respectively Figure 14A The package substrate 401, the external connector 403 and the sealing member 440 in FIG. 4 are substantially the same.

[0132] The first semiconductor device 510 may be provided on the package substrate 501. The first semiconductor device 510 may be mounted on the package substrate 501 through a flip-chip bonding scheme. For example, the first semiconductor device 510 may be mounted on the package substrate 501 such that an active surface of the first semiconductor device 510, on which a die pad is provided, faces the package substrate 501. The die pad of the first semiconductor device 510 may be a connection pad electrically connected to the package substrate 501 through a solder bump (e.g., uBump) 537 as a conductive bump.

[0133] The first semiconductor device 510 may include a semiconductor substrate 512 and a wiring layer 514. The semiconductor substrate 512 may include a circuit structure (not shown) such as a transistor, and may include a plurality of through-electrodes (e.g., through-silicon vias) 533 penetrating the semiconductor substrate 512. Although not shown in detail, the wiring layer 514 may include a plurality of connection wirings 531 and a plurality of vias.

[0134] The second semiconductor device 520 may be disposed on the first semiconductor device 510. The second semiconductor device 520 may be mounted on the first semiconductor device 510 through a flip-chip bonding scheme. For example, the second semiconductor device 520 may be mounted on the first semiconductor device 510 such that an active surface of the second semiconductor device 520, on which a die pad is disposed, faces the first semiconductor device 510. The die pad of the second semiconductor device 520 may be electrically connected to a plurality of through-electrodes (e.g., through-silicon vias) 533 of the first semiconductor device 510 through solder bumps (e.g., C4 bumps) 535 as conductive bumps.

[0135] The second semiconductor device 520 may include a semiconductor substrate 522 and a wiring layer 524. The semiconductor substrate 522 may include a circuit structure (not shown) such as a transistor. Although not shown in detail, the wiring layer 524 may include a plurality of connection wirings 532 and a plurality of vias.

[0136] although Figure 14B The semiconductor package 500 is shown to include a first semiconductor device 510 and a second semiconductor device 520, but the embodiment is not limited thereto. For example, at least one other second semiconductor device may be stacked on the second semiconductor device 520. In this example, like the first semiconductor device 510, the semiconductor substrate 522 of the second semiconductor device 520 may include a through electrode.

[0137] exist Figure 14B In the example of FIG. 5 , the plurality of through electrodes 533, the solder bumps 535, and the plurality of connection wirings 531 and 532 in the wiring layers 514 and 524 may be the same as those in FIG. Figure 12 and 13 The channel described corresponds to.

[0138] The present invention can be applied to various electronic devices and systems including transmitters, receivers, and storage systems. For example, the present invention can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0139] The foregoing is an illustration of the embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described for ease of understanding, it will be readily understood by those skilled in the relevant art that various modifications in the disclosed embodiments and other embodiments are possible without departing substantially from the teachings of the present disclosure. Therefore, it should be understood that the foregoing is an illustration of descriptive embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the present disclosure. Therefore, all such embodiments may be included within the scope and spirit of the present disclosure as limited only by the limits of the claims.

Claims

1. A transmitter, comprising: a multiplexer configured to generate a plurality of time-interleaved data signals based on a plurality of input data signals input in parallel and a multi-phase clock signal, the plurality of input data signals each having at least two voltage levels different from each other; control logic configured to generate a plurality of control signals based on the plurality of time-interleaved data signals, at least one control signal of the plurality of control signals having a temporarily boosted voltage level; as well as A voltage-mode driver is configured to generate an output data signal having at least three voltage levels different from one another based on the plurality of control signals.

2. The transmitter according to claim 1, wherein: The plurality of input data signals include a first input data signal, a second input data signal, a third input data signal, and a fourth input data signal, The multi-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal whose phases partially overlap, and The plurality of time-interleaved data signals include a first time-interleaved data signal and a second time-interleaved data signal.

3. The transmitter according to claim 2, wherein The multiplexer comprises: a first transistor connected between a first input node receiving the first input data signal and a first output node providing the first time-interleaved data signal, and having a gate electrode receiving the first clock signal; a second transistor connected between a second input node receiving the second input data signal and a second output node providing the second time-interleaved data signal, and having a gate electrode receiving the second clock signal; a third transistor connected between a third input node receiving the third input data signal and the first output node and having a gate electrode receiving the third clock signal; and A fourth transistor is connected between a fourth input node receiving the fourth input data signal and the second output node, and has a gate electrode receiving the fourth clock signal.

4. The transmitter according to claim 2, wherein: the plurality of control signals include at least one pull-down control signal having a voltage level that is not temporarily boosted and a plurality of pull-up control signals having a voltage level that is temporarily boosted, The at least one pull-down control signal includes a first pull-down control signal, and The plurality of pull-up control signals include a first pull-up control signal and a second pull-up control signal.

5. The transmitter according to claim 4, wherein The control logic includes: a first NAND gate configured to perform a NAND operation on the first time-interleaved data signal and the second time-interleaved data signal; a NOR gate configured to generate the first pull-down control signal by performing a NOR operation on the first time-interleaved data signal and the second time-interleaved data signal; an inverter configured to invert an output of the NOR gate; a second NAND gate configured to perform a NAND operation on an output of the first NAND gate and an output of the inverter; a first boost circuit configured to generate the first pull-up control signal based on an output of the first NAND gate; and A second boost circuit is configured to generate the second pull-up control signal based on an output of the second NAND gate.

6. The transmitter according to claim 5, wherein At least one of the first boost circuit or the second boost circuit comprises: a pulse generator connected to an input node receiving an output of the corresponding NAND gate and configured to generate a pulse signal based on the output of the corresponding NAND gate; a first transistor connected between a first power supply voltage and a first node and having a gate electrode receiving the pulse signal; a capacitor connected between the gate electrode of the first transistor and the first node; a second transistor connected between the first node and an output node providing a corresponding pull-up control signal and having a gate electrode connected to the input node; and A third transistor is connected between the output node and a ground voltage and has a gate electrode connected to the input node.

7. The transmitter according to claim 6, wherein: When the voltage at the input node has a high level, the capacitor is precharged based on the first power supply voltage, and When the voltage at the input node transitions from the high level to the low level, the output node is boosted for a predetermined time interval based on the charge precharged in the capacitor.

8. The transmitter according to claim 4, wherein The at least three voltage levels of the output data signal include a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level.

9. The transmitter according to claim 8, wherein The voltage mode driver comprises: a first transistor connected between an output node providing the output data signal and a ground voltage having the first voltage level and having a gate electrode receiving the first pull-down control signal; a second transistor connected between the first power supply voltage having the third voltage level and the output node and having a gate electrode receiving the second pull-up control signal; and a third transistor connected between a second power supply voltage having the second voltage level and the output node and having a gate electrode receiving the first pull-up control signal; 10. The transmitter according to claim 1, wherein: the plurality of input data signals having a first data rate, The plurality of time-interleaved data signals have a second data rate higher than the first data rate, and The plurality of control signals and the output data signal have a third data rate higher than the second data rate.

11. The transmitter according to claim 1 , wherein: The plurality of input data signals are binary signals having two voltage levels different from each other, The plurality of output data signals are duobinary signals having three voltage levels different from each other, The voltage mode driver is configured to sequentially output a sum of two adjacent input data signals among the plurality of input data signals as the output data signal.

12. A receiver, comprising: a first flip-flop configured to receive an input data signal having at least three voltage levels different from each other, a first clock signal, a first reference voltage, and a first selection signal, form a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal, generate a first output data signal based on the input data signal, the first clock signal, the first reference voltage, and the first selection signal, and provide the first output data signal as a second selection signal, the first output data signal being a signal having at least two voltage levels different from each other; as well as a second flip-flop configured to receive the input data signal, a second clock signal different from the first clock signal, the first reference voltage, and the second selection signal, generate a second output data signal based on the input data signal, the second clock signal, the first reference voltage, and the second selection signal, and provide the second output data signal as the first selection signal, the second output data signal being a signal having at least two voltage levels different from each other.

13. The receiver according to claim 12, wherein The first trigger includes: a first circuit configured to generate a first data signal and a second data signal based on a power supply voltage, the input data signal, the first clock signal, the first reference voltage, and the first selection signal, and including a first structure configured to form the second reference voltage and a second structure configured to boost the first data signal and the second data signal; a second circuit configured to generate a third data signal and a fourth data signal based on the power supply voltage, the first and second data signals, and the first clock signal; and An output circuit is configured to generate the first output data signal based on the third data signal and the fourth data signal.

14. The receiver according to claim 13, wherein The first circuit includes: a first transistor, a second transistor, and a third transistor, wherein the first transistor, the second transistor, and the third transistor are connected in parallel between a first node and a first data node providing the first data signal, the first transistor having a gate electrode receiving the power supply voltage, the second transistor having a gate electrode receiving the input data signal, and the third transistor having a gate electrode connected to a second data node providing the second data signal; a fourth transistor, a fifth transistor, and a sixth transistor, wherein the fourth transistor, the fifth transistor, and the sixth transistor are connected in parallel between the first node and the second data node, the fourth transistor having a gate electrode connected to the first data node, the fifth transistor having a gate electrode receiving the first reference voltage, and the sixth transistor having a gate electrode receiving the first selection signal; a seventh transistor connected between the power supply voltage and the first node and having a gate electrode receiving the first clock signal; an eighth transistor connected between the first data node and a ground voltage and having a gate electrode receiving the first clock signal; and A ninth transistor is connected between the second data node and the ground voltage and has a gate electrode receiving the first clock signal.

15. The receiver of claim 14, wherein: The sixth transistor corresponds to the first structure and provides a driving current corresponding to the second reference voltage to the second data node based on the first selection signal, and The third transistor and the fourth transistor correspond to the second structure.

16. The receiver according to claim 13, wherein The second circuit includes: a first inverter and a second inverter, wherein the first inverter and the second inverter are configured to receive the first data signal and the second data signal, respectively; a first transistor having a gate electrode connected to a first data node providing the third data signal and connected between the first node and a second data node providing the fourth data signal; a second transistor and a third transistor, the second transistor and the third transistor being connected in parallel between the second data node and a ground voltage, the second transistor having a gate electrode receiving the output of the first inverter, the third transistor having a gate electrode connected to the first data node; a fourth transistor connected between the first node and the first data node and having a gate electrode connected to the second data node; a fifth transistor and a sixth transistor connected in parallel between the first data node and the ground voltage, the fifth transistor having a gate electrode connected to the second data node, the sixth transistor having a gate electrode receiving an output of the second inverter; and A seventh transistor is connected between the power supply voltage and the first node and has a gate electrode receiving the first clock signal.

17. The receiver according to claim 13, wherein The output circuit includes: a first inverter and a second inverter, the first inverter and the second inverter being configured to receive the third data signal and the fourth data signal, respectively; and An SR NAND latch is configured to generate the first output data signal and an inverted first output data signal based on an output of the first inverter and an output of the second inverter.

18. The receiver of claim 12, wherein: The input data signal is a duobinary signal having three voltage levels different from each other, The three voltage levels of the input data signal include a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level, The voltage level of the first reference voltage is between the second voltage level and the third voltage level, and the voltage level of the second reference voltage is between the first voltage level and the second voltage level, The first output data signal is a binary signal having two voltage levels different from each other, and The two voltage levels of the first output data signal include the first voltage level and a fourth voltage level higher than the third voltage level.

19. A storage system, comprising: a transmitter configured to output write data to be stored in a memory device or read data to be retrieved from the memory device; a channel, wherein the channel is configured to transmit the write data or the read data; as well as a receiver configured to receive the write data or the read data, Wherein, the transmitter includes: a multiplexer configured to generate a plurality of time-interleaved data signals based on a plurality of input data signals input in parallel and a multi-phase clock signal, the plurality of input data signals each having at least two voltage levels different from each other; control logic configured to generate a plurality of control signals based on the plurality of time-interleaved data signals, at least one control signal of the plurality of control signals having a temporarily boosted voltage level; and a voltage-mode driver configured to generate an output data signal based on the plurality of control signals, the output data signal having at least three voltage levels different from each other, Wherein, the receiver includes: a first flip-flop configured to receive the output data signal, a first clock signal, a first reference voltage, and a first selection signal, form a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal, generate a first data signal based on the output data signal, the first clock signal, the first reference voltage, and the first selection signal, and provide the first data signal as a second selection signal, the first data signal being at least one input data signal of the plurality of input data signals having at least two voltage levels different from each other; and a second flip-flop configured to receive the output data signal, a second clock signal, the first reference voltage, and the second selection signal, generate a second data signal based on the output data signal, the second clock signal, the first reference voltage, and the second selection signal, and provide the second data signal as the first selection signal, wherein the second data signal is at least one input data signal among the plurality of input data signals having at least two voltage levels different from each other, and the second clock signal is different from the first clock signal. The plurality of input data signals, the output data signal, the first data signal, and the second data signal correspond to the write data or the read data.

20. The storage system of claim 19, wherein: The memory device comprises a high bandwidth memory device, The channel includes at least one through silicon via.

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