Input sensing devices and display devices

Abstract

This disclosure relates to an input device and a display device. The input sensing device includes: a sensor pixel, initialized in response to a reset signal provided via a reset line, and outputting a sensing signal to a readout line in response to a scan signal provided via a scan line; a controller, generating at least one start signal and a clock signal; a selector, selectively providing at least one start signal and a clock signal to a first control line or a second control line; a reset driver, connected to the first control line, and supplying a reset signal to at least some of the reset lines based on at least one start signal and a clock signal provided via the first control line; and a scan driver, connected to the second control line, and supplying a scan signal to at least some of the scan lines based on at least one start signal and a clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0102731, filed on August 14, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some exemplary embodiments of the present invention relate to an input sensing device and a display device including said input sensing device. Background Technology

[0004] Recently, with the widespread use of display devices such as smartphones and tablet PCs in various fields, biometric authentication methods using user fingerprints have become widely adopted. To provide fingerprint sensing functionality, fingerprint sensors can be provided in the form of being embedded in or attached to the upper and / or lower portion of the display device. This integration of a fingerprint sensor into a display device is known as in-display fingerprint scanning (FoD).

[0005] For example, a FoD can be configured with a light-sensing sensor. A light-sensing FoD can use light-emitting elements provided in the pixels as a light source and can include a light sensor array. The light sensor array can be implemented as, for example, a CMOS image sensor (CIS).

[0006] As FoDs become larger, they include more light sensors, and the input detector (or readout IC) requires more channels (or signal lines) to drive the light sensors and receive sensing signals from them.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0008] Some exemplary embodiments of the present invention include an input sensing device and a display device including the input sensing device, which can reduce the number of channels (or signal lines) of the input detector and reduce manufacturing costs.

[0009] The embodiments of the present invention are not limited to the features described above, and various extensions can be made without departing from the spirit and scope of the embodiments of the present invention.

[0010] Some exemplary embodiments of the present invention include an input sensing device comprising: a reset line; a scan line; a readout line; sensor pixels connected to the reset line, the scan line, and the readout line, wherein each of the sensor pixels is initialized in response to a reset signal provided by a corresponding reset line in the reset line, and outputs a sensing signal to a corresponding readout line in the readout line in response to a scan signal provided by a corresponding scan line in the scan line; a controller that generates at least one start signal and a clock signal; a selector that selectively provides at least one start signal and a clock signal to a first control line or a second control line; a reset driver connected to the first control line and supplying a reset signal to at least some of the reset lines based on at least one start signal and a clock signal provided by the first control line; and a scan driver connected to the second control line and supplying a scan signal to at least some of the scan lines based on at least one start signal and a clock signal provided by the second control line.

[0011] According to some example embodiments, the controller can output at least one start signal and a clock signal to a reference control line; and the selector can include: a first switch unit connected between the reference control line and the first control line, and connected to the reference control line and the first control line respectively in response to a reset enable signal; and a second switch unit connected between the reference control line and the second control line, and connected to the reference control line and the second control line respectively in response to a scan enable signal.

[0012] According to some example embodiments, each of the sensor pixels can be divided into multiple unit blocks including at least one sensor pixel, and the reset driver can include sub-reset drivers corresponding to the unit blocks respectively, wherein each of the sub-reset drivers can provide a corresponding reset signal in the reset signal to the corresponding unit block in the unit block, and the controller can generate a start signal corresponding to the sub-reset driver respectively.

[0013] According to some example embodiments, each of the sub-reset drivers may include a stage that generates a corresponding reset signal while sequentially shifting a corresponding start signal in a start signal based on a clock signal.

[0014] According to some example embodiments, a scan driver may include sub-scan drivers that correspond to cell blocks respectively, wherein each of the sub-scan drivers may provide a corresponding scan signal in the scan signal to a corresponding cell block in the cell block.

[0015] According to some example embodiments, the sensing period may include a first period, a second period, and a third period classified based on the periodic variation of a clock signal, and in the first period: the controller may simultaneously (or concurrently) generate a start signal of a pulse having a conduction voltage level; the selector may provide the start signal and the clock signal to a first control line; and the sub-reset driver may simultaneously (or concurrently) output at least some of the reset signals in response to the start signal.

[0016] According to some example embodiments, during a first time period, the controller may generate a start signal, wherein each of the start signals may have multiple pulses of a conduction voltage level.

[0017] According to some example embodiments, during the second time period, the controller may sequentially generate some of the start signals among the start signals; and during the second time period, the selector may provide some of the start signals and the clock signal among the start signals to the first control line.

[0018] According to some example embodiments, the controller may set the period of the clock signal in the second time period to be greater than the period of the clock signal in the first time period.

[0019] According to some example embodiments, the input sensing device may further include: a multiplexer connecting k readout lines (where k is an integer of 2 or greater) to an output line, and sequentially connecting the k readout lines to the output line.

[0020] According to some example embodiments, during the third time period, the selector can provide a start signal and a clock signal to the second control line.

[0021] According to some example embodiments, the clock signal may include a first clock signal and a second clock signal; the third time period may include a first sub-time period and a second sub-time period that are repeated sequentially; in the first sub-time period, the controller may generate a first clock signal with pulses having an on-state voltage level and may maintain a second clock signal at an off-state voltage level; and in the second sub-time period, the controller may generate a second clock signal with pulses having an on-state voltage level and may maintain a first clock signal at an off-state voltage level.

[0022] According to some example embodiments, the number of pulses of the conduction voltage level in the first sub-period can be k.

[0023] According to some example embodiments, the repetition period of the first sub-time period and the second sub-time period may be the same as the period of the clock signal in the second time period.

[0024] According to some example embodiments, each of the sensor pixels may include: a photodiode; a first transistor including a first electrode connected to a first power line, a second electrode, and a gate electrode connected to an electrode of the photodiode; a second transistor including a first electrode connected to a second electrode of the first transistor, a second electrode connected to a corresponding readout line in the readout line, and a gate electrode connected to a corresponding scan line in the scan line; a third transistor including a first electrode connected to a second power line, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a corresponding reset line in the reset line; and a capacitor connected in parallel to the photodiode.

[0025] According to some exemplary embodiments of the present invention, a display device is provided, comprising: a display panel for displaying an image; and an input sensing device positioned on a surface of the display panel. The input sensing device may include: a reset line; a scan line; a readout line; sensor pixels connected to the reset line, scan line, and readout line, wherein each of the sensor pixels is initialized in response to a reset signal provided by a corresponding reset line in the reset line, senses light emitted from the display panel and reflected by a target object to generate a sensing signal, and outputs the sensing signal to a corresponding readout line in response to a scan signal provided by a corresponding scan line in the scan line; a controller that generates at least one start signal and a clock signal; a selector that selectively provides at least one start signal and a clock signal to a first control line or a second control line; a reset driver connected to the first control line and supplying a reset signal to at least some of the reset lines based on at least one start signal and a clock signal provided by the first control line; and a scan driver connected to the second control line and supplying a scan signal to at least some of the scan lines based on at least one start signal and a clock signal provided by the second control line.

[0026] According to some example embodiments, the display panel can emit light in the area touched by the target object based on touch position information provided from the outside, and the input sensing device can be locally driven corresponding to the area touched by the target object.

[0027] According to some example embodiments, each of the sensor pixels can be divided into multiple unit blocks including at least one sensor pixel; the reset driver can include sub-reset drivers corresponding to the unit blocks respectively, wherein each of the sub-reset drivers can provide a corresponding reset signal in the reset signal to the corresponding unit block in the unit block; and the controller can generate start signals corresponding to the sub-reset drivers respectively.

[0028] According to some example embodiments, the sensing period may include a first period, a second period, and a third period classified based on the periodic variation of a clock signal, and in the first period: the controller may simultaneously (or concurrently) generate a start signal of a pulse having a conduction voltage level; the selector may provide the start signal and the clock signal to a first control line; and the sub-reset driver may simultaneously (or concurrently) output at least some of the reset signals in response to the start signal.

[0029] According to some example embodiments, during the second time period, the controller may sequentially generate some of the start signals, and during the second time period, the selector may provide some of the start signals and clock signals to the first control line.

[0030] According to some example embodiments, an input sensing device and a display device including an input sensing device according to embodiments of the present invention can selectively provide a start signal and a clock signal to a reset driver or a scan driver by using a selector. Therefore, the number of channels / pads / signal lines for the input detector used to output or transmit the start signal and clock signal can be reduced, and the area and manufacturing cost of the input detector can be reduced.

[0031] According to some example embodiments, the input sensing device and display device may further include: a multiplexer positioned between the sensor pixel and the input detector to sequentially provide the sensing signal of the sensor pixel to the input detector, and a scan signal having multiple pulses can be provided to a scan line in response to the timing of the switches in the multiplexer being operated respectively. Therefore, the introduction of noise into the sensing signal of the sensor pixel can be prevented or reduced by the on / off state of the switches in the multiplexer, and the accuracy of fingerprint sensing can be improved.

[0032] However, the embodiments of the present invention are not limited to the features described above, and various extensions can be made without departing from the spirit and scope of the embodiments of the present invention. Attached Figure Description

[0033] Figure 1A This is a block diagram of a display device according to some exemplary embodiments of the present invention.

[0034] Figure 1B This is a block diagram of a display device according to some exemplary embodiments of the present invention.

[0035] Figure 2A These are some exemplary embodiments of the present invention. Figure 1A A cross-sectional view of an example display device.

[0036] Figure 2B These are some exemplary embodiments of the present invention. Figure 1A A cross-sectional view of an example display device.

[0037] Figure 3 This includes some example embodiments of the present invention. Figure 1A A block diagram of an example of an input sensing device in a display device.

[0038] Figure 4 This includes some example embodiments of the present invention. Figure 3 A circuit diagram of an example sensor pixel in an input sensing device.

[0039] Figure 5A These are some exemplary embodiments of the present invention. Figure 3 A block diagram of an example input sensing device.

[0040] Figure 5B This includes some example embodiments of the present invention. Figure 5A A circuit diagram of an example multiplexer in an input sensing device.

[0041] Figure 6 This includes some example embodiments of the present invention. Figure 3 A top plan view of an example of a light sensor in an input sensing device.

[0042] Figure 7 This includes some example embodiments of the present invention. Figure 3 A block diagram of an example of a horizontal driver in an input sensing device.

[0043] Figure 8 This includes some example embodiments of the present invention. Figure 7 A block diagram illustrating an example of a sub-drive in a horizontal drive.

[0044] Figure 9 This includes some example embodiments of the present invention. Figure 8 A circuit diagram of an example stage in a sub-driver.

[0045] Figure 10 This includes some example embodiments of the present invention. Figure 3 A circuit diagram of an example selector in an input sensing device.

[0046] Figure 11 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform diagram of the operation of the input sensing device.

[0047] Figure 12 This is for explaining some exemplary embodiments according to the present invention. Figure 5AThe waveform of the operation of the input sensing device during the first time period.

[0048] Figure 13 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform diagram of the operation of the input sensing device in the second time period.

[0049] Figure 14 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform diagram of the operation of the input sensing device in the third time period. Detailed Implementation

[0050] A number of exemplary embodiments of the invention will be described more fully below with reference to the accompanying drawings, in which embodiments of the invention are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the embodiments according to this disclosure.

[0051] To more clearly describe various aspects of the embodiments according to the present invention, descriptions of elements or components that are not essential for enabling those skilled in the art to understand the invention may be omitted, and identical or similar constituent elements throughout the specification are indicated by the same reference numerals. Therefore, the reference numerals mentioned above may be used in other figures.

[0052] Furthermore, in the accompanying drawings, the dimensions and thicknesses of each element are shown arbitrarily for ease of description, and the embodiments according to this disclosure are not necessarily limited to those shown in the drawings. In the drawings, the thicknesses of layers, films, panels, areas, etc., may be exaggerated for clarity.

[0053] Figure 1A This is a block diagram of a display device according to some exemplary embodiments of the present invention. Figure 1B This is a block diagram of a display device according to some exemplary embodiments of the present invention.

[0054] For convenience, Figure 1A and Figure 1B The display panel 100 and driver 200 are shown to be separate, but embodiments of the invention are not limited thereto. For example, all or part of the driver 200 may be integrally implemented as a component (e.g., a single component) on the display panel 100.

[0055] Reference Figure 1A and Figure 1B The display device 1000 may include a display panel 100 and a driver 200. The driver 200 may include a panel driver 210 and a fingerprint detector 220 (or an input detector).

[0056] All or at least part of the display device 1000 may be flexible.

[0057] Display panel 100 includes a display area AA and a non-display area NA. The display area AA is an area in which a plurality of pixels PXL (pixels PXL are also referred to as subpixels) are provided, and may be referred to as an active area. According to some example embodiments, each of the pixels PXL may include at least one light-emitting element. Display device 1000 displays an image in the display area AA by driving the pixels PXL in response to image data input from an external source (e.g., from an external data source).

[0058] According to some example embodiments, the display area AA may include a fingerprint sensing area FSA. The fingerprint sensing area FSA may include at least some of the pixels PXL provided in the display area AA.

[0059] According to some example embodiments, such as Figure 1A As shown, the entire display area AA can be set as the fingerprint sensing area FSA. In this case, when fingerprint sensing is performed, the fingerprint sensing operation can be performed only on the part that is actually touched by the user.

[0060] According to some example embodiments, such as Figure 1B As shown, at least a portion of the display area AA can be set as the fingerprint sensing area FSA.

[0061] at the same time, Figure 1B An example is shown in which only one fingerprint sensing area (FSA) is formed in the display area AA, but the embodiments of the present invention are not limited thereto. For example, multiple fingerprint sensing areas (FSAs) may be arranged regularly (e.g., in a preset or predetermined pattern) or irregularly in the display area AA.

[0062] also, Figure 1A and Figure 1B An example is shown in which the fingerprint sensing region FSA is formed in at least a portion of the display region AA, but embodiments of the invention are not limited thereto. That is, according to some example embodiments, the display region AA and the fingerprint sensing region FSA may be provided to overlap each other only in at least a portion of the display region AA and the fingerprint sensing region FSA.

[0063] The non-display area NA is the area surrounding the display area AA and can be referred to as the non-active area. For example, the non-display area NA can include wiring areas, pad areas, and various dummy areas.

[0064] According to some example embodiments, the display device 1000 may further include a plurality of sensor pixels SPXL provided in the fingerprint sensing area FSA. The sensor pixels SPXL may be included in a light sensor PS for sensing light. According to some example embodiments, when light emitted from a light source (or pixel PXL) provided in the display device 1000 is reflected by a user's finger, the sensor pixels SPXL can output a corresponding electrical signal (e.g., a voltage signal) by sensing the reflected light. The electrical signal can be transmitted to a driver 200 (e.g., a fingerprint detector 220) for fingerprint sensing. In the following description, although embodiments of the present invention are used as examples with respect to the sensor pixels SPXL for fingerprint sensing, the sensor pixels SPXL can be used to perform various functions such as those found in touch sensors or scanners.

[0065] When sensor pixel SPXL is positioned within the fingerprint sensing area FSA in a planar view, sensor pixel SPXL may overlap with pixel PXL or may be arranged around pixel PXL. For example, some or all of sensor pixels SPXL may overlap with pixel PXL or may be positioned between pixels PXL. According to some example embodiments, sensor pixels SPXL and pixel PXL may have the same or different sizes. The relative size and arrangement between sensor pixels SPXL and pixel PXL are not particularly limited.

[0066] When sensor pixel SPXL is arranged adjacent to or at least partially overlaps with pixel PXL, sensor pixel SPXL can use the light-emitting element provided in pixel PXL as a light source. According to some example embodiments, sensor pixel SPXL, together with the light-emitting element provided in pixel PXL, can constitute a photosensitive fingerprint sensor (or a light sensor PS). Thus, when the fingerprint sensor embedded display device is configured to use pixel PXL as a light source without a separate external light source, the module thickness of the photosensitive fingerprint sensor and the display device having the photosensitive fingerprint sensor can be reduced, and manufacturing costs can be lowered.

[0067] According to some example embodiments, the sensor pixels SPXL may be arranged on another surface (e.g., the rear surface) opposite the surface on which the image is displayed (e.g., the front surface) of the display panel 100 is located. However, embodiments of the present invention are not limited thereto.

[0068] Driver 200 can drive display panel 100. For example, driver 200 can output a data signal DS corresponding to image data to display panel 100. Furthermore, driver 200 can output a drive signal for sensor pixel SPXL and can receive electrical signals (e.g., sensing signal SS) from sensor pixel SPXL. Driver 200 can detect the user's fingerprint type using electrical signals and can detect forged fingerprints.

[0069] According to some example embodiments, the driver 200 may include a panel driver 210 and a fingerprint detector 220. For convenience, Figure 1A and Figure 1B The panel driver 210 and the fingerprint detector 220 are shown to be separate, but embodiments of the invention are not limited thereto. For example, at least a portion of the fingerprint detector 220 may be integrated with the panel driver 210, or may operate in conjunction with the panel driver 210.

[0070] The panel driver 210 can supply a data signal DS corresponding to the image data to the pixels PXL while sequentially scanning the pixels PXL of the display area AA. Therefore, the display panel 100 can display an image corresponding to the image data.

[0071] According to some example embodiments, the panel driver 210 may supply a driving signal for fingerprint sensing to the pixel PXL. The driving signal may be provided such that the pixel PXL emits light and operates as a light source for the sensor pixel SPXL. According to some example embodiments, the driving signal for fingerprint sensing may be provided to the pixel PXL located in a specific area of ​​the display panel 100 (e.g., the pixel PXL located in the fingerprint sensing area FSA, or the pixel PXL corresponding to the area where a user's touch occurs).

[0072] According to some example embodiments, the driving signal for fingerprint sensing can be provided by the fingerprint detector 220.

[0073] The fingerprint detector 220 can transmit a driving signal (e.g., a driving voltage) to the sensor pixel SPXL, and can detect a user's fingerprint based on the electrical signal received from the sensor pixel SPXL. For example, the fingerprint detector 220 can perform fingerprint authentication based on a sensing signal SS supplied from the sensor pixel SPXL (e.g., a light sensor PS). The sensor pixel SPXL (or light sensor PS) and the fingerprint detector 220 can constitute an input sensing device FDD (or a fingerprint sensing device, fingerprint sensor).

[0074] As described above, the display device 1000 includes an input sensing device FDD, and the input sensing device FDD may include a light sensor PS and a fingerprint detector 220 positioned on a surface of the display panel 100, and the input sensing device FDD may use a pixel PXL provided in the display panel 100 as a light source.

[0075] Figure 2A These are some exemplary embodiments of the present invention. Figure 1A A cross-sectional view of an example display device. For example, Figure 2A It shows Figure 1A and Figure 1B An example of a cross-section in the fingerprint sensing area FSA of the display device 1000 shown.

[0076] Reference Figures 1A to 2A The display device 1000 may include a display panel 100 in the fingerprint sensing area FSA and a light sensor PS positioned on one surface of the display panel 100. Furthermore, the display device 1000 may include a substrate SUB and a circuit element layer BPL, a light-emitting element layer LDL, a first passivation layer PTL1, a first adhesive layer ADL1, and a window WIN sequentially arranged on one surface (e.g., the upper surface) of the substrate SUB. Additionally, the display device 1000 may include a second adhesive layer ADL2 and a second passivation layer PTL2 sequentially arranged on another surface (e.g., the lower surface) of the substrate SUB in the fingerprint sensing area FSA.

[0077] The substrate SUB is a base substrate used for the display panel 100 and can be a substantially transparent transmissive substrate. The substrate SUB can be a rigid substrate including glass or tempered glass, or it can be a flexible substrate made of plastic material. However, the material of the substrate SUB is not limited to these, and the substrate SUB can be made of a variety of materials.

[0078] The circuit element layer BPL can be positioned on one surface of the substrate SUB and can include at least one conductive layer. For example, the circuit element layer BPL can include multiple circuit elements forming pixel circuitry for pixel PXL, as well as wiring for supplying various power supplies and signals for driving pixel PXL. In this case, the circuit element layer BPL can include various circuit elements such as at least one transistor and a capacitor, as well as multiple conductive layers for forming wiring connected to the various circuit elements. Furthermore, the circuit element layer BPL can include at least one insulating layer provided between the multiple conductive layers.

[0079] The light-emitting element layer (LDL) can be positioned on one surface of the circuit element layer (BPL). The LDL may include multiple light-emitting elements (LDs) connected to the BPL via contact holes or the like. According to some example embodiments, at least one of multiple light-emitting element LDs may be provided for each pixel (PXL). For example, the light-emitting element LD may be composed of an organic light-emitting diode or an inorganic light-emitting diode such as a micro-light-emitting diode or a quantum dot light-emitting diode. Furthermore, the light-emitting element LD may be a light-emitting element made of a composite of organic and inorganic materials. Additionally, each pixel (PXL) may include a single light-emitting element LD, but according to some example embodiments, each pixel (PXL) may include multiple light-emitting element LDs, and the multiple light-emitting element LDs may be connected in series, in parallel, or in a series-parallel connection.

[0080] Each of the pixels PXL may include a circuit element located in the circuit element layer BPL and at least one light-emitting element LD located in the light-emitting element layer LDL on the circuit element layer BPL.

[0081] The first passivation layer PTL1 can be positioned on the light-emitting element layer LDL to cover the display area AA. The first passivation layer PTL1 may include a sealing member such as a thin-film encapsulation (TFE) layer or an encapsulation substrate, and may additionally include a passivation film in addition to the sealing member.

[0082] The first adhesive layer ADL1 is positioned between the first passivation layer PTL1 and the window WIN to bond the first passivation layer PTL1 and the window WIN. The first adhesive layer ADL1 may include a transparent adhesive such as optically clear adhesive (OCA) and may include various adhesive materials.

[0083] The window WIN may be a protective member positioned at the uppermost part of a module of a display device 1000 including a display panel 100, and may be a substantially transparent transmissive substrate. The window WIN may have a multilayer structure selected from glass substrates, plastic films, and plastic substrates. The window WIN may include a rigid or flexible substrate, and the materials included in the window WIN are not particularly limited.

[0084] According to some example embodiments, the display device 1000 may also include a polarizing plate, an anti-reflective layer, and / or a touch sensor layer (touch electrode layer). For example, the display device 1000 may also include a polarizing plate and / or a touch sensor layer positioned between the first passivation layer PTL1 and the window WIN.

[0085] The touch sensor layer may include multiple sensing electrodes (or sensing units). In this case, refer to... Figure 1AThe described driver 200 can sense the presence or absence of touch input and the location (or coordinates) of touch input based on the capacitance change between sensing electrodes.

[0086] The second passivation layer PTL2 can be positioned on another surface of the substrate SUB. The second passivation layer PTL2 can be bonded to the substrate SUB via the second adhesive layer ADL2.

[0087] The second adhesive layer ADL2 can firmly bond (or attach) to the substrate SUB and the second passivation layer PTL2. The second adhesive layer ADL2 may include a transparent adhesive such as OCA. The second adhesive layer ADL2 may include a pressure-sensitive adhesive (PSA), which acts as an adhesive material when pressure is applied to it for adhesion to the adhesive surface.

[0088] The second passivation layer PTL2 prevents oxygen and moisture from being introduced from the outside and can be formed as a single layer or multiple layers. The second passivation layer PTL2 can be formed in the form of a film to further ensure the flexibility of the display panel 100. The second passivation layer PTL2 can be bonded to the light sensor PS by another adhesive layer including a transparent adhesive such as OCA.

[0089] The light sensor PS is attached to the back side (e.g., rear side) of the display panel 100 by an adhesive or the like so as to overlap with at least one area of ​​the display panel 100. For example, the light sensor PS may be arranged to overlap with the display panel 100 in the fingerprint sensing area FSA. The light sensor PS may include a plurality of sensor pixels SPXL dispersed at a predetermined resolution and / or interval.

[0090] According to some example embodiments, an optical system can be provided on the optical sensor PS to provide an optical path by converging and guiding light to the optical sensor PS. The width of the light transmission portion guiding the light in the optical system can be determined by considering sensing accuracy and light conversion efficiency. The optical system can improve the convergence rate of light incident on the optical sensor PS. According to some example embodiments, the optical system can be formed of optical fibers and silicon, etc.

[0091] The sensor pixels SPXL can have an appropriate number, size, and arrangement so that an identifiable fingerprint image can be generated from the electrical signals output by the sensor pixels SPXL. The spacing between the sensor pixels SPXL can be densely arranged so that light reflected from the target object (e.g., a fingerprint) can be incident on at least two adjacent sensor pixels SPXL.

[0092] Sensor pixels SPXL can sense external light to output corresponding electrical signals, such as voltage signals. Due to the valleys and ridges formed on a user's finger (or, palm prints and dermal patterns formed on the palm and skin), the reflected light received by each sensor pixel SPXL can have optical properties (e.g., frequency, wavelength, size, etc.). Therefore, each of the sensor pixels SPXL can output a sensing signal SS with different electrical properties corresponding to the optical properties of the reflected light.

[0093] According to some example embodiments, the sensing signal SS output by the sensor pixel SPXL can be converted into image data by the fingerprint detector 220 for use in user fingerprint recognition (that is, fingerprint authentication).

[0094] Figure 2B These are some exemplary embodiments of the present invention. Figure 1A A cross-sectional view of an example display device. For example, Figure 2B It shows Figure 1A and Figure 1B An example of a cross-section in the fingerprint sensing area FSA of the display device 1000 shown.

[0095] refer to Figure 1A , Figure 2A and Figure 2B , Figure 2B An example embodiment utilizing a light-blocking layer (PHL) including a pinhole PIH as an optical system is shown. The light-blocking layer (PHL) can be positioned within the display panel 100 or between the display panel 100 and the sensor pixel SPXL to block a portion of the light incident on the sensor pixel SPXL. For example, a portion of the light incident on the light-blocking layer (PHL) can be blocked, and the remaining portion of the light incident on the light-blocking layer (PHL) can pass through the pinhole PIH to reach the sensor pixel SPXL below the light-blocking layer (PHL). The pinhole PIH can operate as an optical system and can be used in conjunction with other optical systems.

[0096] A pinhole PIH can refer to an optical hole and can be a type of light transmission hole. For example, a pinhole PIH can be a light transmission hole with a minimum size (or area) in the path of reflected light passing through the display panel 100 in a diagonal or vertical direction to incident on the sensor pixel SPXL, in which the layers of the display device 1000 overlap each other.

[0097] The pinhole PIH can have a predetermined width, for example, a width ranging from 5 μm to 20 μm. In this way, as the pinhole PIH moves away from the light-blocking layer PHL (that is, as the pinhole PIH moves in the upward or downward direction of the light-blocking layer PHL), the width of the optical opening area to be ensured in each layer of the display device 1000 can be gradually increased.

[0098] The width (or diameter) of the pinhole PIH can be set to approximately 10 times or more the wavelength of the reflected light, for example, approximately 4 μm or 5 μm or more, to prevent or reduce light diffraction. Furthermore, the width of the pinhole PIH can be set to a size sufficient to prevent or reduce image blurring and to more clearly sense the shape of the fingerprint. For example, the width of the pinhole PIH can be set to approximately 15 μm or less. However, embodiments according to the invention are not limited thereto, and the width of the pinhole PIH can vary depending on the wavelength band of the reflected light and / or the thickness of each layer of the module.

[0099] Only the reflected light passing through the pinhole PIH can reach the sensor pixel SPXL of the optical sensor PS. The phase of the light reflected from the fingerprint through the pinhole PIH, which has a very narrow width, can have a phase difference of 180 degrees with the phase of the image formed on the optical sensor PS.

[0100] The sensor pixel SPXL can output a sensing signal SS corresponding to the received reflected light, such as a voltage signal.

[0101] According to some example embodiments, the infrared blocking filter may be further positioned between the optical system (e.g., the light blocking layer PHL) and the light sensor PS, or between the display panel 100 and the optical system.

[0102] However, this is merely an example, and the configuration, arrangement, and driving method of the optical sensor used to detect reflected light from fingerprints are not limited to this. Figure 2A or Figure 2B PS optical sensor.

[0103] at the same time, Figure 2B The image shows a pinhole-type optical sensor, but embodiments of the invention are not limited thereto, and for example, microlens-type or collimator-type optical sensors can be used.

[0104] Figure 3 This includes some example embodiments of the present invention. Figure 1A A block diagram illustrating an example of an input sensing device in a display device. For example, Figure 3 It shows that it includes Figure 1A and Figure 1B An example of an input sensing device FDD in a display device 1000.

[0105] refer to Figures 1A to 3 The input sensing device FDD may include a light sensor PS and a fingerprint detector 220.

[0106] The light sensor PS may include an array of sensor pixels SPXL. According to some example embodiments, the sensor pixels SPXL may be arranged in a two-dimensional array, but embodiments of the invention are not limited thereto. Each sensor pixel SPXL may include a photoelectric device that converts incident light into electrical charge based on the amount of light.

[0107] The fingerprint detector 220 may include a horizontal driver 221, a vertical driver 222, a controller CON, and a selector SWU. The horizontal driver 221 and the selector SWU may be formed on a substrate together with the optical sensor PS, and the vertical driver 222 and the controller CON may be implemented as integrated circuits (e.g., an input detection circuit ROIC) and may be connected to the optical sensor PS, etc., via a flexible circuit board. However, embodiments of the present invention are not limited thereto.

[0108] The horizontal driver 221 may include a reset driver RSDR and a scan driver SCDR. The reset driver RSDR and the scan driver SCDR are connected to the power line PVS, and the required power supply voltage (e.g., a first power supply voltage having an on-state voltage level for turning on the internal transistor, a second power supply voltage having an off-state voltage level for turning off the internal transistor, and a ground voltage) that drives each of the reset driver RSDR and the scan driver SCDR may be applied to the power line PVS.

[0109] The reset driver RSDR can be connected to the sensor pixel SPXL via reset lines RSL1 to RSLn (n is a positive integer). The reset driver RSDR can be configured with a shift register or an address decoder. According to some example embodiments, the reset driver RSDR can apply a reset signal to at least some of the sensor pixels SPXL to initialize the sensor pixels SPXL (e.g., to initialize or discharge the photoelectric conversion charge charging in the sensor pixels SPXL).

[0110] According to some example embodiments, the reset driver RSDR is connected to a first control line CL1, and the reset driver RSDR can supply reset signals to at least some of the reset lines RSL1 to RSLn based on at least one start signal FLMS and a clock signal CLKS provided through the first control line CL1. Here, at least one start signal FLMS and a clock signal CLKS can be provided to the reset driver RSDR from the controller CON through the selector SWU. According to some example embodiments, the reset driver RSDR can output reset signals sequentially in units of sensor pixel rows. However, the reset driver RSDR is not limited to this, and according to some example embodiments, the reset driver RSDR can output at least some of the reset signals simultaneously (or concurrently) to sensor pixels SPXL.

[0111] Please refer to later Figures 7 to 9 This describes the configuration and operation of the reset driver RSDR in more detail.

[0112] The scan driver SCDR can be connected to the sensor pixels SPXL via scan lines SCL1 to SCLn. The scan driver SCDR can be configured with a shift register or an address decoder. According to some example embodiments, the scan driver SCDR can apply scan signals to a selection of sensor pixels SPXL to drive the sensor pixels SPXL. The scan driver SCDR can apply scan signals on a per-sensor pixel-row basis.

[0113] According to some example embodiments, the scan driver SCDR is connected to a second control line CL2, and the scan driver SCDR can supply scan signals to at least some of the scan lines SCL1 to SCLn based on at least one start signal FLMS and a clock signal CLKS provided through the second control line CL2. Here, at least one start signal FLMS and clock signal CLKS can be provided to the scan driver SCDR from the controller CON through the selector SWU.

[0114] Please refer to later Figures 7 to 9 This describes the configuration and operation of the Scan Driver SCDR in more detail.

[0115] The sensor pixel SPXL, selected and driven by the scan driver SCDR, senses light using photoelectric elements provided in the sensor pixel SPXL and outputs an electrical signal (sensing signal SS) corresponding to the sensed light, such as an analog voltage signal. For example, when the sensor pixel SPXL is connected to the i-th reset line RSLi (where i is a positive integer less than or equal to n) and the i-th scan line SCLi (where i is a positive integer less than or equal to n), the sensor pixel SPXL can be initialized in response to a reset signal provided through the i-th reset line RSLi (e.g., the charge generated by the photoelectric element can be initialized), and the sensor pixel SPXL can output an electrical signal in response to a scan signal provided through the i-th scan line SCLi (e.g., an electrical signal generated by the photoelectric element after the reset signal is applied and before the scan signal is applied).

[0116] Please refer to later Figure 4 Describe the more specific configuration and operation of the SPXL sensor pixels.

[0117] The vertical driver 222 can be connected to the sensor pixel SPXL via readout lines RL1 to RLm (where m is a positive integer). For example... Figure 3 As shown, when the sensor pixel SPXL is connected to the j-th readout line RLj (where j is a positive integer less than or equal to m), the vertical driver 222 can receive the electrical signal output from the sensor pixel SPXL through the j-th readout line RLj.

[0118] The vertical driver 222 can process the signal output from the sensor pixel SPXL. For example, the vertical driver 222 can perform correlated double sampling (CDS) processing to remove noise from the received electrical signal. Furthermore, the vertical driver 222 can convert the analog signal received from the sensor pixel SPXL into a digital signal. According to some example embodiments, an analog-to-digital converter is provided for each sensor pixel array, enabling parallel processing of the analog signals received from the sensor pixel array.

[0119] The controller CON can control the horizontal driver 221 and the vertical driver 222.

[0120] According to some example embodiments, the controller CON can generate at least one start signal FLMS and a clock signal CLKS. According to some example embodiments, the controller CON can generate at least one start signal FLMS (e.g., a reset start signal) and a clock signal CLKS (e.g., a reset clock signal) for resetting the RSDR driver in a first time period, and can generate at least one start signal FLMS (e.g., a scan start signal) and a clock signal CLKS (e.g., a scan clock signal) for scanning the SCDR in a second time period different from the first time period.

[0121] According to some example embodiments, the controller CON can generate image data corresponding to the sensing signal SS received from the vertical driver 222, and can process the generated image data. Furthermore, according to some example embodiments, the controller CON can detect fingerprints from the processed image data, or can transmit the detected fingerprints to authentication and / or external systems. However, these are merely examples, and the image data generation and fingerprint detection are not performed by the controller CON, but can be performed by an external host processor.

[0122] The selector SWU can selectively provide at least one start signal FLMS and clock signal CLKS generated by the controller CON to either the first control line CL1 or the second control line CL2. For example... Figure 3 As shown, the selector SWU can receive at least one start signal FLMS and clock signal CLKS through the reference control line CL0, and can provide at least one start signal FLMS and clock signal CLKS to the reset driver RSDR or the scan driver SCDR in response to the enable signal EN.

[0123] As will refer to Figure 3 and Figure 6 As described, in order to allocate sufficient sensing time to the sensor pixels SPXL associated with the large-area light sensor PS, the horizontal driver 221 can divide the light sensor PS into multiple cell blocks to drive only some of the cell blocks locally. For example, the light sensor PS can be divided into 40 cell blocks for a single sensor pixel array. To independently supply reset and scan signals from other cell blocks to one cell block, a start signal FLMS (e.g., reset start signal) for the reset driver RSDR and another start signal FLMS (e.g., scan start signal) for the scan driver SCDR may be required. To supply the reset and scan signals separately to each of the 40 cell blocks, 80 start signals FLMS (e.g., 40 reset start signals and 40 scan start signals) may be required. That is, the number of output channels of the controller CON can be increased, and the number of reference control lines CL0 and pads can be increased accordingly.

[0124] Therefore, the input sensing device FDD sequentially generates at least one start signal FLMS (e.g., 40 reset start signals) for the reset driver RSDR and at least one start signal FLMS (e.g., 40 scan start signals) for the scan driver SCDR via the controller CON, and can selectively provide at least one start signal FLMS (e.g., 40 reset start signals or 40 scan start signals) to the reset driver RSDR and the scan driver SCDR by using a selector SWU. Thus, the number of output channels and pads of the controller CON used to transmit at least one start signal FLMS can be reduced to approximately half (e.g., 80 channels can be reduced to 40 channels), and the area and manufacturing cost of the controller CON and the input sensing circuit ROIC can be reduced.

[0125] For reference Figure 3 As described, the input sensing device FDD can selectively provide at least one start signal FLMS and a clock signal CLKS to the reset driver RSDR and the scan driver SCDR using a selector SWU. Therefore, the number of output channels and pads of the controller CON used to transmit at least one start signal FLMS and clock signal CLKS can be reduced, and the area and manufacturing cost of the controller CON and the input sensing circuit ROIC can be reduced.

[0126] Figure 4 This includes some example embodiments of the present invention. Figure 3 A circuit diagram of an example sensor pixel in an input sensing device. The reset line RSL can be one of the reset lines RSL1 to RSLn, the scan line SCL can be one of the scan lines SCL1 to SCLn, and the readout line RL can be one of the readout lines RL1 to RLm.

[0127] Reference Figure 3 and Figure 4 The sensor pixel SPXL may include a first transistor T1, a second transistor T2, a third transistor T3, a photodiode PD, and a capacitor C_PD. Figure 4 An example is shown in which transistors T1, T2, and T3 are P-type transistors; however, according to some example embodiments, at least some of the transistors may be N-type transistors, and accordingly, the circuit structure of the sensor pixel SPXL may be modified in various ways.

[0128] The anode of the photodiode PD can be connected to the second power supply line PL2, and the cathode of the photodiode PD can be connected to the gate electrode of the first transistor T1. The bias voltage VBIAS used to drive the photodiode PD can be applied to the second power supply line PL2.

[0129] A capacitor C_PD is formed between the gate electrode of the first transistor T1 and the second power supply line PL2, and can be connected in parallel to the photodiode PD. The capacitor C_PD can store the charge converted by the photodiode PD.

[0130] The first electrode of the third transistor T3 can be connected to the first power supply line PL1, the second electrode of the third transistor T3 can be connected to the gate electrode of the first transistor T1, and the gate electrode of the third transistor T3 can be connected to the reset line RSL. Here, the reset voltage VRST can be applied to the first power supply line PL1. The third transistor T3 can electrically connect the first power supply line PL1 and the gate electrode of the first transistor T1 in response to a reset signal applied to the reset line RSL. In this case, the voltage applied to the gate electrode of the first transistor T1 (or the voltage stored in the capacitor C_PD) can be initialized or reset by the reset voltage VRST.

[0131] The first electrode of the first transistor T1 can be connected to the third power supply line PL3, the second electrode of the first transistor T1 can be connected to the first electrode of the second transistor T2, and the gate electrode of the first transistor T1 can be connected to the cathode of the photodiode PD. A common voltage VCOM can be applied to the third power supply line PL3. The first transistor T1 can control the amount of current flowing from the third power supply line PL3 to the second transistor T2 in response to the voltage stored in the capacitor C_PD (that is, the charge converted by photoelectric conversion by the photodiode PD). The first transistor T1 can operate as an amplifier that amplifies and outputs the voltage stored in the capacitor C_PD.

[0132] The first electrode of the second transistor T2 can be connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2 can be connected to the readout line RL, and the gate electrode of the second transistor T2 can be connected to the scan line SCL. The second transistor T2 can form a current flow path between the first transistor T1 (or the third power supply line PL3) and the readout line RL in response to a scan signal applied to the scan line SCL. For example, the second transistor T2 can be turned on in response to a scan signal with a turn-on voltage level, and the second electrode of the first transistor T1 can be electrically connected to the readout line RL. In this case, during the time period from the time the reset signal is applied to the reset line RSL to the time the scan signal is applied to the scan line SCL, an electrical signal corresponding to the voltage stored in the capacitor C_PD (that is, the voltage corresponding to the charge converted by photoelectric conversion in the photodiode PD) can be output to the outside (e.g., vertical driver 222, see...) via the readout line RL. Figure 3 ).

[0133] According to some example embodiments, the structure of the sensor pixel SPXL is not limited to the structure described above, and the sensor pixel SPXL may include, for example, four or more, or two or fewer transistors.

[0134] Figure 5A These are some exemplary embodiments of the present invention. Figure 3 A block diagram of an example input sensing device. Figure 5B This includes some example embodiments of the present invention. Figure 5A A circuit diagram of an example multiplexer in an input sensing device. Figure 5A and Figure 5B The image shows a first sub-multiplexer MUX_S1 included in a multiplexer MUX, and further shows sensor pixels SPXL1 to SPXL4 to illustrate the operation of the first sub-multiplexer MUX_S1.

[0135] refer to Figure 3 , Figure 5A and Figure 5B The fingerprint detector 220 (or input sensing device FDD) may also include a multiplexer MUX and output lines OL1 to OLp (where p is a positive integer less than m).

[0136] The multiplexer MUX can be connected between the readout lines RL1 to RLm and the output lines OL1 to OLp, and the multiplexer MUX can connect some selected from the readout lines RL1 to RLm to the output lines OL1 to OLp. In this case, the vertical driver 222 can be connected to the output lines OL1 to OLp. The multiplexer MUX can be formed on a substrate together with the optical sensor PS, but is not limited to this.

[0137] According to some example embodiments, a multiplexer MUX may include multiple sub-multiplexers. A multiplexer MUX may include a k:1 multiplexer (or sub-multiplexer) that selects and outputs one of k inputs (where k is a positive integer). For example, a multiplexer MUX may include a 4:1 multiplexer that selects and outputs one of four inputs. In this case, p is m / 4, and the multiplexer MUX may include m / 4 sub-multiplexers. However, this is merely an example, and the input-to-output ratio of the sub-multiplexers can be varied.

[0138] like Figure 5A and Figure 5BAs shown, the first sub-multiplexer MUX_S1 can be connected between the first read line RL1, the second read line RL2, the third read line RL3, and the fourth read line RL4, and one of the first read line RL1, the second read line RL2, the third read line RL3, and the fourth read line RL4 can be connected to the first output line OL1.

[0139] like Figure 5B As shown, the first sub-multiplexer MUX_S1 may include a first switch SW_M1, a second switch SW_M2, a third switch SW_M3, and a fourth switch SW_M4. Each of the first switch SW_M1, the second switch SW_M2, the third switch SW_M3, and the fourth switch SW_M4 can be implemented as a transistor, and, for example, each of the first switch SW_M1, the second switch SW_M2, the third switch SW_M3, and the fourth switch SW_M4 can be implemented as a P-type transistor.

[0140] like Figure 5A and Figure 5B As shown, the first switch SW_M1 can be connected between the first read line RL1 and the first output line OL1, and can connect the first read line RL1 and the first output line OL1 in response to the first switch control signal MUX_C1. Here, the first switch control signal MUX_C1 (as well as the second switch control signal MUX_C2, the third switch control signal MUX_C3, and the fourth switch control signal MUX_C4) can be provided by the controller CON, but is not limited thereto.

[0141] For reference, when the first switch control signal MUX_C1 at the conduction voltage level is applied to the first switch SW_M1 (that is, when the first switch SW_M1 is turned on), a scan signal at the conduction voltage level can be applied to the scan line SCL. In this case, in response to the scan signal at the conduction voltage level, the sensing signal of the first sensor pixel SPXL1 can be transmitted from the first sensor pixel SPXL1 to the first output line OL1 through the second transistor T2, the first readout line RL1, and the first switch SW_M1.

[0142] Similar to the first switch SW_M1, the second switch SW_M2 can be connected between the second readout line RL2 and the first output line OL1, and can connect the second readout line RL2 and the first output line OL1 in response to the second switch control signal MUX_C2. When the second switch control signal MUX_C2 at the on-state voltage level is applied to the second switch SW_M2 (that is, when the second switch SW_M2 is on), a scan signal at the on-state voltage level can be applied to the scan line SCL. In this case, in response to the scan signal at the on-state voltage level, the sensing signal of the second sensor pixel SPXL2 can be transmitted from the second sensor pixel SPXL2 to the first output line OL1 through the second transistor T2, the second readout line RL2, and the second switch SW_M2.

[0143] The third switch SW_M3 can be connected between the third readout line RL3 and the first output line OL1, and can connect the third readout line RL3 and the first output line OL1 in response to the third switch control signal MUX_C3. When the third switch control signal MUX_C3 at the conduction voltage level is applied to the third switch SW_M3, a scan signal at the conduction voltage level can be applied to the scan line SCL. In this case, in response to the scan signal at the conduction voltage level, the sensing signal of the third sensor pixel SPXL3 can be transmitted from the third sensor pixel SPXL3 to the first output line OL1 through the second transistor T2, the third readout line RL3, and the third switch SW_M3.

[0144] The fourth switch SW_M4 can be connected between the fourth readout line RL4 and the first output line OL1, and can connect the fourth readout line RL4 and the first output line OL1 in response to the fourth switch control signal MUX_C4. When the fourth switch control signal MUX_C4 at the conduction voltage level is applied to the fourth switch SW_M4, a scan signal at the conduction voltage level can be applied to the scan line SCL. In this case, in response to the scan signal at the conduction voltage level, the sensing signal of the fourth sensor pixel SPXL4 can be transmitted from the fourth sensor pixel SPXL4 to the first output line OL1 through the second transistor T2, the fourth readout line RL4, and the fourth switch SW_M4.

[0145] According to some example embodiments, because the first switch SW_M1, the second switch SW_M2, the third switch SW_M3, and the fourth switch SW_M4 are selectively turned on, that is, because the first switch SW_M1, the second switch SW_M2, the third switch SW_M3, and the fourth switch SW_M4 are turned on at different times, a scan signal (or pulse) of the turn-on voltage level can be applied to the scan line SCL multiple times in response to the first switch SW_M1, the second switch SW_M2, the third switch SW_M3, and the fourth switch SW_M4.

[0146] For reference, it can be assumed that a scan signal with an on-voltage level is applied to scan line SCL only during the period when the first switch control signal MUX_C1 has an on-voltage level, and that a scan signal with an on-voltage level is not applied to scan line SCL during the periods when the second switch control signal MUX_C2, the third switch control signal MUX_C3, and the fourth switch control signal MUX_C4 have on-voltage levels. In this case, the sensing signal of the second sensor pixel SPXL2 can be temporarily stored in the second readout line RL2 and can then be output through the first output line OL1 at the time when the second switch control signal MUX_C2 has an on-voltage level. Although the sensing signal of the second sensor pixel SPXL2 is temporarily stored in the second readout line RL2, noise may be introduced into the sensing signal of the second sensor pixel SPXL2 through parasitic capacitance between adjacent lines and the on / off operation of the second switch SW_M2. Similarly, noise may be introduced into the sensing signals of the third sensor pixel SPXL3 and the fourth sensor pixel SPXL4.

[0147] Therefore, in response to the first switch control signal MUX_C1, the second switch control signal MUX_C2, the third switch control signal MUX_C3, and the fourth switch control signal MUX_C4, when a scan signal (or pulse) of the conduction voltage level is applied multiple times to the scan line SCL, the sensing signal of each of the sensor pixels SPXL1, SPXL2, SPXL3, and SPXL4 can be transmitted to the corresponding readout line and directly output to the first output line OL1 through the corresponding switch. Therefore, noise introduced into each of the sensing signals output from the sensor pixels SPXL1, SPXL2, SPXL3, and SPXL4 can be reduced, and the accuracy of fingerprint sensing can be improved. (See below for further details.) Figure 11 and Figure 14 This describes a configuration in which a scan signal with a conduction voltage level is applied multiple times to the scan line SCL.

[0148] For reference Figure 5A and Figure 5B As described, the input sensing device FDD may also include a multiplexer MUX. In this case, the number of channels and pads for the vertical driver 222 used to receive the sensing signal can be reduced, and the area and manufacturing cost of the vertical driver 222 and the input detection circuit ROIC can be reduced.

[0149] Figure 6 This includes some example embodiments of the present invention. Figure 3 A top plan view of an example of a light sensor in an input sensing device. Figure 6The optical sensor PS can also be applied to Figure 5A The input sensing device FDD.

[0150] Reference Figure 3 , Figure 5A and Figure 6 A light sensor PS (or sensor pixel SPXL) can be divided into unit blocks UB comprising at least one sensor pixel SPXL. Unit blocks UB (or unit blocks UB included in a row) can be driven independently of each other. For example, each unit block UB may include 32×32 sensor pixels SPXL. The number of sensor pixels SPXL included in each unit block UB is not limited to this, and, for example, the number of sensor pixels SPXL included in each unit block UB may be greater than or less than 32×32. For better understanding and ease of description, it is assumed below that each unit block UB comprises 32×32 sensor pixels SPXL.

[0151] The unit sensing block USB can be defined as part of an optical sensor PS that must be activated to sense fingerprints corresponding to the size of the user's fingerprint FP (or finger) when touch input occurs. For example, the unit sensing block USB can be set to a size of approximately 1cm × 1cm, approximately 2cm × 2cm, etc., and can include 4×4 unit blocks UB (or 128×128 sensor pixels SPXL). The number of unit blocks UB included in each of the unit sensing blocks USB is not limited to this, and, for example, the number of unit blocks UB included in each of the unit sensing blocks USB can be greater than or less than 4×4. Meanwhile, the remaining part of the optical sensor PS other than the unit sensing block USB may not be operational.

[0152] The unit sensing block USB can be variably set based on the point where the touch input occurs (e.g., the center point of the touch input). That is, the position of the unit sensing block USB and the position of the unit block UB included in the unit sensing block USB can be set differently each time a touch input occurs.

[0153] For reference Figure 5A and Figure 6 As described, the optical sensor PS can operate independently for each unit block UB. For individual driving of each unit block UB, the horizontal driver 221 should be able to provide a reset signal and a scan signal for each unit block UB, and for this, please refer to... Figure 7 Describe the horizontal driver 221.

[0154] Figure 7 This includes some example embodiments of the present invention. Figure 3 A block diagram of an example horizontal driver in an input sensing device. Figure 7 The image further illustrates the optical sensor PS to illustrate the operation of the horizontal driver 221. Figure 7 The horizontal driver 221 can also be applied to Figure 5A The input sensing device FDD.

[0155] Reference Figure 3 , Figure 5A , Figure 6 and Figure 7 The horizontal driver 221 may include a reset driver RSDR and a scan driver SCDR.

[0156] The reset driver RSDR can include sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4, and RSDR_S5 corresponding to the unit blocks UB11, UB21, UB31, UB41, and UB51 of the optical sensor PS. That is, unit blocks UB11, UB21, UB31, UB41, and UB51 are the smallest units used to configure the sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4, and RSDR_S5, and the sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4, and RSDR_S5 are driven independently of each other. Meanwhile, the above references... Figure 6 The described unit sensing block USB is a necessary unit for fingerprint sensing.

[0157] The reset driver RSDR can be connected to the reset start signal lines FLM_RSL1, FLM_RSL2, FLM_RSL3, FLM_RSL4, and FLM_RSL5, and the reset clock lines CLKL1_RS and CLKL2_RS, for independently driving the sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4, and RSDR_S5. The reset start signal lines FLM_RSL1, FLM_RSL2, FLM_RSL3, FLM_RSL4, and FLM_RSL5, and the reset clock lines CLKL1_RS and CLKL2_RS can be included in the first control line CL1 (see...). Figure 3 The reset start signal can be applied independently to the reset start signal lines FLM_RSL1, FLM_RSL2, FLM_RSL3, FLM_RSL4, and FLM_RSL5. A first reset clock signal and a second reset clock signal are applied to the reset clock lines CLKL1_RS and CLKL2_RS, respectively. For example, the second reset clock signal may have a waveform that inverts the first reset clock signal, or it may have a waveform that delays the first reset clock signal by 180 degrees or by a specific time.

[0158] The first sub-reset driver RSDR_S1 can be connected to the first reset start signal line FLM_RSL1. It can generate a reset signal corresponding to the first reset start signal (that is, the reset start signal applied to the first reset start signal line FLM_RSL1) using a reset clock signal, and can provide the reset signal to the eleventh unit block UB11. For example, the first sub-reset driver RSDR_S1 can sequentially generate the reset signal by sequentially shifting the first reset start signal using a reset clock signal. Figure 7 As shown, the first sub-reset driver RSDR_S1 can be connected to the first reset line RSL1 to the thirty-second reset line RSL32 corresponding to the eleventh unit block UB11, and can sequentially provide the reset signals (e.g., the first reset start signal to the thirty-second reset start signal) corresponding to the first reset start signal to the first reset line RSL1 to the thirty-second reset line RSL32.

[0159] Similar to the first sub-reset driver RSDR_S1, the second sub-reset driver RSDR_S2 can be connected to the second reset start signal line FLM_RSL2. It can generate a reset signal corresponding to the second reset start signal (that is, the reset start signal applied to the second reset start signal line FLM_RSL2) using a reset clock signal, and can provide the reset signal to the twenty-first unit block UB21. Figure 7 As shown, the second sub-reset driver RSDR_S2 can be connected to the 33rd reset line RSL33 to the 64th reset line RSL64 corresponding to the 21st unit block UB21, and can sequentially provide the reset signal (e.g., the 33rd reset start signal to the 64th reset start signal) corresponding to the second reset start signal to the 33rd reset line RSL33 to the 64th reset line RSL64.

[0160] The third sub-reset driver RSDR_S3 can be connected to the third reset start signal line FLM_RSL3. It can generate a reset signal corresponding to the third reset start signal (that is, the reset start signal applied to the third reset start signal line FLM_RSL3) by using a reset clock signal, and can provide the reset signal to the sixty-fifth reset line RSL65 to the ninety-sixth reset line RSL96 corresponding to the thirty-first unit block UB31.

[0161] The fourth sub-reset driver RSDR_S4 can be connected to the fourth reset start signal line FLM_RSL4. It can generate a reset signal corresponding to the fourth reset start signal (that is, the reset start signal applied to the fourth reset start signal line FLM_RSL4) by using a reset clock signal, and can provide the reset signal to the 97th reset line RSL97 to the 128th reset line RSL128 corresponding to the 41st unit block UB41.

[0162] The fifth sub-reset driver RSDR_S5 can be connected to the fifth reset start signal line FLM_RSL5. It can generate a reset signal corresponding to the fifth reset start signal (that is, the reset start signal applied to the fifth reset start signal line FLM_RSL5) by using a reset clock signal, and can provide the reset signal to the 129th reset line RSL129 to the 160th reset line RSL160 corresponding to the 51st unit block UB51.

[0163] When the eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41 can be included in a single unit sensing block USB, according to some example embodiments, only the first reset start signal to the fourth reset start signal can be sequentially provided to the first sub-reset driver RSDR_S1, the second sub-reset driver RSDR_S2, the third sub-reset driver RSDR_S3, and the fourth sub-reset driver RSDR_S4, and the reset start signal may not be provided to the fifth sub-reset driver RSDR_S5 (and the other sub-reset drivers). That is, only the first sub-reset driver RSDR_S1, the second sub-reset driver RSDR_S2, the third sub-reset driver RSDR_S3, and the fourth sub-reset driver RSDR_S4 can operate sequentially. However, embodiments of the present invention are not limited thereto, and, for example, according to some example embodiments, all sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4 and RSDR_S5 (that is, all reset drivers RSDR) may operate simultaneously (or in parallel) only before the first sub-reset driver RSDR_S1, the second sub-reset driver RSDR_S2, the third sub-reset driver RSDR_S3 and the fourth sub-reset driver RSDR_S4 operate sequentially.

[0164] The scan driver SCDR may include sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4, and SCDR_S5 corresponding to the unit blocks UB11, UB21, UB31, UB41, and UB51 of the optical sensor PS. The scan driver SCDR may be connected to scan start signal lines FLM_SCL1, FLM_SCL2, FLM_SCL3, FLM_SCL4, and FLM_SCL5, and scan clock lines CLKL1_SC and CLKL2_SC, for independently driving the sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4, and SCDR_S5. The scan start signal lines FLM_SCL1, FLM_SCL2, FLM_SCL3, FLM_SCL4, and FLM_SCL5, and the scan clock lines CLKL1_SC and CLKL2_SC may be included in the second control line CL2 (see...). Figure 3 The scan start signal can be applied independently to the scan start signal lines FLM_SCL1, FLM_SCL2, FLM_SCL3, FLM_SCL4, and FLM_SCL5. The first scan clock signal and the second scan clock signal are applied to the scan clock lines CLKL1_SC and CLKL2_SC, respectively, and, for example, the second scan clock signal can have a waveform in which the first scan clock signal is out of phase, or it can have a waveform in which the first scan clock signal is delayed by 180 degrees, or in which the first scan clock signal is delayed by a specific time.

[0165] The first sub-scan driver SCDR_S1 can be connected to the first scan start signal line FLM_SCL1. It can generate a scan signal corresponding to the first scan start signal (that is, the scan start signal applied to the first scan start signal line FLM_SCL1) using a scan clock signal, and can provide the scan signal to the eleventh unit block UB11. For example, the first sub-scan driver SCDR_S1 can sequentially generate scan signals by sequentially shifting the first scan start signal using a scan clock signal. Figure 7 As shown, the first sub-scan driver SCDR_S1 can be connected to the first scan line SCL1 to the thirty-second scan line SCL32 corresponding to the eleventh unit block UB11, and can sequentially provide scan signals (e.g., the first scan start signal to the thirty-second scan start signal) corresponding to the first scan start signal to the first scan line SCL1 to the thirty-second scan line SCL32.

[0166] Similar to the first sub-scan driver SCDR_S1, the second sub-scan driver SCDR_S2 can be connected to the second scan start signal line FLM_SCL2. It can generate a scan signal corresponding to the second scan start signal (that is, the scan start signal applied to the second scan start signal line FLM_SCL2) by using the scan clock signal, and can provide the scan signal to the thirty-third scan line SCL33 to the sixty-fourth scan line SCL64 corresponding to the twenty-first unit block UB21.

[0167] The third sub-scan driver SCDR_S3 can be connected to the third scan start signal line FLM_SCL3. It can generate a scan signal corresponding to the third scan start signal (that is, the scan start signal applied to the third scan start signal line FLM_SCL3) by using the scan clock signal, and can provide the scan signal to the sixty-fifth scan line SCL65 to the ninety-sixth scan line SCL96 corresponding to the thirty-first unit block UB31.

[0168] The fourth sub-scan driver SCDR_S4 can be connected to the fourth scan start signal line FLM_SCL4. It can generate a scan signal corresponding to the fourth scan start signal (that is, the scan start signal applied to the fourth scan start signal line FLM_SCL4) by using the scan clock signal, and can provide the scan signal to the 97th scan line SCL97 to the 128th scan line SCL128 corresponding to the 41st unit block UB41.

[0169] The fifth sub-scan driver SCDR_S5 can be connected to the fifth scan start signal line FLM_SCL5. It can generate a scan signal corresponding to the fifth scan start signal (that is, the scan start signal applied to the fifth scan start signal line FLM_SCL5) by using the scan clock signal, and can provide the scan signal to the 129th scan line SCL129 to the 160th scan line SCL160 corresponding to the 51st unit block UB51.

[0170] When the eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41 can be included in a single unit sensing block USB, according to some example embodiments, only the first scan start signal to the fourth scan start signal can be sequentially provided to the first sub-scan driver SCDR_S1, the second sub-scan driver SCDR_S2, the third sub-scan driver SCDR_S3, and the fourth sub-scan driver SCDR_S4, and the scan start signal may not be provided to the fifth sub-scan driver SCDR_S5 (and the other sub-scan drivers). That is, only the first sub-scan driver SCDR_S1, the second sub-scan driver SCDR_S2, the third sub-scan driver SCDR_S3, and the fourth sub-scan driver SCDR_S4 can operate sequentially.

[0171] For reference Figure 6 and Figure 7 As described, the horizontal driver 221 may include sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4 and RSDR_S5 and sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4 and SCDR_S5 for each of the individual drive unit blocks UB. Each of the sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4 and RSDR_S5 can operate independently in response to a corresponding reset start signal, and each of the sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4 and SCDR_S5 can operate independently in response to a corresponding scan start signal.

[0172] Figure 8 This includes some example embodiments of the present invention. Figure 7 A block diagram illustrating an example of a child drive in a horizontal drive. Because Figure 7 The sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4, and RSDR_S5 shown are substantially the same as or similar to the sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4, and SCDR_S5 except for the lines connecting them (i.e., the reset / scan start signal line, clock line, and reset / scan line). Therefore, the description of sub-driver GDR_S, including sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4, and RSDR_S5, and sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4, and SCDR_S5, will be provided.

[0173] refer to Figure 7 and Figure 8 The sub-driver GDR_S can include multiple stages ST1 to ST4. Each of stages ST1 to ST4 is connected to one of the gate lines HL1, HL2, HL3, and HL4 (hereinafter referred to as HL1 to HL4) and is driven to correspond to clock lines CLKL1 and CLKL2. Here, gate lines HL1 to HL4 can correspond to... Figure 7 The reset lines RSL1 to RSL32 and RSL33 to RSL64 or the scan lines SCL1 to SCL32 and SCL33 to SCL64 shown are shown, and the clock lines CLKL1 and CLKL2 can correspond to... Figure 7 The reset clock lines CLKL1_RS and CLKL2_RS or the scan clock lines CLKL1_SC and CLKL2_SC are shown. Levels ST1 to ST4 can be constructed from circuits that are substantially equivalent to each other.

[0174] Each of ST1 to ST4 may provide a first input terminal 2211 to a third input terminal 2213 and an output terminal 2214.

[0175] The first input terminal 2211 of each of stages ST1 to ST4 is connected to the start signal line FLML or the output terminal 2214 of the previous stage, and the first input terminal 2211 can receive a start signal or the output signal of the previous stage (e.g., the previous reset signal or the previous scan signal). Here, the start signal line FLML can correspond to... Figure 7 The reset start signal lines FLM_RSL1, FLM_RSL2, FLM_RSL3, FLM_RSL4 and FLM_RSL5 or the scan start signal lines FLM_SCL1, FLM_SCL2, FLM_SCL3, FLM_SCL4 and FLM_SCL5 are shown.

[0176] The first input terminal 2211 of the first stage ST1 can be connected to the start signal line FLML to receive the start signal, and the first input terminals 2211 of the remaining stages ST2 to ST4 can receive the output signals of the previous stage.

[0177] In odd-numbered stages ST1 and ST3, the second input terminal 2212 can be connected to the second clock line CLKL2 to receive the second clock signal, and the third input terminal 2213 can be connected to the first clock line CLKL1 to receive the first clock signal. In even-numbered stages ST2 and ST4, the second input terminal 2212 can be connected to the first clock line CLKL1 to receive the first clock signal, and the third input terminal 2213 can be connected to the second clock line CLKL2 to receive the second clock signal.

[0178] The first clock signal and the second clock signal have the same period, and the phases of the first clock signal and the second clock signal may not overlap.

[0179] You can refer to this. Figure 9 The configuration of each of the description levels ST1 to ST4.

[0180] Figure 9 This includes some example embodiments of the present invention. Figure 8 A circuit diagram of an example stage in a sub-driver. Figure 8 In this context, because odd-numbered levels ST1 and ST3 are essentially the same or similar to each other, and even-numbered levels ST2 and ST4 are essentially the same or similar to each other, for better understanding and ease of description, Figure 9 Examples of ST1 and ST2 are shown in the figure.

[0181] refer to Figure 8 and Figure 9 The first level ST1 may include a first node controller 221a, a second node controller 221b, and a buffer section 221c.

[0182] The first node controller 221a can transmit the start signal FLMS or the first voltage VGH (or the first power supply voltage) to the third node N3 based on the first clock signal CLK1 and the second clock signal CLK2. The first node controller 221a may include a first switching element M1, a second switching element M2 and a third switching element M3.

[0183] The first switching element M1 may include a first electrode connected to the first input terminal 2211, a second electrode connected to the third node N3, and a gate electrode connected to the second input terminal 2212.

[0184] The second switching element M2 may include a first electrode that receives a first voltage VGH (or is connected to a first power supply line to which the first voltage VGH is applied), a second electrode that is connected to a third node N3 via a third switching element M3, and a gate electrode that is connected to a first node N1.

[0185] The third switching element M3 may include a first electrode connected to the second electrode of the second switching element M2, a second electrode connected to the third node N3, and a gate electrode connected to the third input terminal 2213. Here, the second switching element M2 and the third switching element M3 may be connected in series with each other.

[0186] The second node controller 221b can transmit a second voltage VGL (or, a second power supply voltage) or the second clock signal CLK2 to the first node N1 based on the second clock signal CLK2 and the signal (or voltage level) of the third node N3. The second node controller 221b may include a fourth switching element M4 and a fifth switching element M5. Furthermore, the second node controller 221b may also include an eighth switching element M8.

[0187] The fourth switching element M4 may include a first electrode connected to the first node N1, a second electrode connected to the second input terminal 2212, and a gate electrode connected to the third node N3.

[0188] The fifth switching element M5 may include a first electrode connected to the first node N1, a second electrode receiving a second voltage VGL (or connected to a second power supply line to which the second voltage VGL is applied) and a gate electrode connected to the second input terminal 2212.

[0189] The eighth switching element M8 may include a first electrode connected to the third node N3, a second electrode connected to the second node N2, and a gate electrode that receives the second voltage VGL.

[0190] The buffer section 221c can output a first gate signal (e.g., a reset signal or a scan signal) including the first clock signal CLK1 as a pulse based on the signals from the first node N1 and the second node N2. The first gate signal can be provided as a carry signal to the second stage ST2.

[0191] The buffer section 221c may include a sixth switching element M6 (or a pull-up switching element) and a seventh switching element M7 (or a pull-down switching element). The sixth switching element M6 may include a first electrode receiving a first voltage VGH (or a first power supply line to which the first voltage VGH is applied), a second electrode connected to the output terminal 2214, and a gate electrode connected to the first node N1.

[0192] The seventh switching element M7 may include a first electrode connected to the output terminal 2214, a second electrode connected to the third input terminal 2213, and a gate electrode connected to the second node N2.

[0193] The buffer section 221c may also include a first capacitor C1 and a second capacitor C2.

[0194] The first capacitor C1 can be formed or connected between the first electrode and the gate electrode of the seventh switching element M7. The second capacitor C2 can be formed or connected between the first electrode and the gate electrode of the sixth switching element M6.

[0195] like Figure 9 As shown, since the circuit configuration of the second stage ST2 is basically the same as that of the first stage ST1, redundant descriptions will not be repeated.

[0196] At the same time, Figure 9 In the illustration, the first switching element M1 to the seventh switching element M7 are shown as P-type transistors, but this is merely an example and the embodiments according to the invention are not limited thereto. For example, the first switching element M1 to the seventh switching element M7 can be implemented as N-type transistors.

[0197] For reference Figure 8 and Figure 9 As described, sub-drive GDR_S (or, Figure 7 The sub-reset drivers RSDR_S1, RSDR_S2, RSDR_S3, RSDR_S4 and RSDR_S5 shown, and the sub-scan drivers SCDR_S1, SCDR_S2, SCDR_S3, SCDR_S4 and SCDR_S5 shown can output gate signals while sequentially shifting the start signal FLMS.

[0198] Figure 10 This includes some example embodiments of the present invention. Figure 3 A circuit diagram of an example selector in an input sensing device. Figure 10 The selector SWU can also be applied to Figure 5A The input sensing device FDD.

[0199] refer to Figure 3 , Figure 5A as well as Figures 6 to 10 The selector SWU may include a first switch unit SW1 (or a first switch block) and a second switch unit SW2 (or a second switch block).

[0200] The first switching unit SW1 can be connected between pads PAD_CLK1, PAD_CLK2, and PAD_FLM1 to PAD_FLM40 and the reset driver RSDR. Here, pads PAD_CLK1, PAD_CLK2, and PAD_FLM1 to PAD_FLM40 are connected to the controller CON. A first clock signal CLK1 can be applied to the first clock pad PAD_CLK1, a second clock signal CLK2 can be applied to the second clock pad PAD_CLK2, and multiple start signals (e.g., 40 start signals FLM1 to FLM40) can be applied to the start signal pads PAD_FLM1 to PAD_FLM40 respectively.

[0201] like Figure 10As shown, the first switching unit SW1 may include a transistor connected between the first clock line CLKL1 and the first reset clock line CLKL1_RS, a transistor connected between the second clock line CLKL2 and the second reset clock line CLKL2_RS, and a transistor connected between the start signal line FLML and the reset start signal line FLM_RSL. Here, the first clock line CLKL1, the second clock line CLKL2, and the start signal line FLML may be included in the reference... Figure 3 The reference control line CL0 is described.

[0202] The gate electrode of each of the transistors included in the first switching unit SW1 is connected to the second enable signal pad PAD_EN2, and each of the transistors can be turned on in response to a reset enable signal RS_EN applied to the second enable signal pad PAD_EN2. That is, in response to the reset enable signal RS_EN, the first clock signal CLK1, the second clock signal CLK2, and the start signals FLM1 to FLM40 can be provided to the reset driver RSDR.

[0203] The second switching unit SW2 can be connected between pads PAD_CLK1, PAD_CLK2, and PAD_FLM1 to PAD_FLM40 and the scan driver SCDR.

[0204] like Figure 10 As shown, the second switching unit SW2 may include a transistor connected between the first clock line CLKL1 and the first scan clock line CLKL1_SC, a transistor connected between the second clock line CLKL2 and the second scan clock line CLKL2_SC, and a transistor connected between the start signal line FLML and the scan start signal line FLM_SCL. The gate electrode of each of the transistors included in the second switching unit SW2 is connected to the first enable signal pad PAD_EN1, and each of the transistors can be turned on in response to a scan enable signal SC_EN applied to the first enable signal pad PAD_EN1. That is, in response to the scan enable signal SC_EN, the first clock signal CLK1, the second clock signal CLK2, and the start signals FLM1 to FLM40 can be provided to the scan driver SCDR.

[0205] Meanwhile, the reset driver RSDR and the scan driver SCDR can be connected to the first power pad PAD_P1 via the first power line PVL1, to the second power pad PAD_P2 via the second power line PVL2, and to the third power pad PAD_P3 via the third power line PVL3. Figure 10The first voltage VGH, the second voltage VGL, and the ground voltage GND described herein can be applied to the first power pad PAD_P1, the second power pad PAD_P2, and the third power pad PAD_P3, respectively. The ground voltage GND can cover the reset driver RSDR and the scan driver SCDR, and can be used as a shield to prevent or reduce noise from being introduced from the outside.

[0206] For reference Figure 10 As described, the selector SWU can provide the first clock signal CLK1, the second clock signal CLK2, and start signals FLM1 to FLM40 to the reset driver RSDR in response to the reset enable signal RS_EN, or it can provide the first clock signal CLK1, the second clock signal CLK2, and start signals FLM1 to FLM40 to the scan driver SCDR in response to the scan enable signal SC_EN. Therefore, the number of pads and control lines used for transmitting the first clock signal CLK1, the second clock signal CLK2, and start signals FLM1 to FLM40 to the reset driver RSDR and the scan driver SCDR, as well as the controller CON (see [link to controller CON]), can be reduced. Figure 3 The number of output channels can be reduced, and the input detection circuit ROIC (see [link to ROIC]) can be decreased. Figure 3 (area and manufacturing cost)

[0207] Figure 11 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform diagram of the operation of the input sensing device. Figure 12 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform of the operation of the input sensing device during the first time period. Figure 13 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform diagram of the operation of the input sensing device in the second time period. Figure 14 This is for explaining some exemplary embodiments according to the present invention. Figure 5A The waveform diagram of the operation of the input sensing device in the third time period.

[0208] In the following text, as an example, references will be described. Figure 6 and Figure 7The eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41 described are included in a unit sensing block USB. That is, according to local driving (or local sensing), only the eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41 included in the unit sensing block USB are activated, and for this purpose, only the first sub-reset driver RSDR_S1, the second sub-reset driver RSDR_S2, the third sub-reset driver RSDR_S3, and the fourth sub-reset driver RSDR_S4 corresponding to the eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41, as well as the first sub-scan driver SCDR_S1, the second sub-scan driver SCDR_S2, the third sub-scan driver SCDR_S3, and the fourth sub-scan driver SCDR_S4 can be activated. Sub-reset drivers (e.g., fifth sub-reset driver RSDR_S5 and subsequent sub-reset drivers) and sub-scan drivers (e.g., fifth sub-scan driver SCDR_S5 and subsequent sub-scan drivers) corresponding to the remaining cell blocks (e.g., the fifty-first cell block UB51 and subsequent cell blocks) not included in the cell sensing block USB can be deactivated.

[0209] refer to Figures 5A to 14 The input sensing device FDD performing a fingerprint sensing operation can include a first time period P1, a second time period P2, and a third time period P3. For example... Figure 11 As shown, the first time period P1, the second time period P2, and the third time period P3 can be classified based on the periodic changes of clock signals CLK1 and CLK2.

[0210] During the first time period P1 and the second time period P2, the reset enable signal RS_EN can have a turn-on voltage level (or a logic low level), and the scan enable signal SC_EN can have a turn-off voltage level (or a logic high level). Therefore, Figure 10 The selector SWU connects the clock lines CLKL1 and CLKL2 and the start signal line FLML to the reset driver RSDR, and the clock signals CLK1 and CLK2 and the start signals FLM1 to FLM40 can be provided only to the reset driver RSDR.

[0211] According to some example embodiments, during the first time period P1, the controller CON may simultaneously (or concurrently) generate a first start signal FLM1 to a fourth start signal FLM4 of a pulse PLS with a conduction voltage level.

[0212] like Figure 12As shown, at the first time point t1 in the first time period P1, the eleventh unit block UB11 (see...) Figure 7 ) to the forty-first unit block UB41 (see Figure 7 The first start signal FLM1 to the fourth start signal FLM4 can simultaneously (or concurrently) have pulses PLS with a conduction voltage level (for simplicity of the diagram, Figure 12 The PLS identified by FLM1 can be applied to the pulses of the first start signal FLM1 to the fourth start signal FLM4 described later.

[0213] like Figure 3 , Figure 7 and Figure 12 As shown, because the controller CON and the reset driver RSDR are connected via the selector SWU, the first start signal FLM1 to the fourth start signal FLM4, as well as the clock signals CLK1 and CLK2, can be provided to the first sub-reset driver RSDR_S1 to the fourth sub-reset driver RSDR_S4 (see...). Figure 7 ), and the first sub-reset driver RSDR_S1 to the fourth sub-reset driver RSDR_S4 (see Figure 7 The first sub-reset driver RSDR_S1 can output reset signals simultaneously (or concurrently). For example, in response to the first start signal FLM1, the first sub-reset driver RSDR_S1 can output a first reset signal RST1 with an on-state voltage level synchronized with the first clock signal CLK1 to the first reset line RSL1. Then, the first sub-reset driver RSDR_S1 can shift the first reset signal RST1 to output a second reset signal RST2 with an on-state voltage level synchronized with the second clock signal CLK2 to the second reset line RSL2. In this way, the first sub-reset driver RSDR_S1 can output reset signals sequentially.

[0214] Similar to the first sub-reset driver RSDR_S1, the second sub-reset driver RSDR_S2 can output a 33rd reset signal RST33 at the on-state voltage level to the 33rd reset line RSL33 in response to the second start signal FLM2. Subsequently, the second sub-reset driver RSDR_S2 can shift the 33rd reset signal RST33 to output a 34th reset signal RST34 at the on-state voltage level to the 34th reset line RSL34. In this way, the second sub-reset driver RSDR_S2 can sequentially output reset signals.

[0215] Furthermore, the third sub-reset driver RSDR_S3 can sequentially output the sixty-fifth reset signal RST65 and the sixty-sixth reset signal RST66 at the conduction voltage level to the sixty-fifth reset line RSL65 and the sixty-sixth reset line RSL66 in response to the third start signal FLM3, and the fourth sub-reset driver RSDR_S4 can sequentially output the ninety-seventh reset signal RST97 and the ninety-eighth reset signal RST98 at the conduction voltage level to the ninety-seventh reset line RSL97 and the ninety-eighth reset line RSL98 in response to the fourth start signal FLM4.

[0216] Applied to the first reset line RSL1 (that is, the eleventh unit block UB11 (see) Figure 7 The first reset signal RST1 of the first reset line is applied to the thirty-third reset line RSL33 (that is, the twenty-first unit block UB21 (see...) Figure 7 The thirty-third reset signal RST33 of the first reset line is applied to the sixty-fifth reset line RSL65 (that is, the thirty-first unit block UB31 (see Figure 7 The sixty-fifth reset signal RST65 of the first reset line and the ninety-seventh reset line RSL97 (that is, the forty-first unit block UB41) are applied to the reset line. Figure 7 The 97th reset signal RST97 of the first reset line of the optical sensor PS can have a conduction voltage level simultaneously (or concurrently). Therefore, some of the sensor pixels SPXL provided in the optical sensor PS can be initialized simultaneously (or concurrently). That is, cell blocks UB11, UB21, UB31 and UB41 can be initialized simultaneously (or concurrently) and sequentially.

[0217] Simultaneously, it is applied to USB not included in the unit sensing block (see...) Figure 6 The unit blocks in ), such as the fifty-first unit block UB51 (see Figure 7 The fifth start signal FLM5 of the corresponding fifth sub-reset driver RSDR_S5 can be maintained at a cutoff voltage level. However, embodiments of the present invention are not limited thereto, and according to some example embodiments, the fifth start signal FLM5 applied to the fifth sub-reset driver RSDR_S5 in the first time period P1 can have a cutoff voltage level. That is, initialization can also be performed on inactive cell blocks (e.g., cell blocks that have not been previously activated and initialized).

[0218] According to some example embodiments, during the first time period P1, the controller CON can generate a first start signal FLM1 to a fourth start signal FLM4 with a pulse PLS having a conduction voltage level multiple times.

[0219] like Figure 3 and Figure 12 As shown, in the sub-segment P_M (or multi-sensing period) within the first time period P1, each of the first start signal FLM1 to the fourth start signal FLM4 may have two or more pulses PLS with a conduction voltage level. In this case, the sensor pixel SPXL provided in the light sensor PS is repeatedly initialized, and thus the charge (i.e., photoelectric conversion charge) charged in the sensor pixel SPXL can be completely eliminated.

[0220] Meanwhile, in the first time period P1, clock signals CLK1 and CLK2 can have pulses with a conduction voltage level in each first cycle PW1.

[0221] According to some example embodiments, after sub-period P_M (or in the second period P2), the periods of clock signals CLK1 and CLK2 can be set to be greater than the periods in the first period P1.

[0222] like Figure 12 As shown, at the third time point t3, the first clock signal CLK1 can have a pulse with a conduction voltage level. Here, the third time point t3 can be the time point after a predetermined time from the second time point t2 and the start point of the second time period P2. Furthermore, at the fourth time point t4, the second clock signal CLK2 can have a pulse with a conduction voltage level. Here, the fourth time point t4 can be the time point after the second period PW2 from the second time point t2. That is, during the second time period P2, clock signals CLK1 and CLK2 can have the second period PW2.

[0223] like Figure 3 and Figure 12 As shown, in the first time period P1, clock signals CLK1 and CLK2 have a relatively small first period PW1, allowing the sensor pixel SPXL in the photosensitive sensor PS to be initialized quickly and several times. In the second time period P2, clock signals CLK1 and CLK2 can have a relatively large second period PW2, allowing a specific sensor pixel SPXL to generate photoelectric conversion charge. For example, the second period PW2 can be ten times or more than the first period PW1. Clock signals CLK1 and CLK2 can have the same period in each time period. For example, clock signals CLK1 and CLK2 can have the same second period PW2 in the second time period P2.

[0224] According to some example embodiments, after the sub-period P_M, the controller CON can sequentially generate some of the start signals for a specific unit block used for fingerprint sensing.

[0225] When reference Figure 3 , Figure 6 and Figure 7 When the eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41 are configured as a unit sensing block USB (that is, a part of the optical sensor PS to be operated for fingerprint sensing), the controller CON can sequentially generate the first start signal FLM1 to the fourth start signal FLM4. In other words, when a touch input occurs, the eleventh unit block UB11, the twenty-first unit block UB21, the thirty-first unit block UB31, and the forty-first unit block UB41 corresponding to the area where the touch input is recognized can be activated to form a unit sensing block USB. At the same time, other unit blocks that do not form a unit sensing block USB (e.g., the fifty-first unit block UB51) are deactivated, and for this purpose, the controller CON may not generate start signals other than the first start signals FLM1 to the fourth start signals FLM4 (e.g., the fifth start signal FLM5), or may maintain them at the cutoff voltage level.

[0226] like Figure 12 and Figure 13 As shown, at the second time point t2, which is the end point of the sub-period P_M, only the first start signal FLM1 can have a pulse PLS with a conduction voltage level. In this case, the first sub-reset driver RSDR_S1 (see...) Figure 7 It can sequentially generate the first reset signal RST1 to the thirty-second reset signal RST32 in response to the first start signal FLM1. For example... Figure 13 As shown, the first reset signal RST1 may have a pulse with a conduction voltage level at the third time point t3. At the fourth time point t4, the second reset signal RST2 may have a pulse with a conduction voltage level. Thereafter, the reset signals may sequentially have conduction voltage levels, and the thirty-second reset signal RST32 may have a pulse with a conduction voltage level exactly before the fifth time point t5.

[0227] Additionally, at the fifth time point t5, only the second start signal FLM2 can have a pulse PLS with a conduction voltage level. In this case, the second sub-reset driver RSDR_S2 (see...) Figure 7 It can sequentially generate the thirty-third reset signal RST33 to the sixty-fourth reset signal RST64 in response to the second start signal FLM2.

[0228] At the sixth time point t6, only the third start signal FLM3 can have a pulse PLS with a conduction voltage level. In this case, the third sub-reset driver RSDR_S3 (see...) Figure 7 It can sequentially generate the sixty-fifth reset signal RST65 to the ninety-sixth reset signal RST96 in response to the third start signal FLM3.

[0229] At the seventh time point t7, only the fourth start signal FLM4 can have a pulse PLS with a conduction voltage level. In this case, the fourth sub-reset driver RSDR_S4 (see...) Figure 7 It can sequentially generate the 97th reset signal RST97 to the 128th reset signal RST128 in response to the fourth start signal FLM4.

[0230] Simultaneously, the fifth start signal FLM5 (and other start signals) can be maintained at the cutoff voltage level after the sub-period P_M. Therefore, the 129th reset signal RST129 (and other reset signals) can be maintained at the cutoff voltage level during the second period P2.

[0231] like Figure 10 and Figure 11 As shown, in the third time period P3, the reset enable signal RS_EN can have a cutoff voltage level, and the scan enable signal SC_EN can have a turn-on voltage level. Therefore, Figure 10 The selector SWU connects the clock lines CLKL1 and CLKL2 and the start signal line FLML to the scan driver SCDR, and the clock signals CLK1 and CLK2 and the start signals FLM1 to FLM40 can be provided only to the scan driver SCDR.

[0232] According to some example embodiments, the third time period P3 may include a first sub-time period P_S1 and a second sub-time period P_S2 that are repeated sequentially, and the controller CON (see...) Figure 3 A first clock signal CLK1 with a conduction voltage level pulse can be generated in the first sub-period P_S1, and the controller CON (see...) Figure 3 A second clock signal CLK2 with a conduction voltage level can be generated in the second sub-period P_S2. In the first sub-period P_S1, the second clock signal CLK2 can be maintained at the cutoff voltage level, and in the second sub-period P_S2, the first clock signal CLK1 can be maintained at the cutoff voltage level.

[0233] According to some example embodiments, the repetition period of each of the first sub-time period P_S1 and the second sub-time period P_S2 may be the same as the second period PW2 of the clock signals CLK1 and CLK2 in the second time period P2.

[0234] like Figure 14As shown, the first clock signal CLK1 can have pulses with a conduction voltage level at the eighth time point t8, the ninth time point t9, the tenth time point t10, and the eleventh time point t11, respectively. Simultaneously, in the first sub-period P_S1 between the eighth time point t8 and the twelfth time point t12, the first scan signal SC1, corresponding to the first start signal FLM1 and the first clock signal CLK1, can have pulses with a conduction voltage level applied to the first scan line SCL1.

[0235] like Figure 14 As shown, the second clock signal CLK2 can have pulses with a conduction voltage level at time points t12, t13, t14, and t15, respectively. In the second sub-period P_S2 between time point t12 and time point t16, the second scan signal SC2, corresponding to the second clock signal CLK2, applied to the second scan line SCL2, can have pulses with a conduction voltage level.

[0236] According to some example embodiments, the number of pulses of the conduction voltage level of the first clock signal CLK1 in the first sub-time period P_S1 can be compared with the reference. Figure 5A The input / output ratio of the described multiplexer MUX is the same.

[0237] like Figure 5B and Figure 14 As shown, at the eighth time point t8, the first switch control signal MUX_C1 can have a conduction voltage level. In this case, the first switch SW_M1 (see...) Figure 5B The sensor can be turned on, and the first readout line RL1 and the first output line OL1 can be connected. At the eighth time point t8, because the first scan signal SC1 has a conduction voltage level, the sensing signal can be output from the first sensor pixel SPXL1 to the first readout line RL1. Because the first readout line RL1 and the first output line OL1 are connected, the sensing signal of the first sensor pixel SPXL1 can be output through the first output line OL1.

[0238] Similarly, at the ninth time point t9, the second switch control signal MUX_C2 can have a conduction voltage level. In this case, the second switch SW_M2 (see...) Figure 5B The signal can be turned on, and the second readout line RL2 and the first output line OL1 can be connected. At the ninth time point t9, because the first scan signal SC1 has a conduction voltage level, the sensing signal can be output from the second sensor pixel SPXL2 to the second readout line RL2. Because the second readout line RL2 and the first output line OL1 are connected, the sensing signal of the second sensor pixel SPXL2 can be output through the first output line OL1.

[0239] In contrast, when the first scan signal SC1 and the first clock signal CLK1 have a cutoff voltage level at the ninth time point t9, the sensing signal of the second sensor pixel SPXL2, which is output to the second readout line RL2 at the eighth time point t8, can be output through the second switch SW_M2. Due to the conduction operation of the second switch SW_M2 between the eighth time point t8 and the ninth time point t9, and the parasitic capacitance between adjacent wirings, noise may be introduced into the sensing signal of the second sensor pixel SPXL2, which is output to the second readout line RL2 at the eighth time point t8.

[0240] According to some exemplary embodiments of the present invention, because the first scan signal SC1 has a conduction voltage level at the ninth time point t9, a noise-free sensing signal can be output from the second sensor pixel SPXL2 through the second readout line RL2 and the first output line OL1. That is, noise introduced into the sensing signal of the second sensor pixel SPXL2 can be reduced, and the accuracy of fingerprint sensing can be improved.

[0241] At the tenth time point t10, the third switch control signal MUX_C3 can have a conduction voltage level. In this case, the third switch SW_M3 (see...) Figure 5B The signal can be turned on, and the third readout line RL3 and the first output line OL1 can be connected. At the tenth time point t10, because the first scan signal SC1 has a conduction voltage level, the sensing signal can be output from the third sensor pixel SPXL3 to the third readout line RL3. Because the third readout line RL3 and the first output line OL1 are connected, the sensing signal of the third sensor pixel SPXL3 can be output through the first output line OL1.

[0242] At time point eleven (t11), the fourth switch control signal MUX_C4 can have a conduction voltage level. In this case, the fourth switch SW_M4 (see...) Figure 5B The sensor can be turned on, and the fourth readout line RL4 and the first output line OL1 can be connected. At the eleventh time point t11, because the first scan signal SC1 has a turn-on voltage level, the sensing signal can be output from the fourth sensor pixel SPXL4 to the fourth readout line RL4. Because the fourth readout line RL4 and the first output line OL1 are connected, the sensing signal of the fourth sensor pixel SPXL4 can be output through the first output line OL1.

[0243] Simultaneously, at time points t12, t13, t14, and t15, the first switch control signal MUX_C1 to the fourth switch control signal MUX_C4, the second clock signal CLK2, the second scan signal SC2, and the input sensing device FDD (see...) Figure 5A The operation based on these signals can be performed with the first switch control signal MUX_C1 to the fourth switch control signal MUX_C4, the first clock signal CLK1, the first scan signal SC1, and the input sensing device FDD (see [link to relevant documentation]) at the eighth time point t8, the ninth time point t9, the tenth time point t10, and the eleventh time point t11, respectively. Figure 5A The operations based on these signals are essentially the same or similar. Therefore, some repetitive descriptions may not be repeated.

[0244] After time point t16, scan driver SCDR (see Figure 7 It can sequentially output scan signals, each with four conduction voltage levels (that is, ...). Figure 11 and Figure 14 The third scan signal SC3, the fourth scan signal SC4, the thirty-second scan signal SC32, the thirty-third scan signal SC33, the one hundred and twenty-sixth scan signal SC126, the one hundred and twenty-seventh scan signal SC127, and the one hundred and twenty-eighth scan signal SC128 shown.

[0245] For example, such as Figure 13 and Figure 14 As shown, exactly before the seventeenth time point t17 (that is, at the time when the thirty-second scan signal SC32 is output to the thirty-second scan line SCL32), the second start signal FLM2 can have a pulse with a conduction voltage level. In this case, the second sub-reset driver RSDR_S2 (see...) Figure 7 It can generate the 33rd scan signal SC33 in response to the second start signal FLM2, and can output the 33rd scan signal SC33 to the 33rd scan line SCL33.

[0246] For reference Figure 5A , Figure 5B , Figures 11 to 14 As described, the input sensing device FDD can use clock signals CLK1 and CLK2, which have relatively small periods in the first time period P1, to initialize the sensor pixel SPXL in the optical sensor PS substantially simultaneously (or concurrently) and several times. Furthermore, the input sensing device FDD can continuously use clock signals with multiple pulses in the third time period P3 to provide a scan signal with multiple pulses to a single scan line. Therefore, the introduction of noise into the sensing signal of the sensor pixel SPXL can be prevented or reduced by turning on / off the switches SW_M1 to SW_M4 in the multiplexer MUX, thus improving the accuracy of fingerprint sensing.

[0247] also, Figure 10The selector SWU can provide clock signals CLK1 and CLK2 and start signals FLM1 to FLM5 to the reset driver RSDR in response to the reset enable signal RS_EN during the first period P1 and the second period P2, and can provide clock signals CLK1 and CLK2 and start signals FLM1 to FLM5 to the scan driver SCDR in response to the scan enable signal SC_EN during the third period P3. Therefore, the number of pads and control lines used for transmitting clock signals CLK1 and CLK2 and start signals FLM1 to FLM5 to the reset driver RSDR and scan driver SCDR, as well as the number of output channels of the controller CON, can be reduced, and the number of input detection circuits ROIC (see [link to ROIC]) can be reduced. Figure 3 (area and manufacturing cost)

[0248] Although the invention has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0249] Therefore, the technical scope of the embodiments according to this disclosure can be determined by the technical scope of the appended claims and their equivalents.

Claims

1. An input sensing device, wherein, The input sensing device includes: a plurality of reset lines; a plurality of scan lines; a plurality of readout lines; a plurality of sensor pixels connected to the reset lines, the scan lines, and the readout lines, wherein each of the sensor pixels is configured to be initialized in response to a reset signal provided through a respective one of the reset lines, and to output a sensing signal to a respective one of the readout lines in response to a scan signal provided through a respective one of the scan lines; a controller configured to generate at least one start signal and a clock signal; a selector configured to selectively provide the at least one start signal and the clock signal to a first control line or a second control line; a reset driver connected to the first control line and configured to supply the reset signal to at least some of the reset lines based on the at least one start signal and the clock signal provided through the first control line; and a scan driver connected to the second control line and configured to supply the scan signal to at least some of the scan lines based on the at least one start signal and the clock signal provided through the second control line.

2. The input sensing device of claim 1, wherein, The controller is configured to output the at least one start signal and the clock signal to a reference control line; and wherein the selector includes: a first switch unit connected between the reference control line and the first control line and configured to connect the reference control line and the first control line, respectively, in response to a reset enable signal; and a second switch unit connected between the reference control line and the second control line and configured to connect the reference control line and the second control line, respectively, in response to a scan enable signal.

3. The input sensing device of claim 1, wherein, Each of the sensor pixels is divided into a plurality of unit blocks including at least one sensor pixel, wherein the reset driver includes sub-reset drivers corresponding to the unit blocks, respectively, wherein each of the sub-reset drivers is configured to provide a respective one of the reset signals to a respective one of the unit blocks, and wherein the controller is configured to generate start signals corresponding to the sub-reset drivers, respectively.

4. The input sensing device of claim 3, wherein, Each of the sub-reset drivers includes a stage configured to generate a respective reset signal while sequentially shifting a respective one of the start signals based on the clock signal.

5. The input sensing device of claim 3, wherein, The scan driver includes sub-scan drivers corresponding to the unit blocks, respectively, wherein each of the sub-scan drivers is configured to provide a respective one of the scan signals to a respective one of the unit blocks.

6. The input sensing device of claim 5, wherein, A sensing period includes a first period, a second period, and a third period classified based on a period variation of the clock signal, and wherein in the first period: the controller is configured to concurrently generate the start signals with pulses having an on-voltage level; the selector is configured to provide the start signals and the clock signal to the first control line; and The sub-reset driver is configured to output at least some of the reset signals concurrently in response to the start signals.

7. The input sensing device of claim 6, wherein, In the first period, the controller is configured to generate start signals, wherein each of the start signals has a plurality of pulses of the on voltage level.

8. The input sensing device of claim 6, wherein, In the second period, the controller is configured to sequentially generate some of the start signals; and In the second period, the selector is configured to provide the some of the start signals and the clock signal to the first control line.

9. The input sensing device of claim 8, wherein, The controller is configured to set a period of the clock signal in the second period to be greater than a period of the clock signal in the first period.

10. The input sensing device of claim 6, wherein, The input sensing device further includes: a multiplexer connected between k readout lines among the readout lines and an output line, and configured to sequentially connect the k readout lines to the output line, wherein k is an integer of 2 or more.

11. The input sensing device of claim 10, wherein, In the third period, the selector is configured to provide the start signals and the clock signal to the second control line.

12. The input sensing device of claim 11, wherein, The clock signal includes a first clock signal and a second clock signal, wherein the third period includes a first sub-period and a second sub-period which are sequentially repeated; wherein in the first sub-period, the controller is configured to generate the first clock signal having pulses of the on voltage level and to maintain the second clock signal at an off voltage level; and wherein in the second sub-period, the controller is configured to generate the second clock signal having pulses of the on voltage level and to maintain the first clock signal at an off voltage level.

13. The input sensing device of claim 12, wherein, The number of the pulses of the on voltage level in the first sub-period is k.

14. The input sensing device of claim 12, wherein, A repetition period of the first sub-period and the second sub-period is the same as a period of the clock signal in the second period.

15. The input sensing device of claim 1, wherein, Each of the sensor pixels includes: a photodiode; a first transistor including a first electrode connected to a first power supply line, a second electrode, and a gate electrode connected to one electrode of the photodiode; a second transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to a corresponding readout line among the readout lines, and a gate electrode connected to a corresponding scan line among the scan lines; a third transistor including a first electrode connected to a second power supply line, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a corresponding reset line among the reset lines; and a capacitor connected to the photodiode in parallel.

16. A display device comprising: The display device includes: a display panel configured to display an image; and an input sensing device on a surface of the display panel, wherein the input sensing device includes: a plurality of reset lines; a plurality of scan lines; a plurality of readout lines; a plurality of sensor pixels connected to the reset lines, the scan lines, and the readout lines, wherein each of the sensor pixels is configured to be initialized in response to a reset signal provided through a respective one of the reset lines, to sense light emitted from the display panel and reflected by a target object to generate a sensing signal, and to output the sensing signal to a respective one of the readout lines in response to a scan signal provided through a respective one of the scan lines; a controller configured to generate at least one start signal and a clock signal; a selector configured to selectively provide the at least one start signal and the clock signal to a first control line or a second control line; a reset driver connected to the first control line and configured to supply the reset signals to at least some of the reset lines based on the at least one start signal and the clock signal provided through the first control line; and a scan driver connected to the second control line and configured to supply the scan signals to at least some of the scan lines based on the at least one start signal and the clock signal provided through the second control line.

17. The display device of claim 16, wherein, the display panel is configured to emit light in an area contacted by a target object based on touch position information provided from outside, and wherein the input sensing device is locally driven in correspondence with the area contacted by the target object.

18. The display device of claim 16, wherein, each of the sensor pixels is divided into a plurality of unit blocks including at least one sensor pixel, wherein the reset driver includes sub-reset drivers respectively corresponding to the unit blocks, wherein each of the sub-reset drivers is configured to provide a respective one of the reset signals to a respective one of the unit blocks, and wherein the controller is configured to generate start signals respectively corresponding to the sub-reset drivers.

19. The display device of claim 18, wherein, a sensing period includes a first period, a second period, and a third period classified based on a period variation of the clock signal, and wherein in the first period: the controller is configured to concurrently generate the start signals with pulses having an on-voltage level; the selector is configured to provide the start signals and the clock signal to the first control line; and the sub-reset drivers are configured to concurrently output at least some of the reset signals in response to the start signals.

20. The display device of claim 19, wherein, in the second period, the controller is configured to sequentially generate some of the start signals, and wherein in the second period, the selector is configured to provide the some of the start signals and the clock signal to the first control line.

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