Display substrate, preparation method thereof, display panel and display device

Abstract

The application discloses a display substrate, a preparation method thereof, a display panel and a display device, and relates to the technical field of display, and is used for improving the problem of dark lines appearing in a display picture and improving the display effect of the display panel. The display substrate comprises a substrate, a connecting lead layer, a semiconductor layer and a light shielding pattern. The connecting lead layer is arranged on the substrate and comprises a target connecting lead. The semiconductor layer is arranged on the side, away from the substrate, of the connecting lead layer and comprises a semiconductor pattern. The light shielding pattern is arranged on the side, away from the substrate, of the semiconductor layer. The target connecting lead comprises a target part. The orthogonal projection of the target part on the substrate is separated from the orthogonal projection of the semiconductor pattern on the substrate, and the orthogonal projection of the target part on the substrate at least partially overlaps with the orthogonal projection of the light shielding pattern on the substrate. The display substrate is applied to the display panel to display a picture of the display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a preparation method therefor, a display panel and a display device. BACKGROUND

[0002] A micro light emitting diode display (Micro LED) uses a micron-scale LED that self-emits as a light-emitting pixel unit, and assembles the light-emitting pixel unit onto a driving panel to form a high-density LED array. Due to the characteristics of small size, high integration and self-emission of the Micro LED chip, the Micro LED chip has great advantages in brightness, resolution, contrast, energy consumption, service life, response speed and thermal stability when applied to a display.

[0003] However, when displaying a picture by using a Micro LED display device, dark stripes are prone to appear in the picture, which causes uneven display brightness and poor display effect. SUMMARY

[0004] The present disclosure aims to provide a display substrate and a preparation method therefor, a display panel and a display device, which are used to improve the problem of dark stripes appearing in a picture and improve the display effect of a display panel.

[0005] To achieve the above-mentioned purpose, the present disclosure provides the following technical solutions:

[0006] In one aspect, a display substrate is provided. The display substrate includes a substrate, a connection lead layer, a semiconductor layer and a light-shielding pattern. The connection lead layer is disposed on the substrate and includes a target connection lead. The semiconductor layer is disposed on a side of the connection lead layer away from the substrate and includes a semiconductor pattern. The light-shielding pattern is disposed on a side of the semiconductor layer away from the substrate. The target connection lead includes a target portion, a projection of the target portion on the substrate is separated from a projection of the semiconductor pattern on the substrate, and the projection of the target portion on the substrate at least partially overlaps with a projection of the light-shielding pattern on the substrate.

[0007] In some embodiments, the display substrate further includes a first pad disposed on a side of the substrate away from the connection lead layer. The substrate includes an opening, and the first pad is disposed on a side of the opening away from the semiconductor layer. The target connection lead is electrically connected to the first pad through the opening.

[0008] In some embodiments, the display substrate further comprises an interlayer dielectric layer and a filling portion. The interlayer dielectric layer is disposed on a side of the semiconductor layer away from the substrate; the interlayer dielectric layer has a recess in a portion corresponding to the opening; the filling portion is disposed on a side of the interlayer dielectric layer away from the substrate, and the filling portion is located in the recess; wherein the light-shielding pattern is disposed on a side of the interlayer dielectric layer away from the substrate, and the light-shielding pattern and the filling portion are of the same material.

[0009] In some embodiments, the display substrate further comprises a first source-drain conductive layer, the first source-drain conductive layer is disposed on a side of the interlayer dielectric layer away from the substrate; the first source-drain conductive layer comprises a first source-drain conductive pattern, and there is a gap between the first source-drain conductive pattern and the light-shielding pattern.

[0010] In some embodiments, the display substrate further comprises a shielding pattern, the shielding pattern is disposed between the connection lead layer and the semiconductor layer; wherein a normal projection of the semiconductor pattern on the substrate is located inside a normal projection of the shielding pattern on the substrate, and a normal projection of the target portion of the target connection lead on the substrate is separated from the normal projection of the shielding pattern on the substrate.

[0011] In some embodiments, the target portion of the target connection lead and the light-shielding pattern extend along a set direction; in a direction perpendicular to the set direction, a size of the target portion is smaller than a size of the light-shielding pattern, and there is a spacing between a boundary of the normal projection of the target portion on the substrate and a boundary of the normal projection of the light-shielding pattern on the substrate.

[0012] In some embodiments, the display substrate further comprises a second pad, the second pad is disposed on a side of the light-shielding pattern away from the substrate; the second pad is used for electrically connecting a light-emitting device; wherein, in a direction perpendicular to the substrate, a ratio of a distance from the target portion of the target connection lead to the second pad to a distance from the target portion to the light-shielding pattern is m; in a direction perpendicular to the set direction, a distance between two adjacent second pads is n times a distance between the boundary of the normal projection of the target portion on the substrate and the boundary of the normal projection of the light-shielding pattern on the substrate, and m is equal to n.

[0013] In some embodiments, the display substrate further comprises a first voltage line, the first voltage line is disposed on a side of the connection lead layer away from the substrate, and is electrically connected to the target connection lead.

[0014] In some embodiments, the display substrate further comprises a second source-drain conductive layer, the second source-drain conductive layer comprises the first voltage line; the first voltage line is disposed on a side of the light-shielding pattern away from the substrate.

[0015] In some embodiments, a projection of the first voltage line on the substrate and a projection of the target connection lead on the substrate intersect.

[0016] In some embodiments, the material of the light-shielding pattern comprises resin.

[0017] In some embodiments, the light transmittance of the light-shielding pattern is less than or equal to 15%.

[0018] In another aspect, a method for manufacturing a display substrate is provided. The method for manufacturing a display substrate comprises:

[0019] forming a first pad on a carrier, the substrate being formed on a side of the first pad distal to the carrier; the substrate comprising an opening, the opening being formed on the side of the first pad distal to the carrier.

[0020] forming a connection lead layer on the substrate, the connection lead layer comprising a target connection lead; the target connection lead being electrically connected to the first pad through the opening.

[0021] forming a semiconductor layer on a side of the connection lead layer distal to the substrate, the semiconductor layer comprising a semiconductor pattern.

[0022] forming an interlayer dielectric layer on a side of the semiconductor layer distal to the substrate; the interlayer dielectric layer having a recess in a portion corresponding to the opening.

[0023] forming a light-shielding pattern and a filling portion on a side of the interlayer dielectric layer distal to the substrate, the filling portion being located in the recess.

[0024] wherein the target connection lead comprises a target portion, a projection of the target portion on the substrate is separated from a projection of the semiconductor pattern on the substrate, and the projection of the target portion on the substrate at least partially overlaps with a projection of the light-shielding pattern on the substrate.

[0025] In yet another aspect, a display panel is provided. The display panel comprises the display substrate according to any one of the above embodiments, a light-emitting device, and a driving chip. The light-emitting device is disposed on a side of a film layer of the display substrate on which the light-shielding pattern is located, distal to a substrate of the display substrate, and is electrically connected to the display substrate. The driving chip is disposed on a side of the substrate distal to the light-shielding pattern, and is electrically connected to the target connection lead of the display substrate.

[0026] In still another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments.

[0027] The display substrate, the preparation method thereof, the display panel and the display device have the following beneficial effects.

[0028] In the display substrate provided by the present disclosure, the light shielding pattern is located on the side of the connecting lead layer away from the substrate, and the orthographic projection of the light shielding pattern on the substrate at least partially overlaps with the orthographic projection of the target part of the target connecting lead on the substrate. In this way, when the display substrate is electrically connected with the light emitting device and the light emitting device is located on the side of the light shielding pattern away from the substrate, the light shielding pattern can block at least part of the light emitted by the light emitting device from being directed to the target part of the target connecting lead, thereby avoiding the light emitted by the light emitting device from being irradiated onto the target part of the target connecting lead and further reflected by the target part. As a result, the interference and cancellation between the reflected light and the light emitted by the light emitting device are avoided, the problem of dark lines appearing in the part of the display screen corresponding to the target connecting lead due to the interference and cancellation of the light is improved, and the display effect of the display panel using the display substrate is improved.

[0029] The display substrate, the preparation method thereof, the display panel and the display device provided by the present disclosure have the same beneficial effects as those of the display substrate provided by the above technical solution, and thus the detailed description is omitted here. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products, methods, signals, etc. involved in the embodiments of the present disclosure.

[0031] Figure 1 A structural diagram of a display panel according to some embodiments;

[0032] Figure 2 A partial cross-sectional view of the display panel shown in FIG. 8; Figure 1

[0033] Figure 3 A top view of a display panel according to some embodiments;

[0034] Figure 4 A light path diagram of a power bus reflecting light emitted by a light emitting device according to some embodiments;

[0035] Figure 5 A top view of a display substrate according to some embodiments;

[0036] Figure 6 A top view of a display substrate according to some embodiments; Figure 5 ​A cross-sectional view of the display substrate shown at A-A’;

[0037] Figure 7 A light path diagram of a light blocking pattern blocking light of a light emitting device according to some embodiments;

[0038] Figure 8 A top view of another display substrate according to some embodiments;

[0039] Figure 9 A cross-sectional view of the display substrate shown at B-B’; Figure 8 A cross-sectional view of the display substrate shown at B-B’;

[0040] Figure 10 A cross-sectional view of the display substrate shown at B-B’; Figure 8 A cross-sectional view of the display substrate shown at B-B’;

[0041] Figure 11 A cross-sectional view of the display substrate shown at B-B’; Figure 8 A cross-sectional view of the display substrate shown at B-B’;

[0042] Figure 12 A position relationship diagram of a target connecting lead and a light blocking pattern according to some embodiments;

[0043] Figure 13 A cross-sectional view of the display substrate shown at B-B’; Figure 8 A cross-sectional view of the display substrate shown at B-B’;

[0044] Figure 14 A structure diagram of another display substrate according to some embodiments;

[0045] Figure 15 A top view of another display substrate according to some embodiments;

[0046] Figure 16 A cross-sectional view of the display substrate shown at B-B’; Figure 8 A cross-sectional view of the display substrate shown at B-B’;

[0047] Figure 17 A flow chart of a manufacturing method of a display substrate according to some embodiments;

[0048] Figures 18-22 A state diagram corresponding to the flow chart of the manufacturing method of the display substrate shown; Figure 17 A state diagram corresponding to the flow chart of the manufacturing method of the display substrate shown;

[0049] Figure 23 A structure diagram of a display panel according to some embodiments;

[0050] Figure 24 A structure diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0052] Unless otherwise required by context, the term "include" and its other forms, such as "including", "includes", and "include", are used in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" are intended to indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0053] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0054] In describing some embodiments, "coupled" and "connected", and their derivatives, can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact with each other. However, the terms "coupled" or "communicatively coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0055] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0056] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0057] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "upon" or "in response to a determination" or "in response to a detection of, depending on context. Similarly, the phrase "if determined" or "if detected [a stated condition or event]" is, optionally, interpreted as meaning "upon a determination" or "in response to a determination" or "upon a detection of [a stated condition or event]" or "in response to a detection of [a stated condition or event]", depending on context.

[0058] Additionally, use of "based on" means open and inclusive, in that a process, step, calculation, or other action "based on" one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited.

[0059] In some embodiments, as shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 1 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 1 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA.

[0060] As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA.

[0061] As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 1 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA.

[0062] As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 1 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA.

[0063] As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 1 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 2 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA. Figure 1 As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA.

[0064] As shown in FIG. 1A, the display panel 1000' can include a display area AA and a peripheral area BB located at least one side of the display area AA.

[0065] The multiple thin-film transistors 102 included in the driving circuit 101 can all be N-type transistors, or all be P-type transistors, or a combination of both, depending on the actual needs. Furthermore, the multiple thin-film transistors 102 included in the driving circuit 101 can all be low-temperature polysilicon (LTPS) transistors, or all be oxide transistors, or a combination of both.

[0066] For example, such as Figure 1 As shown, the display panel 1000' may further include multiple scan lines GL arranged along the horizontal direction X and multiple data lines DL extending along the vertical direction. Each scan line GL is electrically connected to a row of subpixels P, used to control the opening and closing of the corresponding row of subpixels P. Each data line DL is electrically connected to a column of subpixels P, used to provide data signals to the corresponding column of subpixels P.

[0067] For example, such as Figure 1 As shown, the display panel 1000' may also include multiple power supply voltage lines VDD extending in a vertical direction, each power supply voltage line VDD being electrically connected to at least one column of subpixels. Figure 1 The following example illustrates the connection between a power supply voltage line VDD and a column of subpixels P. The power supply voltage line VDD is used to provide a high-level voltage to the subpixels P during the display process of the display panel.

[0068] In order to simultaneously supply high-level voltage to the aforementioned multiple power supply voltage lines VDD, such as Figure 3 As shown, for example, the display panel 1000' may also include a power bus BL extending in the horizontal direction X.

[0069] For example, such as Figure 3 As shown, the display panel 1000' may also include a driver chip 300', which is electrically connected to the power bus BL and is used to provide a high-level voltage to the power bus BL.

[0070] For example, such as Figure 2 As shown, when the display panel 1000' includes a power bus BL, the active layer 104 of the thin-film transistor 102 at least partially overlaps with the power bus BL.

[0071] like Figure 4As shown, in the process of displaying by the display panel 1000' using the light emitting device 200', the light emitting device 200' is located at one side of the power bus BL, among the light emitted by the light emitting device 200', the light Q1 is emitted towards the direction where the power bus BL is located, and the light Q2 is emitted away from the direction of the power bus BL. The part of the power bus BL that is not blocked is easily irradiated by the light Q1. When the light Q1 is irradiated on the power bus BL, it will be reflected by the power bus BL and emitted away from the direction of the power bus BL. At this time, the light Q1 reflected by the power bus BL and the light Q2 are likely to interfere and cancel each other out, so that the part of the display corresponding to the power bus BL appears dark stripes, resulting in uneven display brightness and poor display effect.

[0072] To solve the above problems, some embodiments of the present disclosure provide a display substrate 100. As shown in Figure 5 and Figure 6 The display substrate 100 includes a substrate 10, a connection lead layer 20, a semiconductor layer 30, and a light shielding pattern 40. The connection lead layer 20 is disposed on the substrate 10, and the connection lead layer 20 includes a target connection lead 21. The semiconductor layer 30 is disposed on the side of the connection lead layer 20 away from the substrate 10, and the semiconductor layer 30 includes a semiconductor pattern 31. The light shielding pattern 40 is disposed on the side of the semiconductor layer 30 away from the substrate 10.

[0073] The target connection lead 21 includes a target part 211, and the orthogonal projection of the target part 211 on the substrate 10 is separated from the orthogonal projection of the semiconductor pattern 31 on the substrate 10, and the orthogonal projection of the target part 211 on the substrate 10 at least partially overlaps the orthogonal projection of the light shielding pattern 40 on the substrate 10.

[0074] In some examples, the material of the substrate 10 can include polyimide (PI).

[0075] It should be noted that in addition to the target connection lead 21, the connection lead layer 20 can also include other connection leads. The present disclosure does not limit the setting position and extension direction of the other connection leads.

[0076] The orthogonal projection of the target part 211 on the substrate 10 at least partially overlaps the orthogonal projection of the light shielding pattern 40 on the substrate 10, for example, the orthogonal projection of the target part 211 on the substrate 10 can completely overlap the orthogonal projection of the light shielding pattern 40 on the substrate 10.

[0077] Or, "the orthographic projection of the target portion 211 on the substrate 10 at least partially overlaps the orthographic projection of the light-shielding pattern 40 on the substrate 10", for example, can be that the orthographic projection of the target portion 211 on the substrate 10 only partially overlaps the orthographic projection of the light-shielding pattern 40 on the substrate 10.

[0078] It can be understood that, as shown in Figure 6 the display substrate 100 provided by the present disclosure can include the driving circuit 101 described in the above embodiments, and the semiconductor layer 30 can be the active layer 104 in the above thin film transistor 101.

[0079] In some embodiments of the present disclosure, the light-shielding pattern 40 is located on the side of the connecting lead layer 20 away from the substrate 10, and the orthographic projection of the light-shielding pattern 40 on the substrate 10 at least partially overlaps the orthographic projection of the target connecting lead 21 on the substrate 10. In this way, as shown in Figure 7 when the display substrate 100 is electrically connected with the light-emitting device 200, and the light-emitting device 200 is located on the side of the light-shielding pattern 40 away from the substrate 10, the light-shielding pattern 40 can block at least part of the light L of the light-emitting device 200 from being emitted to the target portion 211 of the target connecting lead 21, thereby avoiding the light of the light-emitting device from being irradiated to the target portion of the target connecting lead and further reflected by the target portion. As a result, the interference cancellation between the reflected light and the light I of the light-emitting device is avoided, and the problem of dark stripes appearing in the part of the display screen corresponding to the target connecting lead due to the interference cancellation of the light is improved, and the display effect of the display panel using the display substrate 100 is improved.

[0080] In some embodiments, the material of the light-shielding pattern 40 can include resin. In order to avoid the light of the light-emitting device 200 from being irradiated to the target portion 211 through the light-shielding pattern 40, carbon can be further included in the material of the light-shielding pattern 40, so as to absorb the light of the light-emitting device 200 emitted to the target portion 211 of the target connecting lead 21.

[0081] In some embodiments, the light transmittance of the light-shielding pattern 40 is less than or equal to 15%. In this way, the light transmittance of the light-shielding pattern 40 is small, and the light of the light-emitting device 200 can be better blocked by the light-shielding pattern 40, so as to avoid the light of the light-emitting device 200 from being irradiated to the target portion 211 of the target connecting lead 21 and further reflected by the target connecting lead. As a result, the interference cancellation between the reflected light and the light of the light-emitting device is avoided, and the problem of dark stripes appearing in the part of the display screen corresponding to the target connecting lead due to the interference cancellation of the light is improved, and the display effect of the display panel using the display substrate 100 is improved.

[0082] In some embodiments, as shown in Figure 6As shown, the thickness h of the light-shielding pattern 40 is approximately 1.7 microns in the direction Z perpendicular to the substrate 10. It can be understood that the thickness h of the light-shielding pattern 40 is not limited to this in the present disclosure, as long as the light transmittance of the light-shielding pattern 40 is less than or equal to 15%.

[0083] In some embodiments, as shown in Figure 8 and Figure 9 The display substrate 100 further includes a first pad 50. The first pad 50 is disposed on the side of the substrate 10 away from the connection lead layer 20. The substrate 10 includes an opening 11, and the first pad 50 is disposed on the side of the opening 11 away from the semiconductor layer 30, and the target connection lead 21 is electrically connected to the first pad 50 through the opening 11.

[0084] For example, the material of the first pad 50 can include metal.

[0085] It should be noted that the number, shape and size of the first pad 50 are not limited in the present disclosure. It can be understood that Figure 8 Only one possible arrangement of the first pad 50 is shown, which does not limit the arrangement of the first pad 50 in the present disclosure.

[0086] For example, as shown in Figure 8 and Figure 9 The connection lead layer 20 further includes a plurality of connection lines 22, which are electrically connected to the target connection lead 21, and the extension direction of the plurality of connection lines 22 intersects with the extension direction of the target connection lead 21.

[0087] The connection line 22 electrically connects the first pad 50 and the target connection lead 21 through the opening 11.

[0088] The material of the connection line 22 can be the same as that of the target connection lead 21.

[0089] For example, the first pad 50 can be used to electrically connect to the driving chip, so as to transmit the electrical signal provided by the driving chip to the target connection lead 21.

[0090] In this way, after the display substrate 100 is electrically connected to the driving chip, there is no need to provide additional leads on the side of the display substrate 100 to connect the target connection lead 21 and the driving chip, thereby facilitating the reduction of the manufacturing cost of the display panel and improving the use stability of the display panel using the display substrate 100.

[0091] In some examples, as shown in Figure 9 The display substrate 100 can further include a separation layer 51. The separation layer 51 is disposed on the side of the first pad 50 away from the substrate 10.

[0092] The separation layer 51 can have a peelable metal feature. In this way, during the process of preparing the display substrate 100, the separation layer 51 can be formed on a carrier substrate first, and then the first pad 50 can be formed on the separation layer 51. Thus, when the display substrate 100 is subsequently peeled from the carrier substrate, the first pad 50 is separated from the carrier substrate, thereby protecting the first pad 50.

[0093] In some examples, as shown in FIG. 1, the display substrate 100 can further include a first insulating layer 52. The first insulating layer 52 is disposed between the first pad 50 and the substrate 10. Figure 9

[0094] In some embodiments, as shown in FIG. 2, the display substrate 100 further includes an interlayer dielectric layer 60 and a filling portion 70. The interlayer dielectric layer 60 is disposed on a side of the semiconductor layer 30 away from the substrate 10. The interlayer dielectric layer 60 has a recess 61 corresponding to the portion of the opening 11. The filling portion 70 is disposed on a side of the interlayer dielectric layer 60 away from the substrate 10, and the filling portion 70 is located in the recess 61. Figure 10 The light-shielding pattern 40 is disposed on a side of the interlayer dielectric layer 60 away from the substrate 10, and the material of the light-shielding pattern 40 is the same as that of the filling portion 70.

[0095]

[0096] For example, the material of the interlayer dielectric layer 60 can be an insulating material, such as silicon oxide or silicon nitride.

[0097] In some embodiments of the present disclosure, the filling portion 70 is formed in the recess 61 of the interlayer dielectric layer 60, thereby effectively reducing the height difference of the display substrate 100 at the corresponding recess 61, and facilitating the formation of subsequent film layers on a side of the interlayer dielectric layer 60 away from the substrate 10.

[0098] At the same time, since the light-shielding pattern 40 and the filling portion 70 are both disposed on a side of the interlayer dielectric layer 60 away from the substrate 10, and the material of the light-shielding pattern 40 is the same as that of the filling portion 70, the light-shielding pattern 40 can be formed synchronously with the filling portion 70, without the need to add additional film layers and mask plates to prepare the light-shielding pattern 40, thereby saving costs.

[0099] In some embodiments, as shown in FIG. 3, the display substrate 100 can further include a gate metal layer 62 disposed on a side of the second gate insulating layer 107 away from the substrate 10. The interlayer dielectric layer 60 can be disposed on a side of the gate metal layer 62 away from the substrate 10. Figure 10

[0100] For example, the upper plate of the storage capacitor 103 can be disposed in the gate metal layer 62.

[0101] In some embodiments, as shown in FIG. 4, the display substrate 100 can further include a gate metal layer 62 disposed on a side of the second gate insulating layer 107 away from the substrate 10. The interlayer dielectric layer 60 can be disposed on a side of the gate metal layer 62 away from the substrate 10. Figure 10 ​​​As shown, the display substrate 100 further comprises a first source-drain conductive layer 80 disposed on the side of the interlayer dielectric layer 60 away from the substrate 10. The first source-drain conductive layer 80 comprises a first source-drain conductive pattern 81, and a gap d1 exists between the first source-drain conductive pattern 81 and the light-shielding pattern 40.

[0102] For example, the gap d1 can have a value of 2-4 microns.

[0103] For example, as shown in FIG. 1B, the first source-drain conductive pattern 81 can comprise a source electrode 108 and a drain electrode 109 of a thin-film transistor 102. Figure 10

[0104] For example, as shown in FIG. 1B, the first source-drain conductive pattern 81 can comprise a source electrode 108 and a drain electrode 109 of a thin-film transistor 102. Figure 10

[0105] In this way, the first source-drain conductive pattern 81 and the light-shielding pattern 40 are both located on the side of the connection lead layer 20 away from the substrate 10, and the first source-drain conductive pattern 81 and the light-shielding pattern 40 are spaced apart by a small distance, so the first source-drain conductive pattern 81 and the light-shielding pattern 40 can both be used to block light emitted by the light-emitting device from reaching the target portion 211 of the target connection lead 21, thereby further avoiding the light emitted by the light-emitting device from being incident on the target portion 211, being reflected by the target portion 211, and interfering destructively with the light emitted by the light-emitting device, further improving the problem of dark lines appearing in the portion of the display screen corresponding to the target connection lead due to the interference and destructive interference of the light, and improving the display effect of the display panel using the display substrate 100.

[0106] In some embodiments, as shown in FIG. 1B, the display substrate 100 further comprises a shielding pattern 90. The shielding pattern 90 is disposed between the connection lead layer 20 and the semiconductor layer 30. Figure 11

[0107] In this way, the first source-drain conductive pattern 81 and the light-shielding pattern 40 are both located on the side of the connection lead layer 20 away from the substrate 10, and the first source-drain conductive pattern 81 and the light-shielding pattern 40 are spaced apart by a small distance, so the first source-drain conductive pattern 81 and the light-shielding pattern 40 can both be used to block light emitted by the light-emitting device from reaching the target portion 211 of the target connection lead 21, thereby further avoiding the light emitted by the light-emitting device from being incident on the target portion 211, being reflected by the target portion 211, and interfering destructively with the light emitted by the light-emitting device, further improving the problem of dark lines appearing in the portion of the display screen corresponding to the target connection lead due to the interference and destructive interference of the light, and improving the display effect of the display panel using the display substrate 100.

[0108] ​​​It can be understood that "the orthogonal projection of the semiconductor pattern 31 on the substrate 10 is located inside the orthogonal projection of the shielding pattern 90 on the substrate 10" includes not only the case where the orthogonal projection of the semiconductor pattern 31 on the substrate 10 is located inside the orthogonal projection of the shielding pattern 90 on the substrate 10, and there is a distance between the boundary of the orthogonal projection of the semiconductor pattern 31 on the substrate 10 and the boundary of the orthogonal projection of the shielding pattern 90 on the substrate 10, but also the case where the orthogonal projection of the semiconductor pattern 31 on the substrate 10 is located inside the orthogonal projection of the shielding pattern 90 on the substrate 10, and at least a portion of the boundary of the orthogonal projection of the semiconductor pattern 31 on the substrate 10 overlaps with the boundary of the orthogonal projection of the shielding pattern 90 on the substrate 10.

[0109] Among them, "the orthographic projection of the target portion 211 of the target connection lead 21 on the substrate 10 is separated from the orthographic projection of the shielding pattern 90 on the substrate 10", that is, the part of the target connection lead 21 that does not overlap with the shielding pattern 90 is the target portion 211.

[0110] For example, the material of the shielding pattern 90 may include metal.

[0111] By using this configuration, on the one hand, the shielding pattern 90 can mitigate the impact of the electric field generated around the target connection lead 21 on the thin-film transistor 102 during signal transmission, thus preventing abnormal display of the light-emitting device. On the other hand, the shielding pattern 90 can block the target connection lead 21, preventing the light emitted by the light-emitting device 200 from shining on other parts of the target connection lead 21 (excluding the target portion 211) after the display substrate and the light-emitting device 200 are electrically connected. This avoids the light from being reflected by other parts of the target connection lead 21, thus preventing interference and cancellation between the reflected light and the light from the light-emitting device 200. This improves the problem of dark stripes appearing in the display screen corresponding to the target connection lead 21 due to light interference and cancellation, thereby improving the display effect of the display panel using this display substrate.

[0112] In some embodiments, such as Figure 11 As shown, the display substrate 100 may further include a second insulating layer 91 disposed between the shielding pattern 90 and the connecting lead layer 20, and a third insulating layer 92 disposed between the shielding pattern 90 and the semiconductor layer 30.

[0113] Thus, by providing the second insulating layer 91, the shielding pattern 90 and the connecting lead layer 20 can be insulated from each other, and by providing the third insulating layer 92, the shielding pattern 90 and the semiconductor layer 30 can be insulated from each other.

[0114] In some embodiments, such as Figure 12As shown, the target portion 211 of the target connecting lead 21 and the light shielding pattern 40 extend along a setting direction O. In a direction perpendicular to the setting direction O, the size of the target portion 211 is smaller than the size of the light shielding pattern 40, and there is a spacing between the boundary of the orthographic projection of the target portion 211 on the substrate 10 and the boundary of the orthographic projection of the light shielding pattern 40 on the substrate 10.

[0115] It can be understood that, when the target portion 211 extends along the setting direction O, the target connecting lead 21 also extends along the setting direction O.

[0116] In some embodiments, as shown in Figure 12 the setting direction O is parallel to the horizontal direction X, that is, the setting direction O can be the row direction of the arrangement of sub-pixels in the display panel. Based on this, the "direction perpendicular to the setting direction O" can be the vertical direction Y.

[0117] In other embodiments, the setting direction O can be parallel to the vertical direction Y, that is, the setting direction O can be the column direction of the arrangement of sub-pixels in the display panel. Based on this, the "direction perpendicular to the setting direction O" can be the horizontal direction X.

[0118] By such an arrangement, the light shielding pattern 40 can better shield the target portion 211 of the target connecting lead 21, thereby better avoiding the light emitted by the light emitting device 200 from being irradiated onto the target portion 211 of the target connecting lead 21 after the display substrate 100 is electrically connected with the light emitting device 200, being reflected by the target portion 211, and further avoiding the interference and cancellation between the light emitted by the light emitting device 200 in the direction away from the substrate 10, so as to avoid the problem of dark stripes in the position corresponding to the target portion 211 in the display panel, and improve the display effect of the display panel using the display substrate 100.

[0119] In some embodiments, as shown in Figure 13 and Figure 14 the display substrate 100 further includes a second pad 110, which is arranged on the side of the light shielding pattern 40 away from the substrate 10. The second pad 110 is used for electrically connecting the light emitting device.

[0120] Herein, in a direction Z perpendicular to the substrate 10, the ratio of the distance d2 from the target portion 211 of the target connecting lead 21 to the second pad 110 to the distance d3 from the target portion 211 to the light shielding pattern 400 is m.

[0121] In a direction Y perpendicular to the setting direction X, the ratio of the distance d4 between the two adjacent second pads 110 to the distance d5 between the boundary of the orthographic projection of the target portion 211 on the substrate and the boundary of the orthographic projection of the light shielding pattern 40 on the substrate is n, and m is equal to n.

[0122] It is worth noting that "m is equal to n" can include the case where m and n are exactly equal, and also include the case where m and n are approximately equal. For example, when m and n are approximately equal, the difference between m and n is not more than 0.01.

[0123] It can be understood that the distance d4 between the two adjacent second pads 110 is the distance between the two second pads 110 respectively connected to two different light emitting devices.

[0124] For example, in the direction Z perpendicular to the substrate 10, the distance d2 from the target portion 211 of the target connection lead 21 to the second pad 110 can be 6.4 microns, and the distance d3 from the target portion 211 to the light shielding pattern 40 can be 1.6 microns. In the direction Y perpendicular to the set direction X, the distance d4 between the two adjacent second pads 110 can be 176 microns, and at this time, the distance d5 between the boundary of the orthographic projection of the target portion 211 and the boundary of the orthographic projection of the light shielding pattern 40 can be 45 microns.

[0125] By setting in this way, the light shielding pattern 40 can not only shield the light emitted by the light emitting device overlapping with the target connection lead, but also block the light emitted by the light emitting device not overlapping with the target connection lead, thereby better avoiding the problem of dark stripes in the display screen corresponding to the target connection lead, and improving the display effect of the display panel using the display substrate 100.

[0126] For example, as shown in Figure 13 The display substrate 100 can further include a fourth insulating layer 111 disposed on the side of the second pad 110 away from the substrate 10. The fourth insulating layer 111 can include a plurality of openings to expose part of the second pad 110.

[0127] In some embodiments, as shown in Figure 15 The display substrate 100 further includes a first voltage line 120. The first voltage line 120 is disposed on the side of the connection lead layer 20 away from the substrate 10, and is electrically connected to the target connection lead 21.

[0128] For example, the first voltage line 120 can be the power voltage line VDD described in the above embodiments, for providing a high-level voltage to the sub-pixel P during the display process of the display panel.

[0129] Based on this, the target connection lead 21 can be the power bus BL described in the above embodiments, for simultaneously providing a high-level voltage to the plurality of power voltage lines VDD (the first voltage line 120).

[0130] In some embodiments, as shown in Figure 16As shown, the display substrate 100 also includes a second source / drain conductive layer 130, which includes a first voltage line 120. The first voltage line 120 is disposed on the side of the light-shielding pattern 40 away from the substrate 10.

[0131] For example, such as Figure 16 As shown, the second source / drain conductive layer 130 can be located between the first source / drain conductive layer 80 and the second pad 110.

[0132] The second source-drain conductive layer 130 may include not only the first voltage line 120, but also a connecting electrode 131. The connecting electrode 131 may be used to connect the source 108 or drain 109 in the first source-drain conductive layer 80 to the second pad 110.

[0133] Based on this, for example, such as Figure 16 As shown, the display substrate 100 may further include a fifth insulating layer 132 disposed between the first source / drain conductive layer 80 and the second source / drain conductive layer 130, and a sixth insulating layer 133 and a seventh insulating layer 134 disposed between the second source / drain conductive layer 130 and the second pad 110.

[0134] In some embodiments, such as Figure 15 As shown, the orthographic projection of the first voltage line 120 on the substrate 10 and the orthographic projection of the target connection lead 21 on the substrate 10 intersect. In this way, the distance between the target connection lead 21 and the multiple first voltage lines 120 is short, which facilitates the electrical connection of the target connection lead 21 to the multiple first voltage lines 120, thereby simultaneously providing voltage to the multiple first voltage lines 120.

[0135] like Figure 17 As shown in some embodiments of this disclosure, a method for fabricating a display substrate 100 is provided, including:

[0136] S1, such as Figure 18 As shown, a first pad 50 is formed on a carrier plate 01, and a substrate 10 is formed on the side of the first pad 50 away from the carrier plate 01. The substrate 10 includes an opening 11 located on the side of the first pad 50 away from the carrier plate 01.

[0137] For example, a separation layer 51 may also be formed on the carrier plate 01 before the first liner 50 is formed on the carrier plate 01.

[0138] S2, such as Figure 19 As shown, a connection lead layer 20 is formed on the substrate 10. The connection lead layer 20 includes a target connection lead 21. The target connection lead 21 is electrically connected to the first pad 50 through the opening 11.

[0139] For example, such as Figure 18As shown, the connection lead layer 20 can further include a plurality of connection lines 22, which are electrically connected with the target connection lead 21.

[0140] S3, as shown in the figure, a semiconductor layer 30 is formed on the side of the connection lead layer 20 away from the substrate 10, and the semiconductor layer 30 includes a semiconductor pattern 31. Figure 20

[0141] S4, as shown in the figure, an interlayer dielectric layer 60 is formed on the side of the semiconductor layer 30 away from the substrate 10. The interlayer dielectric layer 60 has a recess 61 corresponding to the part of the opening 11. Figure 21

[0142] S5, as shown in the figure, a light shielding pattern 40 and a filling part 70 are formed on the side of the interlayer dielectric layer 60 away from the substrate 10, and the filling part 70 is located in the recess 61. Figure 22

[0143] The target connection lead 21 includes a target part 211, and the orthographic projection of the target part 211 on the substrate 10 is separated from the orthographic projection of the semiconductor pattern 31 on the substrate 10, and the orthographic projection of the target part 211 on the substrate 10 at least partially overlaps the orthographic projection of the light shielding pattern 40 on the substrate 10.

[0144] It should be noted that after the display substrate 100 is formed on the carrier, the display substrate 100 needs to be peeled off.

[0145] The display substrate 100 obtained by the manufacturing method of the display substrate 100 provided by the above-mentioned embodiments of the present disclosure has the light shielding pattern 40 located on the side of the connection lead layer 20 away from the substrate 10, and the orthographic projection of the light shielding pattern 40 on the substrate 10 at least partially overlaps the orthographic projection of the target part 211 of the target connection lead 21 on the substrate 10. In this way, when the display substrate 100 is electrically connected with the light emitting device 200, and the light emitting device 200 is located on the side of the light shielding pattern 40 away from the substrate 10, the light shielding pattern 40 can block at least part of the light emitted by the light emitting device 200 from being directed to the target part 211 of the target connection lead 21, thereby avoiding the light emitted by the light emitting device 200 from being irradiated onto the target part 211 of the target connection lead 21 and further being reflected by the target part 211, and thus avoiding the interference and cancellation between the reflected light and the light emitted by the light emitting device, and further improving the problem of dark lines appearing in the part of the display screen corresponding to the target connection lead due to the interference and cancellation of the light, and improving the display effect of the display panel using the display substrate 100.

[0146] ​​​It is worth pointing out that in the manufacturing method of the display substrate 100 provided by some embodiments of the present disclosure, the light shielding pattern 40 can be formed synchronously with the filling part 70, so that no additional film layer needs to be added in the display substrate 100, and no additional mask plate needs to be added. That is, some embodiments of the present disclosure can improve the problem of dark stripes appearing in the display picture and improve the display effect of the display panel without increasing the cost.

[0147] As shown in Figure 23 some embodiments of the present disclosure provide a display panel 1000, which comprises the display substrate 100 described in any of the above embodiments, a light emitting device 200 and a driving chip 300.

[0148] The light emitting device 200 is arranged on the side of the film layer where the light shielding pattern 40 of the display substrate 100 is away from the substrate 10 of the display substrate 100, and is electrically connected with the display substrate 100.

[0149] The driving chip 300 is arranged on the side of the substrate 10 away from the light shielding pattern 40, and is electrically connected with the target connection lead 21 of the display substrate 100.

[0150] The display panel 1000 provided by the present disclosure can achieve the same beneficial effects as the display substrate 100 provided by any of the above embodiments, and will not be repeated here.

[0151] As shown in Figure 24 some embodiments of the present disclosure provide a display device 2000, which comprises the display panel 1000 described in any of the above embodiments.

[0152] The display device 2000 described above can be any component with display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc.

[0153] The display device 2000 provided by the present disclosure can achieve the same beneficial effects as the display substrate 100 provided by any of the above embodiments.

[0154] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a connection lead layer disposed on the substrate, comprising a target connection lead; a semiconductor layer disposed on a side of the connection lead layer away from the substrate, comprising a semiconductor pattern; a light shielding pattern disposed on a side of the semiconductor layer away from the substrate; wherein the target connection lead comprises a target part, a projection of the target part on the substrate is separated from a projection of the semiconductor pattern on the substrate, and the projection of the target part on the substrate at least partially overlaps with a projection of the light shielding pattern on the substrate; the display panel further comprises: a first pad disposed on a side of the substrate away from the connection lead layer; wherein the substrate comprises an opening, the first pad is disposed on a side of the opening away from the semiconductor layer, and the target connection lead is electrically connected to the first pad through the opening; a light emitting device disposed on a side of a film layer where the light shielding pattern is located away from the substrate; a second pad disposed on a side of the light shielding pattern away from the substrate; the second pad is electrically connected to the light emitting device.

2. The display panel of claim 1, wherein, Further comprising: an interlayer dielectric layer disposed on a side of the semiconductor layer away from the substrate; a portion of the interlayer dielectric layer corresponding to the opening has a recess; a filling part disposed on a side of the interlayer dielectric layer away from the substrate, and the filling part is located in the recess; wherein the light shielding pattern is disposed on a side of the interlayer dielectric layer away from the substrate, and the material of the light shielding pattern is the same as that of the filling part.

3. The display panel of claim 2, wherein, Further comprising: a first source-drain conductive layer disposed on a side of the interlayer dielectric layer away from the substrate; the first source-drain conductive layer comprises a first source-drain conductive pattern, and there is a gap between the first source-drain conductive pattern and the light shielding pattern.

4. The display panel of claim 1, wherein, Further comprising: a shielding pattern disposed between the connection lead layer and the semiconductor layer; wherein a projection of the semiconductor pattern on the substrate is located inside a projection of the shielding pattern on the substrate, and a projection of the target part of the target connection lead on the substrate is separated from a projection of the shielding pattern on the substrate.

5. The display panel of claim 1, wherein, The target part of the target connection lead and the light shielding pattern extend along a set direction; in a direction perpendicular to the set direction, a size of the target part is smaller than a size of the light shielding pattern, and there is a gap between a boundary of the projection of the target part on the substrate and a boundary of the projection of the light shielding pattern on the substrate.

6. The display panel of claim 5, wherein, in a direction perpendicular to the substrate, a ratio of a distance from the target part of the target connection lead to the second pad to a distance from the target part to the light shielding pattern is m; in a direction perpendicular to the set direction, a distance between two adjacent second pads is in a ratio n to a distance between the boundary of the projection of the target part on the substrate and the boundary of the projection of the light shielding pattern on the substrate, and m is equal to n.

7. The display panel of claim 1, wherein, Further comprising: a first voltage line disposed on a side of the connection lead layer away from the substrate and electrically connected to the target connection lead.

8. The display panel of claim 7, wherein, Further comprising: The second source-drain conductive layer includes the first voltage line; and the first voltage line is disposed on a side of the light-shielding pattern away from the substrate.

9. The display panel of claim 7, wherein, A projection of the first voltage line on the substrate and a projection of the target connecting lead on the substrate intersect.

10. The display panel of any one of claims 1-9, wherein, The material of the light-shielding pattern includes resin.

11. The display panel of any one of claims 1-9, wherein, The light transmittance of the light-shielding pattern is less than or equal to 15%.

12. The display panel of any one of claims 1-9, wherein, Further comprising: A driving chip disposed on a side of the substrate away from the light-shielding pattern and electrically connected to the target connecting lead.

13. A method for manufacturing a display panel, characterized by, Further comprising: Forming a first pad on a carrier substrate, and forming a substrate on a side of the first pad away from the carrier substrate; The substrate includes an opening located on a side of the first pad away from the carrier substrate; Forming a connecting lead layer on the substrate, the connecting lead layer including a target connecting lead; the target connecting lead being electrically connected to the first pad through the opening; Forming a semiconductor layer on a side of the connecting lead layer away from the substrate, the semiconductor layer including a semiconductor pattern; Forming an interlayer dielectric layer on a side of the semiconductor layer away from the substrate; A portion of the interlayer dielectric layer corresponding to the opening has a recess; Forming a light-shielding pattern and a filling portion on a side of the interlayer dielectric layer away from the substrate, the filling portion being located in the recess; Forming a second pad and a light-emitting device on a side of the light-shielding pattern in sequence, the second pad being electrically connected to the light-emitting device; The target connecting lead includes a target portion, a projection of the target portion on the substrate and a projection of the semiconductor pattern on the substrate are separated, and a projection of the target portion on the substrate and a projection of the light-shielding pattern on the substrate at least partially overlap.

14. A display device comprising: Further comprising: The display panel according to any one of claims 1-12.

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