Thread scheduling method, processor and electronic device

Abstract

A thread scheduling method, a processor and an electronic device. The thread scheduling method comprises: in response to receiving a resource allocation request for a thread group, determining whether private storage resource allocation can be performed on the thread group independently of shared storage resource; in response to determining that private storage resource allocation can be performed on the thread group independently of shared storage resource, allocating private storage resource for the thread group to the thread group; and in response to the shared storage resource meeting the allocation requirement of the thread group, allocating shared storage resource for the thread group to the thread group. The thread scheduling method divides the resource allocation process into two steps, separates the private storage resource allocation and the shared storage resource allocation into two independent processes, postpones the allocation of the shared storage resource that temporarily does not meet the allocation requirement, and allocates the private storage resource in advance, so as to achieve the purpose of allocating resources in advance, thereby improving the running efficiency and shortening the time for completing the entire task.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a thread scheduling method, a processor and an electronic device. BACKGROUND

[0002] A graphics processing unit (GPU), also known as a display core, a visual processor, or a display chip, is a microprocessor specially designed for image and graphics related computing work on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). The GPU can convert the display information required by the computer system and provide a horizontal scanning signal to the display, thereby controlling the display to display correctly. The GPU is an important element connecting the display and the computer motherboard (the computer motherboard includes, for example, a central processing unit), and is also one of the important devices for realizing "man-machine dialogue". SUMMARY

[0003] At least one embodiment of the present disclosure provides a thread scheduling method, comprising: in response to receiving a resource allocation request for a thread group, determining whether private storage resources can be allocated to the thread group independently of shared storage resources; in response to determining that private storage resources are allocated to the thread group independently of shared storage resources, allocating private storage resources for the thread group to the thread group; and in response to the shared storage resources meeting the allocation needs of the thread group, allocating shared storage resources for the thread group to the thread group.

[0004] For example, the thread scheduling method provided by at least one embodiment of the present disclosure further comprises: after allocating private storage resources for the thread group to the thread group, recording the thread group as a partially allocated thread group in a to-be-allocated thread group set; wherein the to-be-allocated thread group refers to a thread group that has completed private storage resource allocation and has not yet performed shared storage resource allocation.

[0005] For example, in the thread scheduling method provided by at least one embodiment of the present disclosure, allocating shared storage resources for the thread group to the thread group comprises: based on the allocation information of the thread group as a to-be-allocated thread group, allocating shared storage resources for the thread group to the thread group.

[0006] For example, in the thread scheduling method provided by at least one embodiment of the present disclosure, determining whether private storage resources can be allocated to the thread group independently of shared storage resources comprises: according to the resource allocation request, determining whether private storage resources can be allocated to the thread group and whether shared storage resources can be allocated to the thread group; and in response to private storage resources being allocable to the thread group and shared storage resources being unallocable to the thread group, determining that private storage resources are allocated to the thread group independently of shared storage resources.

[0007] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, determining to allocate private storage resources to the thread group independently of shared storage resources comprises: determining whether the number of partial allocation state operations is less than a preset threshold, wherein the partial allocation state operation refers to an operation that has completed private storage resource allocation and has not performed shared storage resource allocation; and in response to the number of partial allocation state operations being less than the preset threshold, determining to allocate private storage resources independently of shared storage resources.

[0008] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, determining whether the number of partial allocation state operations is less than a preset threshold comprises: determining whether the number of members of the set of to-be-allocated thread groups is less than a preset threshold.

[0009] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, the allocation information of the to-be-allocated thread group in the partial allocation state is stored in the information allocation memory, and determining whether the number of members of the set of to-be-allocated thread groups is less than a preset threshold comprises: checking whether the number of items of allocation information corresponding to the set of to-be-allocated thread groups in the information allocation memory is less than a preset threshold, wherein the number of items of allocation information corresponding to the set of to-be-allocated thread groups is equal to the number of members of the set of to-be-allocated thread groups.

[0010] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, the information allocation memory comprises a first-in-first-out memory, and the depth of the first-in-first-out memory is greater than or equal to the preset threshold.

[0011] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, the preset threshold is greater than or equal to 2.

[0012] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, recording the thread group as the to-be-allocated thread group in the partial allocation state comprises: notifying a control unit of the allocation information and writing the allocation information into the information allocation memory.

[0013] For example, in the thread scheduling method provided by at least one of the embodiments of the present disclosure, the allocation information comprises an address and a size of the private storage resource for the thread group and a resource identifier to which the thread group is allocated.

[0014] For example, the thread scheduling method provided by at least one of the embodiments of the present disclosure further comprises: after allocating the shared storage resource for the thread group to the thread group, notifying the control unit of the shared storage resource attribute allocated to the thread group and deleting the allocation information corresponding to the resource allocation request in the information allocation memory.

[0015] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, determining whether private storage resources can be allocated to the thread group independently of shared storage resources further includes: in response to the fact that neither private storage resources nor shared storage resources can be allocated to the thread group, or in response to the fact that the number of partial allocation state operations is greater than or equal to a preset threshold, determining that private storage resource allocation independent of shared storage resources will not be performed.

[0016] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, determining whether private storage resources can be allocated to a thread group and whether shared storage resources can be allocated to a thread group according to a resource allocation request includes: checking the current resource status through a resource mask matrix, and determining whether the private storage resources and shared storage resources meet the requirements of the resource allocation request based on the current resource status.

[0017] For example, the thread scheduling method provided in at least one embodiment of this disclosure further includes: monitoring a resource mask matrix, determining whether any shared storage resources have been released, and determining whether the shared storage resources meet the allocation needs of the thread group.

[0018] For example, in at least one embodiment of the thread scheduling method provided in this disclosure, the thread scheduling method is used for thread scheduling of kernel programs.

[0019] At least one embodiment of this disclosure provides a processor, including: a processing unit configured to execute a thread group; and a resource manager configured to allocate private storage resources to the thread group when it is determined that the allocation of private storage resources to the thread group is independent of shared storage resources.

[0020] For example, in a processor provided in at least one embodiment of this disclosure, the processing unit includes: a control unit configured to provide allocation information of a partially allocated thread group to a resource manager.

[0021] For example, in a processor provided in at least one embodiment of this disclosure, the resource manager is further configured to: in response to receiving a resource allocation request for a thread group, determine whether it is possible to allocate private storage resources to the thread group independently of shared storage resources; after allocating private storage resources to the thread group, in response to the shared storage resources meeting the allocation needs of the thread group, allocate shared storage resources for the thread group to the thread group.

[0022] For example, in the processor provided in at least one embodiment of this disclosure, the processing unit further includes a plurality of vector processing units and shared memory; each vector processing unit includes a vector register and a scalar register, which are provided as private storage resources to the thread group; the shared memory is provided as a shared storage resource to the thread group.

[0023] At least one embodiment of this disclosure provides an electronic device including a processor provided in at least one embodiment of this disclosure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 This is a schematic diagram of the structure of a shader processing unit;

[0026] Figure 2A This is a schematic diagram of a vector register mask matrix;

[0027] Figure 2B A schematic diagram of a scalar register mask matrix;

[0028] Figure 2C A schematic diagram of a mask matrix for shared storage resources;

[0029] Figure 3A A timing diagram illustrating thread allocation and kernel program execution is shown.

[0030] Figure 3B A timing diagram illustrating thread allocation and kernel program execution provided in at least one embodiment of this disclosure is shown.

[0031] Figure 4A A flowchart of a thread scheduling method provided in at least one embodiment of this disclosure is shown;

[0032] Figure 4B At least one embodiment of the present disclosure is shown. Figure 4A The flowchart of step S401 in the text;

[0033] Figure 4C A flowchart illustrating an exemplary thread scheduling method provided in some embodiments of this disclosure is shown.

[0034] Figure 5 A schematic diagram of a processor provided in at least one embodiment of the present disclosure is shown;

[0035] Figure 6A A schematic diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0036] Figure 6B A schematic diagram of another electronic device provided for at least one embodiment of this disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0040] Figure 1 This is a schematic diagram of the structure of a shader processing unit (SPU) 100.

[0041] like Figure 1 As shown, the SPU 100 is used to execute tasks such as GPU kernel programs, and may include multiple Vector Execution Units (VEUs) 101, Thread Cluster Shared Memory (TCSM) 102, Shader Control Units (SCUs) 103, Shader Resource Managers (SRMs) (not shown in the figure), and Command Interface (CI) modules (not shown in the figure). It should be noted that... Figure 1 Four VEU 101s are illustrated, but this does not constitute a limitation on the embodiments of this disclosure. The number of VEU 101s can be any number, such as two, three, five, etc., which can be determined according to actual needs.

[0042] In parallel computing within the kernel, computational tasks are typically executed through multiple threads. A thread is the smallest unit of execution in GPU computation, capable of performing a single logically meaningful operation. A Thread Cluster (TC) is the smallest thread group unit issued by the Thread Integration Center (CI), containing a maximum of 2048 threads. A Thread Platoon (TP) is the smallest thread group unit processed by the Thread Management Replication (SRM), containing a maximum of 64 threads. The GPU kernel executes within a VEU101. Each VEU101 includes a Vector Register (VR) and a Scalar Register (SR). Each VR contains 64 32-bit registers, each individual 32-bit register used by one thread within a TP. A TP can request multiple VRs as needed. Each SR is a 32-bit register, used by all threads within a TP. A TP can also request multiple SRs as needed. Different TPs belonging to the same TC can share data through a TCSM, which acts as a cache for a TC.

[0043] The SCU 103, acting as the control unit of the SPU 100, is responsible for tasks such as instruction fetching and decoding during the execution of the GPU kernel program. The CI (Computer Interface) is responsible for unpacking the issued tasks, thereby scheduling the unpacked TCs and related information to different SRMs for splitting. The SRM is used to split the TCs sent by the CI into individual TPs, allocate each TP to a different VEU, and allocate corresponding hardware resources for each TP. The GPU kernel program fetches and decodes instructions through the SCU, and then the SRM obtains TPs by splitting the TCs sent by the CI, executing the TP as the smallest unit on the VEU within the SPU. Only after the SRM has allocated the hardware resources for the selected SPU and VEU that meet the TP's hardware resource requirements and notified the SCU that the hardware resource allocation is complete can the kernel program for that TP be fetched, decoded, and executed by the SCU from memory.

[0044] Hardware resources include private storage resources and shared storage resources. Private storage resources belonging to a TP include VR, SR, etc., while shared storage resources belonging to all TPs within the same TC include TCSM, etc. Each VEU stores its own private mask table in the SRM to record the usage of its private storage resources. Multiple mask tables recording the usage of private storage resources for multiple VEUs form a mask matrix. Figure 2A The mask matrix for VR in private storage resources is shown. Figure 2B The mask matrix of SR in the private storage resource is shown. For example... Figure 2Aand Figure 2B As shown, N-1 VEUs correspond to N-1 VR mask tables and N-1 SR mask tables. The N-1 VR mask tables form a VR mask matrix, and the N-1 SR mask tables form an SR mask matrix. Here, N ≥ 2 and is an integer. Similarly, each SPU also has its own private mask table to record the usage of shared storage resources belonging to that SPU. Multiple mask tables also form a mask matrix. Figure 2C The mask matrix for TCSM in shared storage resources is shown. For example... Figure 2C As shown, M-1 SPUs correspond to M-1 TCSM mask tables, and these M-1 TCSM mask tables form a TCSM mask matrix. Here, M ≥ 2 and is an integer.

[0045] exist Figure 2A , Figure 2B , Figure 2C In the mask matrix, the vertical axis represents the SPU / VEU number. For example, if the vertical axis is VEU_0, it means that the row with the vertical axis VEU_0 stores the mask table of the private storage resources corresponding to the VEU with the number VEU_0. When a TP's resource request receives a response from the SRM, all hardware resources allocated to that TP are marked as in use in the corresponding resource mask table of the VEU allocated to that TP. That is, the status of the corresponding resource is marked as in use in the mask table. In this way, subsequent TPs cannot use the occupied resources, thereby avoiding resource conflicts and duplicate allocation. For example, in one example, assuming each VEU has 100 VRs, the first TP is allocated 20 VRs, and subsequent TPs can only allocate from the remaining 80 VRs.

[0046] When a TP requests hardware resources from the SRM, the SRM iterates through the mask matrices of all hardware resources (e.g., the mask matrices of VR, SR, and TCSM). The SRM only responds to the TP's hardware resource request if all available hardware resources can meet its requirements. Once the TP's hardware resource request is responded to, the SRM assigns a VEU on an SPU that meets its hardware resource requirements to execute the kernel program, and selects the shared memory resource number allocated to the SPU and the private memory resource number allocated to the VEU. Simultaneously, the SRM stores the hardware resource attributes (address and size of the hardware resources) used by the TP in a memory location.

[0047] Shared storage resources are hardware resources belonging to the SPU and shared by all TPs within a TC. Therefore, all TPs in this TC must be allocated to the same SPU to ensure that shared storage resources can be used. When searching for all VEUs that meet the criteria, the needs of subsequent TPs in the same TC must be considered, not just the currently allocated TPs, to prevent subsequent TPs from not having enough free resources. Therefore, from the SRM's perspective, the first TP in a TC has the largest hardware resource requirement. As long as there are available VEUs and SPUs to meet the first TP's needs, all TPs in the entire TC can be allocated sequentially; conversely, the splitting of the entire TC will be paused until the TPs allocated to the previous TC finish execution and release sufficient hardware resources before allocation continues.

[0048] When the SCU retrieves an instruction from memory and performs decoding, and determines that the instruction is the last instruction of the kernel program (i.e., the END instruction) based on the decoding result, the SCU will notify the SRM to release all resources occupied by the TP after the END instruction is executed. After receiving the SPU number, VEU number, and TP number allocated to the TP from the SCU, the SRM saves the memory location of the hardware resources used by the TP based on these three numbers, obtains the hardware resource attributes used by the TP, and then releases the hardware resources according to the hardware resource attributes and updates the hardware resource mask matrix (i.e., sets the corresponding hardware resources in the mask table of the resource mask matrix to unused). For shared memory resources, the SRM will only release the shared memory resources according to the hardware resource attributes stored in memory when the SCU notifies the SRM that the currently completed TP is the last TP in the entire TC. All TPs in a TC can be allocated consecutively if all the hardware resources required by the first TP meet the conditions. If any resource does not meet the conditions, all TPs in the entire TC cannot be allocated.

[0049] However, in different kernel programs, TCSM resources may only be used in the final part of the kernel program. Therefore, a TP does not need to use TCSM resources when it starts executing the kernel program. However, since TCSM resources are only released after the last TP in a TC has finished executing the kernel program, if the next TC has insufficient TCSM resources at this time, all TPs in the entire TC will not be allocated resources and must wait until the last TP in the previous TC has finished executing the entire kernel program. This greatly reduces the parallelism of tasks and increases the total execution time of all tasks.

[0050] At least one embodiment of this disclosure provides a thread scheduling method, including: in response to receiving a resource allocation request for a thread group, determining whether it is possible to allocate private storage resources to the thread group independently of shared storage resources; in response to determining that it is possible to allocate private storage resources to the thread group independently of shared storage resources, allocating private storage resources for the thread group to the thread group; and in response to the shared storage resources meeting the allocation needs of the thread group, allocating shared storage resources for the thread group to the thread group.

[0051] At least one embodiment of this disclosure also provides a processor to which the above-described thread scheduling method is applied and an electronic device including the processor.

[0052] The thread scheduling method provided in the above embodiments of this disclosure can divide the resource allocation process into two steps. That is, when the shared storage resources do not meet the allocation requirements, private storage resources are allocated independently first, and then shared storage resources are allocated when the allocation requirements are met. By delaying the allocation of shared storage resources that do not meet the allocation requirements, the purpose of allocating resources in advance can be achieved, thereby shortening the overall task completion time. Moreover, since the thread scheduling method provided in the above embodiments of this disclosure does not require any software modifications, performance is improved while simplifying software design. For example, in some examples, by using this thread scheduling method, private storage resources can be allocated separately when the TCSM resources do not meet the allocation requirements, and then the TCSM resources can be allocated again when the TCSM resources meet the requirements. Thus, if TCSM resources can be allocated in stages, allowing resources that meet the requirements first to be allocated, the TP in the next TC can execute the kernel program in advance due to the allocation of private storage resources. Therefore, the next TC can execute program segments unrelated to temporarily unnecessary resources in advance, which can overlap with the execution of the kernel program by the previous TC, thereby improving the parallelism of the task and shortening the total execution time of the entire task.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0054] Figure 3A A timing diagram illustrating TP allocation and kernel program execution is shown.

[0055] like Figure 3AAs shown, the horizontal axis represents time, and the vertical axis represents the executed task. In this example, there are a total of 2 TCs (TC0 and TC1). TC0 contains 3 TPs (TC0_TP0, TC0_TP1, and TC0_TP2), and TC1 contains 3 TPs (TC1_TP0, TC1_TP1, and TC1_TP2). Each TP executes its corresponding kernel program. First, TC0_TP0 is created and allocated. When the creation and allocation of TC0_TP0 is complete, TC0_TP0 begins executing its kernel program, while TC0_TP1 is created and allocated simultaneously. When the creation and allocation of TC0_TP1 is complete, TC0_TP1 begins executing its kernel program, while TC0_TP2 is created and allocated simultaneously. After the creation and allocation of TC0_TP2 is complete, TC0_TP2 begins executing its kernel program. For the shared memory resource TCSM, after TC0_TP2 completes the execution of its kernel program, the TCSM resource of TC0 is released, and then TC1_TP0 is created and allocated. The timing of the three TP execution tasks in TC1 is similar to that of the three TP execution tasks in TC0, and will not be repeated here. In this embodiment, data operations on private storage resources are performed in the first part of the kernel program execution process, and data operations on shared storage resources are performed in the last part.

[0056] As discussed above, if data operations on shared storage resources are performed at the end of the kernel program, a TP (Transaction Processor) does not require shared storage resources to meet its needs when it begins executing the kernel program. Therefore, when the last TP in a TC (Transaction Controller) completes creation and allocation, if the next TC only lacks sufficient shared storage resources, the creation and allocation of the next TC can be performed earlier (e.g., allocating private storage resources independently first, and delaying the allocation of shared storage resources), thus obtaining a new timing diagram. The new timing diagram... Figure 3B As shown in the image.

[0057] Figure 3B A timing diagram illustrating TP allocation and kernel program execution provided in at least one embodiment of this disclosure is shown.

[0058] like Figure 3BAs shown, first, TC0_TP0 is created and allocated. Once TC0_TP0 is created and allocated, its kernel program begins execution, and simultaneously, TC0_TP1 is created and allocated. Once TC0_TP1 is created and allocated, its kernel program begins execution, and simultaneously, the last TP (TC0_TP2) in TC0 is created and allocated. Once TC0_TP2 is created and allocated, the creation and allocation of TC1_TP0 begins (i.e., allocating hardware resources other than TCSM to TC1). Assuming that TC0's TCSM resources are released when TC0_TP2 finishes executing its kernel program, TCSM resources are then allocated to TC1. Figure 3B As can be seen, when TC1 was allocated TCSM resources, TC1_TP0 had not yet started data operations on shared storage resources. Therefore, the above resource allocation method will not affect the execution of TC1_TP0. The subsequent process and... Figure 3A Similarly, I will not go into details here.

[0059] contrast Figure 3A and Figure 3B As shown in the sequence diagram, dividing the resource allocation process into two steps (i.e., first allocating private storage resources independently, and then allocating TCSM resources that do not yet meet the allocation requirements) can achieve the goal of allocating resources in advance, thereby shortening the overall task completion time. The time saved is... Figure 3B As shown in the image. Regarding... Figure 3B The corresponding thread scheduling methods will be explained further below.

[0060] Figure 4A A flowchart of a thread scheduling method provided in at least one embodiment of the present disclosure is shown.

[0061] like Figure 4A As shown, the thread scheduling method includes steps S401 to S403. For example, this thread scheduling method is used for thread scheduling of the GPU kernel program.

[0062] Step S401: In response to receiving a resource allocation request for a thread group, determine whether it is possible to allocate private storage resources to the thread group independently of shared storage resources.

[0063] For example, a thread group can be a TC as described above, shared storage resources can include TCSM, and private storage resources can include VR and SR. Allocating private storage resources to a thread group independently of shared storage resources means allocating private storage resources only and temporarily not allocating shared storage resources. Furthermore, shared storage resources are not limited to TCSM mentioned above; they can be any other type of storage resource, as long as it is a resource shared by the same TC.

[0064] In some embodiments of this disclosure, in step S401, determining whether private storage resource allocation to the thread group can be performed independently of shared storage resources may include steps S411 to S412. Figure 4B As shown in the image.

[0065] Step S411: Based on the resource allocation request, determine whether the private storage resource can be allocated to the thread group and whether the shared storage resource can be allocated to the thread group.

[0066] In some embodiments of this disclosure, determining whether private storage resources can be allocated to a thread group and whether shared storage resources can be allocated to a thread group based on a resource allocation request includes: checking the current resource status through a resource mask matrix, and determining whether the private storage resources and shared storage resources meet the requirements of the resource allocation request based on the current resource status.

[0067] For example, the resource mask matrix can include Figure 2A , Figure 2B The mask matrix of the private storage resources shown and Figure 2C The diagram shows a mask matrix for shared storage resources. The resource mask matrix stores a mask table. Various hardware resources that have been allocated to the thread group are marked as in use in the corresponding mask table. By using the resource mask matrix, we can know the hardware resources that are not currently in use, and thus determine whether the unused hardware resources meet the requirements of the resource allocation request.

[0068] Step S412: In response to the fact that private storage resources can be allocated to thread groups and shared storage resources cannot be allocated to thread groups, determine the allocation of private storage resources to thread groups independently of shared storage resources.

[0069] In some embodiments of this disclosure, in step S412, determining to allocate private storage resources to the thread group independently of shared storage resources may include: determining whether the number of partial allocation state operations is less than a preset threshold, wherein a partial allocation state operation refers to an operation that has completed the allocation of private storage resources but has not yet performed the allocation of shared storage resources; in response to the number of partial allocation state operations being less than the preset threshold, determining to allocate private storage resources independently of shared storage resources.

[0070] In some embodiments of this disclosure, the preset threshold is greater than or equal to 2, and the specific value of the preset threshold can be determined according to the actual situation.

[0071] For example, in some examples, if the preset threshold is 2, and the number of partial allocation status operations is less than 2, it indicates that there are fewer than 2 operations that have completed private storage resource allocation but have not yet performed shared storage resource allocation. In this case, private storage resource allocation can be performed separately without performing shared storage resource allocation. If the number of partial allocation status operations is greater than or equal to 2, it indicates that there are more than or equal to 2 operations that have completed private storage resource allocation but have not yet performed shared storage resource allocation. In this case, separate private storage resource allocation is not performed to avoid too many operations waiting for allocation affecting the execution sequence of the entire task.

[0072] In some embodiments of this disclosure, in step S401, determining whether private storage resources can be allocated to the thread group independently of shared storage resources may further include: in response to the fact that neither private storage resources nor shared storage resources can be allocated to the thread group, or in response to the number of partial allocation state operations being greater than or equal to a preset threshold, determining not to perform private storage resource allocation independent of shared storage resources.

[0073] Step S402: In response to determining that private storage resources are allocated to the thread group independently of shared storage resources, the private storage resources for the thread group are allocated to the thread group.

[0074] In some embodiments of this disclosure, after the private storage resources for the thread group are allocated to the thread group, the thread group is recorded as a partially allocated thread group awaiting allocation. For example, a thread group awaiting allocation refers to a thread group that has completed the allocation of private storage resources but has not yet completed the allocation of shared storage resources, and belongs to the set of thread groups awaiting allocation.

[0075] For example, the number of members in the set of thread groups to be assigned is the number of thread groups to be assigned contained in the set of thread groups to be assigned.

[0076] The number of thread groups to be allocated in the set of thread groups to be allocated is equal to the number of partial allocation state operations. Therefore, determining whether the number of partial allocation state operations is less than the preset threshold includes: determining whether the number of members in the set of thread groups to be allocated is less than the preset threshold.

[0077] In some embodiments of this disclosure, the allocation information of the thread groups to be allocated in a partially allocated state is stored in an information allocation memory. Determining whether the number of members in the set of thread groups to be allocated is less than a preset threshold may include checking whether the number of items in the allocation information corresponding to the set of thread groups to be allocated in the information allocation memory is less than the preset threshold. For example, the number of items in the allocation information corresponding to the set of thread groups to be allocated is equal to the number of members in the set of thread groups to be allocated.

[0078] For example, the allocation information for a partially allocated thread group includes the address and size of the private storage resources used by the thread group, as well as the resource identifier to which the thread group is allocated.

[0079] For example, the resource identifiers assigned to a thread group include the SPU number where the thread group is located, the thread group number, and the TCSM requirement.

[0080] For example, the information allocation memory includes a First-In-First-Out (FIFO) memory, the depth of which is greater than or equal to a preset threshold. For instance, an item in the allocation information occupies one depth of the FIFO memory. This item includes various information such as the address and size of the private storage resource corresponding to the thread group to be allocated, and the identifier of the allocated resource. An item in the allocation information can be understood as all the resource information that needs to be recorded for a specific thread group to be allocated. For example, different items in the allocation information correspond to different thread groups to be allocated.

[0081] In some embodiments of this disclosure, recording a thread group as a thread group to be allocated in a partially allocated state includes: notifying the control unit of allocation information and writing the allocation information into the information allocation memory.

[0082] For example, the control unit is Figure 1 The SCU 103 shown. Recording a thread group as a partially allocated thread group to be allocated includes notifying the SCU of allocation information and writing the allocation information to the aforementioned first-in-first-out memory.

[0083] Step S403: In response to the shared storage resources meeting the allocation needs of the thread group, the shared storage resources for the thread group are allocated to the thread group.

[0084] In some embodiments of this disclosure, in step S403, allocating shared storage resources for a thread group to a thread group may include: allocating shared storage resources for a thread group to a thread group based on allocation information of the thread group as a thread group to be allocated.

[0085] For example, based on allocation information (e.g., the SPU number where the thread group is located), the memory storing the attributes of the thread group to be allocated is indexed to obtain shared storage resources (e.g., TCSM) and the shared storage resources are allocated to the thread group.

[0086] In some embodiments of this disclosure, after allocating shared storage resources for thread groups to thread groups, the thread scheduling method may further include: notifying the control unit of the attributes of the shared storage resources allocated to the thread groups and deleting allocation information corresponding to the resource allocation request from the information allocation memory.

[0087] For example, shared storage resource attributes include the address and size of the shared storage resource (e.g., TCSM).

[0088] For example, after a shared memory resource for a thread group is allocated to the thread group, the thread group is no longer a thread group to be allocated, so the corresponding allocation information needs to be read from the information allocation memory (e.g., first-in-first-out memory) (that is, the allocation information is deleted from the information allocation memory).

[0089] For example, in some examples, between steps S402 and S403, the thread scheduling method may also include step S413: monitoring the resource mask matrix, determining whether any shared storage resources have been released, and determining whether the shared storage resources meet the allocation needs of the thread group.

[0090] For example, the resource mask matrix is Figure 2C The TCSM mask matrix shown contains multiple TCSM mask tables.

[0091] For example, after allocating private storage resources for a thread group to the thread group, it is necessary to continuously monitor the TCSM mask table on the SPU where the thread group is located (the TCSM mask table records the usage of each type of shared storage resource belonging to the SPU) to determine whether the TCSM resource requirements of the thread group are met, so as to allocate TCSM resources to the thread group in a timely manner when the TCSM resource requirements are met.

[0092] Figure 4C A flowchart illustrating an exemplary thread scheduling method provided by some embodiments of this disclosure is shown.

[0093] like Figure 4C As shown, first, SRM receives a new TC resource request.

[0094] Next, SRM uses the resource mask matrix to determine whether there are SPUs / VEUs that can meet all the resources required by TC (both private and shared storage resources meet TC's resource requirements).

[0095] If an SPU / VEU meets all the resource requirements of the TC, all resources are allocated and the SCU is notified that the allocation is complete. Simultaneously, the SRM stores the allocated hardware resource attributes (resource address and resource size) in a memory.

[0096] If no SPU / VEU can meet all the resource requirements of the TC, then it is determined whether other hardware resources besides TCSM resources can meet the requirements. If neither private storage resources nor TCSM resources can be allocated to the TC, then it is determined that no resource allocation will be performed.

[0097] If all hardware resources other than TCSM resources meet the requirements, then determine whether the number of partial allocation state operations is less than a preset threshold.

[0098] If the number of partial allocation state operations is less than a preset threshold, private storage resources are allocated first. After the allocation operation is completed, the TC is recorded as a thread group to be allocated in a partial allocation state. That is, the SCU is notified of the allocation information of the TC and the allocation information of the TC is written into the FIFO memory (the depth of the FIFO memory is greater than or equal to the preset threshold).

[0099] Next, the mask table of TCSM on the SPU corresponding to TC is continuously monitored. After the TCSM resource requirements of the TC are met, TCSM resources are allocated, the SCU is notified of the attributes of the allocated TCSM resources, and the contents of the FIFO memory are read out, thus completing the entire resource allocation process of the TC.

[0100] If the number of partially allocated operations is greater than or equal to a preset threshold, no resource allocation will be performed until the number of TCs in the partially allocated state is less than the preset threshold before the resource request of that TC can be responded to. For example, in some examples, the resource request of that TC can only be responded to after all TCs in the partially allocated state have been allocated.

[0101] The use of FIFO memory is to prevent SRM from blocking previously partially allocated thread groups from obtaining TCSM allocation after receiving a new thread group resource request, thus serving as a request for arbitration.

[0102] The thread scheduling method provided in the embodiments of this disclosure can divide the resource allocation process into two steps. By allocating private storage resources separately and delaying the allocation of shared storage resources that do not yet meet the allocation requirements, the goal of allocating resources in advance can be achieved, thereby shortening the overall task completion time. Moreover, since the TCSM is shared by all TPs in the entire TC, when the TCSM is allocated, the SRM only needs to package the attributes of the TCSM and the TC number to notify the SCU once, without affecting the response to resource requests from other TCs.

[0103] It should be noted that, in the embodiments of this disclosure, the above-described thread scheduling method may include more or fewer steps, and is not limited to the steps described above. The execution order of each step is not restricted and can be determined according to actual needs.

[0104] Figure 5 A schematic diagram of a processor 500 provided in at least one embodiment of the present disclosure is shown.

[0105] like Figure 5As shown, the processor 500 includes a processing unit 501 and a resource manager 502.

[0106] Processing unit 501 is configured to execute thread groups. Processing unit 501 includes control unit 503, multiple vector processing units 504, and shared memory 505. Control unit 503 is configured to provide allocation information for thread groups in a partially allocated state to resource manager 502. Each vector processing unit 504 includes VR and SR, which are provided as private storage resources to the thread group. Shared memory 505 is provided as shared storage resources to the thread group.

[0107] Resource Manager 502 is configured to allocate private storage resources to a thread group when it is determined that private storage resource allocation to the thread group is independent of shared storage resources. Resource Manager 502 is also configured to, in response to receiving a resource allocation request for a thread group, determine whether private storage resource allocation to the thread group is possible independent of shared storage resources. Resource Manager 502 is further configured to, after allocating private storage resources to the thread group, allocate shared storage resources intended for the thread group to the thread group in response to the shared storage resources meeting the thread group's allocation needs.

[0108] Processing unit 501 is, for example, Figure 1 The SPU 100 shown, the resource manager 502 is, for example, the SRM mentioned above, and the control unit 503 is, for example, Figure 1 The SCU 103 shown contains multiple vector processing units 504, for example... Figure 1 The VEU 101 shown has a shared memory 505, for example, Figure 1 The TCSM 102 is shown. Detailed descriptions of each unit or module can be found in the preceding text and will not be repeated here. For example, processor 500 can be any type of processor such as a CPU or GPU. Processor 500 may also include more units and modules to implement processing and computing functions. The technical effects of processor 500 can be found in the description of the thread scheduling method above and will not be repeated here.

[0109] The following is combined with Figure 5 An embodiment of the thread scheduling method provided in at least one embodiment of this disclosure will be briefly described.

[0110] After responding to the resource request from the TC, the resource manager 502 first checks through the resource mask matrix whether there are processing units 501 / vector processing units 504 that can satisfy all the hardware resources required by the TC. If there are processing units 501 / vector processing units 504 that can satisfy all the hardware resources required by the TC, then all hardware resources are allocated and the control unit 503 is notified of the attributes (resource address and resource size) of the allocated hardware resources. If neither the private storage resources nor the shared memory 505 can be allocated to the TC, then no resource allocation is performed. If the private storage resources can be allocated to the TC but the shared memory 505 cannot be allocated to the TC, then it is determined whether the number of allocation information items stored in the FIFO memory is less than a preset threshold, that is, whether the number of thread groups waiting to be allocated in a partially allocated state is less than a preset threshold. If the number of allocation information items is less than the preset threshold, then the private storage resources are allocated separately first. After the allocation operation is completed, the control unit 503 is notified of the allocation information of the TC and the allocation information of the TC is written into the FIFO memory. Next, the mask table of shared memory 505 on the SPU corresponding to the TC is continuously monitored. After the shared memory resource requirements of the TC are met, shared memory 505 is allocated, the attributes of the allocated shared memory 505 are notified to the control unit 503, and the contents of the FIFO memory are read out, completing the entire resource allocation process for the TC. If the number of items in the allocation information is greater than or equal to a preset threshold, no resource allocation is performed until the number of items in the allocation information is less than the preset threshold or all TCs in the partially allocated state have completed their allocation before the resource request of the TC can be responded to.

[0111] Figure 6A This is a schematic diagram of the structure of an electronic device 600 provided for at least one embodiment of the present disclosure.

[0112] like Figure 6A As shown, the electronic device 600 includes Figure 5 The processor 500 shown. Figure 6A The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0113] Figure 6B This is a schematic diagram of the structure of another electronic device 700 provided in at least one embodiment of the present disclosure. The electronic device 700 in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 6B The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0114] For example, such as Figure 6B As shown, in some examples, electronic device 700 includes a processing unit (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 608 into random access memory (RAM) 603. For example, processing unit 601 can be the aforementioned processor 500. Various programs and data required for the operation of the computer system are also stored in RAM 603. Processing unit 601, ROM 602, and RAM 603 are connected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0115] For example, the following components can be connected to I / O interface 605: input devices 606 such as touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 such as liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 608 such as magnetic tapes, hard disks, etc.; and communication devices 609 including network interface cards such as LAN cards, modems, etc. Communication device 609 allows electronic device 700 to exchange data wirelessly or wiredly with other devices, performing communication processing via networks such as the Internet. Drive 610 is also connected to I / O interface 605 as needed. Removable media 611, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 610 as needed so that computer programs read from them can be installed into storage device 609 as needed. Although Figure 6B An electronic device 700 including various means is shown; however, it should be understood that implementation or inclusion of all the means shown is not required. More or fewer means may be implemented or included alternatively.

[0116] For example, the electronic device 700 may further include a peripheral interface (not shown). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 609 can communicate wirelessly with networks and other devices, such as the Internet, intranets, and / or wireless networks such as cellular telephone networks, wireless local area networks (LANs), and / or metropolitan area networks (MANs). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0117] For example, electronic device 700 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or any combination of electronic devices and hardware. The embodiments disclosed herein do not limit this.

[0118] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0119] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0120] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0121] The following points should be noted regarding this disclosure:

[0122] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0123] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0124] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A thread scheduling method, comprising: in response to receiving a resource allocation request for a thread group, determining whether private storage resource allocation for the thread group can be performed independently of a shared storage resource; in response to determining that private storage resource allocation for the thread group can be performed independently of the shared storage resource, allocating private storage resource for the thread group to the thread group; after the allocating private storage resource for the thread group to the thread group, recording the thread group as a partially allocated thread group in a partially allocated state, and in response to the shared storage resource satisfying allocation needs of the thread group, allocating the shared storage resource for the thread group to the thread group, wherein the partially allocated thread group refers to a thread group that has completed private storage resource allocation and has not yet performed shared storage resource allocation, and belongs to a set of partially allocated thread groups.

2. The thread scheduling method of claim 1, wherein, allocating the shared storage resource for the thread group to the thread group comprises: allocating the shared storage resource for the thread group to the thread group based on allocation information of the thread group as the partially allocated thread group.

3. The thread scheduling method of claim 2, wherein, determining whether private storage resource allocation for the thread group can be performed independently of the shared storage resource comprises: judging, according to the resource allocation request, whether the private storage resource is allocable to the thread group and whether the shared storage resource is allocable to the thread group; in response to the private storage resource being allocable to the thread group and the shared storage resource being inallocable to the thread group, determining that private storage resource allocation for the thread group can be performed independently of the shared storage resource.

4. The thread scheduling method of claim 3, wherein, determining that private storage resource allocation for the thread group can be performed independently of the shared storage resource comprises: judging whether a number of partially allocated state operations is less than a preset threshold, wherein the partially allocated state operation refers to an operation that has completed private storage resource allocation and has not yet performed shared storage resource allocation; in response to the number of partially allocated state operations being less than the preset threshold, determining that private storage resource allocation can be performed independently of the shared storage resource.

5. The thread scheduling method of claim 4, wherein, judging whether the number of partially allocated state operations is less than the preset threshold comprises: judging whether a number of members of the set of partially allocated thread groups is less than the preset threshold.

6. The thread scheduling method of claim 5, wherein, allocation information of the partially allocated thread group in the partially allocated state is stored in an information allocation storage, judging whether the number of members of the set of partially allocated thread groups is less than the preset threshold comprises: checking whether a number of items of allocation information corresponding to the set of partially allocated thread groups in the information allocation storage is less than the preset threshold, wherein the number of items of allocation information corresponding to the set of partially allocated thread groups is equal to the number of members of the set of partially allocated thread groups. 7.The thread scheduling method according to claim 6, wherein the information allocation storage comprises a first-in-first-out storage, and a depth of the first-in-first-out storage is greater than or equal to the preset threshold.

8. The thread scheduling method of claim 4, wherein, the preset threshold is greater than or equal to 2.

9. The thread scheduling method of claim 7, wherein, recording the thread group as the partially allocated thread group in the partially allocated state comprises: The allocation information is notified to a control unit and written into the information allocation memory.

10. The thread scheduling method of claim 9, wherein, The allocation information comprises an address and size of the private storage resource for the thread group and a resource identification to which the thread group is allocated.

11. The thread scheduling method of claim 10, further comprising: after allocating the shared storage resource for the thread group to the thread group, notifying the control unit of the shared storage resource attribute allocated to the thread group and deleting the allocation information corresponding to the resource allocation request in the information allocation memory.

12. The thread scheduling method of claim 4, wherein, determining whether the private storage resource allocation for the thread group can be performed independently of the shared storage resource, further comprises: in response to neither the private storage resource nor the shared storage resource being allocable to the thread group, or in response to the number of partial allocation state operations being greater than or equal to the preset threshold, determining that the private storage resource allocation independent of the shared storage resource is not performed.

13. The thread scheduling method of claim 3, wherein, judging whether the private storage resource is allocable to the thread group and whether the shared storage resource is allocable to the thread group according to the resource allocation request, comprises: checking a current resource state through a resource mask matrix and judging whether the private storage resource and the shared storage resource satisfy the requirement of the resource allocation request according to the current resource state.

14. The thread scheduling method of claim 13, further comprising: monitoring the resource mask matrix to judge whether the shared storage resource is released and whether the shared storage resource satisfies the allocation requirement of the thread group.

15. The thread scheduling method according to any one of claims 1-14, wherein, The thread scheduling method is used for thread scheduling of a kernel program.

16. A processor, comprising: a processing unit configured to execute a thread group; a resource manager configured to, in response to receiving a resource allocation request for the thread group, determine whether the private storage resource allocation for the thread group can be performed independently of the shared storage resource, in a case of determining that the private storage resource allocation for the thread group is performed independently of the shared storage resource, allocate the private storage resource to the thread group, after allocating the private storage resource to the thread group, record the thread group as a to-be-allocated thread group in a partial allocation state, and in response to the shared storage resource satisfying the allocation requirement of the thread group, allocate the shared storage resource for the thread group to the thread group, wherein the to-be-allocated thread group refers to a thread group that has completed the private storage resource allocation and has not performed the shared storage resource allocation, and belongs to a to-be-allocated thread group set.

17. The processor of claim 16, wherein, the processing unit comprises: a control unit configured to provide allocation information of the to-be-allocated thread group in the partial allocation state to the resource manager.

18. The processor of claim 16, wherein: the processing unit further comprises a plurality of vector processing units and a shared memory; each vector processing unit comprises a vector register and a scalar register, and the vector register and the scalar register are provided to the thread group as the private storage resource; The shared memory is provided as the shared storage resource to the thread group.

19. An electronic device comprising a processor according to any of claims 16-18.

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