Straight wire bonding of silicon dies

Abstract

A method includes stacking a number of silicon dies such that one or more edges of the dies are vertically aligned, where the one or more edges include a number of connection pads. The method also includes positioning a connection wire on an axis substantially perpendicular to the one or more edges. The connection wire includes a number of solder bumps formed thereon. The solder bumps are spaced apart at intervals associated with a distance between a first set of aligned connection pads on the dies. The connection wire is positioned such that the solder bumps are in contact with the first set of aligned connection pads. The method also includes applying heat to reflow the solder bumps and physically and electrically couple the connection wire to the connection pads.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 077,069, filed September 11, 2020, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This application generally relates to providing electrical connections between silicon dies, and more specifically, to electrically connecting silicon dies along vertical edges.

[0004] In some silicon die structures, connection pads are placed on top or bottom of the die. This takes up valuable space used to form transistors, and when dies are stacked, the required connections between them necessitate a staggered, stepped arrangement, resulting in more space needed to form a complete or packaged integrated device. Summary of the Invention

[0005] The processes, apparatus, and systems described herein describe electrically connecting dies along the vertical edges of silicon dies, thereby reducing the required lateral space. Specifically, by placing connection pads on the vertical edges of the dies, the dies can be stacked vertically without the need for staggered dies to achieve connections via connection pads located at the top or bottom. In effect, linear connections can be made along vertically aligned, edge-mounted connection pads, allowing the silicon dies to be stacked in a completely vertical arrangement. This reduces the lateral coverage area of ​​the silicon dies, resulting in a smaller overall footprint. Furthermore, transistors are generally formed on the top and / or bottom of the silicon die, rather than on the vertical edges. By placing connection pads on the edges, previously unused space on the silicon die can be used for interconnects, thus freeing up space for transistor formation on the top and / or bottom of the silicon die.

[0006] The methods and systems described herein provide a novel and advantageous interconnection technique for interconnecting silicon dies using interconnect pads formed at the edges, and more specifically, for vertically stacked silicon dies.

[0007] This disclosure also provides an apparatus comprising a substrate and two or more silicon dies, wherein a first die is disposed on the substrate and a second die is disposed on or stacked on the first die. The silicon die includes an upper flat surface parallel to the substrate, a lower flat surface parallel to the upper flat surface and spaced a first distance from the first flat surface, a first edge portion disposed between and perpendicular to the upper and lower flat surfaces, and a first set of vertically aligned connection pads disposed on the first edge portion. The apparatus further includes conductive elements configured to couple to the one or more connection pads, and a plurality of solder blocks. The solder blocks are coupled to the conductive elements and spaced apart by a distance associated with the distance between the first set of connection pads. In some embodiments, the solder blocks include a first groove having a width measured to be substantially the same as the width of the first edge portion and configured to receive an edge of the silicon die within the first groove.

[0008] This disclosure provides a method comprising: stacking a plurality of silicon dies such that one or more edges of the silicon dies are vertically aligned, wherein the one or more edges include a plurality of connection pads. The method further comprises positioning a generally linear conductor on an axis substantially perpendicular to the one or more edges, wherein the linear conductor contacts one or more of the connection pads. The method further comprises applying conductive solder to the one or more connection pads and one or more portions of the linear conductor in contact with the one or more connection pads. The method further comprises applying heat to reflow the solder, such that the solder physically and electrically couples the one or more portions of the linear conductor to the one or more connection pads in contact therewith.

[0009] This disclosure also provides a method comprising stacking a plurality of silicon dies such that one or more edges of the plurality of silicon dies are vertically aligned, wherein the one or more edges comprise a plurality of connection pads. The method further comprises positioning connection wires on an axis substantially perpendicular to the one or more edges. The connection wires comprise a plurality of solder blocks. The solder blocks are spaced apart by a distance associated with a distance between a first set of aligned connection pads on the silicon dies. The connection wires are positioned such that the solder blocks contact the first set of aligned connection pads. The method further comprises applying heat to reflow the solder blocks, such that the solder blocks physically couple the connection wires to the aligned connection pads.

[0010] In this way, various aspects of this disclosure achieve improvements at least in the field of silicon die interconnects and their design and architecture. While this disclosure is particularly applicable to connecting stacked dies, those skilled in the art will understand that this disclosure can be used in other embodiments, such as those in which the dies are orthogonally arranged to the substrate. The foregoing summary is intended only to give general ideas about various aspects of this disclosure and does not limit the scope of this disclosure in any way. Attached Figure Description

[0011] Figure 1 is a perspective view of a known method of connecting one or more silicon dies according to some embodiments of the present disclosure.

[0012] Figure 2a This is a perspective view of a silicon die having one or more vertical edge connection pads according to some embodiments of the present disclosure.

[0013] Figure 2b According to some embodiments of this disclosure Figure 2a A cross-sectional side view of a silicon wafer.

[0014] Figure 3 This is a flowchart illustrating a process for connecting two or more silicon dies according to some embodiments of this disclosure.

[0015] Figure 4a This is a cross-section of a silicon wafer according to some embodiments of the present disclosure, showing... Figure 3 This is part of the process described in the document.

[0016] Figure 4b This is a cross-section of a silicon wafer according to some embodiments of the present disclosure, showing... Figure 3 Another part of the process described in the text.

[0017] Figure 5 The use of some embodiments of this disclosure in Figure 3 A perspective view of two silicon dies electrically coupled by the process described in the figure.

[0018] Figure 6 This is a bottom view of a solder block according to some embodiments of the present disclosure.

[0019] Figure 7 This is a flowchart illustrating a process for connecting multiple silicon dies to form a packaged IC or another packaged silicon device, according to some embodiments of this disclosure.

[0020] Figure 8 This is a perspective view of a plurality of silicon dies prepared for electrical coupling according to some embodiments of the present disclosure.

[0021] Figure 9 This is a perspective view of a plurality of electrically coupled silicon dies according to some embodiments of the present disclosure.

[0022] Figure 10 This is a perspective view of a plurality of silicon dies coupled to a substrate according to some embodiments of the present disclosure.

[0023] Figure 11 This is an alternative arrangement of a silicon die coupled to a substrate according to some embodiments of this disclosure. Detailed Implementation

[0024] In the following description, numerous details, such as silicon-based die configurations, silicon die electrical interconnection methods, etc., are set forth in order to provide an understanding of one or more aspects of this disclosure. It will be readily apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of this application. The following description is intended only to give a general idea of ​​the various aspects of this disclosure and does not limit the scope of this disclosure in any way.

[0025] Figure 1 is a perspective view of a conventional method of connecting one or more silicon dies 100 within a packaged integrated circuit (“packaged IC”) or another packaged silicon device (“package”), such as a memory device. As shown in Figure 1, the silicon die 100 includes one or more connection pads 102 positioned on the top surface 104 of the silicon die 100. To connect the connection pads 102 of the silicon die 100, the silicon dies 100 are staggered such that the connection pads 102 of each subsequent silicon die are exposed or accessible. This staggering of the silicon dies requires additional space within the package, which often increases the package size. Furthermore, as more dies are stacked, the upper dies will protrude more, causing them to become off-center, which may cause the dies to tilt and / or subject the dies to stresses that could cause the dies to crack.

[0026] Turn now Figure 2a According to some embodiments, a perspective view of a silicon die 200 having one or more connection pads 202a, 202b positioned on a vertical edge 204 is shown. The die 200 has a generally flat upper surface 206 and a generally flat lower surface 208, the lower surface being parallel to and spaced apart from the upper surface 206 by a first distance. In the illustrated embodiment, the first distance is the width of the die 200. The vertical edge 204 is disposed between and perpendicular to the upper flat surface 206 and the lower flat surface 208. By positioning the connection pads 202a, 202b on the vertical edge, one or more silicon dies 200 can be stacked vertically without having to stagger or offset the silicon dies 200 as shown in FIG. 1. This results in a smaller space requirement when stacking multiple silicon dies 200 within an integrated circuit.

[0027] Figure 2bThis is a cross-sectional side view of the silicon die 200, showing the connection pad 202a. (See image.) Figure 2b As shown, the connector pad 202a may partially overlap with the upper surface 206 and the lower surface 208. However, in some embodiments, there may be no external overlap of the connector pad 202a on the upper surface 206 and / or the lower surface 208. For example, the connector pad 202a (and connector pad 202b) may only be exposed on the vertical edge 204, while the rest of the connector pad 202a is located within the silicon die 200. In some embodiments, the connector pad may have a first length 210 of 25 micrometers. However, lengths greater than or less than 25 micrometers are also contemplated. In some embodiments, this length may be equal to the width of the vertical edge 204 of the silicon die 200.

[0028] Turn now Figure 3 According to some embodiments, a process 300 for connecting two or more silicon dies is shown. At process frame 302, conductive connection wires are positioned onto a first connection pad of a first silicon die. The connection wires may be constructed of one or more metals or other conductive materials, such as copper, aluminum, gold, palladium, indium, iridium, various silver / tin mixtures, lead, and binary and / or ternary metal alloys. In one embodiment, the connection wire includes a copper core plated with a metal such as tin to prevent oxidation of the copper. In one embodiment, the connection wire is a circular or substantially circular wire. However, in other instances, the connection wire may be a flat or strip-shaped wire. In some embodiments, the connection wire may have a diameter of approximately 24 μm. In other embodiments, the connection wire may have a diameter in the range of about 16 μm to about 50 μm. In still other embodiments, the connection wire may have a diameter less than 16 μm or greater than 50 μm.

[0029] In some embodiments, the silicon die is positioned such that the interconnect wires can be laid across the interconnect pads and their position is maintained by gravity. See also... Figure 4a This illustrates conductive connection wires 400 positioned on connection pads 402 of a silicon die 404. However, in other embodiments, various other methods can be used to hold the connection wires in place on the connection pads.

[0030] Once the connecting wire 400 is positioned on the first connecting pad 402 of the first silicon die, liquid solder is applied to the first connecting pad 402 and the connecting wire 400 at process frame 304. See [link to process frame 304] for more details. Figure 4bThis illustrates a large mass of liquid solder 406 applied to the first connector pad 402 and subsequently covering the connector wire 400. In some embodiments, the solder is gold solder. In other embodiments, the solder may be silver solder, palladium solder, iridium solder, indium solder, silver / tin mixture solder, one or more binary or ternary metal alloy solders, lead solder, or other types of solder that can be applied. Generally, the solder is heated to reflow it into a liquid state for dispensing onto the connector pad 402.

[0031] Once solder is applied, heat is applied to the solder, connecting wire 400, and / or first connecting pad at process frame 306. The heat melts or reflows the solder, creating a solder joint between the first connecting pad and the connecting wire. In some embodiments, the first connecting pad and / or connecting wire may be coated with flux material to facilitate the formation of a suitable solder joint between the first connecting pad and the connecting wire. Although process 300 described above relates to connecting connecting wire 400 to first connecting pad 402 using solder, other joining processes, such as welding, brazing, laser welding, etc., can be used.

[0032] Process 300 can be used across multiple silicon dies. For example, such as Figure 5 As shown, a first silicon die 500 having a first connection pad 502 on a first edge 506 is aligned with a second silicon die 508 having a second connection pad 510 on a first edge 512 of a second silicon die 508. The first and second silicon dies 500 and 508 are assumed to be the same size, and their associated connection pads 502 and 510 are positioned in the same location to facilitate the stacking of the silicon dies 500 and 508. As described above with respect to process 300, a connecting wire 514 is positioned across both the first connection pad 502 and the second connection pad 510. Similarly, the silicon dies 500 and 508 can be positioned such that the first connection pad 502 and the second connection pad 510 face upwards, allowing gravity to exert a downward force on the connecting wire 514, thereby assisting in holding the connecting wire in place. Liquid solder can then be placed in a first blob (or “spot”) 516 on the first connection pad 502 and then in a second blob 518 on the second connection pad 510. Then, heat is applied to cause the solder to reflow, thereby promoting the solder joint between the connecting wire 514 and the first connecting pad 502 and the second connecting pad 510.

[0033] In some embodiments, heat may be concentrated on the bonding pads (and associated solder clumps and connecting wires), such as via flame jet or laser heating. However, in other embodiments, general heat is applied to the silicon die (e.g., silicon die 500, 508) to facilitate solder melting or reflow at the bonding pads. For example, the silicon die may be placed in a reflow furnace or subjected to a generalized heat source, such as via a diffusion furnace.

[0034] Turn now Figure 6 According to some embodiments, a bottom view of solder block 600 is shown. Solder block 600 can be made of various soldering materials, such as indium, gold, silver, palladium, iridium, lead, or other types of solder that can be applied. Figure 6 As shown, solder block 600 may have a square shape, but other shapes are also contemplated. Solder block 600 may include a first groove or recess 602 and a second groove or recess 604. The size of the first groove 602 may be configured to accommodate connecting wires, such as those described above. In one embodiment, the width of the first groove is approximately 15 micrometers. However, widths less than or greater than 15 micrometers are also contemplated. The first groove 602 may be deeper within solder block 600 than the second groove 604, such that the second groove 604 can accommodate all or part of the connecting pads, such as the connecting pads described above.

[0035] As described above, the second trench 604 is configured to receive all or part of the bonding pads of the silicon die, as discussed above. In one embodiment, the width of the second trench 604 is 25 micrometers. However, widths greater than 25 micrometers and less than 25 micrometers are contemplated. Furthermore, it should be understood that the size of the second trench 604 can be set to accommodate bonding pads of different sizes as needed. For example, the second trench 604 may be approximately 10% wider than the width of the bonding pads of the silicon die. However, where appropriate, the second trench may be wider than 10% or less than 10%. The depth of the second trench 604 can be set to receive bonding pads to a depth that allows for the formation of effective solder joints (described in more detail below) when the solder block 600 is heated. For example, the depth of the second trench may be 5 micrometers. However, depths greater than 5 micrometers and less than 5 micrometers are also contemplated.

[0036] In some embodiments, solder blocks 600 may be coupled to connection wires during the fabrication of the connection wires. For example, multiple solder blocks 600 may be coupled to connection wires and spaced apart by a distance associated with the spacing between silicon dies. This allows connection wires to be positioned to contact multiple silicon dies such that the solder blocks 600 are positioned above the connection pads of the respective silicon dies.

[0037] Turn now Figure 7According to some embodiments, a process 700 for joining multiple silicon dies to form an integrated circuit is illustrated. At process block 702, two or more silicon dies are positioned together. As described above, the silicon dies can be stacked vertically such that the die edges are aligned with a common axis. In some instances, a die attachment film or die attachment film adhesive can be placed between the silicon dies to hold them in place relative to each other. In other embodiments, a paste or other liquid adhesive can be placed between the silicon dies to hold them in place relative to each other. In some embodiments, the die attachment film can provide a spacing distance between the silicon dies equal to the thickness of the die attachment film. For example, the die attachment film may have a thickness of 10 micrometers. However, thicknesses greater than 10 micrometers or less than 10 micrometers are also contemplated. In other embodiments, the size of the die attachment film may be set so as not to reach the edges of the dies, resulting in small gaps at the die edges. In other embodiments, spacers, such as silicon die blanks, can be used to separate adjacent dies.

[0038] The silicon die can also be positioned such that the bonding pads face upwards. For example, a workchuck holding the die can be rotated to rotate the bonding pads upwards, allowing gravity to help hold the connecting wires in place, as further described herein. In some embodiments, the workchuck can be configured to rotate the silicon die in multiple locations to allow different bonding pads to face upwards during wire bonding / soldering processes. Further consideration has been given to positioning the silicon die using known die positioning techniques.

[0039] The positioning of the silicon wafer is Figure 8 As shown in the image. Figure 8 As shown, according to some embodiments, the device includes a first silicon die 802, a second silicon die 804, and a third silicon die 806. Each of the silicon dies 802, 804, and 806 includes two bonding pads 808, 810, 812, 814, 816, and 818. The first silicon die 802 and the second silicon die 804 are separated by a first die attachment film 820, and the second silicon die 804 and the third silicon die 806 are separated by a second die attachment film 822. Figure 8 As shown, connecting pads 808, 812, and 816 are in a first alignment and form a first group, while connecting pads 810, 814, and 818 are in a second alignment and form a second group.

[0040] Once the silicon die has been positioned at process frame 702, a connector wire having two or more integrated solder pads is positioned onto the two or more silicon dies at process frame 704. In one embodiment, the connector wire is positioned such that the integrated solder pads are aligned with a set of vertically aligned connector pads (i.e., a first set or a second set). For example, as... Figure 9As shown, a first connecting wire 902 is positioned above connecting pads 808, 812, and 816 of a first silicon die 802, a second silicon die 804, and a third silicon die 806, respectively. The first connecting wire 902 has a first solder block 906, a second solder block 908, and a third solder block 910, which are spaced apart to align with connecting pads 808, 812, and 814, as shown. Similarly, a second connecting wire 904 is positioned above connecting pads 810, 814, and 818 of a first silicon die 802, a second silicon die 804, and a third silicon die 806, respectively. The first connecting wire 902 has a first solder block 912, a second solder block 914, and a third solder block 916, which are spaced apart to align with connecting pads 808, 812, and 814, as shown.

[0041] Now go back to Figure 7 Once the connector wires are positioned in process frame 704, heat is applied at process frame 706 to reflow the solder block. In one embodiment, heat is applied to the solder block, connector pads, and connector wires as described above. In some embodiments, heat may be concentrated on the solder block (and associated connector pads and connector wires), for example, via flame jet or laser heating. However, in other embodiments, general heat is applied to the silicon die to facilitate solder melting or reflow at the die's connector pads. For example, the silicon die may be placed in a reflow furnace or subjected to a generalized heat source, such as via a diffusion furnace.

[0042] Turn now Figure 10 The silicon dies 802, 804, and 806 described above are coupled to the substrate 1000 via connecting wires 902 and 904. The substrate 1000 may include a first connecting pad 1002 and a second connecting pad 1004, which are respectively used for connection to the first connecting wire 902 and the second connecting wire 904. In some embodiments, the substrate 1000 may include a channel 1006. In some embodiments, the channel 1006 allows the connecting wires 902 and 904 to be mounted onto the substrate 1000 without requiring any bending or other deformation of the connecting wires. Although Figure 8 , 9 Examples 10 and 10 illustrate an instance of three silicon dies connected via two interconnecting wires; however, it is considered that the process 700 described above can be scaled up as needed for use with more than three silicon dies and more than two interconnecting wires. Therefore, Figure 8 , 9 The examples of 10 are for illustrative purposes only and should not be construed as limiting the process described herein to the specific components shown in the figures.

[0043] Turn now Figure 11An alternative arrangement of silicon dies is shown in the form of assembly 1100. Assembly 1100 includes a first silicon die 1102, a third silicon die 1104, and a fifth silicon die 1106, each including a connecting pad 1108 located on a first edge 1110 of the dies 1102, 1104, and 1106. A second silicon die 1112, a fourth silicon die 1114, and a sixth silicon die 1116 are alternately positioned between the first silicon die 1102, the third silicon die 1104, and the fifth silicon die 1106, respectively. The second silicon die 1112, the fourth silicon die 1114, and the sixth silicon die 1116 include a connecting pad 1118 located on a second edge 1120 opposite to the first edge of the first silicon die 1102, the third silicon die 1104, and the fifth silicon die 1106. A first connecting wire 1122 is coupled to a connection pad 1108 of a first silicon die 1102, a third silicon die 1104, and a fifth silicon die 1106, and a second connecting wire 1124 is coupled to a connection pad 1118 of a second silicon die 1112, a fourth silicon die 1114, and a sixth silicon die 1116. The first connecting wire 1122 is coupled to a substrate 1126 at a first substrate connection pad 1128. Similarly, the second connecting wire 1124 is coupled to a substrate 1126 via a second connection pad 1130.

[0044] Assembly 1100, referred to as a dual-channel structure, enables connections every other die. This configuration also allows for more space between connections due to the alternation of silicon dies, thereby reducing the risk of short circuits caused by soldering the connection wires to the die connection pads. The solder joints connecting the connection wires to the connection pads can be performed using the processes described above, such as process 300 and / or process 700, thereby enabling connections along the vertical sides of the respective silicon dies. In some instances, a four-channel structure can be used, allowing connections every three dies along a given edge of the silicon die. Figure 11 The examples shown are for illustrative purposes, and it is understood that the dual-channel or quad-channel designs described above can be used to connect multiple dies, depending on the needs of a given application.

[0045] The described embodiments are particularly suitable for electrically connecting stacked silicon dies. For example, some versions of electronic memory devices include multiple stacked NAND dies. Therefore, memory devices having multiple NAND dies stacked on a substrate will benefit from the features and die electrical interconnect methods disclosed herein.

[0046] Regarding the processes, systems, methods, heuristics, etc., described herein, it should be understood that although the steps of the processes, etc., have been described as being performed in a certain order, the processes can be practiced in a manner other than the order described herein. Furthermore, it should be understood that some steps may be performed simultaneously, other steps may be added, and some steps described herein may be omitted. In other words, the description of the processes herein is provided to illustrate certain embodiments and should in no way be construed as limiting the scope of the claims.

[0047] As used herein, terms generally mean approximately, almost, or within 10-20% above or below the term they modify. For example, “generally linear” means that the object is within 10-20% of being perfectly linear (i.e., straight). Similarly, “generally circular” means that the object may have a deformation or deflection of 10-20% relative to the dimensions of a perfect circle.

[0048] Therefore, it should be understood that the above description is intended to be illustrative rather than restrictive. After reading the above description, many embodiments and applications beyond the examples provided will become clear. The scope of the invention should not be determined by reference to the above description, but rather by reference to the appended claims and the full scope of their authorized equivalents. Future developments are anticipated and desired in the art discussed herein, and the disclosed apparatus, methods, and devices will be incorporated into these future embodiments. In summary, it should be understood that modifications and changes to this application are possible.

[0049] Unless expressly indicated otherwise herein, all terms used in the claims are intended to have their broadest reasonable construction and common meaning as understood by a person skilled in the art as described herein. Specifically, unless the claims expressly limit this to the contrary, the use of singular articles such as “a”, “the / said”, etc., should be understood as enumerating one or more of the represented elements.

[0050] An abstract is provided to enable the reader to quickly determine the nature of this technical disclosure. It is submitted with the understanding that the abstract will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplification. This approach of the disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim stands alone as a separately asserted subject matter.

Claims

1. An apparatus comprising: Substrate; Two or more silicon dies, wherein a first die is disposed on the substrate, and a second die is stacked on the first die, and the dies comprise: The upper flat surface is parallel to the substrate; The lower flat surface is parallel to the upper flat surface and spaced a first distance from the upper flat surface; At least a first edge portion, disposed between and perpendicular to the upper flat surface and the lower flat surface; and At least a first set of connecting pads, each of the at least first set of connecting pads being disposed on the at least first edge portion of each bare die, and wherein the first set of connecting pads are vertically aligned with each other; A conductive element configured to be coupled to the first set of connecting pads; and Multiple solder blocks, coupled to the conductive element and spaced apart by intervals associated with the distance between the connecting pads in the first set of connecting pads; and Each of the plurality of solder blocks includes a first groove and a second groove orthogonal to each other, and The second groove is configured to receive all or part of the connecting pads in the first set of connecting pads; and The size of the first groove is set to accommodate the conductive element.

2. The apparatus of claim 1, wherein the solder block is configured to be heated such that the solder block reflows and creates a solder joint between the conductive element and the first set of connecting pads.

3. The apparatus of claim 1, wherein the solder block includes the second groove having a width measured approximately the same as the first distance and configured to receive the edge of the silicon die within the second groove.

4. The device according to claim 3, wherein the width of the second groove is 10% wider than the first distance.

5. The device according to claim 4, wherein the first distance is 25 micrometers.

6. The device of claim 1, wherein the conductive element is electrically connected to the substrate.

7. The device of claim 6, wherein the substrate comprises a channel, and the conductive element is electrically connected to the substrate within the channel.

8. The device of claim 1, further comprising a component for attaching the first die to the second die.

9. The device of claim 1, further comprising a die attachment film disposed between the first die and the second die and physically connecting the first die and the second die.

10. The device of claim 1, further comprising a component for separating the first die and the second die.

11. The device according to claim 1, wherein the conductive element comprises tin-plated copper wire.

12. The apparatus of claim 1, wherein a first subset of the two or more silicon dies has the first set of connection pads on the first edge, and a second subset of the two or more silicon dies has a second set of connection pads on a second edge, wherein the second edge is different from the first edge.

13. The apparatus of claim 12, wherein the two or more silicon dies are arranged such that each silicon die in the first subset of the two or more silicon dies alternates with the second subset of the two or more silicon dies.

14. The device of claim 1, wherein at least one of the conductive element and the connecting pad is coated with a flux material.

15. The apparatus of claim 1, wherein the solder block comprises at least one selected from the group consisting of gold, indium, iridium, and palladium.

16. A method comprising: Multiple silicon dies are stacked such that one or more edges of each of the multiple silicon dies are vertically aligned, wherein the one or more edges contain multiple bonding pads; A generally linear conductor is positioned on an axis that is generally perpendicular to the one or more edges, wherein the linear conductor contacts one or more of the plurality of connecting pads; Apply conductive solder to one or more connection pads and one or more portions of the linear conductor in contact with the one or more connection pads; as well as Heat is applied to reflow the solder, so that the solder physically and electrically couples the one or more portions of the linear conductor to the one or more connecting pads in contact with it; and The conductive solder includes a first groove and a second groove that are orthogonal to each other, and The second groove is configured to receive all or part of the connecting pads in the one or more connecting pads; and The size of the first groove is set to accommodate the linear conductor.

17. The method of claim 16, further comprising coating the linear conductor with a flux layer.

18. The method of claim 16, wherein the conductive solder is applied by applying heated liquid solder to the one or more connection pads and the one or more portions of the linear conductor in contact with the one or more connection pads.

19. A method comprising: Multiple silicon dies are stacked such that one or more edges of each of the multiple silicon dies are vertically aligned, wherein the one or more edges contain multiple bonding pads; Connecting wires are positioned on an axis substantially perpendicular to the one or more edges, wherein the connecting wires include a plurality of solder blocks spaced apart by a distance associated with the distance between a first set of aligned connection pads on the plurality of silicon dies, and wherein the connecting wires are positioned such that the plurality of solder blocks contact the first set of aligned connection pads. Heat is applied to reflow the solder block, causing the solder block to physically couple the connecting wires to the aligned connection pads; and Each of the plurality of solder blocks includes a first groove and a second groove orthogonal to each other, and The second groove is configured to receive all or part of the connecting pads in the first set of aligned connecting pads; and The size of the first groove is set to accommodate the connecting wire.

20. The method of claim 19, wherein a flame jet heating process is used to reflow the solder block.

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