Superconducting circuit with large inductance layer and preparation method thereof

Abstract

The present invention provides a superconducting circuit with a large inductance layer and a preparation method thereof, wherein the superconducting circuit comprises: a substrate; a bypass resistor formed on the substrate; a Josephson junction formed on the bypass resistor; a large inductance layer formed on the Josephson junction; a wiring layer formed on the large inductance layer; and an insulating material layer, which electrically isolates the bypass resistor, the Josephson junction, the large inductance layer and the wiring layer. The superconducting circuit utilizes the small and medium inductance design of the original wiring layer, and then designs and adds a special large inductance layer to be applied to the superconducting circuit requiring large inductance, which effectively expands the inductance size range in the superconducting circuit, broadens the application scenarios of the superconducting circuit, and improves the integration of the superconducting circuit; in addition, the large inductance layer of a specific material can also be used as a large resistance layer at the same time, thereby further improving the integration of the superconducting circuit.

Description

Technical Field

[0001] The invention relates to the technical field of superconducting circuit design, in particular to a superconducting circuit with a large inductance layer and a preparation method thereof. Background Art

[0002] Superconducting circuits include superconducting quantum interference devices (SQUIDs), single flux quantum devices (SFQs), and other circuits that use superconducting Josephson junctions.

[0003] Superconducting quantum interference device (SQUID) is a superconducting quantum device based on the Josephson effect and the principle of magnetic flux quantization. Its basic structure is to insert two Josephson junctions in a superconducting ring. SQUID is the most sensitive magnetic flux detection sensor known so far. The magnetic flux noise of a typical SQUID device is μΦ0 / Hz. 1 / 2 Magnitude (1Φ0=2.07×10 -15 Wb), whose magnetic field noise is in fT / Hz 1 / 2 Magnitude (1fT = 1×10 -15 T), due to its extremely high sensitivity, can be widely used in medical cardio-encephalography, material detection, earth magnetic field, military, earthquake and archaeology, etc. The flux microscope prepared by it can be used for basic research.

[0004] Single Flux Quantum (SFQ) is a superconducting circuit technology that uses a single flux quantum in a Josephson junction to represent logic "1" and "0". The clock frequency of the superconducting digital circuit based on this device can reach 770GHz, and it can be used in ultra-wideband analog-to-digital / digital-to-analog converters in radar and communication systems, broadband network switches, digital autocorrelators for radio astronomy, and superconducting computers. Due to its advantages of high speed and low power consumption, the United States and Japan are currently investing heavily in strategic research.

[0005] Superconducting circuits are generally composed of Josephson junctions and some resistors, inductors, etc. At present, there are many ways to improve the integration of superconducting circuits. Usually, researchers from various countries focus on reducing the size of Josephson junctions and increasing their critical current density. But in fact, the biggest limit to the integration of superconducting integrated circuits is not the Josephson junction, but the parallel resistors and inductors. Now some units are studying self-parallel Josephson junctions, which can remove parallel resistors, but the demand for inductors is not easy to achieve, because the inductor itself is an indispensable part of superconducting integrated circuits and cannot be removed. At the same time, inductors of different sizes are needed in the circuit. If we simply increase the unit inductance, it will cause trouble for the circuit design of small inductors. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a superconducting circuit with a large inductance layer and a preparation method thereof, so as to solve the problems that the inductance range of the superconducting circuit in the prior art is narrow, which limits the application scenarios of the superconducting circuit and the integration of the superconducting circuit.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a superconducting circuit with a large inductance layer, the preparation method comprising:

[0008] 1) providing a substrate, and forming a bypass resistor on the substrate;

[0009] 2) forming a patterned first insulating material layer having a first opening on the surface of the structure obtained above, wherein the first opening exposes the bypass resistor;

[0010] 3) forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer in sequence on the surface of the structure obtained above;

[0011] 4) etching the three-layer thin film structure from top to bottom with different patterns to form a Josephson junction;

[0012] 5) forming a patterned second insulating material layer on the surface of the structure obtained above, and forming a large inductor layer on the second insulating material layer;

[0013] 6) forming a patterned third insulating material layer having a plurality of second openings on the surface of the structure obtained above, wherein the plurality of second openings respectively expose the upper surfaces of the large inductance layer and the Josephson junction;

[0014] 7) forming a third superconducting material layer on the surface of the structure obtained above, and etching the third superconducting material layer to form a wiring layer.

[0015] Optionally, step 7) further includes:

[0016] 8) forming a fourth insulating material layer on the surface of the structure obtained in step 7), and patterning the fourth insulating material layer;

[0017] 9) forming a fourth superconducting material layer on the surface of the structure obtained above, and etching the fourth superconducting material layer to form a grounding layer.

[0018] Optionally, step 5) further includes: etching the second insulating material layer to form a third opening, wherein the third opening exposes the upper surface of the Josephson junction.

[0019] Optionally, the bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; and the material of the large inductance layer is NbN or MoN.

[0020] Based on the above preparation method, the present invention also provides a superconducting circuit with a large inductance layer, the superconducting circuit comprising:

[0021] substrate;

[0022] a shunt resistor formed on the substrate;

[0023] a Josephson junction formed on the shunt resistor;

[0024] a large inductance layer formed on the Josephson junction;

[0025] a wiring layer formed on the large inductance layer;

[0026] The insulating material layer electrically isolates the bypass resistor, the Josephson junction, the large inductance layer and the wiring layer respectively.

[0027] Optionally, it further includes: a ground layer formed on the wiring layer, and the insulating layer also electrically isolates the ground layer.

[0028] Optionally, the bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; and the material of the large inductance layer is NbN or MoN.

[0029] The present invention also provides another method for preparing a superconducting circuit with a large inductance layer, the method comprising:

[0030] 1) providing a substrate, and forming a bypass resistor and a large inductor layer on the substrate respectively;

[0031] 2) forming a first insulating material layer having a plurality of first openings on the surface of the structure obtained above, wherein the plurality of first openings respectively expose the bypass resistor and the large inductor layer;

[0032] 3) forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer in sequence on the surface of the structure obtained above;

[0033] 4) etching the three-layer thin film structure from top to bottom with different patterns to form a Josephson junction;

[0034] 5) forming a second insulating material layer having a second opening on the surface of the structure obtained above, wherein the second opening exposes the upper surface of the Josephson junction;

[0035] 6) forming a third superconducting material layer on the surface of the structure obtained above, and etching the third superconducting material layer to form a wiring layer.

[0036] Optionally, step 6) further includes:

[0037] 7) forming a third insulating material layer on the surface of the structure obtained in step 6), and patterning the third insulating material;

[0038] 8) forming a fourth superconducting material layer on the surface of the structure obtained above, and etching the fourth superconducting material layer to form a grounding layer.

[0039] Optionally, the bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; and the material of the large inductance layer is NbN or MoN.

[0040] Based on the above preparation method, the present invention also provides a superconducting circuit with a large inductance layer, the superconducting circuit comprising:

[0041] substrate;

[0042] A shunt resistor and a large inductance layer formed on the substrate;

[0043] A Josephson junction formed on the bypass resistor and the large inductance layer;

[0044] a wiring layer formed on the Josephson junction;

[0045] The insulating material layer electrically isolates the bypass resistor, the Josephson junction, the large inductance layer and the wiring layer respectively.

[0046] Optionally, it further includes: a ground layer formed on the wiring layer, and the insulating layer also electrically isolates the ground layer.

[0047] Optionally, the bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; and the material of the large inductance layer is NbN or MoN.

[0048] As described above, the superconducting circuit with a large inductance layer and the preparation method thereof of the present invention utilize the small and medium inductance design of the original wiring layer, and then design and add a special large inductance layer for application in superconducting circuits that require large inductance, thereby effectively expanding the inductance range in the superconducting circuit, broadening the application scenarios of the superconducting circuit, and improving the integration of the superconducting circuit; in addition, the large inductance layer of a specific material can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic flow chart of a method for preparing a superconducting circuit with a large inductance layer according to the first embodiment of the present invention.

[0050] Figures 2 to 15 It is a schematic diagram of the cross-sectional structure presented in each step of the method for preparing a superconducting circuit with a large inductance layer according to the first embodiment of the present invention.

[0051] Fig.16It is a schematic cross-sectional structure diagram of step S1 in the method for preparing a superconducting circuit with a large inductance layer according to the second embodiment of the present invention.

[0052] Component number description

[0053] 100 Substrate

[0054] 101 Bypass resistor

[0055] 102 first insulating material layer

[0056] 103 First opening

[0057] 104 First superconducting material layer

[0058] 105 Barrier material layer

[0059] 106 Second superconducting material layer

[0060] 107 Upper electrode

[0061] 108 Barrier layer

[0062] 109 Lower electrode

[0063] 110 second insulating material layer

[0064] 111 Large Inductance Layer

[0065] 112 Second opening

[0066] 113 third insulating material layer

[0067] 114 The third superconducting material layer

[0068] 115 Wiring layer

[0069] 116 fourth insulating material layer

[0070] 117 Fourth superconducting material layer

[0071] 118 Ground layer

[0072] 119 The third opening

[0073] Steps S1 to S7 DETAILED DESCRIPTION

[0074] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] See also Figures 1 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed according to actual needs, and the component layout type may also be more complicated.

[0076] Embodiment 1

[0077] like Figure 1 As shown, this embodiment provides a method for preparing a superconducting circuit with a large inductance layer, and the preparation method comprises the following steps:

[0078] S1, providing a substrate, and forming a bypass resistor on the substrate;

[0079] S2, forming a patterned first insulating material layer having a first opening on the surface of the structure obtained above, wherein the first opening exposes the bypass resistor;

[0080] S3, sequentially forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer on the surface of the structure obtained above;

[0081] S4, etching the three-layer thin film structure from top to bottom with different patterns to form a Josephson junction;

[0082] S5, forming an imaged second insulating material layer on the surface of the structure obtained above, and forming a large inductor layer on the second insulating material layer;

[0083] S6, forming a patterned third insulating material layer having a plurality of second openings on the surface of the structure obtained above, wherein the plurality of second openings respectively expose the upper surfaces of the large inductance layer and the Josephson junction;

[0084] S7, forming a third superconducting material layer on the surface of the structure obtained above, and etching the third superconducting material layer to form a wiring layer.

[0085] The method for preparing a superconducting circuit with a large inductance layer of this embodiment is described in detail below with reference to the accompanying drawings.

[0086] like Figure 1 S1 and Figure 2 As shown, step S1 is first performed to provide a substrate 100 and form a bypass resistor 101 on the substrate 100 .

[0087] The substrate 100 may include at least one of a silicon substrate, a silicon oxide substrate, a magnesium oxide substrate, a sapphire substrate and a silicon carbide substrate, but is not limited thereto. Any substrate suitable for preparing a superconducting circuit may be used.

[0088] As an example, a specific method for forming the bypass resistor 101 includes: first forming a bypass resistor material layer on the substrate 100; then performing photolithography-etching on the bypass resistor material layer to achieve patterning of the bypass resistor material layer, thereby obtaining the bypass resistor 101. The bypass resistor 101 can be selected as a single Mo layer; or a stacked structure of a Pd layer and a Ti layer, wherein the Ti layer is used as an adhesion layer and the Pd layer is used as a main resistance material layer. The Ti layer can achieve good adhesion between the substrate and the Pd layer. Generally, the thickness of the Ti layer is relatively thin, about 6nm to 20nm, and the thickness of the Pd layer is set according to the needs of the specific resistance size, generally between 20nm and 100nm.

[0089] like Figure 1 S2 and Figure 3 As shown, step S2 is then performed to form a patterned first insulating material layer 102 having a first opening 103 on the surface of the structure obtained above, and the first opening 103 reveals the bypass resistor 101. The shape and layout of the bypass resistor 101 can be designed according to actual needs.

[0090] As a specific example method: firstly, the first insulating material layer 102 is formed by a PECVD process on the surface of the structure obtained above; then, the first insulating material layer 102 is patterned by photolithography-etching, and the first opening 103 is formed.

[0091] The material of the first insulating material layer 102 includes SiO2 or SiNx, but is not limited thereto, and other materials with better insulating properties may also be used.

[0092] like Figure 1 S3 and Figure 4 As shown, step S3 is then performed to sequentially form a three-layer thin film structure of a first superconducting material layer 104, a barrier material layer 105, and a second superconducting material layer 106 on the surface of the structure obtained above.

[0093] Specifically, the first superconducting material layer 104 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be one of them or a laminated structure composed of the two; the second superconducting material layer 106 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be one of them or a laminated structure composed of the two; in addition, the barrier material layer 105 is an aluminum-containing material layer, and the aluminum-containing material layer includes at least one of an aluminum layer, an aluminum oxide layer and an aluminum nitride layer, that is, it can be one of them or a laminated structure composed of two or more. In this embodiment, the first superconducting material layer 104 is a Nb layer; the second superconducting material layer 106 is a Nb layer; and the barrier material layer 105 is an Al-AlOx layer.

[0094] like Figure 1 S4 and Figure 5 As shown, step S4 is then performed, and the three-layer thin film structure is etched from top to bottom with different patterns to form a Josephson junction. Specifically, the second superconducting material layer 106 is first photolithographically etched to obtain an upper electrode layer 107; then the barrier material layer 105 is photolithographically etched to obtain a barrier layer 108; finally, the first superconducting material layer 104 is photolithographically etched to obtain a lower electrode layer 109, and the lower electrode layer 109 is electrically connected to the bypass resistor 101. The Josephson junction is formed by the upper electrode layer 107, the barrier layer 108 and the lower electrode layer 109. The shapes and layouts of the upper electrode layer 107, the barrier layer 108 and the lower electrode layer 109 are designed according to actual needs.

[0095] like Figure 1 S5 and Figures 6 to 9 As shown, step S5 is then performed to form a patterned second insulating material layer 110 on the surface of the structure obtained above, and a large inductor layer 111 is formed on the second insulating material layer 110. The shape and layout of the large inductor layer are designed according to actual needs.

[0096] like Figure 6 As shown, after forming the second insulating material layer 110, the second insulating material layer 110 may not be etched to form an opening to expose the upper surface of the Joseph junction; Fig. 9 As shown, a large inductor layer 111 is then formed on the second insulating material layer 110. In this way, after the third insulating material layer 113 is subsequently formed, the second insulating material layer 110 and the third insulating material layer 113 are etched together to form an opening exposing the upper surface of the Josephson junction, as shown in FIG. Fig.10 shown.

[0097] like Figure 7 As shown, after forming the second insulating material layer 110, the second insulating material layer 110 may be etched to form a third opening 119 exposing the upper surface of the Joseph junction; Figure 8 As shown, a large inductor layer 111 is then formed on the second insulating material layer 110. This method can be used to etch only the third insulating material layer 113 to form an opening that exposes the upper surface of the Josephson junction after the third insulating material layer 113 is subsequently formed. Fig.10 shown.

[0098] As an example, the material of the second insulating material layer 110 includes SiO 2 or SiN x , but is not limited thereto, and other materials with better insulating properties may also be used.

[0099] As an example, the material of the large inductance layer 111 is NbN or MoN. If the material of the large inductance layer 111 is MoN, the large inductance layer 111 can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit.

[0100] like Figure 1 S6 and Fig.10 As shown, step S6 is then performed to form a patterned third insulating material layer 113 having a plurality of second openings 112 on the surface of the structure obtained above, wherein the plurality of second openings 112 respectively expose the upper surfaces of the large inductor layer 111 and the Josephson junction.

[0101] As an example, the material of the third insulating material layer 113 includes SiO 2 or SiNx, but is not limited thereto, and other materials with better insulating properties may also be used.

[0102] like Figure 1 S7 and Fig.11 and Fig.12 As shown, step S7 is finally performed to form a third superconducting material layer 114 on the surface of the structure obtained above, and the third superconducting material layer 114 is etched to form a wiring layer 115, so as to lead out the corresponding electrical signal. The material of the wiring layer 115 can be at least one of niobium nitride or niobium. In this embodiment, the material of the wiring layer 115 is niobium.

[0103] In addition, in some scenarios, the superconducting circuit needs to be grounded to shield external noise. At this time, it is necessary to form a grounding layer in the superconducting circuit. The specific preparation method is as follows: Fig.13 As shown, a fourth insulating material layer 116 is formed on the surface of the structure obtained above, and the fourth insulating material layer 116 is patterned. The material of the fourth insulating material layer 116 includes SiO2 or SiNx, but is not limited thereto. Other materials with better insulating properties may also be used; Fig.14 As shown, a fourth superconducting material layer 117 is then formed on the surface of the structure obtained above, as shown in FIG. Fig.15 As shown, the fourth superconducting material layer 117 is etched to form a grounding layer 118, so as to lead out the corresponding electrical signal.

[0104] It should be noted that the materials of the insulating material layers used in the method for preparing the superconducting circuit of this embodiment, such as the first insulating material layer 102, the second insulating material layer 110, the third insulating material layer 113 and the fourth insulating material layer 116, can be kept consistent, thereby achieving homogeneous growth of the insulating material layers. There is no obvious interface during homogeneous growth, and there is no impact on subsequent processes.

[0105] Based on the above superconducting circuit preparation method, such as Fig.12 See Figures 1 to 11 This embodiment further provides a superconducting circuit with a large inductance layer, the superconducting circuit comprising:

[0106] A substrate 100; a bypass resistor 101 formed on the substrate 100; a Josephson junction formed on the bypass resistor 101, wherein the Josephson junction is composed of the upper electrode layer 107, the barrier layer 108 and the lower electrode layer 109; a large inductance layer 111 formed on the Josephson junction; a wiring layer 115 formed on the large inductance layer 111; and an insulating material layer, which electrically isolates the bypass resistor 101, the Josephson junction, the large inductance layer 111 and the wiring layer 115, respectively, and the insulating material layer includes the first insulating material layer 102, the second insulating material layer 110 and the third insulating material layer 113.

[0107] like Fig.15 See Figure 13 to Figure 14 As an example, the superconducting circuit further includes a grounding layer 118 formed on the wiring layer 115 , and the insulating layer further electrically isolates the grounding layer 118 , that is, the insulating material layer further includes the fourth insulating material layer 116 .

[0108] As an example, the bypass resistor 101 is a stack of a Mo layer or a Pd layer and a Ti layer; the material of the large inductance layer 111 is NbN or MoN. If the material of the large inductance layer 111 is MoN, the large inductance layer 111 can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit.

[0109] Based on the above-mentioned superconducting circuit preparation method and superconducting circuit, a special large inductance layer is designed and added to the small and medium inductance design of the original wiring layer for application in superconducting circuits requiring large inductance, which effectively expands the inductance range in the superconducting circuit, broadens the application scenarios of the superconducting circuit, and improves the integration of the superconducting circuit; in addition, the large inductance layer of a specific material can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit.

[0110] Embodiment 2

[0111] This embodiment provides another method for preparing a superconducting circuit with a large inductance layer. The method is basically the same as the method for preparing the superconducting circuit in the first embodiment, except that: Fig.16 As shown, after providing a substrate 100, the large inductance layer 111 is prepared on the substrate 100 while the bypass resistor 101 is prepared, that is, the large inductance layer 111 formed by the preparation method of this embodiment is formed on the substrate. The preparation method is specifically as follows:

[0112] S1, providing a substrate, and forming a bypass resistor and a large inductor layer on the substrate respectively;

[0113] S2, forming a first insulating material layer having a plurality of first openings on the surface of the structure obtained above, wherein the plurality of first openings respectively expose the bypass resistor and the large inductance layer;

[0114] S3, sequentially forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer on the surface of the structure obtained above;

[0115] S4, etching the three-layer thin film structure from top to bottom with different patterns to form a Josephson junction;

[0116] S5, forming a second insulating material layer having a second opening on the surface of the structure obtained above, wherein the second opening exposes the upper surface of the Josephson junction;

[0117] S6, forming a third superconducting material layer on the surface of the structure obtained above, and etching the third superconducting material layer to form a wiring layer.

[0118] As an example, in some scenarios, the superconducting circuit needs to be grounded to shield external noise. At this time, a grounding layer needs to be formed in the superconducting circuit. The specific preparation method is: first, a third insulating material layer is formed on the surface of the above-obtained structure, and the third insulating material is patterned; then, a fourth superconducting material layer is formed on the surface of the above-obtained structure, and the fourth superconducting material layer is etched to form a grounding layer.

[0119] As an example, the bypass resistor is a stack of a Mo layer or a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN. If the material of the large inductance layer is MoN, the large inductance layer can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit.

[0120] Based on the preparation method, this embodiment also provides a superconducting circuit with a large inductance layer, the superconducting circuit comprising:

[0121] A substrate; a bypass resistor and a large inductance layer formed on the substrate; a Josephson junction formed on the bypass resistor and the large inductance layer; a wiring layer formed on the Josephson junction; and an insulating material layer, electrically isolating the bypass resistor, the Josephson junction, the large inductance layer and the wiring layer.

[0122] As an example, the superconducting circuit further includes a ground layer formed on the wiring layer, and the insulating material layer further electrically isolates the ground layer, that is, the insulating material layer further includes the third insulating material layer.

[0123] As an example, the bypass resistor is a stack of a Mo layer or a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN. If the material of the large inductance layer is MoN, the large inductance layer can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit.

[0124] Based on the above-mentioned superconducting circuit preparation method and superconducting circuit, a special large inductance layer is designed and added to the small and medium inductance design of the original wiring layer for application in superconducting circuits requiring large inductance, which effectively expands the inductance range in the superconducting circuit, broadens the application scenarios of the superconducting circuit, and improves the integration of the superconducting circuit; in addition, the large inductance layer of a specific material can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit.

[0125] In summary, the present invention provides a superconducting circuit with a large inductance layer and a preparation method thereof. By utilizing the small and medium inductance design of the original wiring layer, a special large inductance layer is designed and added to the superconducting circuit that requires a large inductance, which effectively expands the inductance range in the superconducting circuit, broadens the application scenarios of the superconducting circuit, and improves the integration of the superconducting circuit; in addition, the large inductance layer of a specific material can also be used as a large resistance layer, thereby further improving the integration of the superconducting circuit. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0126] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a superconducting circuit having a large inductance layer, characterized in that: The preparation method comprises: 1) providing a substrate and forming a bypass resistor on the substrate; 2) forming a patterned first insulating material layer having a first opening on the surface of the structure obtained above, wherein the first opening exposes the bypass resistor; 3) forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer in sequence on the surface of the structure obtained above; 4) etching the three-layer thin film structure from top to bottom with different patterns to form a Josephson junction; 5) forming a patterned second insulating material layer on the surface of the structure obtained above, and forming a large inductor layer on the second insulating material layer; 6) forming a patterned third insulating material layer having a plurality of second openings on the surface of the structure obtained above, wherein the plurality of second openings respectively expose the upper surfaces of the large inductance layer and the Josephson junction; 7) forming a third superconducting material layer on the surface of the structure obtained above, and etching the third superconducting material layer to form a wiring layer.

2. The method for preparing a superconducting circuit with a large inductance layer according to claim 1, characterized in that: Step 7) also includes: 8) forming a fourth insulating material layer on the surface of the structure obtained in step 7), and patterning the fourth insulating material layer; 9) forming a fourth superconducting material layer on the surface of the structure obtained above, and etching the fourth superconducting material layer to form a grounding layer.

3. The method for preparing a superconducting circuit with a large inductance layer according to claim 1, characterized in that: Step 5) also includes: etching the second insulating material layer to form a third opening, wherein the third opening exposes the upper surface of the Josephson junction.

4. The method for preparing a superconducting circuit with a large inductance layer according to claim 1, characterized in that: The bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.

5. A method for preparing a superconducting circuit having a large inductance layer, characterized in that: The preparation method comprises: 1) Providing a substrate, and forming a bypass resistor and a large inductor layer on the substrate respectively; 2) forming a first insulating material layer having a plurality of first openings on the surface of the structure obtained above, wherein the plurality of first openings respectively expose the bypass resistor and the large inductance layer; 3) forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer in sequence on the surface of the structure obtained above; 4) etching the three-layer thin film structure from top to bottom with different patterns to form a Josephson junction; 5) forming a second insulating material layer having a second opening on the surface of the structure obtained above, wherein the second opening exposes the upper surface of the Josephson junction; 6) forming a third superconducting material layer on the surface of the structure obtained above, and etching the third superconducting material layer to form a wiring layer.

6. The method for preparing a superconducting circuit with a large inductance layer according to claim 5, characterized in that: Step 6) also includes: 7) forming a third insulating material layer on the surface of the structure obtained in step 6), and patterning the third insulating material; 8) forming a fourth superconducting material layer on the surface of the structure obtained above, and etching the fourth superconducting material layer to form a grounding layer.

7. The method for preparing a superconducting circuit with a large inductance layer according to claim 5, characterized in that: The bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.

8. A superconducting circuit having a large inductance layer, characterized in that: The superconducting circuit comprises: substrate; a shunt resistor formed on the substrate; a Josephson junction formed on the shunt resistor; a large inductance layer formed on the Josephson junction; a wiring layer formed on the large inductance layer; The insulating material layer electrically isolates the bypass resistor, the Josephson junction, the large inductance layer and the wiring layer respectively.

9. The superconducting circuit with a large inductance layer according to claim 8, characterized in that: Also includes: A ground layer is formed on the wiring layer, and the insulating material layer also electrically isolates the ground layer.

10. The superconducting circuit with a large inductance layer according to claim 8, characterized in that: The bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.

11. A superconducting circuit having a large inductance layer, characterized in that: The superconducting circuit comprises: substrate; A shunt resistor and a large inductance layer formed on the substrate; A Josephson junction formed on the bypass resistor and the large inductance layer; a wiring layer formed on the Josephson junction; The insulating material layer electrically isolates the bypass resistor, the Josephson junction, the large inductance layer and the wiring layer respectively.

12. The superconducting circuit with a large inductance layer according to claim 11, characterized in that: Also includes: A ground layer is formed on the wiring layer, and the insulating material layer also electrically isolates the ground layer.

13. The superconducting circuit with a large inductance layer according to claim 11, characterized in that: The bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.

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