A method for managing fifo interrupts
By using the FIFO interrupt management method, interrupt requests are synchronized and written into the priority FIFO, solving the problem that integrated circuit interrupt managers cannot expand ports and priorities, and realizing complete processing of interrupt requests and improving system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN JINHANG INST OF TECH PHYSICS
- Filing Date
- 2021-11-25
- Publication Date
- 2026-07-10
AI Technical Summary
Existing integrated circuit interrupt managers cannot effectively manage multiple interrupt requests, resulting in interrupt loss and interrupt overwriting, and cannot expand the number and priority of interrupt ports, nor can they save the number of interrupt requests.
The FIFO interrupt management method is adopted. The interrupt request is synchronized by the interrupt synchronization clock and written into the FIFO of the corresponding priority. The flag signal bit is used to represent the valid interrupt request. The interrupt enable module reads the interrupt vector according to the priority.
It enables flexible management of interrupt ports and priorities, avoids interrupt loss and overwriting, ensures that all interrupt requests are processed, and improves system reliability and efficiency.
Smart Images
Figure CN114201276B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of interrupt management methods, and in particular to a FIFO-based interrupt management method. Background Technology
[0002] Interrupt technology is a commonly used and important technology in integrated circuits, primarily used to improve the real-time response requirements of integrated circuits. In practical applications, there are often more than one interrupt port, interrupt requests may come from inside or outside the integrated circuit, interrupt response priorities have different requirements, and the synchronization relationships between interrupts and between interrupts and the integrated circuit are unclear. These situations place high demands on the interrupt management within the integrated circuit.
[0003] Existing application-specific integrated circuits (ASICs), reduced instruction set processors (ARMs), and digital signal processors (DSPs) all have dedicated interrupt managers. These typically handle fewer than 32 interrupt ports with fewer than 3 priority levels, and the number and priority can only be configured within this maximum range, without expansion. For the same interrupt port, if one or more interrupt requests occur while the current interrupt request is waiting for a response, the dedicated interrupt manager only responds once and cannot save the number of interrupt requests. Interrupt loss and interrupt overwriting are unacceptable for high-accuracy systems. Therefore, this application proposes a FIFO-based interrupt management method. Summary of the Invention
[0004] The purpose of this application is to provide a FIFO-based interrupt management method to address the above problems.
[0005] This application provides a method for FIFO interrupt management, the method comprising the following steps:
[0006] Acquire several interrupt requests sent from inside or outside the FPGA, wherein the interrupt requests include priority information and port number information;
[0007] The FIFO corresponding to the priority information and the synchronization module corresponding to the port number information are determined; each interrupt request is configured with an independent synchronization module; each synchronization module of the same priority FIFO uses the same interrupt synchronization clock;
[0008] The interrupt request is synchronized using the interrupt synchronization clock;
[0009] Write the interrupt request into the FIFO of the corresponding priority;
[0010] The interrupt enable module reads the interrupt vectors corresponding to the interrupt requests stored in each FIFO according to priority.
[0011] According to certain embodiments of the present application, synchronizing the interrupt request using the interrupt synchronization clock specifically includes:
[0012] The interruption request is cached for two cycles.
[0013] The interrupt request is sampled on both sides to determine the interrupt type; the interrupt type includes high-level triggered interrupt, low-level triggered interrupt, rising edge triggered interrupt, and falling edge triggered interrupt;
[0014] The interrupt request is converted to a rising edge triggered interrupt type, and the interrupt request is high for one interrupt synchronization clock width before going low.
[0015] According to the technical solutions provided in certain embodiments of this application, writing the interrupt request into a FIFO of a corresponding priority specifically includes:
[0016] Output a high-level active interrupt request signal with the width of the interrupt synchronization clock pulse to the corresponding bit of the corresponding priority FIFO; the write data and read data bit widths of the same priority FIFO are the same, and are equal to the number of interrupt ports of the FIFO of that priority.
[0017] According to the technical solutions provided in certain embodiments of this application, each FIFO has a flag signal bit, which is used to characterize whether a valid interrupt request is stored in the corresponding FIFO.
[0018] The technical solutions provided according to certain embodiments of this application also include:
[0019] If the result of bitwise ORing the interrupt request signals output by all synchronization modules in the same priority FIFO is 1, set the flag signal of the corresponding FIFO to high level; otherwise, set it to low level.
[0020] According to the technical solutions provided in certain embodiments of this application, reading the interrupt vectors corresponding to the interrupt requests stored in each FIFO according to priority by the interrupt enable module specifically includes:
[0021] Read the FIFO data with the highest priority where the current flag signal bit is high;
[0022] The sum of each data bit in the read data is used to obtain the number of valid interrupt requests in the current priority FIFO at this moment;
[0023] The interrupt vectors of each valid interrupt request are output to the interrupt response routine according to the port number size represented by the port number information; the smaller the port number, the higher the priority.
[0024] Upon receiving the interrupt response completion signal from the interrupt response routine, set the data bit corresponding to the interrupt request to 0.
[0025] According to the technical solutions provided in certain embodiments of this application, when all valid interrupt requests in the same priority FIFO have completed the interrupt response, the flag signal of the FIFO is at a low level.
[0026] Compared with the prior art, the beneficial effects of this application are as follows: This invention uses an interrupt synchronization clock to synchronize internal or external interrupt requests, and writes the synchronized interrupt requests into corresponding priority FIFOs. Different priority FIFOs have different flag signal bits. The interrupt enable module first reads the data of the highest priority FIFO when the flag signal bit is high, and outputs the interrupt vectors in sequence when the interrupt response completion signal is high. The CPU calls the corresponding interrupt service routine according to the interrupt vector. The FIFO-based interrupt management method proposed in this application can realize the interrupt management function in FPGA and overcome the problems of interrupt loss and interrupt overwriting in common integrated circuits. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of a FIFO interrupt management system applied to an FPGA, as provided in an embodiment of this application. Detailed Implementation
[0028] To enable those skilled in the art to better understand the technical solution of this application, the application will be described in detail below with reference to the accompanying drawings. The description in this section is only exemplary and explanatory, and should not be used to limit the scope of protection of this application.
[0029] like Figure 1 As shown, this embodiment provides a FIFO-based interrupt management system for FPGA, which includes an interrupt enable module, several FIFOs with different priorities, and several synchronization modules.
[0030] Each FIFO is configured with several synchronization modules. All synchronization modules corresponding to a FIFO use the same interrupt synchronization clock. Synchronization modules of FIFOs with different priorities can use the same or different interrupt synchronization clocks.
[0031] The number of synchronization modules configured in each FIFO is the same as the number of interrupt requests that the FIFO can receive; that is, each interrupt request is configured with an independent synchronization module.
[0032] The number of priorities set in the system is consistent with the number of priority FIFOs, and the smaller the priority number, the higher the priority level. Priority FIFOs with the same priority are not allowed. When there are not enough interrupt ports for a certain priority, the data bit width of the corresponding priority FIFO can be increased.
[0033] Each priority FIFO uses independent write and read clocks. The write clock is the interrupt synchronization clock of the synchronization module, and the read clock is the system clock of the interrupt enable module. The write and read data bit widths of the FIFO are the same, and are equal to the number of interrupt ports of that priority FIFO.
[0034] Figure 1 In this context, a priority 1 FIFO has four interrupt ports, meaning it can receive four priority 1 interrupt requests. These four priority 1 interrupt requests correspond to four synchronization modules using the same interrupt synchronization clock. The write and read data widths of a priority 1 FIFO are both four bits. A priority N FIFO has six interrupt ports, meaning it can receive six priority N interrupt requests. These six priority N interrupt requests correspond to six synchronization modules using the same interrupt synchronization clock. The write and read data widths of a priority N FIFO are both six bits.
[0035] Each priority FIFO has a flag signal bit, which is used to indicate whether a valid interrupt request is stored in the corresponding priority FIFO. When a valid interrupt request is stored, the flag signal bit is high, otherwise it is low.
[0036] The interrupt enable module is used to read the interrupt vectors corresponding to valid interrupt requests stored in each priority FIFO in descending order of priority, and transmit them to the CPU interrupt response program. When the CPU completes the interrupt response, it will send the corresponding completion signal to the interrupt enable module.
[0037] This embodiment also provides a FIFO interrupt management method, which is based on the above-mentioned FIFO interrupt management system applied to FPGA, and the method includes the following steps:
[0038] S1. Obtain several interrupt requests sent from inside or outside the FPGA. The interrupt requests include priority information and port number information.
[0039] The priority information indicates the priority of the FIFO to which the current interrupt request belongs, and the port number information indicates the port number of the current interrupt request in the priority FIFO. The port number generally starts from 1.
[0040] S2. Determine the FIFO corresponding to the priority information and the synchronization module corresponding to the port number information; each interrupt request is configured with an independent synchronization module; each synchronization module of the same priority FIFO uses the same interrupt synchronization clock.
[0041] S3. Synchronize the interrupt request using the interrupt synchronization clock.
[0042] Specifically, the synchronization module uses an interrupt synchronization clock to synchronize each interrupt request, which can come from outside the FPGA or from inside the FPGA. The synchronization module performs two-step buffering and dual-edge sampling on the interrupt request. The purpose of the two-step buffering is to determine and convert the types of different interrupt requests, and to uniformly convert different interrupt request types into rising edge triggered interrupt types. The interrupt types that can be received are high-level triggered interrupt, low-level triggered interrupt, rising edge triggered interrupt, and falling edge triggered interrupt.
[0043] S4. Write the interrupt request into the FIFO of the corresponding priority.
[0044] Specifically, after synchronizing the interrupt request, the synchronization module will output a high-level active interrupt request signal with the width of the interrupt synchronization clock pulse to the corresponding bit of the corresponding priority FIFO; the write data and read data bit widths of the same priority FIFO are the same, and are equal to the number of interrupt ports of the FIFO of that priority.
[0045] The write enable of each priority FIFO is the result of bitwise ORing of the interrupt request signals output by all synchronization modules, and the write data is the result of bitwise concatenation of the interrupt request signals output by all synchronization modules.
[0046] Specifically, when the result of the bitwise OR operation of the interrupt request signals output by all synchronization modules in the same priority FIFO is 1, it means that at least one valid interrupt request is stored in that priority FIFO. Therefore, the flag signal of the corresponding priority FIFO is set to a high level. Conversely, when the result of the bitwise OR operation of the interrupt request signals output by all synchronization modules in the same priority FIFO is 0, it means that there is no valid interrupt request in that priority FIFO. Therefore, the flag signal of the corresponding priority FIFO is set to a low level.
[0047] If a certain priority FIFO has four interrupt ports, which can receive interrupt request 1, interrupt request 2, interrupt request 3 and interrupt request 4 of that priority respectively, and interrupt request 1 and interrupt request 4 are received at the same time, then the data written in the current priority FIFO, that is, the result of stitching together the interrupt request signals output by all synchronization modules, is: 1001.
[0048] S5. The interrupt vectors corresponding to the interrupt requests stored in each FIFO are read out according to priority by the interrupt enable module. Specifically, this includes:
[0049] Read the FIFO data with the highest priority where the current flag signal bit is high;
[0050] The sum of each data bit in the read data is used to obtain the number of valid interrupt requests in the current priority FIFO at this moment;
[0051] The interrupt vectors of each valid interrupt request are output to the interrupt response routine according to the port number size represented by the port number information; the smaller the port number, the higher the priority.
[0052] Upon receiving the interrupt response completion signal from the interrupt response routine, set the data bit corresponding to the interrupt request to 0.
[0053] Specifically, the interrupt enable module receives data from different priority FIFOs whose current flag signal bit is high. When the previous interrupt is processed, it first reads the data from the highest priority FIFO among all the different priority FIFOs whose current flag signal bit is high. The sum of the bits in the highest priority FIFO data is the number of valid interrupt requests to be processed in the current priority FIFO. According to the principle that the smaller the port number, the higher the priority, the interrupt vector of the interrupt request with the smaller port number is first output to the interrupt response program. After the interrupt response program completes the interrupt response, it returns a completion signal to the interrupt enable module. At this time, the data bit corresponding to the interrupt request is set to 0. The above steps are repeated. When all valid interrupt requests in the highest priority FIFO have completed the interrupt response, the flag signal bit of the priority FIFO is set to low, and the interrupt processing is completed.
[0054] After the highest priority FIFO in the system completes the interrupt handling, the data from the highest priority FIFO with the flag signal bit high is read and processed in a similar manner. The specific steps will not be described here.
[0055] Next, we will further explain the above-mentioned FIFO-based interrupt management method with examples:
[0056] Suppose a FIFO interrupt-managed system applied to an FPGA has two priority FIFOs, denoted as the first priority FIFO and the second priority FIFO. The first priority FIFO is numbered 1, and the second priority FIFO is numbered 2. The first priority FIFO is configured with four interrupt ports, corresponding to four synchronization modules, and the second priority FIFO is configured with six interrupt ports, corresponding to six synchronization modules. The four synchronization modules corresponding to the first priority FIFO use an interrupt synchronization clock of 200MHz (clock period 5ns), and the write clock of the first priority FIFO is 200MHz, with a write and read data bit width of 4. The six synchronization modules corresponding to the second priority FIFO use an interrupt synchronization clock of 100MHz (clock period 10ns), and the write clock of the second priority FIFO is 100MHz, with a write and read data bit width of 6. The interrupt enable module clock is 160MHz (clock period 6.25ns). The read clocks of the first priority FIFO and the second priority FIFO are both 160MHz.
[0057] When interrupt requests 1 and 4 of the first priority FIFO simultaneously occur with rising edges, the corresponding synchronization module uses a 200MHz clock to synchronize the first priority interrupt requests 1 and 4, and outputs two 5ns wide high-level active interrupt request signals to the 1st and 4th bits of the write data of the first priority FIFO. At the same time, the first priority FIFO write enable is set to a 5ns wide high level, and the flag signal of the first priority FIFO is set to a high level.
[0058] When the interrupt response completion signal is high, that is, when the previous interrupt is processed, the interrupt enable module reads the data (4`b1001) stored in the first priority FIFO, sums the bits of the data, and determines that the number of valid interrupt requests is 2. According to the principle that the smaller the port number, the higher the priority, the interrupt vector of interrupt request 1 of the first priority FIFO is first output to the interrupt response program, and the interrupt response completion signal goes low. When the interrupt response program completes the interrupt response, the interrupt response completion signal will go high again, and the interrupt enable module will output the interrupt vector of interrupt request 4 of the first priority FIFO.
[0059] The total time from the occurrence of interrupt request 1 in the first priority FIFO to its interrupt vector output is (2+1)*5+(1+1)*6.25=27.5ns; the total time from the occurrence of interrupt request 4 in the first priority FIFO to its interrupt vector output is (2+1)*5+(1+1)*6.25+interrupt request 1 interrupt response time, which is the sum of interrupt request 1 response time and interrupt request 1 processing time.
[0060] It can be seen that the FIFO-based interrupt management method proposed in this application can save interrupt processing time and ensure the reliability and efficiency of the system.
[0061] The FIFO-based interrupt management method provided in this application utilizes a FIFO to implement interrupt management within an FPGA, overcoming the problems of interrupt loss and overwriting common in integrated circuits. The number of interrupt ports and their priorities can be flexibly increased or decreased in this interrupt management method, and all interrupt requests are stored for later interrupt response processing. This method can be applied to interrupt management in high-accuracy infrared search and tracking systems.
[0062] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.
Claims
1. A method for FIFO-based interrupt management, characterized in that, The method includes the following steps: Acquire several interrupt requests sent from inside or outside the FPGA, wherein the interrupt requests include priority information and port number information; Determine the FIFO corresponding to the priority information and the synchronization module corresponding to the port number information; Each interruption request is configured with an independent synchronization module; The synchronization modules of the same priority FIFO use the same interrupt synchronization clock; The interrupt request is synchronized using the interrupt synchronization clock; Write the interrupt request into the FIFO of the corresponding priority; The interrupt vector corresponding to the interrupt request stored in each FIFO is read out according to priority by the interrupt enable module; Synchronizing the interrupt request via the interrupt synchronization clock specifically includes: The interruption request is cached for two cycles; The interrupt request is sampled on both sides to determine the interrupt type; the interrupt type includes high-level triggered interrupt, low-level triggered interrupt, rising edge triggered interrupt, and falling edge triggered interrupt; The interrupt request is converted to a rising edge triggered interrupt type, and the interrupt request is high for one interrupt synchronization clock width before going low. The interrupt vectors corresponding to the interrupt requests stored in each FIFO are read out by the interrupt enable module according to priority. Specifically, this includes: Read the FIFO data with the highest priority where the current flag signal bit is high; The sum of each data bit in the read data is used to obtain the number of valid interrupt requests in the current priority FIFO at this moment; The interrupt vectors of each valid interrupt request are output to the interrupt response routine according to the port number size represented by the port number information; the smaller the port number, the higher the priority. Upon receiving the interrupt response completion signal from the interrupt response routine, set the data bit corresponding to the interrupt request to 0.
2. The method for FIFO-based interrupt management according to claim 1, characterized in that, Writing the interrupt request into the FIFO of the corresponding priority specifically includes: Output a high-level active interrupt request signal of the interrupt synchronization clock pulse width to the corresponding bit of the corresponding priority FIFO; For FIFOs of the same priority, the data width for writing and reading is the same, which is equal to the number of interrupt ports of that priority FIFO.
3. The FIFO-based interrupt management method according to claim 2, characterized in that, Each FIFO has a flag signal bit, which is used to indicate whether a valid interrupt request is stored in the corresponding FIFO.
4. The FIFO-based interrupt management method according to claim 3, characterized in that, Also includes: If the result of bitwise ORing the interrupt request signals output by all synchronization modules in the same priority FIFO is 1, set the flag signal of the corresponding FIFO to high level; otherwise, set it to low level.
5. The FIFO-based interrupt management method according to claim 1, characterized in that, When all valid interrupt requests in a FIFO of the same priority have completed their interrupt responses, the flag signal of that FIFO is set to a low level.