Disk device

Abstract

An embodiment provides a disk device capable of suppressing noise propagation between wirings. The disk device involved in one embodiment comprises a recording medium, a suspension, a magnetic head, an actuator, a circuit substrate, an FPC, a preamplifier, and an actuator driver. The magnetic head and the actuator are mounted on the suspension. The circuit substrate is provided with a control circuit. The FPC is connected to the suspension and the circuit substrate. The preamplifier is mounted on the FPC, outputs a write signal corresponding to the information that the magnetic head is to write to the recording medium to the magnetic head, and receives a read signal corresponding to the information read from the recording medium by the magnetic head from the magnetic head. The actuator driver is mounted on the FPC in a manner away from the preamplifier, and outputs a drive signal to the actuator to drive the actuator.

Description

[0001] This application claims the priority of Japanese Patent Application No. 2020-156422 (filing date: September 17, 2020) as a basic application, and the entire contents of the basic application are incorporated herein by reference. Technical Field

[0002] An embodiment of the present invention relates to a disk device. Background Art

[0003] A disk device such as a hard disk drive reads and writes information on a recording medium using a magnetic head mounted on a suspension. The disk device moves the magnetic head to a target position by, for example, rotating an arm on which the suspension is mounted. Furthermore, the disk device can move the magnetic head to a target position using an actuator provided on the suspension.

[0004] The driver that drives the actuator applies a high-voltage drive signal to the actuator. Therefore, the impedance of the wiring between the driver and the actuator becomes high, and noise is easily propagated to other wirings. Summary of the invention

[0005] An embodiment of the present invention provides a disk device capable of suppressing propagation of noise between wirings.

[0006] A disk device according to one embodiment comprises a disk-shaped recording medium, a suspension, a magnetic head, an actuator, a circuit substrate, a flexible printed wiring board, a preamplifier and an actuator driver. The magnetic head is mounted on the suspension and is configured to read and write information on the recording medium. The actuator is mounted on the suspension and moves the magnetic head. The circuit substrate is provided with a control circuit for controlling the magnetic head and the actuator. The flexible printed wiring board has a first connection portion connected to the suspension and a second connection portion connected to the circuit substrate. The preamplifier is mounted on the flexible printed wiring board and outputs a write signal corresponding to the information to be written by the magnetic head to the recording medium to the magnetic head, and receives a read signal corresponding to the information read from the recording medium by the magnetic head from the magnetic head. The actuator driver is mounted on the flexible printed wiring board in a manner separated from the preamplifier and outputs a drive signal to the actuator for driving the actuator. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a perspective view showing an example of a hard disk drive according to the first embodiment.

[0008] Figure 2 It is a perspective view showing an example of a part of the suspension according to the first embodiment.

[0009] Figure 3It is a plan view schematically showing an example of the flexible printed wiring board according to the first embodiment.

[0010] Figure 4 This is a block diagram schematically showing an example of the function of the hard disk drive according to the first embodiment.

[0011] Figure 5 This is an illustrative timing chart showing an example of a serial signal output by the system on chip according to the first embodiment.

[0012] Figure 6 This is a block diagram schematically showing an example of the function of the hard disk drive according to the second embodiment.

[0013] Figure 7 This is an illustrative timing chart showing an example of a serial signal output by the system on chip according to the third embodiment.

[0014] Figure 8 This is an illustrative timing chart showing an example of a serial signal output by the system on chip according to the fourth embodiment.

[0015] Fig. 9 This is an illustrative timing chart showing an example of a serial signal output by the system on chip according to the fifth embodiment.

[0016] Fig.10 This is a block diagram schematically showing an example of the function of the hard disk drive according to the sixth embodiment.

[0017] Fig.11 This is a block diagram schematically showing an example of the function of the hard disk drive involved in the seventh embodiment. DETAILED DESCRIPTION

[0018] (First embodiment)

[0019] Below, refer to Figure 1 to Figure 5 The first embodiment is described. In addition, in this specification, sometimes the components and descriptions of the components involved in the embodiment are described in multiple expressions. The components and their descriptions are examples and are not limited to the expressions in this specification. The components may also be identified by names different from the names in this specification. In addition, the components may also be described by expressions different from the expressions in this specification.

[0020] Figure 1 1 is a perspective view showing an example of a hard disk drive (HDD) 10 according to the first embodiment. The HDD 10 is an example of a disk device, and may also be called an electronic device, a storage device, an external storage device, or a magnetic disk device.

[0021] The HDD 10 includes a housing 11, a plurality of magnetic disks 12, a spindle motor 13, a plurality of magnetic heads 14, an actuator assembly 15, a voice coil motor (VCM) 16, a ramp loading mechanism 17, a flexible printed wiring board (FPC) 18, and a printed wiring board (PCB) 19. The magnetic disk 12 is an example of a recording medium. The PCB 19 is an example of a circuit board.

[0022] The frame 11 includes a base 21, an inner cover 22, and an outer cover 23. The base 21 is a bottomed container, and includes a bottom wall 25 and a side wall 26. The bottom wall 25 is formed in a substantially rectangular (quadrilateral) plate shape. The side wall 26 protrudes from the edge of the bottom wall 25. The bottom wall 25 and the side wall 26 are made of a metal material such as an aluminum alloy, and are formed integrally.

[0023] The inner cover 22 and the outer cover 23 are made of a metal material such as aluminum alloy. The inner cover 22 is attached to the end of the side wall 26 by screws, for example. The outer cover 23 covers the inner cover 22 and is fixed to the end of the side wall 26 in an airtight manner, for example, by welding.

[0024] The inside of the housing 11 is sealed. Inside the housing 11, a magnetic disk 12, a spindle motor 13, a magnetic head 14, an actuator assembly 15, a VCM 16, a ramp load mechanism 17, and an FPC 18 are arranged.

[0025] The inner cover 22 is provided with a vent 22a. Furthermore, the outer cover 23 is provided with a vent 23a. After the components are installed inside the base 21 and the inner cover 22 and the outer cover 23 are installed on the base 21, the air inside the frame 11 is extracted from the vents 22a and 23a. Furthermore, the inside of the frame 11 is filled with a gas different from air.

[0026] The gas filled into the frame 11 is, for example, a low-density gas having a density lower than that of air, an inert gas having low reactivity, etc. For example, helium is filled into the frame 11. In addition, other fluids may be filled into the frame 11. In addition, the inside of the frame 11 may be maintained at a vacuum, a low pressure close to a vacuum, or a negative pressure lower than the atmospheric pressure.

[0027] The vent 23a of the outer cover 23 is closed by a seal 28. The seal 28 seals the vent 23a in an airtight manner to prevent the fluid filled in the interior of the frame 11 from leaking from the vent 23a.

[0028] The magnetic disk 12 is, for example, a disk having a magnetic recording layer provided on the surface 12a such as the upper and lower surfaces. The diameter of the magnetic disk 12 is, for example, 3.5 inches, but is not limited to this example.

[0029] The spindle motor 13 supports and rotates a plurality of magnetic disks 12 stacked at intervals in the direction in which the surface 12a faces. The plurality of magnetic disks 12 are held by a hub of the spindle motor 13 by, for example, a clamp spring.

[0030] The magnetic head 14 records and reproduces information on the recording layer of the magnetic disk 12. In other words, the magnetic head 14 reads and writes information on the magnetic disk 12. The magnetic head 14 is mounted on the actuator assembly 15.

[0031] The actuator assembly 15 is rotatably supported on a support shaft 31 disposed at a position away from the magnetic disk 12. The VCM 16 rotates the actuator assembly 15 and disposes it at a desired position. When the magnetic head 14 moves to the outermost periphery of the magnetic disk 12 by the rotation of the actuator assembly 15 realized by the VCM 16, the ramp loading mechanism 17 keeps the magnetic head 14 at an unloading position away from the magnetic disk 12.

[0032] The actuator assembly 15 has an actuator block 35, a plurality of arms 36, and a plurality of head suspension assemblies 37. The head suspension assembly 37 is an example of a suspension, and is hereinafter referred to as the suspension 37. The suspension 37 may also be referred to as a head gimbal assembly (HGA).

[0033] The actuator block 35 is rotatably supported on the support shaft 31 via a bearing, for example. A plurality of arms 36 protrude from the actuator block 35 in a direction substantially orthogonal to the support shaft 31. Alternatively, the actuator assembly 15 may be divided and the arms 36 may protrude from the plurality of actuator blocks 35, respectively.

[0034] The plurality of arms 36 are arranged at intervals in the direction in which the support shaft 31 extends. Each of the arms 36 is formed in a plate shape that can enter between adjacent magnetic disks 12. The plurality of arms 36 extend substantially in parallel.

[0035] The actuator block 35 and the plurality of arms 36 are integrally formed of, for example, aluminum. In addition, the materials of the actuator block 35 and the arms 36 are not limited to this example.

[0036] The voice coil of the VCM 16 is provided on a protrusion protruding from the actuator block 35 to the opposite side of the arm 36. The VCM 16 includes a pair of yokes, a voice coil disposed between the yokes, and a magnet provided on the yokes.

[0037] As described above, the VCM 16 rotates the actuator assembly 15. In other words, the VCM 16 rotates (moves) the actuator block 35, the arm 36, and the suspension 37 in an integrated manner.

[0038] The suspension 37 is attached to the front end portion of the corresponding arm 36 and protrudes from the arm 36. Thus, the plurality of suspensions 37 are arranged at intervals in the direction in which the support shaft 31 extends.

[0039] Figure 2 1 is a perspective view showing an example of a part of the suspension 37 of the first embodiment. Figure 2 As shown, the plurality of suspensions 37 each include a base plate 41, a load beam 42, and a flexible portion 43. Further, the magnetic head 14 is mounted on the front end portion 37a of the suspension 37. The front end portion 37a is an end portion mounted on the opposite side of the end portion of the arm 36 from the end portion of the suspension 37 in the direction (length direction) D1 in which the arm 36 and the suspension 37 extend.

[0040] The base plate 41 and the load beam 42 are made of, for example, stainless steel. In addition, the materials of the base plate 41 and the load beam 42 are not limited to this example. The base plate 41 is formed in a plate shape and is attached to the front end of the arm 36. The load beam 42 is formed in a plate shape that is thinner than the base plate 41. The load beam 42 is attached to the front end of the base plate 41 and protrudes from the base plate 41.

[0041] The flexible portion 43 is formed in a long and narrow strip shape. The shape of the flexible portion 43 is not limited to this example. The flexible portion 43 is a laminated plate having a metal plate (lining layer) such as stainless steel, an insulating layer formed on the metal plate, a conductive layer forming a plurality of wirings (wiring patterns) formed on the insulating layer, and a protective layer (insulating layer) covering the conductive layer.

[0042] A gimbal portion (elastic support portion) 45 that is located on the load beam 42 and can be displaced is provided at one end of the flexible portion 43. The gimbal portion 45 is provided at the front end portion 37a of the suspension 37. The magnetic head 14 is mounted on the gimbal portion 45. The other end of the flexible portion 43 is connected to the FPC 18. Thus, the FPC 18 is electrically connected to the magnetic head 14 via the wiring of the flexible portion 43.

[0043] A pair of first microactuators (MA) 47 and a pair of second microactuators (MA) 48 are mounted on the suspension 37. The first MA 47 and the second MA 48 are examples of an actuator and an actuator element, respectively.

[0044] The first MA47 and the second MA48 are piezoelectric elements. The first MA47 and the second MA48 are, for example, bulk, bulk-stacked, or thin-film piezoelectric elements. The first MA47 and the second MA48 are not limited to these examples.

[0045] A pair of first MA47s connect the base plate 41 and the load beam 42, for example. In other words, one end of the first MA47 is mounted on the base plate 41, and the other end is mounted on the load beam 42. In addition, the first MA47 is not limited to this example. The pair of first MA47s is orthogonal to the longitudinal direction D1, and is separated from each other in the direction (width direction) Dw along the surface 12a of the magnetic disk 12.

[0046] As the pair of first MAs 47 expand and contract individually, a portion of the suspension 37 closer to the front end 37a than the first MAs 47 is elastically bent in a direction along the surface 12a of the magnetic disk 12. Thus, the first MAs 47 move the magnetic head 14 mounted on the front end 37a of the suspension 37.

[0047] A pair of second MAs 48 are disposed near the front end portion 37a of the suspension 37. In other words, the pair of second MAs 48 are mounted on the suspension 37 at positions closer to the magnetic head 14 than the first MA 47. For example, the second MAs 48 are mounted on the gimbal portion 45. In addition, the second MAs 48 are not limited to this example, and may be mounted on the load beam 42, for example.

[0048] A pair of second MAs 48 are arranged to be separated from each other in the width direction Dw. By individually extending and retracting the pair of second MAs 48, the front end portion 37a of the suspension 37 is elastically bent in the direction along the surface 12a of the magnetic disk 12. Thus, the second MA 48 moves the magnetic head 14 mounted on the front end portion 37a of the suspension 37.

[0049] As described above, the HDD 10 of this embodiment adjusts the position of the magnetic head 14 by a so-called triple stage actuator (TSA) method in which the magnetic head 14 is moved by the VCM 16, the first MA 47, and the second MA 48. In addition, the HDD 10 is not limited to this example, and the position of the magnetic head 14 can also be adjusted by a so-called dual stage actuator (DSA) method in which the magnetic head 14 is moved by the VCM 16 and the first MA 47.

[0050] Figure 1 The PCB 19 shown is, for example, a rigid substrate such as a glass epoxy substrate, a multilayer substrate or a buildup substrate, etc. The PCB 19 is arranged outside the frame 11 and mounted outside the bottom wall 25 of the base 21. The PCB 19 is mounted on the bottom wall 25, for example, by a plurality of screws.

[0051] The PCB 19 has a mounting surface 19a facing the bottom wall 25. On the mounting surface 19a, for example, an interface (I / F) connector 51, a plurality of electronic components 52, and a relay connector 53 are mounted.

[0052] The I / F connector 51 is a connector conforming to an interface standard such as SerialATA, and is connected to an I / F connector of a host computer. The HDD 10 receives power from the host computer through the I / F connector 51 and transmits and receives various data to and from the host computer.

[0053] The plurality of electronic components 52 include, for example, a system on chip (SoC) 55. Furthermore, the plurality of electronic components 52 include, for example, a servo combo IC (SVC) for driving the spindle motor 13 and the VCM 16, various memories such as RAM, ROM, and buffer memory, and other electronic components such as coils and capacitors.

[0054] SoC55 has, for example, a read-write channel (RWC), a hard disk controller (HDC), and a processor. In addition, RWC, HDC, and the processor may also be separate components.

[0055] The processor of SoC55 is, for example, a CPU (Central Processing Unit). The processor controls the entire HDD10 according to, for example, firmware pre-stored in ROM. For example, the processor loads the firmware of ROM into RAM, and controls the magnetic head 14, RWC, HDC, and other parts according to the loaded firmware.

[0056] A control circuit 56 is provided on the PCB 19, and the control circuit 56 includes a plurality of electronic components 52 and a conductor pattern such as wiring provided on the PCB 19, and the plurality of electronic components 52 includes a SoC 55. The control circuit 56 controls the spindle motor 13, the magnetic head 14, the VCM 16, the first MA 47, and the second MA 48. In addition, the control circuit 56 can also indirectly control the spindle motor 13, the magnetic head 14, the VCM 16, the first MA 47, and the second MA 48 by controlling other circuits provided in a portion different from the PCB 19.

[0057] The relay connector 53 is electrically connected to various components arranged inside the frame 11 through a connector provided on the bottom wall 25, for example. Thus, the PCB 19 is electrically connected to the spindle motor 13, the magnetic head 14, the actuator assembly 15, the VCM 16, the FPC 18, the first MA 47, and the second MA 48 arranged inside the frame 11.

[0058] Figure 3 FIG1 is an exemplary top view schematically showing the FPC 18 of the first embodiment. The FPC 18 includes an insulating layer made of an insulating material such as polyimide, a conductive layer provided on the insulating layer, and an insulating protective layer covering the conductive layer. Figure 3 As shown in FIG. 1 , the FPC 18 is formed in a substantially L-shape. The shape of the FPC 18 is not limited to this example. The FPC 18 includes a first connection portion 61 , a second connection portion 62 , and a third connection portion 63 .

[0059] The first connection portion 61 is provided, for example, at one end of the FPC 18 in the direction in which the FPC 18 extends. A plurality of terminals 65 are provided on the first connection portion 61. The terminals 65 are, for example, pads provided on the surface of the FPC 18. The plurality of terminals 65 are connected to the plurality of terminals of the flexible portion 43, for example, by a conductive adhesive or solder. Thus, the first connection portion 61 is connected to the flexible portion 43 of the suspension 37.

[0060] The second connection portion 62 is, for example, provided at the other end of the FPC 18 in the direction in which the FPC 18 extends. The second connection portion 62 has a connector 66 protruding from the surface of the FPC 18. The connector 66 is, for example, electrically connected to the relay connector 53 of the PCB 19 through a connector provided on the bottom wall 25 of the frame 11. Thus, the second connection portion 62 is connected to the PCB 19. In addition, the connector 66 may also be directly connected to the relay connector 53 of the PCB 19.

[0061] The third connection portion 63 is provided, for example, near the first connection portion 61. The third connection portion 63 has a plurality of VCM terminals 67. The VCM terminals 67 are, for example, pads provided on the surface of the FPC 18. The VCM terminals 67 are connected to a plurality of terminals of the voice coil of the VCM 16, for example, by a conductive adhesive or solder. Thus, the third connection portion 63 is connected to the VCM 16.

[0062] The connector 66 has a plurality of pins 68 as terminals of the connector 66. The pins 68 are connected to the terminals of the connector of the bottom wall 25, so that the FPC 18 is electrically connected to the PCB 19.

[0063] The FPC 18 further includes a plurality of wirings 69. The wirings 69 are, for example, wiring patterns provided on a conductive layer of the FPC 18. The plurality of wirings 69 connect, for example, the plurality of pins 68 and the plurality of terminals 65 or the plurality of VCM terminals 67.

[0064] The FPC 18 is equipped with a preamplifier 71 and a plurality of MA drivers 72. The preamplifier 71 is also called a head amplifier. The MA driver 72 is an example of an actuator driver, a driver element, and an electronic component. The preamplifier 71 and the MA driver 72 are mounted on the FPC 18 separately from each other. That is, the preamplifier 71 and the plurality of MA drivers 72 are separate components.

[0065] Figure 4 1 is an exemplary block diagram schematically showing the functions of the HDD 10 according to the first embodiment. Figure 4 As shown, the preamplifier 71 includes a serial interface (I / F) 81, a logic circuit 82, and an amplifier 83. In addition, the preamplifier 71 may also include other components and circuits.

[0066] The preamplifier 71 is connected to the Figure 3 Terminal 65. Thus, if Figure 4 As shown, the preamplifier 71 is electrically connected to the magnetic head 14 via the flexible portion 43. The preamplifier 71 is electrically connected to the read element 14a, the write element 14b, and the HDI element 14c of the magnetic head 14, for example.

[0067] The read element 14a outputs a read signal by reading information from the magnetic disk 12. The write element 14b writes information to the magnetic disk 12 based on the input write signal. The HDI element 14c, for example, generates heat based on the input signal and adjusts the height of the magnetic head 14 floating from the surface 12a of the magnetic disk 12. In addition, the HDI element 14c outputs a signal for detecting the collision when the magnetic head 14 collides with the surface 12a of the magnetic disk 12, for example.

[0068] The preamplifier 71 is connected to the Figure 3 Thus, as Figure 4 As shown, the preamplifier 71 is electrically connected to the control circuit 56 via the PCB 19. The preamplifier 71 is electrically connected to the SoC 55 including the RWC, for example.

[0069] RWC is a signal processing circuit that encodes write data transmitted from HDC of SoC 55 to convert it into a write signal and outputs the write signal to preamplifier 71. RWC also decodes a read signal output from magnetic head 14 to convert it into read data and outputs the read data to HDC.

[0070] The preamplifier 71 amplifies the write signal output from the RWC of the SoC 55 through the amplifier 83, and transmits it to the write element 14b of the magnetic head 14. The write element 14b writes information to the magnetic disk 12 based on the write signal. In other words, the preamplifier 71 outputs a write signal corresponding to the information that the magnetic head 14 is to write to the magnetic disk 12 to the magnetic head 14.

[0071] The preamplifier 71 amplifies the read signal output from the read element 14a via the amplifier 83 and transmits the amplified signal to the RWC of the SoC 55. In other words, the preamplifier 71 receives a read signal corresponding to information read from the magnetic disk 12 by the magnetic head 14.

[0072] The preamplifier 71 transmits and receives digital signals such as serial signals with the SoC 55 of the control circuit 56 via the serial I / F 81. For example, the SoC 55 outputs a control signal of written power or current, a control signal of the HDI element 14c, and a control signal of the gain of the amplifier 83 to the serial I / F 81. In addition, the digital signals are not limited to these examples. The logic circuit 82 processes these digital signals.

[0073] In addition, the preamplifier 71 also transmits and receives analog signals with the SoC 55. For example, the preamplifier 71 receives a write signal output from the RWC of the SoC 55, and transmits a read signal to the RWC.

[0074] For example, the amplifier 83 amplifies the read signal received from the read element 14a and outputs it to the RWC of the SoC 55. In addition, the amplifier 83 amplifies the write signal received from the RWC and outputs it to the write element 14b. In addition, the amplifier 83 may also amplify other signals.

[0075] The MA driver 72 includes a serial interface (I / F) 85, a logic circuit 86, a plurality of digital-to-analog converters (DACs) 87, and a plurality of MA amplifiers 88. The MA amplifier 88 is an example of an amplifier. In addition, the MA driver 72 may also include other components and circuits.

[0076] The MA driver 72 is connected to the MA driver 72 through at least one of the plurality of wirings 69. Figure 3 Thus, if Figure 4 As shown, the plurality of MA drivers 72 are electrically connected to the first MA 47 and the second MA 48 via the flexible portion 43 .

[0077] The MA driver 72 is connected to the MA driver 72 through at least one of the plurality of wirings 69. Figure 3 Thus, as Figure 4 As shown, the MA driver 72 is electrically connected to the control circuit 56 via the PCB 19. The MA driver 72 is electrically connected to the SoC 55, for example.

[0078] The MA driver 72 transmits and receives digital signals such as serial signals with the SoC 55 of the control circuit 56 via the serial I / F 85. The serial I / F 85 transmits and receives various digital signals output by the SoC 55. For example, the SoC 55 outputs a serial signal for controlling the first MA 47 or the second MA 48 to the serial I / F 85. In addition, the digital signal is not limited to this example.

[0079] The logic circuit 86 processes various serial signals. For example, the logic circuit 86 outputs the serial signal received by the serial I / F 85 to one of the plurality of DACs 87 corresponding to the serial signal. In addition, the logic circuit 86 may also perform other processing.

[0080] The DAC 87 converts the serial signal input from the logic circuit 82 into an analog signal (driving signal) for driving the corresponding first MA 47 or second MA 48 , and outputs the converted driving signal to the corresponding MA amplifier 88 .

[0081] A plurality of MA amplifiers 88 are electrically connected to the corresponding DAC 87 and the corresponding first MA 47 or second MA 48. The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 87 and outputs it to the corresponding first MA 47 or second MA 48. That is, the MA driver 72 outputs the drive signal that drives the first MA 47 or second MA 48 to the first MA 47 or second MA 48.

[0082] The number of MA amplifiers 88 is, for example, equal to the number of the first MA 47 and the second MA 48, and is four in this embodiment. In addition, the number of DACs 87 is, for example, equal to the number of MA amplifiers 88, and is four in this embodiment. In addition, the number of DACs 87 and MA amplifiers 88 is not limited to these examples.

[0083] For example, when differential signals are used, the number of DACs 87 may be half the number of MA amplifiers 88. Furthermore, when the actuators (the first MA 47 and the second MA 48) are controlled collectively, the number of DACs 87 may be one.

[0084] The control circuit 56 further includes a switching power supply 91, an amplifier power supply 92, and a VCM driver 93. The switching power supply 91, the amplifier power supply 92, and the VCM driver 93 are included in, for example, the SVC. In addition, the switching power supply 91, the amplifier power supply 92, and the VCM driver 93 are not limited to this example.

[0085] The switching power supply 91 is a power supply circuit that supplies -3V power to the preamplifier 71. The amplifier power supply 92 is a power supply circuit that supplies power (+V, -V) to the MA amplifier 88 of the MA driver 72. The VCM driver 93 outputs a signal to the VCM 16 to drive the VCM 16.

[0086] like Figure 3As shown, the FPC 18 has a first driver terminal 101, a second driver terminal 102, and a preamplifier terminal 103. The first driver terminal 101 is an example of a first terminal. The preamplifier terminal 103 is an example of a second terminal. The first driver terminal 101, the second driver terminal 102, and the preamplifier terminal 103 are, for example, pads provided on the surface of the FPC 18.

[0087] The terminal 72 a of the MA driver 72 is connected to the first driver terminal 101 by, for example, a conductive adhesive or solder. The terminal 72 a is connected to the MA amplifier 88 of the MA driver 72 . Figure 3 Although one terminal 72a and one first driver terminal 101 are schematically shown for one MA driver 72, the MA driver 72 has a plurality of terminals 72a corresponding to the plurality of MA amplifiers 88. Furthermore, the FPC 18 has a plurality of first driver terminals 101 corresponding to the plurality of terminals 72a.

[0088] The terminal 72 b of the MA driver 72 is connected to the second driver terminal 102 by, for example, a conductive adhesive or solder. The terminal 72 b is connected to the serial I / F 85 of the MA driver 72 .

[0089] The terminal 71a of the preamplifier 71 is connected to the preamplifier terminal 103 by, for example, a conductive adhesive or solder. In addition, the terminal of the VCM 16 is connected to the VCM terminal 67 by, for example, a conductive adhesive or solder.

[0090] The plurality of wirings 69 include a first driver wiring 111, a second driver wiring 112, a power supply wiring 113, and two VCM wirings 114. The first driver wiring 111 is an example of a first wiring and a fourth wiring. The second driver wiring 112 is an example of a fifth wiring. The power supply wiring 113 is an example of a second wiring. The two VCM wirings 114 are an example of a third wiring.

[0091] The first driver wiring 111 connects the first driver terminal 101 to at least one of the plurality of terminals 65 of the first connecting portion 61. Therefore, the first driver wiring 111 connects the terminal 72a of the MA driver 72 to the terminal 65 of the first connecting portion 61.

[0092] The second driver wiring 112 connects the second driver terminal 102 to one pin 68 of the connector 66 of the second connection portion 62. Therefore, the second driver wiring 112 connects the terminal 72b of the MA driver 72 to the pin 68 of the second connection portion 62.

[0093] The power supply wiring 113 connects the preamplifier terminal 103 to one pin 68 of the connector 66 of the second connection portion 62. The switching power supply 91 supplies power to the preamplifier 71 connected to the preamplifier terminal 103 via the second connection portion 62 and the power supply wiring 113. That is, the power supply wiring 113 supplies power to the preamplifier 71.

[0094] The VCM wiring 114 connects the two VCM terminals 67 of the third connection portion 63 to the pins 68 of the connector 66 of the second connection portion 62. In addition, the plurality of wirings 69 include wiring that connects the preamplifier 71 to the terminal 65 of the first connection portion 61 and wiring that connects the preamplifier 71 to the pin 68 of the connector 66 of the second connection portion 62. Figure 3 , some of the plurality of wirings 69 are omitted for illustration. For example, the plurality of wirings 69 include wirings for connecting the amplifier power supply 92 to the MA driver 72 to supply power to the MA amplifier 88, wirings for connecting the RWC of the SoC 55 to the preamplifier 71 to transmit read signals and write signals, and various other wirings.

[0095] The preamplifier 71 and the MA driver 72 are arranged near the first connection portion 61. Therefore, the MA driver 72 is closer to the first connection portion 61 than to the second connection portion 62. In other words, the distance between the MA driver 72 and the first connection portion 61 is shorter than the distance between the MA driver 72 and the second connection portion 62. Therefore, the first driver wiring 111 is shorter than the second driver wiring 112.

[0096] The MA driver 72 is closer to the first connection portion 61 than the preamplifier 71. In other words, the distance between the MA driver 72 and the first connection portion 61 is shorter than the distance between the preamplifier 71 and the first connection portion 61. In addition, the MA driver 72 may be farther from the first connection portion 61 than the preamplifier 71.

[0097] The first driver terminal 101 is closer to the first connection portion 61 than the preamplifier terminal 103. Therefore, the first driver wiring 111 extending from the first driver terminal 101 and the power wiring 113 extending from the preamplifier terminal 103 do not extend side by side. In other words, the first driver wiring 111 and the power wiring 113 are not adjacent.

[0098] The first driver terminal 101 is closer to the first connection portion 61 than the VCM terminal 67 of the third connection portion 63. Therefore, the first driver wiring 111 extending from the first driver terminal 101 and the VCM wiring 114 extending from the VCM terminal 67 do not extend side by side. In other words, the first driver wiring 111 and the VCM wiring 114 are not adjacent to each other.

[0099] The first driver wiring 111 transmits a drive signal whose voltage is amplified by the MA amplifier 88. The current of the drive signal is lower than the voltage, so the impedance of the first driver wiring 111 becomes higher. On the other hand, the second driver wiring 112 transmits a digital signal such as a serial signal. Therefore, the impedance of the second driver wiring 112 is lower than the impedance of the first driver wiring 111.

[0100] In this embodiment, the second driver wiring 112 is branched to connect the preamplifier 71, the MA driver 72, and the second connection portion 62. Figure 4 As shown, the SoC 55, the serial I / F 81 of the preamplifier 71, and the serial I / F 85 of the MA driver 72 are electrically connected to each other.

[0101] Figure 5 1 is an illustrative timing chart showing an example of a serial signal output by the SoC 55 of the first embodiment. The SoC 55 outputs the serial I / F 81 of the preamplifier 71 and the serial I / F 85 of the MA driver 72. Figure 5 The common serial signals are shown.

[0102] For example, the SoC 55, the serial I / F 81 of the preamplifier 71, and the serial I / F 85 of the MA driver 72 are connected in parallel through three wirings. The SoC 55 outputs an enable signal SDEN, a clock signal SCLK, and a data signal SDATA to the serial I / F 81 of the preamplifier 71 and the serial I / F 85 of the MA driver 72. In addition, the serial signal is not limited to this example.

[0103] The data signal SDATA includes an address AD. The address AD is set to a first address AD1 or a second address AD2, the first address AD1 being an address for the preamplifier 71, and the second address AD2 being an address for the MA driver 72. In other words, the SoC 55 of the control circuit 56 outputs a digital signal including the first address AD1 or the second address AD2. In addition, the address AD is not limited to this example. When the serial I / Fs 81 and 85 receive the data signal SDATA, the logic circuits 82 and 86 operate based on the address AD.

[0104] The logic circuit 82 of the preamplifier 71 operates based on the data signal SDATA including the first address AD1. For example, the logic circuit 82 outputs various control signals to the magnetic head 14 through the amplifier 83 based on the data signal SDATA including the first address AD1. For example, the logic circuit 82 outputs a control signal of the power or current of writing, or a control signal of the HDI element 14c to the magnetic head 14 through the amplifier 83. In addition, the logic circuit 82 controls the gain of the amplifier 83 based on the gain control signal. On the other hand, when the logic circuit 82 receives the data signal SDATA including the second address AD2, it ignores the data signal SDATA.

[0105] The logic circuit 86 of the MA driver 72 outputs the data signal SDATA including the second address AD2 to the DAC 87 corresponding to the second address AD2. Thus, the DAC 87 converts the digital signal including the corresponding second address AD2 into a driving signal as an analog signal. On the other hand, when the logic circuit 82 receives the data signal SDATA including the first address AD1, it ignores the data signal SDATA.

[0106] As described above, SoC55 assigns the first address AD1 to the data signal SDATA for causing the preamplifier 71 to output the control signal of the magnetic head 14. In addition, SoC55 assigns the second address AD2 to the data signal SDATA for causing the MA driver 72 to output the drive signal. Thus, even if the preamplifier 71 and the MA driver 72 receive a common digital signal, the preamplifier 71 and the MA driver 72 operate according to the data signal SDATA including the address AD corresponding to themselves, thereby suppressing the occurrence of communication interference.

[0107] As described above, the second driver wiring 112 is branched. Figure 3 As shown, the second driver wiring 112 that transmits the serial signal to the preamplifier 71 and the MA driver 72 is branched in the FPC 18. Therefore, compared with the case where individual wiring transmits the serial signal to the preamplifier 71 and the MA driver 72, and the case where the wiring that transmits the serial signal to the preamplifier 71 and the MA driver 72 is branched in the PCB 19, the number of pins 68 that transmit the serial signal in the connector 66 is reduced.

[0108] In addition, one MA driver 72 is connected in parallel with a plurality of first MAs 47 and second MAs 48. As described above, the logic circuit 86 of the MA driver 72 changes the destination of the signal according to the second address AD2. Therefore, the MA driver 72 can make the number of wirings connected to the serial I / F 85 of the MA driver 72 constant regardless of the number of actuators (first MAs 47 and second MAs 48) connected to the MA driver 72.

[0109] In the above HDD 10, sometimes Figure 4 The switching power supply 91 generates noise. The noise generated by the switching power supply 91 may propagate from the wiring W1 connecting the switching power supply 91 and the preamplifier 71 to other wirings. The wiring W1 is an electrical path including the power wiring 113 and the wiring of the PCB 19 connected to the power wiring 113.

[0110] A wiring with high impedance is prone to propagating noise between the wirings. For example, noise may propagate from the wiring W1 to the wiring W2 connecting the VCM driver 93 and the VCM 16. The wiring W2 is an electrical path including the VCM wiring 114 and the wiring of the PCB 19 connected to the VCM wiring 114.

[0111] On the other hand, the wiring for transmitting digital signals is not easy to propagate noise between other wirings. The wiring W3 connecting the SoC55, the preamplifier 71 and the MA driver 72 transmits a serial signal, so the impedance is low. In addition, the impedance of the wiring W4 connecting the amplifier power supply 92 and the MA driver 72 is also low. Therefore, the wirings W3 and W4 can suppress the propagation of noise from the wirings W1 and W2 to the wirings W3 and W4. The wiring W3 is an electrical path including the second driver wiring 112 and the wiring of the PCB 19 connected to the second driver wiring 112.

[0112] The impedance of the wiring W5 connecting the MA driver 72 to the first MA47 or the second MA48 is high. The wiring W5 is an electrical path including the first driver wiring 111 and the wiring of the flexible portion 43 connected to the first driver wiring 111. However, as described above, the first driver wiring 111 is not adjacent to the power wiring 113 and the VCM wiring 114. Therefore, the first driver wiring 111 (wiring W5) can suppress the propagation of noise from the power wiring 113 (wiring W1) and the VCM wiring 114 (wiring W2) to the first driver wiring 111. In addition, since the wiring W5 is short, the wiring W5 can also suppress noise obtained due to other reasons.

[0113] As described above, the propagation of noise can be suppressed, so, for example, the propagation of noise to the wiring connecting the SoC 55 to the read element 14a and the write element 14b can be suppressed. When noise is mixed in the read signal, the noise is amplified by the preamplifier 71, and it is possible that the reading of information in the HDD 10 becomes difficult and the position control based on the servo signal becomes difficult. In addition, when noise is mixed in the write signal, it is possible that the accurate writing of information in the HDD 10 becomes difficult. In contrast, the HDD 10 of this embodiment can suppress the propagation of noise between the wirings as described above, so it is possible to suppress the situation where noise interferes with the reading and writing of information and position control.

[0114] The voltage of the driving signal transmitted by the first driver wiring 111 is high. Generally, the high voltage wiring is designed to be separated from other wirings in order to ensure the withstand voltage. However, in this embodiment, the first driver wiring 111 is short, so the layout design of the wiring 69 including the first driver wiring 111 in the FPC 18 becomes easy.

[0115] In the HDD10 involved in the first embodiment described above, the MA driver 72 is mounted on the FPC18 in a manner away from the preamplifier 71. The MA driver 72 outputs a driving signal that drives the first MA47 (the second MA48) to the first MA47 (the second MA48). Generally speaking, the driving signal that drives the first MA47 (the second MA48) such as a piezoelectric element has a high voltage and a low current. Therefore, the impedance of the wiring W5 between the MA driver 72 and the first MA47 (the second MA48) is high, and noise is easily propagated between other wirings. However, in this embodiment, the MA driver 72 is mounted on the FPC18, so the wiring W5 between the MA driver 72 and the first MA47 (the second MA48) is shorter than when the MA driver 72 is mounted on the PCB19. Therefore, the propagation of noise between the wiring W5 between the MA driver 72 and the first MA47 (the second MA48) and other wirings can be suppressed. For example, it is possible to suppress the noise from propagating from the wiring W5 between the MA driver 72 and the first MA47 (second MA48) to the wiring between the magnetic head 14 and the preamplifier 71, or the wiring between the control circuit 56 and the preamplifier 71, and further, it is possible to suppress the noise from being mixed into the information read and written by the magnetic head 14. Furthermore, the MA driver 72 is mounted on the FPC18 in a manner away from the preamplifier 71. In other words, the MA driver 72 is a component different from the preamplifier 71. Therefore, by mounting MA drivers 72 corresponding to the number of each first MA47 (second MA48) on multiple types of HDDs 10 having different numbers of first MA47 (second MA48), it is possible to make the design of the MA driver 72 common.

[0116] In addition, when the MA driver 72 is mounted on the PCB 19, the number of wirings connecting the MA driver 72 to the actuator (the first MA 47 and the second MA 48) may increase due to, for example, an increase in the number of actuators and / or an increase in the functions of the actuators. For example, since the HDD 10 adopts the TSA method, performs bias control of the actuator, and performs actuator control for self-servo writing (SSW), the wiring will increase. As the number of wirings increases, for example, the number of pins 68 of the connector 66 of the second connection portion 62 will increase, and the connector 66 will be enlarged. However, in the present embodiment, the MA driver 72 is connected to the FPC 18. Compared with the wiring of the drive signal output from the MA driver 72, the wiring of the control signal for controlling the MA driver 72 is easily reduced. Therefore, the number of pins 68 of the connector 66 can be suppressed from increasing, and the connector 66 can be miniaturized.

[0117] The MA driver 72 is mounted on the FPC18 in a manner away from the preamplifier 71. The first driver wiring 111 is provided on the FPC18 to connect the first connection portion 61 to the MA driver 72. The second driver wiring 112 is provided on the FPC18 to connect the second connection portion 62 to the MA driver 72, and has an impedance lower than the impedance of the first driver wiring 111. That is, the impedance of the first driver wiring 111 is high, and noise is easily propagated between other wirings. However, in the present embodiment, the MA driver 72 is mounted on the FPC18, and therefore, the first driver wiring 111 having a high impedance connected to the MA driver 72 is shortened compared to the case where the MA driver 72 is mounted on the PCB19. Therefore, the propagation of noise between the first driver wiring 111 connected to the MA driver 72 and other wirings can be suppressed.

[0118] The MA driver 72 is closer to the first connection portion 61 than to the second connection portion 62. Therefore, the wiring W5 between the MA driver 72 and the first MA47 (second MA48) is shortened. Therefore, the propagation of noise between the wiring W5 between the MA driver 72 and the first MA47 (second MA48) and other wirings can be suppressed.

[0119] The FPC 18 has a first driver terminal 101 connected to the MA driver 72, a first driver wiring 111 connecting the first driver terminal 101 and the first connecting portion 61, a preamplifier terminal 103 connected to the preamplifier 71, and a power supply wiring 113 connecting the preamplifier terminal 103 and the second connecting portion 62 and supplying power to the preamplifier 71. The first driver terminal 101 is closer to the first connecting portion 61 than the preamplifier terminal 103. Therefore, the first driver wiring 111 and the power supply wiring 113 are not adjacent in a direction (lateral) orthogonal to the direction in which these wirings extend. Therefore, it is possible to suppress the propagation of noise between the first driver wiring 111 and the power supply wiring 113. The first driver wiring 111 transmits a drive signal, so as described above, the impedance is high. In addition, for example, the power supply wiring 113 supplies the preamplifier 71 with power generated by a switching power supply, so noise may flow in the power supply wiring 113. However, in the HDD 10 of the present embodiment, it is possible to suppress the propagation of noise from the power supply wiring 113 to the first driver wiring 111. Therefore, it is possible to suppress the propagation of noise from the first driver wiring 111 to the wiring between the magnetic head 14 and the preamplifier 71, or the wiring between the control circuit 56 and the preamplifier 71, and further, it is possible to suppress the mixing of noise into the information read and written by the magnetic head 14.

[0120] The FPC 18 has a third connection portion 63 connected to the VCM 16, and a VCM wiring 114 connecting the second connection portion 62 and the third connection portion 63. The first driver terminal 101 is closer to the first connection portion 61 than to the third connection portion 63. Therefore, the first driver wiring 111 and the VCM wiring 114 are not adjacent in a direction (lateral direction) orthogonal to the direction in which these wirings extend. Therefore, it is possible to suppress the propagation of noise between the first driver wiring 111 and the VCM wiring 114.

[0121] The SoC55 of the control circuit 56 outputs a digital signal including the first address AD1 or the second address AD2. The preamplifier 71 operates based on the digital signal including the first address AD1. The MA driver 72 has a DAC87 that converts the digital signal including the second address AD2 into a drive signal as an analog signal. The MA driver 72 has an MA amplifier 88 that amplifies the drive signal and outputs it to the first MA47 (the second MA48). That is, the preamplifier 71 and the MA driver 72 operate based on a common digital signal. Therefore, compared with the case where the control circuit 56 outputs individual digital signals to the preamplifier 71 and the MA driver 72, the HDD10 of this embodiment can reduce the number of pins 68 provided on the second connection portion 62. In addition, the preamplifier 71 and the MA driver 72 can operate based on the first address AD1 or the second address AD2, and can suppress malfunctions caused by communication interference.

[0122] (Second embodiment)

[0123] Below, refer to Figure 6 The second embodiment is described. In the following description of the multiple embodiments, the components having the same functions as the components already described are marked with the same reference numerals as the components already described, and the description is sometimes omitted. In addition, the multiple components marked with the same reference numerals are not limited to having all the functions and properties in common, and may also have different functions and properties according to each embodiment.

[0124] Figure 6 2 is an exemplary block diagram schematically showing the functions of the HDD 10 according to the second embodiment. Figure 6 As shown, the preamplifier 71 of the second embodiment includes a logic circuit 202 and a plurality of digital-to-analog converters (DACs) 203 instead of the logic circuit 82. In addition, the preamplifier 71 may include other components and circuits.

[0125] The MA driver 72 of the second embodiment does not include the serial I / F 85, the logic circuit 86, and the DAC 87, but includes a plurality of MA amplifiers 88 corresponding to the plurality of DACs 203. In addition, the MA driver 72 may include other components and circuits.

[0126] In the second embodiment, the wiring W6 replaces the wiring W3 to connect the SoC 55 and the serial I / F 81 of the preamplifier 71. The wiring W6 is an electrical path including the wiring 69 of the FPC 18 and the wiring of the PCB 19 connected to the wiring 69.

[0127] The SoC 55 outputs a serial signal to the serial I / F 81 of the preamplifier 71 via the wiring W6. The preamplifier 71 outputs a control signal to the magnetic disk 12 or a drive signal to the MA driver 72 according to the address AD of the data signal SDATA.

[0128] For example, the logic circuit 202 of the preamplifier 71 operates based on the data signal SDATA including the first address AD1. For example, the logic circuit 202 outputs various control signals to the magnetic head 14 through the amplifier 83 based on the data signal SDATA including the first address AD1.

[0129] On the other hand, the logic circuit 202 outputs the data signal SDATA including the second address AD2 to the DAC 203 corresponding to the second address AD2. Thus, the DAC 203 converts the digital signal including the corresponding second address AD2 into a drive signal as an analog signal. The DAC 203 outputs the converted drive signal to the corresponding MA amplifier 88 of the MA driver 72. The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 203 and outputs it to the corresponding first MA 47 or second MA 48.

[0130] In the HDD 10 of the second embodiment described above, the preamplifier 71 includes the DAC 203. This allows the MA driver 72 to be miniaturized. In addition, since the wiring W6 is not branched, the wiring 69 of the FPC 18 can be simplified.

[0131] (Third embodiment)

[0132] Below, refer to Figure 7 A third embodiment will be described. Figure 7 This is an illustrative timing chart showing an example of a serial signal output by the SoC 55 according to the third embodiment.

[0133] The serial signal of the third embodiment is different from that of the first embodiment and the second embodiment. The configuration of the HDD 10 in the third embodiment may be the same as that of the first embodiment or the second embodiment. Hereinafter, an example in which the configuration of the HDD 10 is the same as that of the first embodiment will be described.

[0134] In the third embodiment, for example, the SoC 55, the serial I / F 81 of the preamplifier 71, and the serial I / F 85 of the MA driver 72 are connected in parallel via four wirings. Figure 7 As shown, the SoC 55 outputs an enable signal SDEN, a clock signal SCLK, a data signal SDATA, and a determination signal SLEV to the serial I / F 81 of the preamplifier 71 and the serial I / F 85 of the MA driver 72 .

[0135] The discrimination signal SLEV is a signal that can be switched between multiple voltage levels such as High, Low, and Open. In addition, the discrimination signal SLEV can be switched between two or more voltage levels or multiple current levels.

[0136] In the third embodiment, the second address AD2 of the data signal SDATA includes, for example, at least one of the address of the first MA47 indicating one side, the address of the first MA47 indicating the other side, the address of the second MA48 indicating one side, and the address of the second MA48 indicating the other side. In addition, the second MA48 is not limited to this example.

[0137] When receiving the data signal SDATA including the second address AD2, the logic circuit 86 of the MA driver 72 determines the address to be used according to the voltage level of the discrimination signal SLEV. That is, the logic circuit 86 uses the address corresponding to the voltage level of the discrimination signal SLEV in the second address AD2 and outputs a serial signal to the DAC 87 corresponding to the address.

[0138] The DAC 87 converts the serial signal input from the logic circuit 82 into an analog signal (driving signal) for driving the corresponding first MA 47 or second MA 48 , and outputs the converted driving signal to the corresponding MA amplifier 88 .

[0139] The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 87 and outputs it to the corresponding first MA 47 or second MA 48. That is, the MA amplifier 88 amplifies the drive signal and outputs it to one of the first MA 47 and the second MA 48 corresponding to the voltage level of the discrimination signal SLEV.

[0140] Hereinafter, an example will be described in which the configuration of the HDD 10 is the same as that of the second embodiment. In this case, the SoC 55 and the serial I / F 81 of the preamplifier 71 are connected in parallel via the above-mentioned four wirings.

[0141] When receiving the data signal SDATA including the second address AD2, the logic circuit 202 of the preamplifier 71 determines the address to be used according to the voltage level of the discrimination signal SLEV. That is, the logic circuit 202 uses the address corresponding to the voltage level of the discrimination signal SLEV in the second address AD2 to output a serial signal to the DAC 203 corresponding to the address.

[0142] The DAC 203 converts the serial signal input from the logic circuit 202 into an analog signal (driving signal) for driving the corresponding first MA 47 or second MA 48 . The DAC 203 outputs the converted driving signal to the corresponding MA amplifier 88 of the MA driver 72 .

[0143] The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 87 and outputs it to the corresponding first MA 47 or second MA 48. That is, the MA amplifier 88 amplifies the drive signal and outputs it to one of the first MA 47 and the second MA 48 corresponding to the voltage level of the discrimination signal SLEV.

[0144] In the HDD 10 of the third embodiment described above, the MA amplifier 88 amplifies the drive signal and outputs it to one of the first MA 47 and the second MA 48 corresponding to the level of the discrimination signal SLEV. Thus, even when the suspension 37 is equipped with a plurality of actuators (the first MA 47 and the second MA 48), the MA driver 72 can output the drive signal to the desired actuator.

[0145] (Fourth embodiment)

[0146] Below, refer to Figure 8 A fourth embodiment will be described. Figure 8 This is an illustrative timing chart showing an example of a serial signal output by the SoC 55 according to the fourth embodiment.

[0147] The serial signal of the fourth embodiment is different from that of the first embodiment and the second embodiment. The configuration of the HDD 10 in the fourth embodiment may be the same as that of the first embodiment or the second embodiment. Hereinafter, an example in which the configuration of the HDD 10 is the same as that of the first embodiment will be described.

[0148] In the fourth embodiment, for example, the SoC 55 , the serial I / F 81 of the preamplifier 71 , and the serial I / F 85 of the MA driver 72 are connected in parallel via two wirings that transmit the clock signal SCLK and the data signal SDATA.

[0149] The SoC 55 and the serial I / F 81 are connected via a wiring for transmitting the first enable signal SDEN (PA) for the preamplifier 71. Further, the SoC 55 and the serial I / F 85 are connected via a wiring for transmitting the second enable signal SDEN (MA) for the MA driver 72. That is, the SoC 55 of the control circuit 56 outputs a digital signal including the first enable signal SDEN (PA) and the second enable signal SDEN (MA).

[0150] The first enable signal SDEN (PA) and the second enable signal SDEN (MA) are signals that can be switched between two voltage levels of an active state and an inactive state. The first enable signal SDEN (PA) and the second enable signal SDEN (MA) switch the voltage level independently of each other. In this embodiment, the SoC 55 sets the first enable signal SDEN (PA) and the second enable signal SDEN (MA) to different voltage levels.

[0151] The logic circuit 82 of the preamplifier 71 operates based on the data signal SDATA when the first enable signal SDEN (PA) is in an effective state. The logic circuit 82 outputs various control signals to the magnetic head 14 based on the data signal SDATA received during the period when the first enable signal SDEN (PA) is in an effective state. On the other hand, the logic circuit 82 ignores the data signal SDATA when the first enable signal SDEN (PA) is in an ineffective state.

[0152] The logic circuit 86 of the MA driver 72 ignores the data signal SDATA when the second enable signal SDEN (MA) is in an invalid state. On the other hand, the logic circuit 86 outputs the data signal SDATA to the DAC 87 when the second enable signal SDEN (MA) is in an effective state. Thus, the DAC 87 converts the digital signal into a drive signal that is an analog signal when the second enable signal SDEN (MA) is in an effective state. The logic circuit 86 outputs the data signal SDATA to, for example, one of the plurality of DACs 87 that corresponds to the address AD of the data signal SDATA.

[0153] The DAC 87 outputs the converted drive signal to the corresponding MA amplifier 88. The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 87, and outputs the amplified drive signal to the corresponding first MA 47 or second MA 48.

[0154] Hereinafter, an example in which the structure of the HDD 10 is the same as that of the second embodiment will be described. In this case, the SoC 55 and the serial I / F 81 of the preamplifier 71 are connected via four wirings. The SoC 55 outputs the first enable signal SDEN (PA), the second enable signal SDEN (MA), the clock signal SCLK, and the data signal SDATA to the serial I / F 81 of the preamplifier 71.

[0155] The logic circuit 202 of the preamplifier 71 operates based on the data signal SDATA when the first enable signal SDEN (PA) is active. The logic circuit 202 outputs various control signals to the magnetic head 14 based on the data signal SDATA received while the first enable signal SDEN (PA) is active.

[0156] On the other hand, the logic circuit 202 outputs the data signal SDATA to the DAC 203 when the second enable signal SDEN (MA) is in an effective state. Thus, the DAC 203 converts the digital signal into a drive signal as an analog signal when the second enable signal SDEN (MA) is in an effective state. The DAC 203 outputs the converted drive signal to the corresponding MA amplifier 88 of the MA driver 72. The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 203 and outputs it to the corresponding first MA 47 or second MA 48.

[0157] In the HDD 10 of the fourth embodiment described above, the control circuit 56 outputs a digital signal including a first enable signal SDEN (PA) and a second enable signal SDEN (MA). The preamplifier 71 operates based on the digital signal when the first enable signal SDEN (PA) is in an effective state. The preamplifier 71 or the MA driver 72 has a DAC 87, 203 that converts the digital signal into a drive signal that is an analog signal when the second enable signal SDEN (MA) is in an effective state. The MA driver 72 has an MA amplifier 88 that amplifies the drive signal and outputs it to the first MA 47 (the second MA 48). That is, the preamplifier 71 and the MA driver 72 operate based on a common digital signal (data signal SDATA). Therefore, compared with the case where the control circuit 56 outputs separate digital signals (data signals SDATA) to the preamplifier 71 and the MA driver 72, the HDD 10 of this embodiment can reduce the number of pins 68 provided on the second connection portion 62. In addition, the preamplifier 71 and the MA driver 72 operate based on the first enable signal SDEN (PA) and the second enable signal SDEN (MA), and can suppress malfunctions due to communication interference.

[0158] (Fifth embodiment)

[0159] Below, refer to Fig. 9 A fifth embodiment will be described. Fig. 9 This is an illustrative timing chart showing an example of a serial signal output by the SoC 55 according to the fifth embodiment.

[0160] The operation of the logic circuits 82, 86, and 202 in the fifth embodiment is different from that in the first embodiment and the second embodiment. The configuration of the HDD 10 in the fifth embodiment may be the same as that in the first embodiment or the second embodiment. Hereinafter, an example in which the configuration of the HDD 10 is the same as that in the first embodiment will be described.

[0161] In the fifth embodiment, for example, the SoC 55, the serial I / F 81 of the preamplifier 71, and the serial I / F 85 of the MA driver 72 are connected in parallel via three wirings. Fig. 9 As shown, the SoC 55 outputs an enable signal SDEN, a clock signal SCLK, and a data signal SDATA to the serial I / F 81 of the preamplifier 71 and the serial I / F 85 of the MA driver 72 .

[0162] The enable signal SDEN is able to Fig. 9 The valid states represented by the solid lines and Fig. 9 A signal for switching between two voltage levels of an invalid state represented by a dotted line in FIG. The valid state is an example of the first state. The invalid state is an example of the second state. In addition, the valid state may be an example of the second state, and the invalid state may be an example of the first state.

[0163] The logic circuit 82 of the preamplifier 71 operates based on the data signal SDATA when the enable signal SDEN is in an effective state. The logic circuit 82 outputs various control signals to the magnetic head 14 based on the data signal SDATA received during the period when the enable signal SDEN is in an effective state. On the other hand, the logic circuit 82 ignores the data signal SDATA when the enable signal SDEN is in an inactive state.

[0164] The logic circuit 86 of the MA driver 72 ignores the data signal SDATA when the enable signal SDEN is in the valid state. On the other hand, the logic circuit 86 outputs the data signal SDATA to the DAC 87 when the enable signal SDEN is in the invalid state. Thus, the DAC 87 converts the digital signal into a drive signal that is an analog signal when the enable signal SDEN is in the invalid state. The logic circuit 86 outputs the data signal SDATA to, for example, one of the plurality of DACs 87 corresponding to the address AD of the data signal SDATA.

[0165] The DAC 87 outputs the converted drive signal to the corresponding MA amplifier 88. The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 87, and outputs the amplified drive signal to the corresponding first MA 47 or second MA 48.

[0166] Hereinafter, an example will be described in which the configuration of the HDD 10 is the same as that of the second embodiment. In this case, the SoC 55 and the serial I / F 81 of the preamplifier 71 are connected via three wirings. The SoC 55 outputs an enable signal SDEN, a clock signal SCLK, and a data signal SDATA to the serial I / F 81 of the preamplifier 71.

[0167] The logic circuit 202 of the preamplifier 71 operates based on the data signal SDATA when the enable signal SDEN is active. The logic circuit 202 outputs various control signals to the magnetic head 14 based on the data signal SDATA received while the enable signal SDEN is active.

[0168] On the other hand, when the enable signal SDEN is in an inactive state, the logic circuit 202 outputs the data signal SDATA to the DAC 203. For example, the logic circuit 86 outputs the data signal SDATA to one DAC 203 corresponding to the address AD of the data signal SDATA among the plurality of DACs 203. Thus, the DAC 203 converts the digital signal into a driving signal that is an analog signal when the enable signal SDEN is in an inactive state.

[0169] The DAC 203 outputs the converted driving signal to the corresponding MA amplifier 88 of the MA driver 72. The MA amplifier 88 amplifies the driving signal input from the corresponding DAC 203, and outputs it to the corresponding first MA 47 or second MA 48.

[0170] In the HDD 10 of the fifth embodiment described above, the SoC 55 of the control circuit 56 outputs a digital signal including the enable signal SDEN. The preamplifier 71 operates based on the digital signal when the enable signal SDEN is in an effective state. The preamplifier 71 or the MA driver 72 has a DAC 87, 203 that converts the digital signal into a drive signal that is an analog signal when the enable signal SDEN is in an inactive state. The MA driver 72 has an MA amplifier 88 that amplifies the drive signal and outputs it to the first MA 47 (the second MA 48). That is, the preamplifier 71 and the MA driver 72 operate based on a common digital signal. Therefore, compared with the case where the control circuit 56 outputs separate digital signals to the preamplifier 71 and the MA driver 72, the HDD 10 of this embodiment can reduce the number of pins 68 provided in the second connection portion 62. In addition, the preamplifier 71 and the MA driver 72 operate based on two different states of the enable signal SDEN, and can suppress malfunctions caused by communication interference.

[0171] (Sixth embodiment)

[0172] Below, refer to Fig.10 A sixth embodiment will be described. Fig.10 1 is a block diagram schematically showing an example of the function of the HDD 10 according to the sixth embodiment. Fig.10 As shown in FIG. 1 , the sixth embodiment is different from the first embodiment in that a plurality of adjustment portions 251 and 252 are provided on the FPC 18 .

[0173] The number of the plurality of adjustment units 251 and 252 is the same as the number of the plurality of MA drivers 72. The number of the plurality of adjustment units 251 and 252 is not limited to this example. The adjustment units 251 and 252 are, for example, resistors. The resistance values ​​of the plurality of adjustment units 251 and 252 are different from each other.

[0174] The wiring W4 connects the amplifier power supply 92 and the plurality of MA drivers 72 in parallel. Furthermore, the wiring W4 in the present embodiment is branched to further connect the amplifier power supply 92 and the adjustment units 251 and 252.

[0175] The adjustment unit 251 is connected to a predetermined terminal (pin) of a corresponding one of the plurality of MA drivers 72. Therefore, the adjustment unit 251 reduces the voltage supplied from the amplifier power supply 92 to a predetermined voltage and applies it to the corresponding MA driver 72. For example, the adjustment unit 251 applies a voltage of 1V to the corresponding MA driver 72. The MA driver 72 uses the voltage supplied from the adjustment unit 251 as a signal for discrimination (discrimination signal).

[0176] The adjustment unit 252 is connected to a predetermined terminal (pin) of a corresponding one of the plurality of MA drivers 72. Therefore, the adjustment unit 252 reduces the voltage supplied from the amplifier power supply 92 to a predetermined voltage and applies it to the corresponding MA driver 72. For example, the adjustment unit 252 applies a voltage of 2V to the corresponding MA driver 72. In this way, different voltages are applied to the plurality of MA drivers 72. The MA driver 72 uses the voltage supplied from the adjustment unit 252 as a discrimination signal.

[0177] The adjustment units 251 and 252 always apply a predetermined voltage to the corresponding MA driver 72. In addition, the voltage supplied by the adjustment units 251 and 252 to the MA driver 72 may be changed. In addition, the adjustment units 251 and 252 may also reduce the voltage of other power supplies such as the switching power supply 91 to a predetermined voltage without being limited to the amplifier power supply 92.

[0178] In the sixth embodiment, the second address AD2 of the data signal SDATA includes, for example, an address corresponding to the MA driver 72 connected to the adjustment section 251 and an address corresponding to the MA driver 72 connected to the adjustment section 252. The second MA 48 is not limited to this example.

[0179] When receiving the data signal SDATA including the second address AD2, the logic circuit 86 of each MA driver 72 determines the address to be used according to the voltage applied from the adjustment units 251 and 252. That is, the logic circuit 86 of each MA driver 72 uses the address corresponding to the voltage applied from the adjustment units 251 and 252 in the second address AD2, and outputs a digital signal to the DAC 87 corresponding to the address.

[0180] The DAC 87 converts the digital signal input from the logic circuit 82 into an analog signal (driving signal) for driving the corresponding first MA 47 or second MA 48 , and outputs the converted driving signal to the corresponding MA amplifier 88 .

[0181] The MA amplifier 88 amplifies the drive signal input from the corresponding DAC 87 and outputs it to the corresponding first MA 47 or second MA 48. As described above, the plurality of MA drivers 72 output drive signals to the corresponding one of the first MA 47 and the second MA 48 according to one of the plurality of addresses of the second address AD2 corresponding to the voltage applied from the adjustment units 251 and 252.

[0182] In the HDD 10 of the sixth embodiment described above, the plurality of MA drivers 72 output drive signals to the corresponding one of the first MA 47 and the second MA 48 according to one of the plurality of addresses of the second address AD2 corresponding to the applied voltage. Thus, even when the suspension 37 is equipped with a plurality of actuators (the first MA 47 and the second MA 48), the desired MA driver 72 can output drive signals to the desired actuator. In addition, even if the circuit designs of the plurality of MA drivers 72 are the same, the plurality of MA drivers 72 can output drive signals to the desired actuators individually according to the voltages applied individually. Thus, the plurality of MA drivers 72 can be commonized, and the cost of the HDD 10 can be reduced.

[0183] (Seventh Implementation Method)

[0184] Below, refer to Fig.11 A seventh embodiment will be described. Fig.11 Schematically showing an example of the function of the HDD 10 according to the seventh embodiment. Fig.11 As shown in FIG. 1 , the seventh embodiment is different from the first embodiment in that a read / write channel (RWC) 301 is mounted on the FPC 18 .

[0185] In the first embodiment, the SoC 55 includes the RWC. In contrast, in the seventh embodiment, the RWC 301 is mounted on the FPC 18 as a component separate from the SoC 55. The RWC 301 is electrically connected to the SoC 55 and the serial I / F 81 of the preamplifier 71.

[0186] RWC301 is a signal processing circuit, which numbers the write data transmitted from the HDC of SoC55 and converts it into a write signal, and outputs the write signal to the serial I / F81 of the preamplifier 71. In addition, RWC301 decodes the read signal output from the magnetic head 14 and converts it into read data, and outputs the read data to the HDC. SoC55 and RWC301 communicate with each other via a high-speed interface using differential signals, for example.

[0187] As described above, in the HDD 10 of the seventh embodiment, various components and circuits mounted on the PCB 19, such as the RWC 301, may be mounted on the FPC 18. In addition, in the above description, an example in which the RWC 301 is mounted on the FPC 18 in the structure of the first embodiment is described, but the RWC 301 may be mounted on the FPC 18 in the structure of the second embodiment.

[0188] Several embodiments of the present invention have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A disk device comprising: a disc-shaped recording medium; Suspension; a magnetic head mounted on the suspension and configured to read and write information on the recording medium; an actuator mounted on the suspension to move the magnetic head; a frame, in which the recording medium, the suspension, the magnetic head and the actuator are arranged; A circuit substrate, which is located outside the frame and is provided with a control circuit for controlling the magnetic head and the actuator; A flexible printed wiring board, which is arranged inside the frame and has a first connection portion connected to the suspension and a second connection portion connected to the circuit substrate; a preamplifier mounted on the flexible printed wiring board, outputting to the magnetic head a write signal corresponding to information to be written by the magnetic head to the recording medium, and receiving from the magnetic head a read signal corresponding to information read by the magnetic head from the recording medium; as well as The actuator driver is mounted on the flexible printed wiring board in a manner separated from the preamplifier, and outputs a drive signal to the actuator to drive the actuator.

2. The disk device according to claim 1, The actuator driver is closer to the first connection portion than to the second connection portion.

3. The disk device according to claim 1, The flexible printed wiring board has a first terminal connected to the actuator driver, a first wiring connecting the first terminal to the first connection portion, a second terminal connected to the preamplifier, and a second wiring connecting the second terminal to the second connection portion and supplying power to the preamplifier. The first terminal is closer to the first connection portion than the second terminal.

4. The disk device according to claim 3, further comprising: an arm to which the suspension is mounted; and a voice coil motor that causes the arm to move; The flexible printed wiring board has a third connection portion connected to the voice coil motor and a third wiring connecting the second connection portion and the third connection portion. The first terminal is closer to the first connection portion than to the third connection portion.

5. The disk device according to any one of claims 1 to 4, The control circuit outputs a digital signal including a first address or a second address, The preamplifier operates based on the digital signal including the first address. The preamplifier or the actuator driver includes a digital-to-analog converter that converts the digital signal including the second address into the drive signal which is an analog signal. The actuator driver includes an amplifier that amplifies the drive signal and outputs the amplified drive signal to the actuator.

6. The disk device according to claim 5, The actuator comprises a plurality of actuator elements, The digital signal includes a discrimination signal that can be switched at a plurality of levels. The amplifier amplifies the drive signal and outputs the amplified drive signal to one actuator element corresponding to the level of the discrimination signal among the plurality of actuator elements.

7. The disk device according to any one of claims 1 to 4, The actuator comprises a plurality of actuator elements, The actuator driver includes a plurality of driver elements to which different voltages are applied. The control circuit outputs a digital signal including a first address or a second address, The second address includes a plurality of addresses corresponding to the plurality of driver elements, The preamplifier operates based on the digital signal including the first address. The plurality of driver elements each outputs the drive signal to a corresponding one of the plurality of actuator elements in accordance with one of the plurality of addresses corresponding to the voltage among the plurality of addresses of the second address.

8. The disk device according to any one of claims 1 to 4, The control circuit outputs a digital signal including a first enable signal and a second enable signal, The preamplifier operates based on the digital signal when the first enable signal is in an effective state. The preamplifier or the actuator driver includes a digital-to-analog converter that converts the digital signal into the drive signal, which is an analog signal, when the second enable signal is in an active state. The actuator driver includes an amplifier that amplifies the drive signal and outputs the amplified drive signal to the actuator.

9. The disk device according to any one of claims 1 to 4, The control circuit outputs a digital signal including an enable signal, The preamplifier operates based on the digital signal when the enable signal is in the first state. The preamplifier or the actuator driver includes a digital-to-analog converter that converts the digital signal into the drive signal, which is an analog signal, when the enable signal is in a second state. The actuator driver includes an amplifier that amplifies the drive signal and outputs the amplified drive signal to the actuator.

10. A disk device comprising: a disc-shaped recording medium; Suspension; a magnetic head mounted on the suspension and configured to read and write information on the recording medium; A circuit substrate provided with a control circuit for controlling the magnetic head; a flexible printed wiring board having a first connection portion connected to the suspension and a second connection portion connected to the circuit substrate; a preamplifier mounted on the flexible printed wiring board, outputting to the magnetic head a write signal corresponding to information to be written by the magnetic head to the recording medium, and receiving from the magnetic head a read signal corresponding to information read by the magnetic head from the recording medium; an electronic component mounted on the flexible printed wiring board in a manner away from the preamplifier; a fourth wiring provided on the flexible printed wiring board and connecting the first connection portion and the electronic component; and A fifth wiring is provided on the flexible printed wiring board, connects the second connection portion to the electronic component, and has an impedance lower than that of the fourth wiring.

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