Display module and electronic device

Abstract

The display module and the electronic equipment provided by the embodiments of the present application relate to the technical field of display. In detail, the embodiments of the present application lead out the multilayer signal traces from different first and second frame areas. Compared with leading out the multilayer signal traces from a single frame area (for example, the first frame area or the second frame area), the trace density of the signal traces in the frame area can be reduced, and the process problem that the frame area cannot be made into traces due to the small wiring space when the frame area is narrowed can be avoided. In this way, the frame can be further compressed under the existing process conditions, and the screen-to-body ratio of the display module can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display module and an electronic device. Background Technology

[0002] With the continuous development and advancement of display technology, consumers have increasingly higher demands for screen-to-body ratios in electronic devices (such as smartphones and tablets). Therefore, improving the screen-to-body ratio is currently a major research focus in electronic devices. In existing technologies, one possible way to improve the screen-to-body ratio is to reduce the screen bezel. However, manufacturing processes limit the compression of the screen bezel, creating a bottleneck. Overcoming the limitations imposed by manufacturing processes on further bezel compression is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] In order to overcome the technical problems mentioned in the above technical background, this application provides a display module and an electronic device.

[0004] A first aspect of this application provides a display module, the display module including an effective display area and a non-display area at least partially surrounding the effective display area, the non-display area including a first border area and a second border area located at opposite ends of the effective display area;

[0005] The display module includes an array substrate, which includes multiple layers of signal traces stacked together, wherein adjacent signal traces are insulated and isolated by an insulating layer.

[0006] The array substrate includes a first trace structure extending from the first border region and a second trace structure extending from the second border region, wherein the first trace structure is composed of a portion of the multilayer signal traces, and the second trace structure is composed of another portion of the multilayer signal traces.

[0007] In the above structure, multi-layer signal traces are routed from different first and second bezel areas. Compared to multi-layer signal traces being routed from a single bezel area (e.g., the first or second bezel area), this reduces the trace density in the bezel area and avoids the manufacturing process problem of insufficient wiring space when the bezel area narrows. It also allows for further bezel compression under existing manufacturing conditions, increasing the screen-to-body ratio of the display module.

[0008] In one possible embodiment of this application, the first routing structure includes a data signal line that transmits data signals to the pixel units of the effective display area, and the second routing structure includes a voltage signal line that provides voltage signals to the pixel units of the effective display area.

[0009] In one possible embodiment of this application, the non-display area further includes a first bent area located on the side of the first border area away from the effective display area, and a second bent area located on the side of the second border area away from the effective display area;

[0010] The first bend region includes a first bonding pin connected to the data signal line, and the second bend region includes a second bonding pin connected to the voltage signal line;

[0011] Preferably, the first border area is the lower border area, and the second border area is the upper border area.

[0012] The above structure allows different flexible circuit boards to be bonded via the first and second bonding pins, thereby obtaining electrical signals provided by different flexible circuit boards.

[0013] In one possible embodiment of this application, the second wiring structure further includes a screen detection signal line for providing a screen detection signal to the display module and a drive signal line for providing a drive signal to the array substrate;

[0014] Preferably, the second bending area further includes a third bonding pin connected to the screen detection signal line and a fourth bonding pin connected to the drive signal line.

[0015] The above configuration allows the number of signal traces originating from the first bezel area to be roughly equal to the number of signal traces originating from the second bezel area. This enables the first and second bezel areas to be compressed to approximately the same bezel size during compression, resulting in a more harmonious bezel size for the display module. Furthermore, it reduces the number of signal traces originating from the first bezel area, allowing for a smaller bezel size and further narrowing of the first bezel area.

[0016] In one possible embodiment of this application, the array substrate includes a first layer of signal traces, a second layer of signal traces, a third layer of signal traces, and a fourth layer of signal traces stacked sequentially.

[0017] The data signal line is formed by at least two of the first layer signal traces, the second layer signal traces, the third layer signal traces, and the fourth layer signal traces located in the first border area;

[0018] The voltage signal line is formed by at least a portion of the third layer signal trace and / or the fourth layer signal trace located in the second border area.

[0019] In one possible embodiment of this application, adjacent data signal lines are formed by signal traces on different layers.

[0020] In one possible embodiment of this application, the adjacent data signal lines are formed by a first layer of signal traces and a third layer of signal traces located in the first border area. The orthographic projection of the data signal line formed by the first layer of signal traces on the plane where the display surface of the display module is located at least partially overlaps with the orthographic projection of the data signal line formed by the third layer of signal traces on the plane where the display surface of the display module is located.

[0021] Alternatively, the adjacent data signal lines are formed by a second layer of signal traces and a fourth layer of signal traces located in the first border area; the orthographic projection of the data signal line formed by the second layer of signal traces on the plane where the display surface of the display module is located at least partially coincides with the orthographic projection of the data signal line formed by the fourth layer of signal traces on the plane where the display surface of the display module is located.

[0022] In one possible embodiment of this application, the data signal line is formed by a first layer signal trace, a second layer signal trace, a third layer signal trace, and a fourth layer signal trace;

[0023] The orthographic projection of the data signal line formed by the third layer signal traces onto the plane where the display surface of the display module is located is between the orthographic projections of the data signal lines formed by the first layer signal traces and the second layer signal traces onto the plane where the display surface of the display module is located.

[0024] The orthographic projection of the data signal line formed by the fourth layer signal traces onto the plane where the display surface of the display module is located is between the orthographic projections of the data signal lines formed by the first layer signal traces and the second layer signal traces onto the plane where the display surface of the display module is located; wherein, the orthographic projection of the data signal line formed by the third layer signal traces onto the plane where the display surface of the display module is located does not overlap with the orthographic projection of the data signal line formed by the fourth layer signal traces onto the plane where the display surface of the display module is located.

[0025] The above settings allow for a smaller capacitance between adjacent data signal lines, thus avoiding signal crosstalk between adjacent data signal lines and improving the display quality of the display module.

[0026] In one possible embodiment of this application, the first wiring structure includes a portion of data signal lines that transmit data signals to the pixel units of the effective display area, and the second wiring structure includes a voltage signal line that provides voltage signals to the pixel units of the effective display area and another portion of data signal lines that transmit data signals to the pixel units of the effective display area.

[0027] Alternatively, the first routing structure includes a portion of data signal lines that transmit data signals to the pixel units of the effective display area and a portion of voltage signal lines that provide voltage signals to the pixel units of the effective display area. The second routing structure includes another portion of voltage signal lines that provide voltage signals to the pixel units of the effective display area and another portion of data signal lines that transmit data signals to the pixel units of the effective display area.

[0028] A second aspect of this application also provides an electronic device, the electronic device comprising the display module described in the first aspect.

[0029] Compared to existing technologies, the display module and electronic device provided in this application draw multi-layer signal traces from different first and second bezel areas. This reduces the trace density in the bezel area compared to drawing multi-layer signal traces from a single bezel area (e.g., the first or second bezel area), avoiding the manufacturing problem of insufficient wiring space when the bezel area narrows. Thus, the bezel can be further compressed under existing manufacturing conditions, increasing the screen-to-body ratio of the display module. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a wiring diagram of a display module in the prior art;

[0032] Figure 2 for Figure 1 A schematic diagram of the film structure of the display module corresponding to region C1 in the middle;

[0033] Figure 3 This is a schematic diagram of the film layers of the display module provided in the embodiments of this application;

[0034] Figure 4 This is a wiring diagram of a display module provided in an embodiment of this application;

[0035] Figure 5 A schematic diagram of a film structure for a data signal line in the first frame region of a display module, as provided in an embodiment of this application.

[0036] Figure 6 This is a schematic diagram of another film layer structure of the data signal line in the first frame area of ​​the display module, which is provided in the embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0039] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0040] In the description of this application, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0042] Please refer to Figure 1 The diagram shows the wiring of a display module 10. The display module 10 includes an effective display area 10A and a non-display area 10B that partially surrounds the effective display area 10A. The display module 10 can be divided into area A corresponding to the upper border area, area B corresponding to the effective display area 10A, area C corresponding to the lower border area, and area D corresponding to the bend area, based on the width of different regions. The bend area is located on the side of the lower border area away from the effective display area 10A. Signal traces in the display module 10 can be led out from one border area of ​​the display module 10, for example... Figure 1The lower border area corresponding to area C has a bending area with a bonding pin that connects to the data signal line 10151 in the lower border area. Since the wiring space for the signal traces (data signal line 10151 and voltage signal line 10161 in the example figure) in the effective display area 10A is larger than the bonding area where the bonding pin is located in the bending area, when the signal traces connect from the effective display area 10A through the lower border area to the bonding pin in the bending area, it is necessary to concentrate the relatively dispersed signal traces. Therefore, the lower border area provides wiring space to transform the relatively dispersed signal traces into relatively concentrated traces.

[0043] However, as the width of the bottom border area is compressed, the trace space becomes smaller. To ensure that signal traces can be led out from the bottom border area, the width of the signal traces must be reduced. However, during the fabrication of signal traces, due to the limited exposure resolution of the lithography machine, when the line width is smaller than the resolution limit of the lithography machine (e.g., 1.5µm), the lithography machine cannot separate adjacent signal traces. Therefore, reducing the width of the signal traces also has a limit to the compression of the border width, restricting further reduction in the border width.

[0044] Furthermore, please refer to the following: Figure 1 and Figure 2 Through long-term research, the inventors discovered that when signal traces in the display module 10 are led out from a border area (e.g., the lower border area) of the display module 10, it is inevitable that different signal traces will overlap in the direction perpendicular to the display surface of the display module 10. For example, data signal line 10151 is generally made using a first layer signal trace M1' and a second layer signal trace M2', and voltage signal line 10161 is generally made using a third layer signal trace M3' and a fourth layer signal trace M4'. Data signal line 10151 and voltage signal line 10161 overlap in the direction perpendicular to the display surface of the display module 10. Among them, the third layer signal trace M3' and the fourth layer signal trace M4' are generally made using a TiAlTi three-layer structure fabricated by physical vapor deposition (PVD). Please refer to... Figure 2 , Figure 2 It shows Figure 1 A schematic diagram of the film structure in region C1 where data signal line 10151 and voltage signal line 10161 overlap. From... Figure 2It can be seen that when the distance d between adjacent data signal lines 10151 formed by the first layer signal trace M1' and the second layer signal trace M2' decreases, the size of the recessed area between adjacent data signal lines 10151 will decrease as the upper film layer (e.g., insulating layer and third layer signal trace M3') is fabricated. This results in the corresponding recessed area becoming smaller. Due to the poor coating properties of physical vapor deposition, when using the fourth layer signal trace M4' to fabricate voltage signal lines 10161, it is difficult to form a film layer covering the recessed area, thus forming aluminum voids 20. The presence of aluminum voids 20 makes it easy for moisture in high temperature and high humidity environments to enter the effective display area 10A through the aluminum voids 20, resulting in poor display (e.g., black spots). In addition, aluminum voids 20 can cause the film layer structure to be unstable. When subjected to external forces, cracks are easily formed at the location of the aluminum voids 20, affecting the reliability of the display module 10.

[0045] It should be noted that the defects in the solutions in the prior art are all the result of the inventors’ practice and careful research. Therefore, the discovery process of the above technical problems and the solutions proposed by the embodiments of this application in the following text should be the inventors’ contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0046] To address the aforementioned technical issues, embodiments of this application route multi-layer signal traces from different first and second bezel areas. Compared to routing multi-layer signal traces from a single bezel area (e.g., the first or second bezel area), this reduces the trace density within the bezel area and avoids the manufacturing problem of insufficient wiring space when the bezel area narrows. Thus, the bezel can be further compressed under existing manufacturing conditions, increasing the screen-to-body ratio of the display module.

[0047] The specific implementation scheme of this application will be described in detail below with reference to the accompanying drawings.

[0048] To better describe the technical solutions provided in the embodiments of this application, the film layer structure of the display module 10 will be introduced first. Now, in conjunction with... Figure 3 The film structure of the array substrate is described in detail.

[0049] The array substrate 101 may include a substrate layer 1011, a buffer layer 1012, and a pixel driving layer.

[0050] The substrate layer 1011 can be a glass substrate, the buffer layer 1012 is located on one side of the substrate layer 1011, and the pixel driving layer is located on the side of the buffer layer 1012 away from the substrate layer 1011. In this embodiment, the buffer layer 1012 can be formed from inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the buffer layer 1012 can be a two-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer sequentially formed on the substrate layer 1011.

[0051] The pixel driving layer may include an active layer 10131, a gate insulating layer 10132, a gate 10133, a source 10134, a drain 10135, a first insulating layer 10136, a second insulating layer 10137, and a first electrode 10138 and a second electrode 10139 for forming a capacitor.

[0052] An active layer 10131 is formed on a buffer layer 1012. The active layer 10131 may be formed of an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, or an oxide semiconductor. The active layer 10131 may include a source region (S), a drain region (D), and a channel region (p-si).

[0053] A gate insulating layer 10132 is formed on the active layer 10131 and the buffer layer 1012 not covered by the active layer 10131 to insulate and isolate the active layer 10131 and the gate 10133. The gate insulating layer 10132 may be made of materials such as silicon oxide or silicon nitride, but is not limited thereto.

[0054] A gate 10133 is formed on the side of the gate insulating layer 10132 corresponding to the active layer 10131 that faces away from the substrate layer 1011. The gate 10133 can be formed using one or more of the following metals: Al, Mo, Cu, Ti, or other low-resistivity metals. Simultaneously, a first electrode 10138 of a capacitor is also formed on the gate insulating layer 10132. The first electrode 10138 is formed on the gate insulating layer 10132, and the material of the first electrode 10138 and the gate 10133 can be the same. A first metal layer M1 can be fabricated on the gate insulating layer 10132 to simultaneously fabricate the gate 10133 and the first electrode 10138 on the gate insulating layer 10132.

[0055] A first insulating layer 10136 is formed on the gate insulating layer 10132 and covers the gate 10133 and the first electrode 10138. A second electrode 10139 is located on the side of the first insulating layer 10136 corresponding to the first electrode 10138 that is away from the substrate layer 1011. The first insulating layer 10136 serves to insulate and isolate the first electrode 10138 from the second electrode 10139, allowing the first electrode 10138 and the second electrode 10139 to form a capacitor. The first insulating layer 10136 can also be formed of inorganic materials, such as silicon nitride and silicon oxide. The second electrode 10139 is located in a second metal layer M2 formed above the first insulating layer 10136.

[0056] The second insulating layer 10137 is formed on the first insulating layer 10136 and covers the second electrode 10139, serving to isolate the source electrode 10134, drain electrode 10135, and second electrode 10139, thereby insulating them from each other. The second insulating layer 10137 can also be formed of inorganic materials (such as silicon nitride and silicon oxide). The structure of the second insulating layer 10137 can be a two-layer or three-layer structure formed of silicon nitride and silicon oxide.

[0057] Source 10134 and drain 10135 are formed on the second insulating layer 10137. Source 10134 is electrically connected to the source region (S) in the active layer 10131 through a via, and drain 10135 is electrically connected to the drain region (D) in the active layer 10131 through a via. The electrode materials of gate 10133, source 10134, drain 10135, first electrode 10138, and second electrode 10139 can all be one or more of metals such as Al, Mo, Cu, Ti, or other low resistivity metals. Source 10134 and drain 10135 are located in a third metal layer M3 fabricated on the second insulating layer 10137.

[0058] A planarization layer 1014 may also be disposed on the side of the pixel driving layer away from the substrate layer 1011. Based on the above structure, a driving element located on the array substrate can be formed, the driving element including a TFT (Thin Film Transistor) formed by a gate 10133, a source 10134, a drain 10135 and an active layer 10131.

[0059] In this embodiment, the planarization layer 1014 may include a first planarization layer 10141 and a second planarization layer 10142. A fourth metal layer M4 may also be disposed between the first planarization layer 10141 and the second planarization layer 10142. The fourth metal layer M4 can be connected to the drain 10135 of the driving element and the anode film layer (not shown in the figure) in the light-emitting device layer through the film layer vias of the planarization layer 10144. For example, the anode film layer can first be connected to the fourth metal layer M4 through the film layer vias of the second planarization layer 10142, and the fourth metal layer M4 can then be connected to the drain 10135 of the driving element located in the third metal layer M3 through the film layer vias of the first planarization layer 10141.

[0060] Please refer to Figure 4 , Figure 4 The diagram shows a wiring schematic of a display module provided in an embodiment of this application. In this embodiment, the display module 10 may include an effective display area 10A and a non-display area 10B that surrounds the effective display area 10A. The non-display area 10B includes a first border area (area C in the figure) and a second border area (area A in the figure) located at opposite ends of the effective display area 10A.

[0061] The array substrate 101 in the display module 10 includes multiple layers of signal traces, which can be constructed from... Figure 3 It is made of a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4. Specifically, the first metal layer M1 can be used to make the first layer signal trace M1', the second metal layer M2 can be used to make the second layer signal trace M2', the third metal layer M3 can be used to make the third layer signal trace M3', and the fourth metal layer M4 can be used to make the fourth layer signal trace M4'.

[0062] The array substrate 101 may include a first trace structure 1015 extending from a first border region and a second trace structure 1016 extending from a second border region. The first trace structure 1015 consists of a portion of signal traces from a multilayer signal trace network, and the second trace structure 1016 consists of another portion of signal traces from a multilayer signal trace network. The first trace structure 1015 may extend from one end of the first border region away from the effective display area 10A, and the second trace structure 1016 may extend from one end of the second border region away from the effective display area 10A.

[0063] Based on the above structure, multi-layer signal traces are led out from different first and second bezel areas. Compared to a scheme where multi-layer signal traces are led out from a single bezel area, this reduces the trace density in the bezel area and avoids the manufacturing process problem of insufficient wiring space when the bezel area narrows. Thus, the bezel can be further compressed under existing manufacturing conditions, increasing the screen-to-body ratio of the display module 10.

[0064] Further, in one possible implementation of this application, the first routing structure 1015 may include a data signal line 10151 for transmitting data signals (Data signals) to the pixel units of the effective display area 10A; the second routing structure 1016 may include a voltage signal line 10161 for providing voltage signals to the pixel units of the effective display area 10A, wherein the voltage signal line 10161 includes a voltage signal line 10161a for providing ELVDD voltage signals and a voltage signal line 10161b for providing ELVSS voltage signals. It is understood that in other possible implementations of this application, the first routing structure 1015 may include a portion of the data signal lines 10151 for transmitting data signals (Data signals) to the pixel units of the effective display area 10A, and the second routing structure 1016 may include a voltage signal line 10161 for providing voltage signals to the pixel units of the effective display area and another portion of the data signal lines 10151 for transmitting data signals (Data signals) to the pixel units of the effective display area 10A. It is understood that in other embodiments, the first wiring structure 1015 may include a portion of data signal lines 10151 that transmit data signals (Data signals) to the pixel units of the effective display area 10A and a portion of voltage signal lines 10161 that provide voltage signals to the pixel units of the effective display area 10A. The second wiring structure 1016 may include another portion of voltage signal lines 10161 that provide voltage signals to the pixel units of the effective display area 10A and another portion of data signal lines 10151 that transmit data signals (Data signals) to the pixel units of the effective display area 10A. The specific configuration can be adjusted according to actual conditions and is not limited here.

[0065] Based on the above settings, the technical problem that the signal trace density in the bezel area is too high when the voltage signal line 10161 and the data signal line 10151 are led out from the same bezel area can be avoided, which would prevent the bezel area from being further compressed and thus prevent the screen ratio from being further improved.

[0066] For ease of description, the following explanation will take the first routing structure 1015, which includes a data signal line 10151, and the second routing structure 1016, which includes a voltage signal line 10161, as examples.

[0067] In this embodiment, the non-display area 10B may further include a first bent area (area D in the figure) located on the side of the first border area away from the effective display area 10A (see area B in the figure), and a second bent area (area E in the figure) located on the side of the second border area (area A in the figure) away from the effective display area. The first bent area includes a first bonding pin 10152 connected to the data signal line 10151, and the second bent area includes a second bonding pin 10162 connected to the voltage signal line 10161.

[0068] Preferably, in this embodiment, the first border area can be the lower border area, and the second border area can be the upper border area. That is, the data signal line 10151 can be led out from the lower border area, and the voltage signal line 10161 can be led out from the upper border area.

[0069] With this configuration, different flexible circuit boards can be bonded at opposite ends of the display module 10 via the first bonding pin 10152 located in the first bending area and the second bonding pin 10162 located in the second bending area, and the corresponding electrical signals can be provided by the different flexible circuit boards.

[0070] Furthermore, in this embodiment, the second trace structure 1016 may further include a screen detection signal line (not shown in the figure) providing a screen detection signal to the display module 10 and a drive signal line (not shown in the figure) providing a drive signal to the array substrate 101. The second bending region also includes a third bonding pin (not shown in the figure) connected to the screen detection signal line and a fourth bonding pin (not shown in the figure) connected to the drive signal line.

[0071] This configuration ensures that the number of signal traces originating from the first border area is roughly equal to the number of signal traces originating from the second border area. This allows the first and second border areas to be compressed to similar border sizes during compression, resulting in a more harmonious border size for the display module 10. Furthermore, it reduces the number of signal traces originating from the first border area, further compressing the first border area and achieving a narrower border.

[0072] In this embodiment, the voltage signal line 10161 can be formed by at least a portion of the third layer signal trace M3' and / or the fourth layer signal trace M4' located in the second border area. Since the voltage signal line 10161 is led out from the second border area, the third layer signal trace M3' and the fourth layer signal trace M4' located in the second border area can be used to form the voltage signal line 10161. The data signal line 10151 can be formed by the first layer signal trace M1', the second layer signal trace M2', the third layer signal trace M3', and the fourth layer signal trace M4' located in the first border area. Specifically, the data signal line 10151 can be formed by at least two of the first layer signal trace M1', the second layer signal trace M2', the third layer signal trace M3', and the fourth layer signal trace M4' located in the first border area.

[0073] To avoid signal crosstalk caused by the capacitance between adjacent signal traces affecting signal transmission, the capacitance between adjacent signal traces can be reduced to weaken the crosstalk. Adjacent data signal lines 10151 refer to adjacent data signal lines 10151 projected onto the plane containing the display surface of the display module 10. Specifically, the distance between adjacent signal traces can be appropriately increased. For example, in this embodiment, adjacent data signal lines can be formed by signal traces from different layers.

[0074] Specifically, please refer to Figure 5 , Figure 5 This illustration shows a schematic diagram of a film structure for data signal line 10151 in display module 10 according to an embodiment of this application. In a possible implementation of this application, in order to increase the distance between adjacent data signal lines, adjacent data signal lines 10151 may be composed of a first layer signal trace M1' and a third layer signal trace M3', or adjacent data signal lines 10151 may be composed of a second layer signal trace M2' and a fourth layer signal trace M4', respectively. Specifically, when adjacent data signal lines 10151 are formed by a first layer signal trace M1' and a third layer signal trace M3', the orthographic projection of the data signal line 10151 formed by the first layer signal trace M1' onto the plane where the display surface of the display module 10 is located at least partially coincides with the orthographic projection of the data signal line 10151 formed by the third layer signal trace M3' onto the plane where the display surface of the display module 10 is located. A first insulating layer 10136 and a second insulating layer 10137 may be provided between the first layer signal trace M1' and the third layer signal trace M3'. When adjacent data signal lines 10151 are formed by the second layer signal trace M2' and the fourth layer signal trace M4', the orthographic projection of the data signal line 10151 formed by the second layer signal trace M2' on the plane where the display surface of the display module 10 is located at least partially coincides with the orthographic projection of the data signal line 10151 formed by the fourth layer signal trace M4' on the plane where the display surface of the display module 10 is located. A second insulating layer 10137 and a first planarization layer 10141 may be provided between the second layer signal trace M2' and the fourth layer signal trace M4'.

[0075] It is understood that the above is merely one possible configuration of data signal lines listed in the embodiments of this application. In other embodiments, other configurations may also exist. For example, adjacent data signal lines 10151 may be formed by a first layer signal trace M1' and a fourth layer signal trace M4', wherein the orthographic projections of the first layer signal trace M1' and the fourth layer signal trace M4' on the plane where the display surface of the display module 10 is located at least partially overlap. Alternatively, adjacent data signal lines 10151 may be formed by a second layer signal trace M2' and a third layer signal trace M3', wherein the orthographic projections of the second layer signal trace M2' and the third layer signal trace M3' on the plane where the display surface of the display module 10 is located at least partially overlap. Furthermore, in a display module 10, some adjacent data signal lines 10151 may be formed by a first layer signal trace M1' and a third layer signal trace M3', while another portion of adjacent data signal lines 10151 may be formed by a second layer signal trace M2' and a fourth layer signal trace M4'. The specific settings can be adjusted according to the actual situation, and no specific limitations are made here.

[0076] Based on the above settings, a small capacitance can be provided between adjacent data signal lines 10151 to avoid signal crosstalk between adjacent data signal lines 10151 and improve the display quality of the display module 10.

[0077] Furthermore, in this embodiment, to avoid the technical problem of aluminum voids occurring when the data signal line 10151 is formed simultaneously using the first layer signal trace M1', the second layer signal trace M2', the third layer signal trace M3', and the fourth layer signal trace M4', please refer to... Figure 6 , Figure 6 This diagram illustrates another film layer structure of the data signal line 10151 in the display module according to an embodiment of this application. In a possible implementation of this application embodiment, the data signal line 10151 located in the first frame area can be configured as follows:

[0078] The orthographic projection of the data signal line 10151 formed by the third layer signal trace M3' onto the plane where the display surface of the display module 10 is located is between the orthographic projections of the data signal line 10151 formed by the first layer signal trace M1' and the second layer signal trace M2' onto the plane where the display surface of the display module 10 is located.

[0079] The orthographic projection of the data signal line 10151 formed by the fourth layer signal trace M4' onto the plane of the display surface of the display module 10 lies between the orthographic projections of the data signal line 10151 formed by the first layer signal trace M1' and the second layer signal trace M2' onto the plane of the display surface of the display module 10; wherein, the orthographic projection of the data signal line 10151 formed by the third layer signal trace M3' onto the plane of the display module does not overlap with the orthographic projection of the data signal line 10151 formed by the fourth layer signal trace M4' onto the plane of the display module. The figure exemplarily illustrates a feasible arrangement.

[0080] When fabricating the fourth signal trace M4', since the third signal trace M3' is not fabricated below the fourth signal trace M4', an insulating layer (e.g., the second insulating layer 10137) can be fabricated only on the second signal trace M2' during film fabrication. This allows the recessed area between the first signal trace M1' and the second signal trace M2' to have a larger size, facilitating effective film formation when fabricating the fourth signal trace M4' using the PVD process.

[0081] Based on the above configuration, when using the third metal layer M3 and the fourth metal layer M4 to fabricate the data signal line 10151, the overlap between the data signal line 10151 formed by the third layer signal trace M3' and the data signal line 10151 formed by the fourth layer signal trace M4' at the position between the first layer signal trace M1' and the second layer signal trace M2' can be avoided. This further avoids the problem of forming aluminum voids when forming the fourth layer signal trace M4'.

[0082] Furthermore, in this embodiment, the orthographic projection of the voltage signal line 10161 onto the plane where the display surface of the display module is located does not overlap with the orthographic projection of the data signal line 10151 onto the plane where the display surface of the display module is located.

[0083] With this configuration, the voltage signal line 10161 and the data signal line 10151 do not overlap, which can avoid the aluminum void phenomenon caused by the manufacturing process and ensure the display quality of the display module 10 and its ability to resist external forces.

[0084] This application also provides an electronic device that includes the aforementioned display module. The electronic device using the aforementioned display module 10 can further narrow the bezel width, increase the screen ratio of the electronic device, and enhance the market competitiveness of the electronic device.

[0085] In summary, the display module and electronic device provided in this application lead out multiple layers of signal traces from different first and second bezel areas. Compared to a scheme where multiple layers of signal traces are led out from a single bezel area (e.g., the first or second bezel area), this reduces the trace density in the bezel area and avoids the manufacturing problem of insufficient wiring space when the bezel area becomes narrower. It also allows for further bezel compression under existing manufacturing conditions, thereby increasing the screen-to-body ratio of the display module.

[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display module, characterized in that, The display module includes an effective display area and a non-display area that at least partially surrounds the effective display area. The non-display area includes a first border area and a second border area located at opposite ends of the effective display area. The display module includes an array substrate, which includes multiple layers of signal traces stacked together, wherein adjacent signal traces are insulated and isolated by an insulating layer. The array substrate includes a first trace structure extending from the first border region and a second trace structure extending from the second border region, wherein the first trace structure is composed of a portion of the multilayer signal traces, and the second trace structure is composed of another portion of the multilayer signal traces. The first routing structure includes a data signal line that transmits data signals to the pixel units of the effective display area, and the second routing structure includes a voltage signal line that provides voltage signals to the pixel units of the effective display area. The adjacent data signal lines are formed by signal traces on different layers.

2. The display module as described in claim 1, characterized in that, The non-display area also includes a first bent area located on the side of the first border area away from the effective display area, and a second bent area located on the side of the second border area away from the effective display area; The first bend region includes a first bonding pin connected to the data signal line, and the second bend region includes a second bonding pin connected to the voltage signal line.

3. The display module as described in claim 2, characterized in that, The first border area is the bottom border area, and the second border area is the top border area.

4. The display module as described in claim 2, characterized in that, The second wiring structure also includes a screen detection signal line that provides a screen detection signal for the display module and a drive signal line that provides a drive signal for the array substrate.

5. The display module as described in claim 4, characterized in that, The second bending area also includes a third bonding pin connected to the screen detection signal line and a fourth bonding pin connected to the drive signal line.

6. The display module as described in claim 1, characterized in that, The array substrate includes a first layer of signal traces, a second layer of signal traces, a third layer of signal traces, and a fourth layer of signal traces stacked sequentially. The data signal line is formed by at least two of the first layer signal traces, the second layer signal traces, the third layer signal traces, and the fourth layer signal traces located in the first border area; The voltage signal line is formed by at least a portion of the third layer signal trace and / or the fourth layer signal trace located in the second border area.

7. The display module as described in claim 6, characterized in that, The adjacent data signal lines are formed by a first layer of signal traces and a third layer of signal traces located in the first border area. The orthographic projection of the data signal line formed by the first layer of signal traces on the plane where the display surface of the display module is located is at least partially coincident with the orthographic projection of the data signal line formed by the third layer of signal traces on the plane where the display surface of the display module is located. Alternatively, the adjacent data signal lines are formed by a second layer of signal traces and a fourth layer of signal traces located in the first border area; the orthographic projection of the data signal line formed by the second layer of signal traces on the plane where the display surface of the display module is located at least partially coincides with the orthographic projection of the data signal line formed by the fourth layer of signal traces on the plane where the display surface of the display module is located.

8. The display module as described in claim 1, characterized in that, The data signal line is formed by a first layer of signal traces, a second layer of signal traces, a third layer of signal traces, and a fourth layer of signal traces; The orthographic projection of the data signal line formed by the third layer signal traces on the plane where the display surface of the display module is located is between the orthographic projections of the data signal lines formed by the first layer signal traces and the second layer signal traces on the plane where the display surface of the display module is located; The orthographic projection of the data signal line formed by the fourth layer signal trace on the plane where the display surface of the display module is located is between the orthographic projections of the data signal lines formed by the first layer signal trace and the second layer signal trace on the plane where the display surface of the display module is located; The orthographic projection of the data signal line formed by the third layer signal traces onto the plane where the display surface of the display module is located does not overlap with the orthographic projection of the data signal line formed by the fourth layer signal traces onto the plane where the display surface of the display module is located.

9. The display module as described in claim 1, characterized in that, The first routing structure includes a portion of data signal lines that transmit data signals to the pixel units of the effective display area, and the second routing structure includes a voltage signal line that provides voltage signals to the pixel units of the effective display area and another portion of data signal lines that transmit data signals to the pixel units of the effective display area. Alternatively, the first routing structure includes a portion of data signal lines that transmit data signals to the pixel units of the effective display area and a portion of voltage signal lines that provide voltage signals to the pixel units of the effective display area. The second routing structure includes another portion of voltage signal lines that provide voltage signals to the pixel units of the effective display area and another portion of data signal lines that transmit data signals to the pixel units of the effective display area.

10. An electronic device, characterized in that, The electronic device includes the display module as described in any one of claims 1-9.

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