Display substrate and display device

Abstract

The embodiments of the present disclosure provide a display substrate and a display device, which relate to the field of display technology, so as to reduce the energy consumption of the display panel of the display device and slow down the temperature rise of the display panel of the display device. The display panel includes a substrate, a second electrode layer and a first voltage signal line, and the first voltage signal line includes a first line and a second line; the first line and the second line are arranged in parallel in the second frame area, the third frame area and the fourth frame area, and both ends of the first line and the second line extend to the first frame area, and the first line and the second line are configured to transmit a first voltage signal; wherein the first line is connected to the second electrode layer on the periphery of the display area, the part of the second line located in the third frame area is connected to the second electrode layer and / or connected to the first line, and the part of the second line located in the first frame area, the second frame area and the fourth frame area is separated from the second electrode layer and the first line. The display substrate provided by the present disclosure is used to manufacture a display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display devices have gradually become prevalent in people's lives. Among them, organic light-emitting diode (OLED) display panels are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response speed, and high contrast. However, medium and large-sized display panels have the problems of high energy consumption and rapid temperature rise. Summary of the invention

[0003] The present disclosure provides a display substrate and a display device, so as to reduce the energy consumption of a display panel of the display device and mitigate the temperature rise of the display panel of the display device.

[0004] In one aspect, a display substrate is provided. The display substrate includes a substrate, a second electrode layer and a first voltage signal line. The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area includes a first frame area, a second frame area, a third frame area and a fourth frame area; the first frame area and the third frame area are located on opposite sides of the display area in a first direction; the second frame area and the fourth frame area are located on opposite sides of the display area in a second direction; the first direction is perpendicular to the second direction. The second electrode layer is arranged on the substrate; the second electrode layer extends from the display area to the peripheral area. The first voltage signal line includes a first routing line and a second routing line; the first routing line and the second routing line are arranged in parallel and are at least located in the second frame area, the third frame area and the fourth frame area, and both ends of the first routing line and the second routing line extend to the first frame area to receive a first voltage signal.

[0005] Among them, the first routing is connected to the second electrode layer in the second border area, the third border area and the fourth border area, the second routing is connected to the second electrode layer and / or connected to the first routing in the third border area, and the second routing is separated from the second electrode layer and the first routing in the second border area and the fourth border area.

[0006] In some embodiments, the display substrate further includes at least one conductive layer disposed between the substrate and the second electrode layer. The first routing includes at least one first routing pattern, each of which is located in one of the at least one conductive layer; when the first routing includes a plurality of first routing patterns, the plurality of first routing patterns are stacked and connected along a direction perpendicular to the substrate. The second routing includes at least one second routing pattern, each of which is located in one of the at least one conductive layer; when the second routing includes a plurality of second routing patterns, the plurality of second routing patterns are stacked and connected along a direction perpendicular to the substrate.

[0007] In some embodiments, at least one first routing pattern and at least one second routing pattern in the first routing and the second routing are located in the same conductive layer. In the second border area and the fourth border area, the first routing pattern and the second routing pattern located in the same conductive layer are arranged alternately. In the third border area, the first routing pattern and the second routing pattern located in the same conductive layer are connected; or, the first routing pattern and the second routing pattern located in the same conductive layer are arranged alternately, and a second routing pattern in the second routing that is farthest from the substrate is connected to the second electrode layer.

[0008] In some embodiments, the at least one conductive layer includes a first source-drain conductive layer and a first electrode layer, and the first electrode layer is located between the first source-drain conductive layer and the second electrode layer.

[0009] In some embodiments, the first routing includes two first routing patterns, which are respectively located in the first source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second border area, the third border area and the fourth border area; the first routing pattern located in the first electrode layer is connected to the second electrode layer. The second routing includes two second routing patterns, which are respectively located in the first source-drain conductive layer and the first electrode layer; the second routing pattern located in the first source-drain conductive layer is at least arranged in the second border area, the third border area and the fourth border area; the second routing pattern located in the first electrode layer is at least arranged in the third border area and connected to the second electrode layer.

[0010] In some embodiments, the first routing includes two first routing patterns, which are respectively located in the first source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second border area, the third border area, and the fourth border area. The second routing includes a second routing pattern, which is located in the first source-drain conductive layer; the second routing pattern is at least arranged in the second border area, the third border area, and the fourth border area, and the second routing pattern is connected to the first routing pattern located in the first source-drain conductive layer in the third border area.

[0011] In some embodiments, the at least one conductive layer further includes a second source-drain conductive layer, and the second source-drain conductive layer is located between the first source-drain conductive layer and the first electrode layer.

[0012] In some embodiments, the first routing includes three first routing patterns, which are respectively located in the first source-drain conductive layer, the second source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second border area, the third border area and the fourth border area. The second routing includes three second routing patterns, which are respectively located in the first source-drain conductive layer, the second source-drain conductive layer and the first electrode layer; the second routing pattern located in the first source-drain conductive layer and the second routing pattern located in the second source-drain conductive layer are both at least arranged in the second border area, the third border area and the fourth border area; the second routing pattern located in the first electrode layer is at least arranged in the third border area and is connected to the second electrode layer.

[0013] In some embodiments, the first routing includes three first routing patterns, which are respectively located in the first source-drain conductive layer, the second source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second border area, the third border area and the fourth border area; the first routing pattern located in the first electrode layer is connected to the second electrode layer. The second routing includes two second routing patterns, which are respectively located in the first source-drain conductive layer and the second source-drain conductive layer; each second routing pattern is at least arranged in the second border area, the third border area and the fourth border area. The first routing pattern and the second routing pattern located in the first source-drain conductive layer are connected in the third border area, and / or the first routing pattern and the second routing pattern located in the second source-drain conductive layer are connected in the third border area.

[0014] In some embodiments, in the third border area, a set line segment of the second routing line is connected to the second electrode layer and / or to the first routing line. The length of the set line segment is equal to the length of the portion of the second routing line located in the third border area; or, the second routing line includes a plurality of set line segments, and the plurality of set line segments are arranged at intervals along the third border area.

[0015] In some embodiments, the first frame area includes a binding area, the display substrate further includes at least one first power pin, and the at least one first power pin is disposed in the binding area. The first power pin is configured to transmit a first voltage signal; and the first voltage signal line is electrically connected to the first power pin.

[0016] In some embodiments, the first wiring and the second wiring are respectively connected to different first power pins in the binding area. Alternatively, the display substrate further includes a power connection line arranged in the first frame area, the first wiring and the second wiring are connected to the power connection line in the first binding area, and the power connection line is connected to the first power pin.

[0017] In some embodiments, the second routing line is disposed between the first routing line and the display area, and the orthographic projection of the second electrode layer on the substrate at least partially overlaps with the orthographic projection of the second routing line on the substrate. Alternatively, the first routing line is disposed between the second routing line and the display area, and there is a gap between the orthographic projection of the second electrode layer on the substrate and the orthographic projection of the second routing line on the substrate.

[0018] In some embodiments, the display substrate further comprises at least one scan control circuit disposed in the peripheral area. The at least one scan control circuit is located between the first voltage signal line and the display area, or between the first wiring and the second wiring.

[0019] In the display substrate provided by some embodiments of the present disclosure, only the portion of the second routing line located in the third frame area is directly electrically connected to the second electrode layer. In this way, in the process of the first voltage signal being transmitted from the first frame along the second routing line to the third frame area, the voltage drop generated by the first voltage signal passing through the portion of the second routing line located in the second frame area and the fourth frame area is relatively low, that is, the voltage drop of the first voltage signal transmitted to the portion of the second routing line located in the third frame area is relatively small; and because it is electrically connected to the upper frame, the second routing line can compensate for the voltage drop of the first routing line at the third frame area, thereby reducing the voltage drop generated by the first voltage signal line as a whole, thereby reducing energy consumption and slowing down temperature rise.

[0020] In another aspect, a display device is provided, comprising a display substrate and a packaging layer covering a light-emitting side of the display substrate, wherein the display substrate is the display substrate described in any of the above embodiments.

[0021] The beneficial effects of the display device provided by some embodiments of the present disclosure are the same as the beneficial effects of the display substrate provided by the above technical solution, and are not elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0023] Figure 1 is a structural diagram of a display device according to some embodiments;

[0024] Figure 2 is a cross-sectional view of a display panel according to some embodiments;

[0025] Figure 3 A structural diagram of a display substrate and a circuit board bound together according to some embodiments;

[0026] Figure 4 is a structural diagram of a pixel driving circuit according to some embodiments;

[0027] Figure 5 is a structural diagram of a display substrate according to some embodiments;

[0028] Figure 6 is a structural diagram of a display substrate according to some other embodiments;

[0029] Figure 7 is a structural diagram of a display substrate according to some further embodiments;

[0030] Figure 8 for Figure 7 A cross-sectional view of a display substrate along section line AA is shown;

[0031] Fig. 9 for Figure 7 A cross-sectional view of a display substrate along section line BB is shown;

[0032] Fig.10 for Figure 7 Another cross-sectional view of a display substrate along the section line BB is shown;

[0033] Fig.11 for Figure 7 Another cross-sectional view of a display substrate along the section line AA is shown;

[0034] Fig.12 for Figure 7 A cross-sectional view of another display substrate along section line BB is shown;

[0035] Fig.13 for Figure 5 or Figure 7 A cross-sectional view of a display substrate along a section line CC is shown;

[0036] Fig.14 for Figure 5 or Figure 7 Another cross-sectional view of the substrate is shown along the section line CC. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms such as the third person singular form "comprises" and the present participle form "comprising" are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0044] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0046] Some embodiments of the present disclosure provide a display substrate 1 and a display device 100. The display substrate 1 and the display device 100 are respectively introduced below.

[0047] like Figure 1 As shown, some embodiments of the present disclosure provide a display device 100, which can be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0048] In some embodiments, Figure 1 The display device 100 includes a display panel 10 .

[0049] For example, see Figure 1 and Figure 3 The display device 100 may further include a frame, a circuit board 20, and other electronic components, etc. The display panel 10 may be disposed in the frame, for example.

[0050] The display panel 10 may be of various types and may be selected according to actual needs.

[0051] Exemplarily, the above-mentioned display panel 10 can be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel, etc., and the present disclosure does not make any specific limitations on this.

[0052] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 10 as an OLED display panel as an example.

[0053] In some embodiments, Figure 2 As shown, the display panel 10 includes the above-mentioned display substrate 1 and an encapsulation layer 2 for encapsulating the display substrate 1 .

[0054] Here, the encapsulation layer 2 may be an encapsulation film or an encapsulation substrate. In some embodiments, the encapsulation layer 2 includes a first inorganic film 21, an organic film 22, and a second inorganic film 23 to prevent moisture and oxygen in the external environment from entering the display panel 10 and damaging the organic materials in the light-emitting device, thereby shortening the life of the display panel 10.

[0055] In some embodiments, Figure 3 As shown, the display substrate 1 has a display area A and a peripheral area B located at at least one side of the display area A. Figure 3 The peripheral area B surrounding the display area A is taken as an example for illustration.

[0056] The display area A is an area for displaying an image, and the display area A is configured to set sub-pixels P.

[0057] For example, Figure 2 and Figure 3 As shown, the display substrate 1 may include a substrate Sub and sub-pixels P disposed on the substrate Sub and located in the display area A. Each sub-pixel P includes a light-emitting device 11 and a pixel driving circuit 12 disposed on the substrate Sub. The pixel driving circuit 12 includes a plurality of thin film transistors 121. The thin film transistor 121 includes an active layer 1211, a source electrode 1212, a drain electrode 1213 and a gate electrode 1214. The source electrode 1212 and the drain electrode 1213 are in contact with the active layer 1211, respectively. In a direction away from the substrate Sub, the light-emitting device 11 includes a first electrode layer 111, a light-emitting functional layer 112 and a second electrode layer 113 disposed in sequence. The first electrode layer 111 is electrically connected to the source electrode 1212 or the drain electrode 1213 of a thin film transistor serving as a driving transistor among the plurality of thin film transistors 121. Figure 2 In the figure, the first electrode layer 111 and the source electrode 1212 of the thin film transistor 121 are electrically connected to each other.

[0058] It should be noted that the source 1212 and the drain 1213 can be interchanged. Figure 2 The 1212 in the figure represents the drain. Figure 2 The 1213 in the figure represents the source.

[0059] In some embodiments, the light-emitting functional layer 112 includes only a light-emitting layer. In other embodiments, the light-emitting functional layer 112 includes, in addition to the light-emitting layer, at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0060] In some embodiments, Figure 2 As shown, the display substrate 1 further includes a pixel defining layer PDL, the pixel defining layer PDL includes a plurality of opening areas, and one light emitting device 15 is disposed in one opening area.

[0061] In some embodiments, Figure 2 As shown, the display substrate 1 further includes a spacer PS, and the spacer PS is disposed between the pixel defining layer PDL and the light emitting layer functional layer 112 .

[0062] In some embodiments, Figure 2 As shown, the display substrate 1 further includes a semiconductor layer, a first gate insulating layer GI1, a first gate conductive layer, a second gate insulating layer GI2, a second gate conductive layer, and an interlayer insulating layer ILD.

[0063] like Figure 2 and Fig.11 As shown, the semiconductor layer, the first gate insulating layer GI1 , the first gate conductive layer, the second gate insulating layer GI2 , the second gate conductive layer and the interlayer insulating layer ILD are sequentially stacked between the substrate Sub and the first electrode layer 111 .

[0064] The material of the semiconductor layer includes amorphous silicon, single crystal silicon, polycrystalline silicon, or metal oxide semiconductor material; for example, the material of the semiconductor layer ACT includes indium gallium zinc oxide (IGZO) and zinc oxide (ZnO), but the present disclosure is not limited thereto. The semiconductor layer includes an active layer 1211 of each transistor.

[0065] The first gate conductive layer overlaps the semiconductor layer to form transistors. The material of the first gate conductive layer includes a conductive metal; for example, the material of the first gate conductive layer includes at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto. The first gate conductive layer includes the gate 235 of each transistor and the first plate of the capacitor.

[0066] The first gate insulating layer GI1 is disposed between the semiconductor layer and the first gate conductive layer to electrically insulate the semiconductor layer from the first gate conductive layer. The material of the first gate insulating layer GI1 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the first gate insulating layer GI1 includes silicon dioxide, but the present disclosure is not limited thereto.

[0067] The second gate conductive layer overlaps the first gate conductive layer to form a storage capacitor. The material of the second gate conductive layer includes a conductive metal; for example, the material of the second gate conductive layer includes at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto. The second gate conductive layer includes a second plate of the capacitor.

[0068] The second gate insulating layer GI2 is disposed between the first gate conductive layer and the second gate conductive layer to electrically insulate the first gate conductive layer from the second gate conductive layer. The material of the second gate insulating layer GI2 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide; for example, the material of the second gate insulating layer GI2 includes silicon dioxide, but the present disclosure is not limited thereto.

[0069] The interlayer dielectric layer ILD is disposed between the first source-drain conductive layer SD1 and the second gate conductive layer, and is used to electrically insulate the first source-drain conductive layer SD1 from the second gate conductive layer. The material of the interlayer dielectric layer ILD includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the second gate insulating layer GI2 includes silicon dioxide, but the present disclosure is not limited thereto.

[0070] The peripheral area B is a non-display area, and the peripheral area B can be configured to set up a scan drive circuit, circuit wiring, and binding pins, etc.

[0071] For example, Figure 2 and Figure 3 As shown, the peripheral area B includes a binding area C, and the circuit board 20 and the display substrate 1 are bound and electrically connected in the binding area C. In detail, the binding area C on the substrate Sub is provided with a plurality of binding pins 13, and the circuit board 20 is provided with a plurality of binding electrodes, and the plurality of binding electrodes are correspondingly connected with the plurality of binding pins 13 to realize the electrical connection between the circuit board 20 and the display substrate 1.

[0072] It should be noted that the plurality of binding pins 13 include a power pin 130, a data pin and a gate pin, etc. The power pin 130 is used to provide a power signal to the sub-pixel P for emitting light, the data pin is used to write a data signal to the pixel driving circuit 12, and the gate pin is used to provide a control signal to the scanning driving circuit 200.

[0073] For example, Figure 2 and Figure 3 As shown, the display substrate 1 may further include a substrate Sub and a scan driving circuit 200 , a source driving circuit 300 , a first voltage signal line VSS and a second voltage signal line VDD which are disposed on the substrate Sub and located in the peripheral area B.

[0074] Here, the scan driving circuit 200 may include a gate driving circuit for inputting a gate scanning signal Gate to the pixel driving circuit 12, and a light emitting driving circuit for inputting a light emitting scanning signal Em to the pixel driving circuit 12. The source driving circuit 300 is used to input a data signal Data to the pixel driving circuit 12. The first voltage signal line VSS is used to input a first voltage signal Vss to the light emitting device 11. The second voltage signal line VDD is used to input a second voltage signal Vdd to the light emitting device 11.

[0075] The potential of the first voltage signal Vss input by the first voltage signal line VSS is less than the potential of the second voltage signal Vdd input by the second voltage signal line VDD. For example, the power pin 130 includes a first power pin 131 and a second power pin 132, the first voltage signal line VSS is electrically connected to the first power pin 131, the first power pin 131 is electrically connected to the negative electrode of the power supply, and is configured to transmit the first voltage signal Vss; the second voltage signal line VDD is electrically connected to the second power pin 132, the second power pin 132 is electrically connected to the positive electrode of the power supply, and is configured to transmit the second voltage signal Vdd.

[0076] In some embodiments, Figure 3 As shown, the first voltage signal line VSS is disposed in the peripheral area B and at least partially surrounds the display area A. The second voltage signal line VDD is disposed in the peripheral area between the binding area C and the display area A.

[0077] It should be noted that the first voltage signal line VSS described here surrounds the display area A, which does not mean that the first voltage signal line VSS strictly completely surrounds the display area A. The first voltage signal line VSS may at least surround the display area A except for the boundary of the binding area C. For example, Figure 3 As shown, the orthographic projection of the first voltage signal line VSS on the substrate Sub is approximately U-shaped.

[0078] For the convenience of explanation, the above-mentioned multiple sub-pixels P in the present disclosure are described by taking the matrix arrangement as an example. In this case, the sub-pixels P arranged in a row along the first direction X are called sub-pixels P in the same row; the sub-pixels P arranged in a column along the second direction Y are called sub-pixels P in the same column. The first direction X is perpendicular to the second direction Y.

[0079] See also Figure 3 Each sub-pixel P includes a pixel driving circuit 12 for controlling the display of the sub-pixel P. The pixel driving circuits 12 in the same row are coupled to the same gate scanning signal line GL and the same light-emitting scanning signal line EM, and the pixel driving circuits 12 in the same column are coupled to the same data line DL.

[0080] Among them, the gate scanning signal line GL is used to transmit the gate scanning signal Gate to the pixel driving circuit 12; the light emitting scanning signal line EM is used to transmit the light emitting scanning signal Em to the pixel driving circuit 12; and the data line DL is used to transmit the data signal Data to the pixel driving circuit 12.

[0081] In some embodiments, Figure 3As shown, the scan driving circuit 200 may be disposed on a side along the extending direction of the gate scan signal line GL, and the source driving circuit 300 may be disposed on a side along the extending direction of the data line DL. Figure 3 In the figure, it is taken as an example that two scan driving circuits 200 are respectively located in the extending direction of the gate scan signal line GL.

[0082] In some embodiments, see Figure 3 The scanning control circuit 200 is a GOA (Gate Driver on Array) circuit, that is, the scanning control circuit 200 is directly integrated in the display substrate 1 to reduce the frame size of the display substrate 1, reduce the manufacturing cost of the display substrate 1, and realize a narrow frame design. The following embodiments are all described by taking the scanning control circuit 200 as a GOA circuit as an example.

[0083] The structure of the pixel driving circuit 12 includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit 12 may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C" structures. Among them, "T" represents a transistor, and the number in front of "T" represents the number of transistors, and "C" represents a storage capacitor, and the number in front of "C" represents the number of storage capacitors.

[0084] The present disclosure takes the external compensation method (sensing the driving transistor) and the pixel driving circuit 12 adopting the "3T1C" structure as an example to schematically illustrate the structure and working process of the sub-pixel P.

[0085] For example, Figure 4 As shown, the pixel driving circuit 12 may include: a switching transistor T1, a driving transistor T2, a sensing transistor T3 and a storage capacitor Cst.

[0086] For example, Figure 4 As shown, the control electrode of the switch transistor T1 is electrically connected to the first scan signal terminal G1, the first electrode of the switch transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the switch transistor T1 is electrically connected to the first node G. The switch transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to the first scan signal received at the first scan signal terminal G1.

[0087] For example, Figure 4As shown, the control electrode of the driving transistor T2 is electrically connected to the first node G, the first electrode of the driving transistor T2 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the driving transistor T2 is electrically connected to the second node S. The driving transistor T2 is configured to, under the control of the voltage of the first node G, receive the first voltage signal line VDD (see Figure 3 ) is transmitted to the second node S.

[0088] For example, Figure 4 As shown, a first end of the storage capacitor Cst is electrically connected to the first node G, and a second end of the storage capacitor Cst is electrically connected to the second node S. In the process of charging the first node G, the switch transistor T1 simultaneously charges the storage capacitor Cst.

[0089] For example, Figure 4 As shown, the anode of the light emitting device 11 is electrically connected to the second node S, and the cathode of the light emitting device 11 is electrically connected to the second voltage signal terminal ELVSS. The light emitting device 11 is configured to receive the first voltage signal from the second node S and the second voltage signal terminal ELVSS from the second voltage signal line VSS (see Figure 3 )'s second voltage signal cooperates with each other to emit light.

[0090] For example, Figure 4 As shown, the control electrode of the sensing transistor T3 is electrically connected to the second scanning signal terminal G2, the first electrode of the sensing transistor T3 is electrically connected to the second node S, and the second electrode of the sensing transistor T3 is electrically connected to the sensing signal terminal Sense. The sensing transistor T3 is configured to detect the electrical characteristics of the driving transistor T2 in response to the second scanning signal received at the second scanning signal terminal G2 to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the driving transistor T2.

[0091] Here, the sensing signal terminal Sense may provide a reset signal or obtain a sensing signal, wherein the reset signal is used to reset the second node S during the display period, and the sensing signal is used to obtain the threshold voltage of the driving transistor T2 during the blanking period.

[0092] In the related art, the first voltage signal line VSS is directly disposed around the peripheral area of ​​the display panel, and the cathode of the light emitting device extends from the display area to the peripheral area and is connected to the first voltage signal line located in the peripheral area.

[0093] However, for medium and large-sized display panels, the first voltage signal line VSS has a long routing length and a large IR-drop, which results in high energy consumption and rapid temperature rise in the display panel, and cannot meet customer requirements.

[0094] Based on this, in some embodiments of the present invention, in the display substrate 1 provided, refer to Figure 1 and Figure 5 , the peripheral area B includes a first border area B1, a second border area B2, a third border area B3 and a fourth border area B4. Figure 1 and Figure 5 As shown, along the first direction X, the first frame area B1 and the third frame area B3 are located on opposite sides of the display area A. Along the second direction Y, the second frame area B2 and the fourth frame area B4 are located on opposite sides of the display area A. The binding area C is located in the first frame area B1.

[0095] It should be noted that the shapes of the outer contours of the first border area B1, the second border area B2, the third border area B3 and the fourth border area B4 are not limited to rectangles, but also include other shapes. For example, the first border area B1, the second border area B2, the third border area B3 and the fourth border area B4 form a ring, and each border area is a section of the ring. The present disclosure does not make specific limitations here.

[0096] See also Figure 1 , Figure 2 and Figure 5 , the second electrode layer 113 extends from the display area A to the peripheral area B. The first voltage signal line VSS includes a first line VSS1 and a second line VSS2, the first line VSS1 and the second line VSS2 are arranged in parallel, and are at least located in the second frame area B2, the third frame area B3 and the fourth frame area B4, and both ends of the first line VSS1 and the second line VSS2 extend to the first frame area B1, and receive the first voltage signal Vss.

[0097] Among them, the first routing line VSS1 is connected to the second electrode layer 113 on the peripheral side of the display area A (including the second frame area B2, the third frame area B3 and the fourth frame area B4), the second routing line VSS2 is connected to the second electrode layer 113 and / or connected to the first routing line VSS1 in the third frame area B3, and the second routing line VSS2 is separated from the second electrode layer 113 and the first routing line VSS1 in the second frame area B2 and the fourth frame area B4.

[0098] That is, the second wiring VSS2 is located in the third border area B3 and is electrically connected to the first wiring VSS1 by being in electrical contact with the second electrode layer 113 ; or is in direct electrical contact with the first wiring VSS1 .

[0099] In this case, only the portion of the second wiring VSS2 located in the third frame area B3 is directly electrically connected to the second electrode layer 113. In this way, in the process of the first voltage signal Vss being transmitted from the first frame B1 to the third frame area B3 along the second wiring VSS2, the voltage drop generated by the first voltage signal Vss passing through the portion of the second wiring VSS2 located in the second frame area B2 and the fourth frame area B4 is relatively low, that is, the voltage drop of the first voltage signal Vss transmitted to the portion of the second wiring VSS2 located in the third frame area B3 is relatively small; and because VSS2 is electrically connected to VSS1 at the upper frame, the second wiring VSS2 can compensate for the voltage drop of the first wiring VSS1 at the third frame area B3, thereby reducing the voltage drop generated by the first voltage signal line VSS as a whole, thereby reducing energy consumption and slowing down temperature rise.

[0100] The relative position relationship between the first wiring VSS1 and the second wiring VSS2 is not unique.

[0101] For example, Figure 5 As shown, the second routing VSS2 is arranged between the first routing VSS1 and the display area A, that is, the first routing VSS1 surrounds the outside of the second routing VSS2, and the orthographic projection of the second electrode layer 113 on the substrate Sub at least partially overlaps with the orthographic projection of the second routing VSS2 on the substrate Sub; for example, the orthographic projection of the second electrode layer 113 on the substrate Sub completely covers the orthographic projection of the second routing VSS2 on the substrate Sub.

[0102] For example, Figure 6 As shown, the first wiring VSS1 is disposed between the second wiring VSS2 and the display area A, that is, there is a distance between the orthographic projection of the second electrode layer 113 on the substrate Sub and the orthographic projection of the second wiring VSS2 on the substrate Sub.

[0103] For the convenience of explanation, the following takes the above-mentioned second wiring VSS2 being arranged between the first wiring VSS1 and the display area A as an example to schematically illustrate some embodiments of the present disclosure.

[0104] In some embodiments, Figure 5 As shown, the scanning control circuit 200 is arranged between the first voltage signal line VSS and the display area A. In this way, the first voltage signal line VSS can play a role of signal shielding to reduce the electromagnetic interference of other electronic devices on the scanning control circuit 200.

[0105] In other embodiments, Figure 6As shown, the scanning control circuit 200 is disposed between the first wiring VSS1 and the second wiring VSS2. At this time, the first wiring VSS1 and the second wiring VSS2 can both play a role in signal shielding, thereby reducing electromagnetic interference of other electronic devices on the scanning control circuit 200.

[0106] In some embodiments, see Figure 7 and Fig.11 The display substrate 1 further includes at least one conductive layer 140 disposed between the substrate Sub and the second electrode layer 113. The film layers included in the at least one conductive layer 140 can be referred to below, and the disclosure will not elaborate on them here.

[0107] See also Figure 7 and Fig.11 The first routing line VSS1 includes at least one first routing pattern 141, and each first routing pattern 141 is located in one of the at least one conductive layer 140. When the first routing line VSS1 includes a plurality of first routing patterns 141, the plurality of first routing patterns 141 are stacked and connected in a direction perpendicular to the substrate Sub.

[0108] Wherein, in the case where the first wiring VSS1 includes a plurality of first wiring patterns 141, the display substrate 1 includes a plurality of conductive layers 140, and an insulating film layer for electrically isolating the plurality of conductive layers 140 is provided between the plurality of conductive layers 140. The insulating film layer for electrically isolating the plurality of conductive layers 140 can be referred to below, and the present disclosure will not elaborate on this. Here, the plurality of first wiring patterns 141 are stacked and connected along a direction perpendicular to the substrate Sub, and a via hole may be provided between the insulating film layers between the plurality of conductive layers 140, and the plurality of first wiring patterns 141 are stacked at the via hole and electrically connected through contact.

[0109] In some embodiments, Figure 8 , Fig. 9 and Fig.10 As shown, the at least one conductive layer 140 includes a first source-drain conductive layer SD1 and / or a first electrode layer 111 .

[0110] Exemplarily, the at least one conductive layer 140 includes a first source-drain conductive layer SD1 and a first electrode layer 111, wherein the first electrode layer 111 is located between the first source-drain conductive layer SD1 and the second electrode layer 113, and the first source-drain conductive layer SD1 is located on a side of the interlayer insulating layer ILD away from the substrate Sub. Figure 2 The first source-drain conductive layer SD1 includes a source electrode 1212 and a drain electrode 1213 of the thin film transistor 121 .

[0111] like Figure 8 , Fig. 9 and Fig.10As shown, the first wiring VSS1 may include two first wiring patterns 141 stacked in a direction perpendicular to the substrate Sub, the two first wiring patterns 141 are respectively located in the first source and drain conductive layer SD1 and the first electrode layer 113, and the two first wiring patterns 141 are stacked to form an electrical connection.

[0112] It should be noted that, see Figure 8 , Fig. 9 and Fig.10 The display substrate 1 further includes a first planar layer PLN1 disposed between the first source-drain conductive layer SD1 and the first electrode layer 113. At this time, a via hole is disposed on the first planar layer PLN1, and two first wiring patterns 141 are overlapped at the via hole and are electrically connected through contact.

[0113] Each first wiring pattern 141 is at least arranged in the second frame area B2, the third frame area B3 and the fourth frame area B4. For example, each first wiring pattern 141 is arranged in the second frame area B2, the third frame area B3, the fourth frame area B4 and the first frame area B1 outside the binding area C. The first wiring pattern 141 located in the first electrode layer 111 is connected to the second electrode layer 113. In this way, the cross-sectional area of ​​the first wiring VSS1 is larger and the resistance is smaller, which can reduce the IR drop generated by the first wiring VSS1.

[0114] It should be noted that the light-emitting functional layer 112 is only arranged in the display area A, and the pixel definition layer PDL is provided with an avoidance opening at the first wiring pattern 141 corresponding to the first electrode layer 111, so that the first wiring pattern 141 located in the first electrode layer 111 can directly contact and form an electrical connection with the second electrode layer 113.

[0115] In some embodiments, the display substrate 1 further includes a second source-drain conductive layer SD2 , and the at least one conductive layer 140 includes at least one of the first source-drain conductive layer SD1 , the second source-drain conductive layer SD2 , and the first electrode layer 111 .

[0116] For example, Figure 8 , Fig. 9 and Fig.10 As shown, the at least one conductive layer 140 includes a first source-drain conductive layer SD1, a second source-drain conductive layer SD2 and a first electrode layer 111, and the second source-drain conductive layer SD2 is located between the first source-drain conductive layer SD1 and the first electrode layer 111. The second source-drain conductive layer SD2 includes a connecting electrode 150 (see Figure 2 ), initialization signal line 151 (see Figure 2 ) and at least one of the auxiliary signal lines, but the present disclosure is not limited thereto.

[0117] See also Figure 11 to Figure 14The first routing line VSS1 includes three first routing patterns 141 stacked in a direction perpendicular to the substrate Sub. The three first routing patterns 141 are respectively located in the first source-drain conductive layer SD1, the second source-drain conductive layer SD2 and the first electrode layer 113, and the three first routing patterns 141 are stacked to form an electrical connection.

[0118] It should be noted that, see Figure 11 to Figure 14 , the display substrate 1 also includes a first flat layer PLN1 disposed between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2, and a second flat layer PLN2 disposed between the second source-drain conductive layer SD2 and the first electrode 111. At this time, vias are provided on both the first flat layer PLN1 and the second flat layer PLN2, and the vias provided on the first flat layer PLN1 at least partially overlap with the vias provided on the second flat layer PLN2, for example, completely overlap. In this way, the three first wiring patterns 141 can be overlapped at the vias and electrically connected through contact.

[0119] Each first wiring pattern 141 is at least arranged in the second frame area B2, the third frame area B3 and the fourth frame area B4. For example, each first wiring pattern 141 is arranged in the second frame area B2, the third frame area B3, the fourth frame area B4 and the first frame area B1 outside the binding area C. The first wiring pattern 141 located in the first electrode layer 111 is connected to the second electrode layer 113. In this way, the cross-sectional area of ​​the first wiring VSS1 is larger and the resistance is smaller, which can reduce the IR drop generated by the first wiring VSS1.

[0120] It should be noted that the light-emitting functional layer 112 is only arranged in the display area A, and the pixel definition layer PDL is provided with an avoidance opening at the first wiring pattern 141 corresponding to the first electrode layer 111, so that the first wiring pattern 141 located in the first electrode layer 111 can directly contact and form an electrical connection with the second electrode layer 113.

[0121] See also Figure 7 and Fig.11 The second trace VSS2 includes at least one second trace pattern 142, each second trace pattern 142 is located in one of the at least one conductive layer 140. When the second trace VSS2 includes a plurality of second trace patterns 142, the plurality of second trace patterns 142 are stacked and connected in a direction perpendicular to the substrate Sub.

[0122] Wherein, in the case where the second wiring VSS2 includes a plurality of second wiring patterns 142, the display substrate 1 includes a plurality of conductive layers 140, and an insulating film layer for electrically isolating the plurality of conductive layers 140 is provided between the plurality of conductive layers 140. The insulating film layer for electrically isolating the plurality of conductive layers 140 can be referred to below, and the present disclosure will not elaborate on this. Here, the plurality of second wiring patterns 142 are stacked and connected along a direction perpendicular to the substrate Sub, and a via hole may be provided between the insulating film layers between the plurality of conductive layers 140, and the plurality of second wiring patterns 142 are stacked at the via hole and electrically connected by contact.

[0123] In some embodiments, Figure 8 , Fig. 9 and Fig.10 As shown, the at least one conductive layer 140 includes a first source-drain conductive layer SD1 and / or a first electrode layer 111 .

[0124] Exemplarily, the at least one conductive layer 140 includes a first source-drain conductive layer SD1 and a first electrode layer 111, wherein the first electrode layer 111 is located between the first source-drain conductive layer SD1 and the second electrode layer 113, and the first source-drain conductive layer SD1 is located on a side of the interlayer insulating layer ILD away from the substrate Sub. Figure 2 The first source-drain conductive layer SD1 includes a source electrode 1212 and a drain electrode 1213 of the thin film transistor 121 .

[0125] See also Figure 8 and Fig.10 The second routing line VSS2 may include two second routing patterns 142 stacked in a direction perpendicular to the substrate Sub, the two second routing patterns 142 are respectively located in the first source-drain conductive layer SD1 and the first electrode layer 113, and the two second routing patterns 142 are stacked to form an electrical connection.

[0126] It should be noted that, see Figure 8 and Fig.10 The display substrate 1 further includes a first planar layer PLN1 disposed between the first source-drain conductive layer SD1 and the first electrode layer 113. At this time, a via hole is disposed on the first planar layer PLN1, and two second wiring patterns 142 are overlapped at the via hole and are electrically connected through contact.

[0127] Among them, the second routing pattern 142 located in the first source and drain conductive layer SD1 is at least arranged in the second border area B2, the third border area B3 and the fourth border area B4. For example, the second routing pattern 142 located in the first source and drain conductive layer SD1 is arranged in the second border area B2, the third border area B3, the fourth border area B4 and the area outside the binding area C in the first border area B1.

[0128] The second wiring pattern 142 located at the first electrode layer 111 is at least arranged in the third border area B3, for example, the second wiring pattern 142 located at the first electrode layer 111 is only arranged in the third border area B3. Among them, the second wiring pattern 142 located at the first electrode layer 111 is connected to the second electrode layer 113 in the third border area B3. In this way, the cross-sectional area of ​​the second wiring VSS2 located in the third border area B3 is larger and the resistance is smaller, which can reduce the IR drop generated by the second wiring VSS2.

[0129] It should be noted that the light-emitting functional layer 112 is only arranged in the display area A, and the pixel definition layer PDL is provided with an avoidance opening corresponding to the second wiring pattern 142 located on the first electrode layer 111, so that the second wiring pattern 142 located on the first electrode layer 111 can directly contact the second electrode layer 113 in the third frame area B3 to form an electrical connection.

[0130] See also Figure 8 and Fig. 9 The second wiring VSS2 may also include only one second wiring pattern 142 , and the second wiring pattern 142 is located in the first source-drain conductive layer SD1 .

[0131] Among them, the second wiring pattern 142 is at least arranged in the second border area B2, the third border area B3 and the fourth border area B4. For example, the second wiring pattern 142 located in the first source and drain conductive layer SD1 is arranged in the second border area B2, the third border area B3, the fourth border area B4 and the area outside the binding area C in the first border area B1. The second wiring pattern 142 is connected to the first wiring pattern 141 located in the first source and drain conductive layer SD1 in the third border area B3. In this way, the preparation process of the second wiring VSS2 is simple and the preparation cost is low.

[0132] In some embodiments, the display substrate 1 further includes a second source-drain conductive layer SD2 , and the at least one conductive layer 140 includes at least one of the first source-drain conductive layer SD1 , the second source-drain conductive layer SD2 , and the first electrode layer 111 .

[0133] For example, Figure 8 , Fig. 9 and Fig.10 As shown, the at least one conductive layer 140 includes a first source-drain conductive layer SD1, a second source-drain conductive layer SD2 and a first electrode layer 111, and the second source-drain conductive layer SD2 is located between the first source-drain conductive layer SD1 and the first electrode layer 111. The second source-drain conductive layer SD2 includes a connecting electrode 150 (see Figure 2 ), initialization signal line 151 (see Figure 2 ) and at least one of the auxiliary signal lines, but the present disclosure is not limited thereto.

[0134] See also Fig.11 , Fig.12 and Fig.13 The second routing VSS2 may include three second routing patterns 142 stacked in a direction perpendicular to the substrate Sub, the three second routing patterns 142 are respectively located in the first source-drain conductive layer SD1, the second source-drain conductive layer SD2 and the first electrode layer 113, and the three second routing patterns 142 are stacked to form an electrical connection.

[0135] It should be noted that, see Fig.11 , Fig.12 and Fig.13 , the display substrate 1 further includes a first flat layer PLN1 disposed between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2, and a second flat layer PLN2 disposed between the second source-drain conductive layer SD2 and the first electrode 111. At this time, vias are disposed on both the first flat layer PLN1 and the second flat layer PLN2, and the vias disposed on the first flat layer PLN1 at least partially overlap with the vias disposed on the second flat layer PLN2. In this way, the three second wiring patterns 142 can be overlapped at the vias and electrically connected through contact.

[0136] Among them, the second routing pattern 142 located in the first source and drain conductive layer SD1, and the second routing pattern 142 located in the second source and drain conductive layer SD2, are both arranged at least in the second border area B2, the third border area B3 and the fourth border area B4. For example, the second routing pattern 142 located in the first source and drain conductive layer SD1, and the second routing pattern 142 located in the second source and drain conductive layer SD2, are both arranged in the second border area B2, the third border area B3, the fourth border area B4 and the area outside the binding area C in the first border area B1.

[0137] The second wiring pattern 142 located at the first electrode layer 111 is at least arranged in the third border area B3, for example, the second wiring pattern 142 located at the first electrode layer 111 is only arranged in the third border area B3. Among them, the second wiring pattern 142 located at the first electrode layer 111 is connected to the second electrode layer 113 in the third border area B3. In this way, the cross-sectional area of ​​the second wiring VSS2 located in the third border area B3 is larger and the resistance is smaller, which can reduce the IR drop generated by the second wiring VSS2.

[0138] It should be noted that the light-emitting functional layer 112 is only arranged in the display area A, and the pixel definition layer PDL is provided with an avoidance opening corresponding to the second wiring pattern 142 located on the first electrode layer 111, so that the second wiring pattern 142 located on the first electrode layer 111 can directly contact the second electrode layer 113 in the third frame area B3 to form an electrical connection.

[0139] See also Fig.11 and Fig.14 The second wiring VSS2 may further include two second wiring patterns 142 stacked in a direction perpendicular to the substrate Sub, and the two second wiring patterns 142 are respectively located in the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2.

[0140] Each second wiring pattern 142 is at least arranged in the second border area B2, the third border area B3 and the fourth border area B4. The first wiring pattern 141 and the second wiring pattern 142 located in the first source and drain conductive layer SD1 are connected in the third border area B3; and / or the first wiring pattern 141 and the second wiring pattern 142 located in the second source and drain conductive layer SD2 are connected in the third border area B3.

[0141] As described above, in the first wiring VSS1 and the second wiring VSS2, at least one first wiring pattern 141 and at least one second wiring pattern 142 may be located in the same conductive layer 140. In this case, refer to Figure 7 and Figure 8 In the second frame area B2 and the fourth frame area B4, the first wiring pattern 141 and the second wiring pattern 142 located in the same conductive layer 140 are arranged alternately. Figure 7 and Fig. 9 In the third border area B3, the first wiring pattern 141 and the second wiring pattern 142 located in the same conductive layer 140 are connected. Figure 7 and Fig.10 In the third border area B3 , the first routing pattern 141 and the second routing pattern 142 located in the same conductive layer 140 are arranged alternately, and a second routing pattern 142 farthest from the substrate Sub in the second routing VSS2 is connected to the second electrode layer 113 .

[0142] In the third border area B3 , the set line segment 160 of the second wiring VSS2 is connected to the second electrode layer 113 and / or to the first wiring VSS1 .

[0143] In some embodiments, Figure 5 and Fig.13 As shown, the length of the line segment 160 is set to be equal to the length of the portion of the second line VSS2 located in the third border area B3. In this case, the area where the second line VSS2 is connected to the second electrode layer 113 and / or the first line VSS1 is larger and the resistance is smaller. In other embodiments, such as Figure 7 As shown, the second wiring VSS2 includes a plurality of set line segments 160 , and the plurality of set line segments 160 are arranged at intervals along the third border area B3 .

[0144] In some embodiments, Figure 5As shown, the first wiring VSS1 and the second wiring VSS2 are connected to different first power pins 131 in the binding area C respectively.

[0145] In other embodiments, Figure 1 and Figure 7 As shown, the display substrate 1 further includes a power connection line 110 disposed in the first frame area B1 , the first wiring VSS1 and the second wiring VSS2 are connected to the power connection line 110 in the first binding area B1 , and the power connection line 110 is connected to the first power pin 131 .

[0146] In order to prove that the IR drop of the first voltage signal line VSS of the above-mentioned display substrate 1 is low, the performance test of the display substrate 1 obtained in the embodiment of the present disclosure is carried out below. The following description is only used to explain the beneficial effects of the display substrate 1 provided by the embodiment of the present disclosure, and is not intended to limit the specific parameters of the display substrate 1.

[0147] The display substrate 1 with a size of 15 inches in the above embodiment and the display substrate 1 with a size of 15 inches in the related art were compared and tested, and the test results are shown in Table 1.

[0148] Table 1

[0149] Related technologies Example 1 Example 2 VSS1 width / μm 2300 1900 1500 VSS2 width / μm 0 400 800 VSS IR drop / V 1.92 1.83 1.71

[0150] It can be seen from Table 1 that, when the total width of the first voltage signal line VSS remains unchanged, compared with the related art, the IR drop of the first voltage signal line VSS in Example 1 is reduced by 0.09 V; compared with the related art, the IR drop of the first voltage signal line VSS in Example 2 is reduced by 0.21 V. Therefore, the display substrate 1 provided in the embodiment of the present disclosure can reduce the IR drop of the first voltage signal line VSS, thereby reducing the energy consumption of the display panel 10 and slowing down the temperature rise of the display panel 10.

[0151] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, It is characterized in that include: A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first frame area, a second frame area, a third frame area and a fourth frame area; the first frame area and the third frame area are located on two opposite sides of the display area in a first direction; the second frame area and the fourth frame area are located on two opposite sides of the display area in a second direction; the first direction is perpendicular to the second direction; A second electrode layer is disposed on the substrate; the second electrode layer extends from the display area to the peripheral area; A first voltage signal line, comprising a first routing line and a second routing line; the first routing line and the second routing line are arranged in parallel and are at least located in the second frame area, the third frame area and the fourth frame area, and both ends of the first routing line and the second routing line extend to the first frame area to receive a first voltage signal; Among them, the first routing is connected to the second electrode layer in the second border area, the third border area and the fourth border area, and the first routing is in electrical contact with the second electrode layer; the second routing is connected to the second electrode layer and / or connected to the first routing in the third border area, and the second routing is separated from the second electrode layer and the first routing in the second border area and the fourth border area.

2. The display substrate according to claim 1, It is characterized in that The display substrate further comprises at least one conductive layer disposed between the substrate and the second electrode layer; The first routing line includes at least one first routing pattern, each first routing pattern is located in one of the at least one conductive layer; in the case where the first routing line includes a plurality of first routing patterns, the plurality of first routing patterns are stacked and connected along a direction perpendicular to the substrate; The second routing includes at least one second routing pattern, each second routing pattern is located in one of the at least one conductive layer; when the second routing includes multiple second routing patterns, the multiple second routing patterns are stacked and connected along a direction perpendicular to the substrate.

3. The display substrate according to claim 2, It is characterized in that Among the first routing lines and the second routing lines, at least one first routing pattern and at least one second routing pattern are located in the same conductive layer; In the second frame area and the fourth frame area, the first wiring pattern and the second wiring pattern located in the same conductive layer are arranged alternately; In the third border area, the first wiring pattern and the second wiring pattern located in the same conductive layer are connected; Alternatively, the first routing pattern and the second routing pattern located in the same conductive layer are arranged at intervals, and a second routing pattern in the second routing that is farthest from the substrate is connected to the second electrode layer.

4. The display substrate according to claim 3, It is characterized in that The at least one conductive layer includes a first source-drain conductive layer and a first electrode layer, and the first electrode layer is located between the first source-drain conductive layer and the second electrode layer.

5. The display substrate according to claim 4, It is characterized in that The first routing includes two first routing patterns, which are respectively located in the first source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second frame area, the third frame area and the fourth frame area; the first routing pattern located in the first electrode layer is connected to the second electrode layer; The second routing includes two second routing patterns, which are respectively located in the first source and drain conductive layer and the first electrode layer. The second routing pattern located in the first source and drain conductive layer is at least arranged in the second border area, the third border area and the fourth border area; the second routing pattern located in the first electrode layer is at least arranged in the third border area and is connected to the second electrode layer.

6. The display substrate according to claim 4, It is characterized in that The first routing includes two first routing patterns, which are respectively located in the first source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second frame area, the third frame area and the fourth frame area; The second routing includes a second routing pattern located in the first source-drain conductive layer; the second routing pattern is at least arranged in the second border area, the third border area and the fourth border area, and the second routing pattern is connected to the first routing pattern located in the first source-drain conductive layer in the third border area.

7. The display substrate according to claim 4, It is characterized in that The at least one conductive layer further includes a second source-drain conductive layer, and the second source-drain conductive layer is located between the first source-drain conductive layer and the first electrode layer.

8. The display substrate according to claim 7, It is characterized in that The first routing includes three first routing patterns, which are respectively located in the first source-drain conductive layer, the second source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second frame area, the third frame area and the fourth frame area; The second routing includes three second routing patterns, which are respectively located in the first source-drain conductive layer, the second source-drain conductive layer and the first electrode layer; the second routing pattern located in the first source-drain conductive layer and the second routing pattern located in the second source-drain conductive layer are both at least arranged in the second border area, the third border area and the fourth border area; the second routing pattern located in the first electrode layer is at least arranged in the third border area and is connected to the second electrode layer.

9. The display substrate according to claim 7, It is characterized in that The first routing includes three first routing patterns, which are respectively located in the first source-drain conductive layer, the second source-drain conductive layer and the first electrode layer; each first routing pattern is at least arranged in the second border area, the third border area and the fourth border area; the first routing pattern located in the first electrode layer is connected to the second electrode layer; The second routing includes two second routing patterns, which are respectively located in the first source-drain conductive layer and the second source-drain conductive layer; each second routing pattern is at least arranged in the second frame area, the third frame area and the fourth frame area; The first routing pattern and the second routing pattern located in the first source-drain conductive layer are connected in the third frame area, and / or the first routing pattern and the second routing pattern located in the second source-drain conductive layer are connected in the third frame area.

10. The display substrate according to any one of claims 1 to 9, It is characterized in that In the third border area, a set line segment of the second routing line is connected to the second electrode layer and / or to the first routing line; The length of the set line segment is equal to the length of a portion of the second routing line located in the third border area; or, the second routing line includes a plurality of set line segments, and the plurality of set line segments are arranged at intervals along the third border area.

11. The display substrate according to any one of claims 1 to 9, It is characterized in that The first frame area includes a binding area, and the display substrate further includes: At least one first power pin is arranged in the binding area; the first power pin is configured to transmit a first voltage signal; and the first voltage signal line is electrically connected to the first power pin.

12. The display substrate according to claim 11, It is characterized in that The first wiring and the second wiring are respectively connected to different first power pins in the binding area; Alternatively, the display substrate further includes a power connection line disposed in the first frame area, the first wiring and the second wiring are connected to the power connection line in the first frame area, and the power connection line is connected to the first power pin.

13. The display substrate according to any one of claims 1 to 9, It is characterized in that The second wiring is arranged between the first wiring and the display area, and the orthographic projection of the second electrode layer on the substrate at least partially overlaps with the orthographic projection of the second wiring on the substrate; Alternatively, the first wiring is arranged between the second wiring and the display area, and there is a distance between the orthographic projection of the second electrode layer on the substrate and the orthographic projection of the second wiring on the substrate.

14. The display substrate according to claim 1, It is characterized in that The display substrate further comprises at least one scanning control circuit disposed in the peripheral area; The at least one scan control circuit is located between the first voltage signal line and the display area, or between the first wiring and the second wiring.

15. A display device, It is characterized in that include: The display substrate according to any one of claims 1 to 14; A packaging layer covers the light-emitting side of the display substrate.

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