Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises: sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one sub-pixel comprises: a drive circuit; the drive circuit comprises: a transistor and a storage capacitor; the display substrate comprises: a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked on the substrate; a power line; the power line comprises: at least one interconnected sub-power line, the sub-power line is connected with the sub-pixel and located in the area where the sub-pixel is located, and the at least one sub-power line comprises at least three power supply parts: a first power supply part, a second power supply part and a third power supply part; the second power supply part connects the first power supply part and the third power supply part; the data line is arranged in parallel with the extension direction of the first power supply part and the third power supply part.

Description

[0001] This application is a divisional application of the application with the application date of November 7, 2019, the application number of 201911082352.5, and the application name of "a display substrate, a manufacturing method thereof, and a display device". TECHNICAL FIELD

[0002] The present document relates to the field of display technology, in particular to a display substrate and a display device. BACKGROUND

[0003] An organic light-emitting diode (OLED) display substrate is a display substrate different from a traditional liquid crystal display (LCD). The OLED display substrate has the advantages of active light-emitting, good temperature characteristics, small power consumption, fast response, bendability, ultra-thinness, and low cost. Therefore, the OLED display substrate has become one of the important development directions of a new generation of display devices and has attracted more and more attention.

[0004] In order to realize high-frequency driving of the OLED display substrate, a double-data-line OLED display substrate is proposed in the related art, that is, the same column of pixels is connected with two data lines. However, the OLED display substrate in the related art can realize high-frequency driving, but the resolution is generally low, which cannot meet the market demand for high resolution of display devices. SUMMARY

[0005] The present application provides a display substrate and a display device, which can improve the resolution of the OLED display substrate.

[0006] In a first aspect, the present disclosure provides a display substrate, comprising: a plurality of sub-pixels arranged in an array, a plurality of data lines, and a plurality of power lines; at least one sub-pixel comprises: a driving circuit; the driving circuit comprises: a transistor and a storage capacitor; the storage capacitor comprises: a first electrode and a second electrode arranged oppositely; the display substrate comprises: a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially stacked on the substrate;

[0007] The semiconductor layer comprises: an active layer of the transistor in at least one driving circuit;

[0008] The first metal layer comprises: the first electrode of the storage capacitor;

[0009] The second metal layer comprises: the second electrode of the storage capacitor;

[0010] The power line comprises at least one sub-power line connected to each other, the sub-power line being connected to a sub-pixel and located in a region where the sub-pixel is located, and the at least one sub-power line comprises at least three power parts, i.e., a first power part, a second power part, and a third power part; the second power part is connected to the first power part and the third power part; and the data line is arranged in parallel with the extension direction of the first power part and the third power part.

[0011] In some possible implementation manners, the data line is located on the fourth metal layer.

[0012] In some possible implementation manners, for the at least one driving circuit, the second electrode of the storage capacitor is arranged to output a write power signal, and the power signal is a signal of a sub-power line.

[0013] In some possible implementation manners, the display substrate further comprises a fourth insulating layer and a fifth insulating layer, the fourth insulating layer is arranged between the third metal layer and the fourth metal layer, the fifth insulating layer is arranged on a side of the fourth metal layer away from the base, and the fourth metal layer further comprises a connection electrode.

[0014] The fifth insulating layer is provided with a via hole exposing the connection electrode, and the fourth insulating layer is provided with a via hole exposing the third metal layer; and a normal projection of the via hole exposing the third metal layer on the base at least partially overlaps a normal projection of the connection electrode on the base.

[0015] In some possible implementation manners, the extension direction of the connection electrode is arranged in parallel with the extension direction of the first power part.

[0016] In some possible implementation manners, the extension direction of the virtual connection line of the via hole exposing the third metal layer and the via hole exposing the connection electrode is parallel to the extension direction of the data line.

[0017] In some possible implementation manners, the normal projection of the via hole exposing the connection electrode on the base at least partially overlaps the normal projection of the via hole exposing the third metal layer on the base.

[0018] In some possible implementation manners, a virtual extension line of the first power part passes through the via hole exposing the connection electrode.

[0019] In some possible implementation manners, a virtual extension line of the first power part passes through the via hole exposing the third metal layer.

[0020] In some possible implementation manners, the display substrate further includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the first insulating layer, the second insulating layer and the third insulating layer are arranged between the third metal layer and the semiconductor layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer.

[0021] The fourth insulating layer is provided with a via hole exposing the third metal layer, the data line is connected with the third metal layer through the via hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.

[0022] In some possible implementation manners, a normal projection of the via hole exposing the third metal layer on the substrate at least partially overlaps with a normal projection of the via hole exposing the semiconductor layer on the substrate.

[0023] In some possible implementation manners, a virtual extension line of the third power supply part passes through the via hole exposing the semiconductor layer.

[0024] In some possible implementation manners, a virtual extension line of the third power supply part passes through the via hole exposing the third metal layer.

[0025] In some possible implementation manners, an included angle between the first power supply part and the second power supply part is greater than or equal to 90 degrees and less than 180 degrees.

[0026] An included angle between the second power supply part and the third power supply part is greater than or equal to 90 degrees and less than 180 degrees.

[0027] In some possible implementation manners, an average width of the first power supply part is greater than or equal to an average width of the second power supply part.

[0028] An average width of the second power supply part is greater than or equal to an average width of the third power supply part.

[0029] An average width of the third power supply part is greater than or equal to an average width of the data line.

[0030] In some possible implementation manners, active layers of adjacent sub-pixels arranged along a first direction or a second direction are mirror-symmetrical, the first direction is perpendicular to the second direction, and the second direction is an extension direction of the data line.

[0031] In some possible implementation manners, the driving circuit includes a second transistor, and a normal projection of the first power supply part on the substrate at least partially overlaps with a normal projection of a part of the second transistor on the substrate.

[0032] In some possible implementation manners, the driving circuit comprises a first transistor, and a projection of the second power supply portion on the base at least partially overlaps with a projection of a part of the first transistor on the base.

[0033] In some possible implementation manners, a projection of the second power supply portion on the base at least partially overlaps with a projection of a part of the second electrode on the base.

[0034] In some possible implementation manners, the first metal layer further comprises a gate line, and a projection of the second power supply portion on the base at least partially overlaps with a projection of the gate line on the base.

[0035] In some possible implementation manners, a projection of the third power supply portion on the base at least partially overlaps with a projection of a part of at least one transistor on the base.

[0036] In some possible implementation manners, the driving circuit comprises a fifth transistor, and a projection of the third power supply portion on the base at least partially overlaps with a projection of a part of the fifth transistor on the base.

[0037] In some possible implementation manners, the driving circuit comprises a sixth transistor, and a projection of the third power supply portion on the base at least partially overlaps with a projection of a part of the sixth transistor on the base.

[0038] In a second aspect, the present disclosure further provides a display device, comprising the display substrate.

[0039] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. Other advantages of the present application will be realized and attained by those of ordinary skill in the art, including studying the following description and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate embodiments of the present application and are used to explain the technical solutions of the present application, but do not constitute limitations on the technical solutions of the present application.

[0041] Figure 1 A structural schematic diagram of a display substrate provided by an embodiment of the present application is shown in the following figure;

[0042] Figure 2 A side view of a sub-pixel in a display substrate provided by an embodiment of the present application is shown in the following figure;

[0043] Figure 3 A top view of a sub-pixel in a display substrate provided by an embodiment of the present application is shown in the following figure;

[0044] Figure 4A Equivalent circuit diagram of the driving circuit provided for the embodiment of the present application;

[0045] Figure 4B Timing diagram of the driving circuit provided for the embodiment of the present application;

[0046] Figure 5 One top view of a plurality of sub-pixels in the display substrate provided for the embodiment of the present application;

[0047] Figure 6A One top view of a sub-pixel corresponding to the first embodiment;

[0048] Figure 6B Another top view of a sub-pixel corresponding to the first embodiment;

[0049] Figure 7A Top view of the second metal layer corresponding to the first embodiment;

[0050] Figure 7B Top view of the third metal layer corresponding to the first embodiment;

[0051] Figure 8A One top view of a sub-pixel corresponding to the second embodiment;

[0052] Figure 8B Another top view of a sub-pixel corresponding to the second embodiment;

[0053] Figure 9A Top view of the second metal layer corresponding to the second embodiment;

[0054] Figure 9B Top view of the third metal layer corresponding to the second embodiment;

[0055] Figure 10 Another top view of a plurality of sub-pixels in the display substrate provided for the embodiment of the present application;

[0056] Figure 11 Flow chart of the manufacturing method of the display substrate provided for the embodiment of the present application;

[0057] Figure 12 First manufacturing schematic diagram of the display substrate provided for the embodiment of the present application;

[0058] Figure 13 Second manufacturing schematic diagram of the display substrate provided for the embodiment of the present application;

[0059] Figure 14A One third manufacturing schematic diagram of the display substrate provided for the embodiment of the present application;

[0060] Figure 14BAnother third manufacturing schematic view of the display substrate provided by the embodiment of the present application is shown in FIG. 6B.

[0061] Figure 15A A fourth manufacturing schematic view of the display substrate provided by the embodiment of the present application is shown in FIG. 7B.

[0062] Figure 15B Another fourth manufacturing schematic view of the display substrate provided by the embodiment of the present application is shown in FIG. 8B.

[0063] Figure 16A A fifth manufacturing schematic view of the display substrate provided by the embodiment of the present application is shown in FIG. 9B.

[0064] Figure 16B Another fifth manufacturing schematic view of the display substrate provided by the embodiment of the present application is shown in FIG. 10B. DETAILED DESCRIPTION

[0065] The present application describes a number of embodiments, but the description is exemplary rather than limiting and it will be apparent to those of ordinary skill in the art that numerous more embodiments and implementations are possible within the scope of the embodiments described in the present application. Although a number of possible combinations of features have been set forth in the appended figures and discussed above, many other combinations of the disclosed features are possible. Unless specifically intended otherwise, any feature or element of any embodiment can be used in combination with any other feature or element of any other embodiment, or in combination with any other feature or element of the same embodiment.

[0066] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional features or elements to form unique inventive solutions that are within the scope of the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution that is within the scope of the claims. Thus, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any appropriate combination. Accordingly, the embodiments are not to be limited by other than in accordance with the restrictions shown and described in the claims and their equivalents. Moreover, various modifications and changes can be made within the scope of the claims.

[0067] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the performance of certain steps, the method or process is not limited to the order of steps presented nor to performing some specific steps before other specific steps, unless the application requires that the steps be performed in that order or that some specific steps be performed before other specific steps, as will be understood by those skilled in the art. Therefore, the particular order presented in the specification of steps should not be construed as limitations on the claims. Additionally, the claims should not be limited to the steps presented in the specification, as some of the steps presented in the specification can be combined or separated into other steps or performed in other orders, as will be understood by those skilled in the art.

[0068] Unless otherwise defined, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in the description of the application herein should be interpreted in accordance with the rules of grammar, except to the extent that it is understood that the term in question is intended to have a special meaning, which special meaning was intended by the person who used the term in that particular passage. The use of "first", "second", and like designations is not intended to denote any order of importance, quantity, or sequence, but is simply intended to distinguish one element from another. The use of "comprise", "include", "have", and like terms is not intended to exclude other elements or steps, but rather to "comprise", "include", "have" at least the elements or steps listed. The use of "connected", "coupled", and like terms is not intended to be limited to a direct or physical connection or coupling, but rather can include an electrical connection or coupling, whether direct or indirect.

[0069] Embodiments of the present disclosure provide a display substrate, comprising: a plurality of sub-pixels arranged in an array, a plurality of data lines, and a plurality of power lines; at least one sub-pixel comprises: a driving circuit; the driving circuit comprises: a transistor and a storage capacitor; the storage capacitor comprises: a first electrode and a second electrode arranged oppositely; the display substrate comprises: a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially stacked on the substrate;

[0070] The semiconductor layer comprises: an active layer of the transistor in the at least one driving circuit;

[0071] The first metal layer comprises: the first electrode of the storage capacitor;

[0072] The second metal layer comprises: the second electrode of the storage capacitor;

[0073] The power line comprises at least one sub-power line connected to each other, the sub-power line being connected to a sub-pixel and located in a region where the sub-pixel is located, and the at least one sub-power line comprises at least three power parts, i.e., a first power part, a second power part, and a third power part; the second power part is connected to the first power part and the third power part; and the data line is arranged in parallel with the extension direction of the first power part and the third power part.

[0074] In an example embodiment, the data line is located on the fourth metal layer.

[0075] In an example embodiment, for at least one driving circuit, the second electrode of the storage capacitor is arranged to output a write power signal, and the power signal is a signal of a sub-power line.

[0076] In an example embodiment, the display substrate further comprises a fourth insulating layer and a fifth insulating layer, the fourth insulating layer is arranged between the third metal layer and the fourth metal layer, and the fifth insulating layer is arranged on a side of the fourth metal layer away from the substrate, and the fourth metal layer further comprises a connection electrode.

[0077] The fifth insulating layer is provided with a via hole exposing the connection electrode, and the fourth insulating layer is provided with a via hole exposing the third metal layer; and the orthographic projection of the via hole exposing the third metal layer on the substrate at least partially overlaps the orthographic projection of the connection electrode on the substrate.

[0078] In an example embodiment, the extension direction of the connection electrode is arranged in parallel with the extension direction of the first power part.

[0079] In an example embodiment, the extension direction of the via hole exposing the third metal layer and the dummy connection line of the via hole exposing the connection electrode is parallel to the extension direction of the data line.

[0080] In an example embodiment, the orthographic projection of the via hole exposing the connection electrode on the substrate at least partially overlaps the orthographic projection of the via hole exposing the third metal layer on the substrate.

[0081] In an example embodiment, a virtual extension line of the first power part passes through the via hole exposing the connection electrode.

[0082] In an example embodiment, a virtual extension line of the first power part passes through the via hole exposing the third metal layer.

[0083] In an example embodiment, the display substrate further comprises a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the first insulating layer, the second insulating layer and the third insulating layer are arranged between the third metal layer and the semiconductor layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer.

[0084] The fourth insulating layer is provided with a via hole exposing the third metal layer, the data line is connected with the third metal layer through the via hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.

[0085] In an example embodiment, the orthographic projection of the via hole exposing the third metal layer on the substrate at least partially overlaps with the orthographic projection of the via hole exposing the semiconductor layer on the substrate.

[0086] In an example embodiment, the virtual extension line of the third power supply part passes through the via hole exposing the semiconductor layer.

[0087] In an example embodiment, the virtual extension line of the third power supply part passes through the via hole exposing the third metal layer.

[0088] In an example embodiment, the included angle between the first power supply part and the second power supply part is greater than or equal to 90 degrees and less than 180 degrees.

[0089] The included angle between the second power supply part and the third power supply part is greater than or equal to 90 degrees and less than 180 degrees.

[0090] In an example embodiment, the average width of the first power supply part is greater than or equal to the average width of the second power supply part.

[0091] The average width of the second power supply part is greater than or equal to the average width of the third power supply part.

[0092] The average width of the third power supply part is greater than or equal to the average width of the data line.

[0093] In an example embodiment, the active layers of adjacent sub-pixels arranged in a first direction or a second direction are mirror-symmetric, the first direction is perpendicular to the second direction, and the second direction is the extension direction of the data line.

[0094] In an example embodiment, the driving circuit comprises a second transistor, and the orthographic projection of the first power supply part on the substrate at least partially overlaps with the orthographic projection of a part of the second transistor on the substrate.

[0095] In an example embodiment, the drive circuit includes a first transistor, and a projection of the second power supply portion on the base at least partially overlaps with a projection of a portion of the first transistor on the base.

[0096] In an example embodiment, a projection of the second power supply portion on the base at least partially overlaps with a projection of a portion of the second electrode on the base.

[0097] In an example embodiment, the first metal layer further includes a gate line, and a projection of the second power supply portion on the base at least partially overlaps with a projection of the gate line on the base.

[0098] In an example embodiment, a projection of the third power supply portion on the base at least partially overlaps with a projection of a portion of at least one transistor on the base.

[0099] In an example embodiment, the drive circuit includes a fifth transistor, and a projection of the third power supply portion on the base at least partially overlaps with a projection of a portion of the fifth transistor on the base.

[0100] In an example embodiment, the drive circuit includes a sixth transistor, and a projection of the third power supply portion on the base at least partially overlaps with a projection of a portion of the sixth transistor on the base.

[0101] Some embodiments of the present application provide a display substrate, Figure 1 A structural schematic diagram of the display substrate provided by the embodiments of the present application is shown in FIG. 1. Figure 2 A side view of one sub-pixel in the display substrate provided by the embodiments of the present application is shown in FIG. 2. Figure 3 A top view of one sub-pixel in the display substrate provided by the embodiments of the present application is shown in FIG. 3. Figures 1-3 As shown in the drawings, the display substrate provided by the embodiments of the present application is provided with a gate line G, a data line D, a power supply line VDD, a reset signal line Reset, an emission control line EM, an initial signal line Vinit, and a plurality of sub-pixels P. Each sub-pixel includes a light emitting device and a drive circuit for driving the light emitting device to emit light. The drive circuit includes a plurality of transistors and a storage capacitor. The display substrate includes a base 10, and a semiconductor layer 20, a first metal layer 30, a second metal layer 40, a third metal layer 50, a fourth metal layer 60, and a fifth metal layer 70 which are disposed on the base 10 and insulated from each other.

[0102] In this embodiment, the semiconductor layer 20 includes: an active layer of multiple transistors; the first metal layer 30 includes: a gate line G, a light-emitting control line EM, a reset signal line Reset, a first electrode C1 of a storage capacitor, and the gate electrode of multiple transistors; the second metal layer 40 includes: an initial signal line Vinit and a second electrode C2 of a storage capacitor; the third metal layer 50 includes: source and drain electrodes of multiple transistors; the fourth metal layer 60 includes: a data line D and a power supply line VDD; and the fifth metal layer 70 includes: the anode of a light-emitting device.

[0103] Specifically, such as Figure 1 As shown, the display substrate in this embodiment is provided with M rows and N columns of sub-pixels, N columns of data lines D1 to DN, N columns of power lines VDD1 to VDDN, M rows of gate lines G1 to GM, M-1 rows of light emission control lines EM1 to EMM-1, a reset signal line Reset, and an initial signal line Vinit. The display substrate also includes: a data driver for providing data signals to the data lines, a scan driver for providing scan signals to the gate lines, a light emission driver for providing light emission control signals to the light emission control lines, and a timing controller for providing drive signals to the data driver, the scan driver, and the light emission driver.

[0104] Optionally, such as Figure 1 As shown, the i-th column of sub-pixels is connected to the i-th column of data lines. Each column of data lines includes: a first sub-data line DO and a second sub-data line DE. The first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines are located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are either the first sub-data line or the second sub-data line.

[0105] Where 1≤i≤N, and N is the total number of columns of sub-pixels.

[0106] Specifically, all data lines between two adjacent columns of sub-pixels are either the first sub-data line or the second sub-data line. That is, when the first sub-data line DOi of the i-th column of data lines is located on the side of the i-th column of sub-pixels closer to the (i+1)-th column of sub-pixels, the first sub-data line DOi+1 of the (i+1)-th column of data lines is located on the side of the (i+1)-th column of sub-pixels closer to the i-th column of sub-pixels. When the second sub-data line DEi of the i-th column of data lines is located on the side of the i-th column of sub-pixels closer to the (i+1)-th column of sub-pixels, the second sub-data line DEi+1 of the (i+1)-th column of data lines is located on the side of the (i+1)-th column of sub-pixels closer to the i-th column of sub-pixels.

[0107] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be one or more of glass and metal sheets, but is not limited to. The flexible substrate can be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited to.

[0108] Optionally, the semiconductor layer 20 can be made of polycrystalline silicon or metal oxide, and this application embodiment does not limit this in any way.

[0109] Optionally, the first metal layer can be made of metals such as silver, aluminum, or copper; this application does not limit this in any way.

[0110] Optionally, the material used to make the second metal layer can be a metal such as silver, aluminum, or copper, and this application embodiment does not limit this in any way.

[0111] Optionally, the third metal layer can be made of metals such as silver, aluminum or copper, and this application embodiment does not limit this in any way;

[0112] Optionally, the fourth metal layer can be made of metals such as silver, aluminum, or copper, and this application embodiment does not limit this in any way.

[0113] Optionally, the fifth metal layer can be made of metals such as silver, aluminum, or copper, and this application embodiment does not limit this in any way.

[0114] Figure 4A This is an equivalent circuit diagram of the driving circuit provided in the embodiments of this application. Figure 4B The timing diagram of the driving circuit provided in the embodiments of this application is as follows: Figure 4A and Figure 4B As shown, Figure 4A The following description uses the driving circuit included in the i-th column sub-pixel and the (i+1)-th column sub-pixel as an example. The driving circuit provided in this application embodiment is a 7T1C structure. The driving circuit includes: a first transistor T1 to a seventh transistor T7 and a storage capacitor C, wherein the storage capacitor C includes a first electrode C1 and a second electrode C2.

[0115] Specifically, the gate electrode of the first transistor T1 is connected with the reset signal line Reset, the first electrode of the first transistor T1 is connected with the initial signal line Vinit, the second electrode of the first transistor T1 is connected with the first electrode C1 of the storage capacitor C, the gate electrode of the second transistor T2 is connected with the gate line G, the first electrode of the second transistor T2 is connected with the first electrode C1 of the storage capacitor C, the second electrode of the second transistor T2 is connected with the second electrode of the sixth transistor T6, the gate electrode of the third transistor T3 is connected with the first electrode C1 of the storage capacitor C, the first electrode of the third transistor T3 is connected with the second electrode of the fourth transistor T4, the second electrode of the third transistor T3 is connected with the second electrode of the sixth transistor T6, the gate electrode of the fourth transistor T4 is connected with the gate line G, the first electrode of the fourth transistor T4 is connected with the data line D, the gate electrode of the fifth transistor T5 is connected with the light-emitting control line EM, the first electrode of the fifth transistor T5 is connected with the power supply line VDD, the second electrode of the fifth transistor T5 is connected with the first electrode of the third transistor T3, the gate electrode of the sixth transistor T6 is connected with the light-emitting control line EM, the second electrode of the sixth transistor T6 is connected with the anode of the light-emitting device, the gate electrode of the seventh transistor T7 is connected with the reset signal line Reset, the first electrode of the seventh transistor T7 is connected with the initial signal line Vinit, the second electrode of the seventh transistor T7 is connected with the anode of the light-emitting device, the second electrode C2 of the storage capacitor is connected with the power supply line VDD, and the cathode of the light-emitting device OLED is connected with the low-level power supply end VSS.

[0116] The third transistor T3 is a driving transistor, and the other transistors are switch transistors, and the first transistor T1 to the seventh transistor T7 provided in the embodiment can be P-type transistors or N-type transistors, which are not limited in the embodiment.

[0117] Specifically, taking the first transistor T1 to the seventh transistor T7 as P-type transistors as an example, the working process of the driving circuit provided in the embodiment includes:

[0118] In the first stage S1, the reset stage, the reset signal line Reset provides an effective level, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal provided by the initial signal line Vinit initializes the signals of the second electrode of the sixth transistor T6 and the first electrode C1.

[0119] In the second stage S2, the writing stage, the gate line G provides an effective level, the second transistor T2 and the fourth transistor T4 are turned on, the data signal provided by the data line D is written to the first electrode of the third transistor T3, and the potential of the signal of the gate electrode and the second electrode of the second transistor T2 is the same, so that the third transistor T3 is turned on.

[0120] The third stage S3, the light emitting stage, the light emitting control line EM provides an effective level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply line VDD provides a driving current to the light emitting device OLED to drive the light emitting device to emit light.

[0121] Optionally, as shown in the embodiment of the present application, the light emitting device can be an OLED. Figure 4A

[0122] The display substrate provided by the embodiment of the present application is provided with gate lines, data lines, power supply lines, reset signal lines, light emitting control lines, initial signal lines and a plurality of sub-pixels, each of the sub-pixels comprises a light emitting device and a driving circuit for driving the light emitting device to emit light, the driving circuit comprises a plurality of transistors and a storage capacitor; the display substrate comprises a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer which are sequentially arranged on the substrate and are insulated from each other; the semiconductor layer comprises active layers of the plurality of transistors, the first metal layer comprises the gate lines, the light emitting control lines, the reset signal lines, first electrodes of the storage capacitor and gate electrodes of the plurality of transistors, the second metal layer comprises the initial signal lines and second electrodes of the storage capacitor; the third metal layer comprises source-drain electrodes of the plurality of transistors, the fourth metal layer comprises the data lines and the power supply lines, and the fifth metal layer comprises anodes of the light emitting devices; an i-th column of sub-pixels is connected with an i-th column of data lines, each column of data lines comprises first sub-data lines and second sub-data lines; the first sub-data lines and the second sub-data lines in the i-th column of data lines are respectively located on two sides of the i-th column of sub-pixels, all the sub-data lines between two adjacent columns of sub-pixels are only the first sub-data lines or the second sub-data lines, 1≤i≤N, and N is a total number of columns of the sub-pixels. The present application is provided with five metal layers, the data lines and the power supply lines are arranged in different layers from the source-drain electrodes of the plurality of transistors, so that the volume occupied by the sub-pixels and the data lines connected with the sub-pixels can be reduced, and the resolution of the high-frequency driven OLED display substrate is improved.

[0123] Optionally, as shown in the embodiment of the present application, each of the sub-pixels in the display substrate is divided into a first region R1, a second region R2 and a third region R3. Figure 3

[0124] Specifically, the storage capacitor is located in the second region R2, the first region R1 and the third region R3 are respectively located on two sides of the second region and are arranged along the extension direction of the data lines, the initial signal line Vinit, the gate line G and the reset signal line Reset connected with the sub-pixel are located in the first region R1, and the light emitting control line EM connected with the sub-pixel is located in the third region R3.

[0125] ​​Specifically, the adjacent sub-pixels in the same column are connected to different sub-data lines, that is, if the sub-pixel in the i-th row and the j-th column is connected to the first sub-data line DOj in the j-th column data line, the sub-pixel in the i+1-th row and the j-th column is connected to the second sub-data line DEj in the j-th column data line, and if the sub-pixel in the i-th row and the j-th column is connected to the second sub-data line DEj in the j-th column data line, the sub-pixel in the i+1-th row and the j-th column is connected to the first sub-data line DOj in the j-th column data line.

[0126] Optionally, as shown in Figure 1 and Figure 3 It can be seen that the i-th column of sub-pixels is also connected to the i-th column of power supply lines, 1≤i≤N.

[0127] The i-th column of power supply lines VDDi is located between the first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines.

[0128] Figure 5 A top view of a plurality of sub-pixels in a display substrate provided by an embodiment of the present application is shown in Figure 5 As shown in the figure, the pixel structures of the adjacent sub-pixels in the same row are mirror-symmetric with respect to the center line CL between the two sub-data lines, the pixel structure of the sub-pixel in the i-th row and the j-th column is the same as the pixel structure of the sub-pixel in the i+1-th row and the j+1-th column, and the pixel structure of the sub-pixel in the i-th row and the j+1-th column is the same as the pixel structure of the sub-pixel in the i+1-th row and the j-th column.

[0129] As shown in Figure 5 The two adjacent columns of power supply lines are mirror-symmetric with respect to the center line between the two adjacent columns of power supply lines.

[0130] Specifically, the center line CL between the two sub-data lines between the sub-pixel in the i-th row and the j-th column and the sub-pixel in the i-th row and the j+1-th column is the same as the center line between the j-th column of power supply lines and the j+1-th column of power supply lines.

[0131] Optionally, as shown in Figure 5 The i-th column of power supply lines includes a plurality of sub-power supply lines connected to each other, which are S1-SN, and the plurality of sub-power supply lines correspond to all sub-pixels in each column of sub-pixels one by one. It should be noted that Figure 5 The above is described by taking the previous two rows and four columns of eight sub-pixels as an example.

[0132] Specifically, in the embodiment, the shape of the sub-power supply line corresponding to the sub-pixel in the i-th row and the j-th column after being flipped along the center line between the first sub-data line and the second sub-data line in the j-th column of data lines is the same as the shape of the sub-power supply line corresponding to the sub-pixel in the i+1-th row and the j-th column.

[0133] Specifically, as shown in Figure 5As shown, each sub-power line includes: a first power supply part SS1, a second power supply part SS2, and a third power supply part SS3, the second power supply part SS2 is used for connecting the first power supply part SS1 and the third power supply part SS3, the first power supply part SS1 and the third power supply part SS3 are arranged in parallel with the data line, and the included angle between the second power supply part SS2 and the first power supply part SS1 is greater than 90 degrees and less than 180 degrees.

[0134] The first power supply part SS1, the second power supply part SS2, and the third power supply part SS3 are integrally formed.

[0135] As shown, the width of the third power supply part SS3 is less than the width of the first power supply part SS1, which is for the layout of the pixel structure on one hand, and on the other hand, since the third power supply part SS3 is relatively close to the power supply line, the smaller width of the third power supply part SS3 can reduce the parasitic capacitance. Figure 5

[0136] Specifically, the first power supply part SS1 in the sub-power line corresponding to the sub-pixel in the i-th row and the j-th column is connected with the third power supply part SS3 in the sub-power line corresponding to the sub-pixel in the i-1-th row and the j-th column, the third power supply part SS3 in the sub-power line corresponding to the sub-pixel in the i-th row and the j-th column is connected with the first power supply part SS1 in the sub-power line corresponding to the sub-pixel in the i+1-th row and the j-th column, and the mutually connected power supply parts are arranged along the extension direction of the data line.

[0137] As shown, the power supply line in the embodiment of the application is a polyline. Figure 5

[0138] In the embodiment, in combination with Figure 5 The working process of each sub-pixel includes: in the reset stage, the reset signal line Reset located in the first metal layer and the initial signal line Vinit located in the second metal layer provide signals to initialize the driving circuit, in the writing stage, the gate line G located in the first metal layer and the data line D located in the fourth metal layer provide signals, and the driving circuit writes the data signal provided by the data line D; in the light emitting stage, the light emitting control line EM located in the first metal layer provides a signal, and the power supply line VDD provides a power supply signal, so that the driving circuit provides a driving current to the light emitting device OLED to drive the light emitting device to emit light.

[0139] The same row of pixels are displayed at the same time, and the adjacent rows of pixels are displayed in sequence.

[0140] Optionally, as shown, the display substrate provided by the application further includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14. Figure 2

[0141] ​​​Specifically, the first insulating layer 11 is arranged between the semiconductor layer 20 and the first metal layer 30, the second insulating layer 12 is arranged between the first metal layer 30 and the second metal layer 40, the third insulating layer 13 is arranged between the second metal layer 40 and the third metal layer 50, and the fourth insulating layer 14 is arranged between the third metal layer 50 and the fourth metal layer 60.

[0142] Optionally, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 can be made of silicon oxide, silicon nitride or a composite of silicon oxide and silicon nitride, and the embodiments of the present application do not make any limitation in this regard.

[0143] In the embodiment, as shown in FIG. 1, for each sub-pixel, the plurality of transistors include a first transistor to a seventh transistor, and a first electrode of the fifth transistor is connected with a power supply line VDD and a second electrode C2 of a storage capacitor respectively. Figure 4A

[0144] In the embodiments of the present application, for each sub-pixel, a power supply line in each sub-pixel is connected with a second electrode of a storage capacitor through a first electrode of the fifth transistor.

[0145] Specifically, the second electrode of the storage capacitor of the sub-pixel located in the second metal layer is also multiplexed as a power supply signal line, which is used to ensure that the power supply signals provided by the power supply lines of adjacent sub-pixels are the same, to avoid display defects of the display substrate and to ensure the display effect of the display substrate.

[0146] In the embodiment, every four continuous sub-pixels constitute a pixel, and in the jth pixel, the four continuous sub-pixels are the ith sub-pixel, the ith+1 sub-pixel, the ith+2 sub-pixel and the ith+3 sub-pixel in turn along the arrangement direction of the gate lines, wherein i can be taken as 4j-3 in turn, and j is a positive integer.

[0147] Specifically, the second electrode of the storage capacitor of the plurality of sub-pixels is connected in a plurality of implementation manners, and as one implementation manner, Figure 6A is a top view of the sub-pixel corresponding to the first implementation manner, Figure 6B is another top view of the sub-pixel corresponding to the first implementation manner, wherein, as shown in FIG. 2, the fourth insulating layer is provided with a first via V1 exposing a part of the first electrode 51 of the fifth transistor, and the power supply line is connected with the first electrode 51 of the fifth transistor through the first via V1; as shown in FIG. 3, the third insulating layer is provided with a second via V2 exposing a part of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor is connected with the second electrode of the storage capacitor through the second via V2. It should be noted that, Figure 6A Figure 6B are described by taking the first implementation manner as an example. Figure 3 Figure 5 are described by taking the first implementation manner as an example.

[0148] ​​​The orthogonal projection of the power supply line connected with the sub-pixel on the substrate covers the orthogonal projection of the first via V1 on the substrate 10, and the orthogonal projection of the second electrode of the storage capacitor on the substrate covers the orthogonal projection of the second via on the substrate.

[0149] Optionally, the number of the first via V1 is one.

[0150] Optionally, the number of the second via V2 is at least one. Since the width of the first electrode of the fifth transistor is narrow, when the number of the second via V2 is multiple, the multiple second vias are arranged along the extension direction of the data line. When the multiple second vias are arranged along the extension direction of the data line, multiple vias can be arranged, and the more the number of the vias, the better the conductivity of the components connected through the vias. Figure 6A is a first via V1, Figure 6B is an example of two second vias V2, and the embodiments of the present application do not limit this.

[0151] Specifically, as shown in Figure 6A , the fourth insulating layer further includes a via exposing the first electrode of the fourth transistor T4, and the data line is connected with the first electrode of the fourth transistor T4 through the via. The fourth insulating layer further includes a via exposing the second electrode of the sixth transistor T6, and the anode of the light emitting device is connected with the second electrode of the sixth transistor T6 through the via.

[0152] Specifically, as shown in Figure 6B , the first insulating layer, the second insulating layer and the third insulating layer further include vias exposing part of the active layer, so that the source-drain electrodes of the transistors are connected with the active layer through the vias.

[0153] Specifically, the first electrode of the fifth transistor is further connected with the active layer through the vias on the first insulating layer, the second insulating layer and the third insulating layer.

[0154] In the embodiments, each pixel includes four sub-pixels, specifically, Figure 7A is a top view of the second metal layer corresponding to the first embodiment, Figure 7B is a top view of the third metal layer corresponding to the first embodiment, in order to more clearly illustrate the structure of the display substrate, Figure 7A and Figure 7B is an example of two pixels arranged along the column direction.

[0155] As shown in Figure 7A , the second electrode of the storage capacitor in the adjacent sub-pixels in the same row directly contacts, as shown in Figure 7B , the first electrodes 51 of the fifth transistors of the adjacent sub-pixels in the same row are arranged with a spacing.

[0156] In the first embodiment, the second electrodes of the storage capacitors arranged on the second metal layer by the plurality of sub-pixels are in contact with each other, so that the power supply signals provided by the power supply lines of adjacent sub-pixels are the same, display defects of the display substrate are avoided, and the display effect of the display substrate is ensured.

[0157] As another embodiment, Figure 8A a top view of a sub-pixel corresponding to the second embodiment, Figure 8B a top view of a plurality of sub-pixels corresponding to the second embodiment, wherein, as shown in Figure 8A The fourth insulating layer is provided with a first via V1 exposing a first electrode 51 of a part of the fifth transistor, and the power supply line is connected to the first electrode 51 of the fifth transistor through the first via V1; as shown in Figure 8B The third insulating layer is provided with a second via V2 exposing a second electrode C2 of a part of the storage capacitor, and the first electrode 51 of the fifth transistor is connected to the second electrode of the storage capacitor through the second via V2.

[0158] As shown in Figure 8A and Figure 8B The area occupied by the second electrode of the storage capacitor of each sub-pixel provided in the first embodiment is different, and the shape of the first electrode 51 of the fifth transistor is also different.

[0159] Specifically, as shown in Figure 8A The fourth insulating layer further includes a via exposing a first electrode of the fourth transistor T4, and the data line is connected to the first electrode of the fourth transistor T4 through the via. The fourth insulating layer further includes a via exposing a second electrode of the sixth transistor T6, and the anode of the light emitting device is connected to the second electrode of the sixth transistor T6 through the via.

[0160] Specifically, as shown in Figure 3 and 8B The first insulating layer, the second insulating layer and the third insulating layer further include: vias exposing a part of the active layer, so that the source-drain electrodes of the transistors are connected to the active layer through the vias. Specifically, the first electrode of the fifth transistor is also connected to the active layer through the vias on the first insulating layer, the second insulating layer and the third insulating layer.

[0161] The orthogonal projection of the power supply line connected to the sub-pixel on the substrate covers the orthogonal projection of the first via V1 on the substrate 10, and the orthogonal projection of the second electrode of the storage capacitor on the substrate covers the orthogonal projection of the second via on the substrate.

[0162] Optionally, the number of the first via V1 is one.

[0163] Optionally, the number of the second via V2 is at least one, and since the width of the first electrode of the fifth transistor is narrow, the plurality of second vias are arranged along the data line extension direction, which can ensure the number of vias, and the more the number of vias, the better the conductivity of the components connected through the vias, Figure 8A is a first via V1, Figure 8B is described by taking two second vias V2 as an example, and the embodiments of the present application are not limited in this regard.

[0164] Specifically, Figure 9A is a top view of the second metal layer corresponding to the second embodiment, Figure 9B is a top view of the third metal layer corresponding to the second embodiment, Figure 10 is another top view of a plurality of sub-pixels in a display substrate provided by the embodiments of the present application, in order to more clearly illustrate the structure of the display substrate, Figure 9A and Figure 9B is described by taking two pixels arranged along the column direction as an example, Figure 10 includes other film layers except the anode of the light emitting device, Figure 10 The plurality of sub-pixels included in the display substrate are sub-pixels corresponding to the second embodiment.

[0165] As shown in Figure 9A and Figure 9B the second electrode of the storage capacitor of the i-th sub-pixel in each pixel in one of the two adjacent rows of pixels directly contacts the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel is spaced apart from the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel directly contacts the second electrode of the storage capacitor of the i+3-th sub-pixel; the second electrode of the storage capacitor of the i-th sub-pixel in each pixel in the other of the two adjacent rows of pixels is spaced apart from the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel directly contacts the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel is spaced apart from the second electrode of the storage capacitor of the i+3-th sub-pixel.

[0166] It should be noted that, Figure 9A is described by taking the second electrode of the storage capacitor of the i-th sub-pixel in the first row of pixels directly contacting the second electrode of the storage capacitor of the i+1-th sub-pixel and the second electrode of the storage capacitor of the i+2-th sub-pixel in the second row of pixels directly contacting the second electrode of the storage capacitor of the i+3-th sub-pixel as an example.

[0167] Optionally, as Figure 10As shown, for each sub-pixel, the first pole of the fifth transistor has an overlapping area on the substrate with the normal projection of the data line connected with the sub-pixel.

[0168] In this embodiment, in combination with Figure 9A , Figure 9B and Figure 10 , for the jth pixel, in the case that the second electrode C2 of the storage capacitor in the ith sub-pixel is in direct contact with the second electrode C2 of the storage capacitor in the ith+1 sub-pixel, the first pole 51 of the fifth transistor in the ith+1 sub-pixel is in direct contact with the first pole 51 of the fifth transistor in the ith+2 sub-pixel; wherein the second electrode C2 of the storage capacitor in the ith sub-pixel in the second metal layer is connected with the second electrode C2 of the storage capacitor in the ith+3 sub-pixel in the second metal layer through the first pole 51 of the fifth transistor in the ith+1 sub-pixel and the first pole 51 of the fifth transistor in the ith+2 sub-pixel in the third metal layer.

[0169] In this embodiment, for the jth pixel, in the case that the second electrode C2 of the storage capacitor in the ith+1 sub-pixel is in direct contact with the second electrode C2 of the storage capacitor in the ith+2 sub-pixel, the first pole 51 of the fifth transistor in the ith sub-pixel is in direct contact with the first pole 51 of the fifth transistor in the ith+1 sub-pixel, and the first pole 51 of the fifth transistor in the ith+2 sub-pixel is in direct contact with the first pole 51 of the fifth transistor in the ith+3 sub-pixel; wherein the second electrode C2 of the storage capacitor in the ith sub-pixel in the second metal layer is connected with the second electrode C2 of the storage capacitor in the ith+1 sub-pixel in the second metal layer through the first pole 51 of the fifth transistor in the ith sub-pixel and the first pole 51 of the fifth transistor in the ith+1 sub-pixel in the third metal layer, and the second electrode C2 of the storage capacitor in the ith+2 sub-pixel in the second metal layer is connected with the second electrode C2 of the storage capacitor in the ith+3 sub-pixel in the second metal layer through the first pole 51 of the fifth transistor in the ith+2 sub-pixel and the first pole 51 of the fifth transistor in the ith+3 sub-pixel in the third metal layer.

[0170] In the second embodiment, the second metal layer and the third metal layer are used to realize the function of the power connection line, so that the power signals provided to each sub-pixel are the same, and the display effect of the display substrate is ensured.

[0171] It should be noted that, since the resistivity of the third metal layer is smaller than that of the second metal layer, the display substrate provided in the second embodiment can further reduce the dynamic crosstalk compared with the display substrate provided in the first embodiment.

[0172] Optionally, as Figure 2As shown, the display substrate provided by the embodiment of the present application further comprises a fifth insulating layer 15 and a planar layer 16 arranged between the fourth metal layer 60 and the fifth metal layer 70, and an organic material layer and a cathode (not shown in the figure) of the light emitting device arranged on the side of the fifth metal layer 70 away from the substrate 10.

[0173] Specifically, the fifth insulating layer 15 is arranged on the side of the planar layer 16 close to the substrate 10, and the cathode is arranged on the side of the organic material layer away from the substrate 10.

[0174] As shown, the fourth metal layer provided by the embodiment of the present application further comprises a connecting electrode 61, wherein the connecting electrode is connected with the second electrode of the sixth transistor. Figure 3

[0175] Specifically, the fifth insulating layer and the planar layer are provided with a via hole exposing the connecting electrode, the fifth metal layer is connected with the connecting electrode through the via hole exposing the connecting electrode, the fourth insulating layer is provided with a via hole exposing the second electrode of the sixth transistor, and the connecting electrode is connected with the second electrode of the sixth transistor through the via hole exposing the second electrode of the sixth transistor.

[0176] Based on the same inventive concept, the embodiment of the present application further provides a manufacturing method of a display substrate for manufacturing the display substrate provided by the above-mentioned embodiments, Figure 11 The flow chart of the manufacturing method of the display substrate provided by the embodiment of the present application is shown in Figure 11 The manufacturing method of the display substrate provided by the embodiment of the present application specifically comprises the following steps:

[0177] Step S1, providing a substrate.

[0178] Step S2, sequentially forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer on the substrate, which are insulated from each other.

[0179] Specifically, the semiconductor layer comprises an active layer of a plurality of transistors, the first metal layer comprises a gate line, a light emitting control line, a reset signal line, a first electrode of a storage capacitor and a gate electrode of a plurality of transistors, the second metal layer comprises an initial signal line and a second electrode of the storage capacitor, the third metal layer comprises a source / drain electrode of a plurality of transistors, the fourth metal layer comprises a data line and a power supply line, and the fifth metal layer comprises an anode of a light emitting device; the i-th column of sub-pixels is connected with the i-th column of data lines, each column of data lines comprises a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on the two sides of the i-th column of sub-pixels, and all the sub-data lines between the adjacent two columns of sub-pixels are only the first sub-data lines or the second sub-data lines.

[0180] Wherein, 1≤i≤N, and N is the total number of columns of sub-pixels.

[0181] ​The method for manufacturing the display substrate provided in this application embodiment is used to manufacture the display substrate provided in the above embodiment. Its implementation principle and effect are similar, and will not be described again here.

[0182] Optionally, step 200 includes: forming a semiconductor layer and a first insulating layer sequentially on a substrate; forming a first metal layer and a second insulating layer sequentially on the first insulating layer; forming a second metal layer and a third insulating layer sequentially on the second insulating layer; forming a third metal layer and a fourth insulating layer sequentially on the third insulating layer; forming a fourth metal layer, a fifth insulating layer and a planarization layer sequentially on the fourth insulating layer; and forming a fifth metal layer, an organic light-emitting layer of the light-emitting device and a cathode of the light-emitting device sequentially on the planarization layer.

[0183] Figure 12 This is a first manufacturing schematic diagram of the display substrate provided in an embodiment of this application. Figure 13 This is a second schematic diagram illustrating the fabrication of a display substrate provided in an embodiment of this application. Figure 14A This is a third manufacturing schematic diagram of the display substrate provided in an embodiment of this application. Figure 14B This is another third schematic diagram of the fabrication of the display substrate provided in an embodiment of this application. Figure 15A This is a fourth manufacturing schematic diagram of a display substrate provided in an embodiment of this application. Figure 15B This is another fourth schematic diagram of the fabrication of the display substrate provided in the embodiments of this application. Figure 16A This is a fifth manufacturing schematic diagram of a display substrate provided in an embodiment of this application. Figure 16B This is another fifth manufacturing schematic diagram of the display substrate provided in the embodiments of this application, combined with... Figures 12-1 6. The following further describes the method for manufacturing the display substrate provided in the embodiments of this application, with specific details as follows:

[0184] Optionally, the patterning process includes processes such as photoresist coating, exposure, development, etching, and photoresist stripping.

[0185] Step 100: Provide a substrate 10, deposit a semiconductor thin film on the substrate 10, and process the semiconductor thin film using a patterning process to form a semiconductor layer 20, such as... Figure 12 As shown.

[0186] The schematic diagram of the active layer fabrication in Implementation Method 1 is the same as that in Implementation Method 2.

[0187] Step 200: Deposit an insulating thin film on the semiconductor layer 20, process the insulating thin film using a patterning process to form a first insulating layer, deposit a metal thin film on the first insulating layer, and process the metal thin film using a patterning process to form a first metal layer 30, specifically as follows... Figure 13 As shown.

[0188] The first metal layer 30 includes a gate line G, a reset signal line Reset, an emission control line EM, and a first electrode C1 of a storage capacitor.

[0189] The manufacturing schematic diagram of the first metal layer in the first embodiment is the same as that in the second embodiment.

[0190] In step 300, an insulating film is deposited on the first metal layer 30, and the insulating film is processed by a patterning process to form a second insulating layer. A metal film is deposited on the second insulating layer, and the metal film is processed by a patterning process to form a second metal layer including an initial signal line Vinit and a second electrode C2 of a storage capacitor. An insulating film is deposited on the second metal layer, and the insulating film is processed by a patterning process to form a third insulating layer, as shown in Figure 14A and 14B .

[0191] The third insulating layer includes a first via V1 exposing the second electrode, a via exposing the initial signal line Vinit, a via exposing the first electrode provided in the second insulating layer and the third insulating layer, and a via exposing the semiconductor layer provided in the first insulating layer, the second insulating layer, and the third insulating layer.

[0192] Figure 14A The manufacturing schematic diagram of the first embodiment is shown in Figure 14B The manufacturing schematic diagram of the second embodiment is shown in

[0193] In step 400, a metal film is deposited on the third insulating layer, and the metal film is processed by a patterning process to form a third metal layer including source and drain electrodes of a plurality of transistors. An insulating film is deposited on the third metal layer, and the insulating film is processed by a patterning process to form a fourth insulating layer, as shown in Figure 15A and Figure 15B .

[0194] The fourth insulating layer includes a first via V1 exposing a fifth transistor, a via exposing a second electrode of a sixth transistor, and a via exposing a first electrode of a fourth transistor.

[0195] It should be noted that Figure 15A The manufacturing schematic diagram of the first embodiment is shown in Figure 15B The manufacturing schematic diagram of the second embodiment is shown in

[0196] In step 500, a metal film is deposited on the fourth insulating layer, and the metal film is processed by a patterning process to form a fourth metal layer including a data line D, a power supply line VDD, and a connection electrode 61. An insulating film is deposited on the fourth metal layer, and the insulating film is processed by a patterning process to form a fifth insulating layer. A planar film is coated on the fifth insulating layer, and the planar film is processed by a patterning process to form a planar layer, as shown inFigure 16A and 16B as shown.

[0197] Specifically, the fifth insulating layer and the planar layer are provided with a via hole exposing the connecting electrode, and the light emitting.

[0198] It should be noted that, Figure 16A is a manufacturing schematic diagram of the first embodiment, Figure 16B is a manufacturing schematic diagram of the second embodiment.

[0199] Step 600, depositing a metal thin film on the planar layer, processing the metal thin film by a patterning process to form a fifth metal layer, coating an organic material thin film on the fifth metal layer, processing the organic material thin film by a patterning process to form an organic material layer, depositing a conductive thin film on the organic material layer, and processing the conductive thin film by a patterning process to form a cathode.

[0200] Based on the same inventive concept, the embodiment of the present application also provides a display device, wherein the display device comprises a display substrate.

[0201] Optionally, the display substrate is an OLED display substrate.

[0202] Specifically, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the embodiment of the present application is not limited thereto.

[0203] The display substrate is the display substrate provided in the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0204] For the sake of clarity, in the drawings used to describe the embodiments of the present application, the thickness and size of a layer or microstructure are exaggerated. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0205] Although the embodiments of the present application are disclosed as above, the content described is only the embodiment adopted for the purpose of understanding the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the implementation form and details without departing from the spirit and scope of the present application, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized by, The display substrate comprises: An array of sub-pixels, a plurality of data lines and a plurality of power lines; At least one sub-pixel comprises a drive circuit, the drive circuit comprises a transistor and a storage capacitor, the storage capacitor comprises a first electrode and a second electrode arranged oppositely, the display substrate comprises a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer sequentially stacked on the substrate; The semiconductor layer comprises an active layer of the transistor in at least one drive circuit; The first metal layer comprises the first electrode of the storage capacitor; The second metal layer comprises the second electrode of the storage capacitor; The power line comprises at least one sub-power line connected to the sub-pixel and located in the area where the sub-pixel is located, and at least one sub-power line comprises three power supply parts: a first power supply part, a second power supply part and a third power supply part; the second power supply part is connected to the first power supply part and the third power supply part; the data line is arranged in parallel with the extension direction of the first power supply part and the third power supply part; The included angle between the first power supply part and the second power supply part is greater than 90 degrees and less than 180 degrees, and the included angle between the second power supply part and the third power supply part is greater than 90 degrees and less than 180 degrees; The average width of the second power supply part is greater than or equal to the average width of the third power supply part; The power line and the data line are single-layer structures and are located in the fourth metal layer; The drive circuit comprises a fifth transistor, the first electrode of the fifth transistor is located in the third metal layer, the orthographic projection of the first electrode of the fifth transistor on the substrate at least partially overlaps the orthographic projection of the second electrode plate of the storage capacitor on the substrate, and at least partially overlaps the orthographic projection of the third power supply part on the substrate.

2. The display substrate of claim 1, wherein, For at least one drive circuit, the second electrode of the storage capacitor is arranged to input a power signal, and the power signal is a signal of the sub-power line. 3.The display substrate of claim 1, wherein, The display substrate further comprises a fourth insulating layer and a fifth insulating layer, the fourth insulating layer is arranged between the third metal layer and the fourth metal layer, the fifth insulating layer is arranged on the side of the fourth metal layer away from the substrate, and the fourth metal layer further comprises a connecting electrode; The fifth insulating layer is provided with a via hole exposing the connecting electrode, and the fourth insulating layer is provided with a via hole exposing the third metal layer; the orthographic projection of the via hole exposing the third metal layer on the substrate at least partially overlaps the orthographic projection of the connecting electrode on the substrate.

4. The display substrate of claim 3, wherein, The extension direction of the connecting electrode is arranged in parallel with the extension direction of the first power supply part. 5.The display substrate of claim 3, wherein, The extension direction of the virtual connection line of the via hole exposing the third metal layer and the via hole exposing the connecting electrode is parallel to the extension direction of the data line. 6.The display substrate of claim 3, wherein, The virtual extension line of the first power supply part passes through the via hole exposing the connecting electrode. 7.The display substrate of claim 3, wherein, The virtual extension line of the first power supply part passes through the via hole exposing the third metal layer. 8.The display substrate of claim 1, wherein, The display substrate further comprises a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the first insulating layer, the second insulating layer and the third insulating layer are arranged between the third metal layer and the semiconductor layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer. The fourth insulating layer is provided with a via hole exposing the third metal layer, the data line is connected with the third metal layer through the via hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer are provided with a via hole exposing the semiconductor layer. 9.The display substrate of claim 8, wherein, The virtual extension line of the third power supply part passes through the via hole exposing the semiconductor layer. 10.The display substrate of claim 8, wherein, The virtual extension line of the third power supply part passes through the via hole exposing the third metal layer. 11.The display substrate of claim 1, wherein, The average width of the third power supply part is greater than or equal to the average width of the data line. 12.The display substrate of claim 1, wherein, The active layers of adjacent sub-pixels arranged in a first direction or a second direction are mirror-symmetrical, the first direction is perpendicular to the second direction, and the second direction is the extension direction of the data line. 13.The display substrate of claim 1, wherein, The driving circuit comprises a second transistor, and a projection of the first power supply part on a base at least partially overlaps a projection of a part of the second transistor on the base. 14.The display substrate of claim 1, wherein, A projection of the second power supply part on a base at least partially overlaps a projection of a part of the second electrode on the base. 15.The display substrate of claim 1, wherein, The first metal layer further comprises a gate line, and a projection of the second power supply part on a base at least partially overlaps a projection of the gate line on the base. 16.The display substrate of claim 1, wherein, A projection of the third power supply part on a base at least partially overlaps a projection of a part of at least one transistor on the base.

17. A display device comprising: The display substrate comprises: The display substrate according to any one of claims 1 to 16.

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