Optically transparent non-volatile transistor memory and preparation method thereof

Abstract

Disclosed are an optically transparent non-volatile transistor memory and a method for preparing the same, belonging to the technical field of memories. The memory has a top-gate structure, comprising, from bottom to top, a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer, and a gate electrode. The substrate, source-drain electrode, polymer semiconductor layer, ferroelectric gate insulating layer, and gate electrode are all made of optically transparent materials, and the polymer semiconductor layer, ferroelectric gate insulating layer, and gate electrode are all prepared by a solution method. The electrical characteristics of the memory tested in a darkroom and under illumination conditions exhibit good repeatability, indicating good optical stability, significant information storage function, good operating reliability, and stability. The entire preparation process of the memory is prepared by a full solution method, with a processing temperature below 150°C. This method has the advantages of simple process, good process continuity, low-temperature preparation, inexpensive preparation equipment, and low preparation cost, which can greatly enhance its commercial competitiveness.

Description

Technical Field

[0001] The present invention belongs to the technical field of memories, and in particular relates to a non-volatile transistor memory having a high optical transparency in the visible light region and a preparation method thereof. Background Art

[0002] As a carrier of information storage, memory holds a pivotal position in the information industry. As the terminal for displaying information, displays also play a crucial role in the information industry chain. Over the past two decades, technological advancements and performance improvements in memory and displays have driven the rapid development of the entire information industry and fueled consumer demand for more diverse information products.

[0003] Depending on whether the information is stored long-term and persistently, memories are divided into two categories: volatile memories and non-volatile memories. To date, the vast majority of memories use metals as electrodes, which have significant visual optical opacity, that is, they are significantly opaque to visible light. Currently, in various information products in the information industry chain, memories, processors, and displays are generally separated; the information stored in the memory is transmitted to other components or displays through public or dedicated lines for related information processing and terminal display. In recent years, an emerging concept, "transparent memory", has been proposed, with the goal of integrating information storage, processing, and terminal display into a visual system; compared to existing product technologies, this system can further improve integration and develop new types of consumer electronic products. Currently, only a small number of literature reports on transparent memories based on oxide semiconductors. Most of these reported transparent memories use atomic layer deposition technology or vacuum magnetron sputtering technology to prepare transparent oxide semiconductors or oxide storage functional layers [Adv.Funct.Mater.2010,20,921; ACS Nano 2012,6,7879; ACSAppl.Mater.Interfaces 2019,11,35169]. The related technical equipment is expensive; and the preparation of the multilayer thin films of the memory device structure uses different technical processes, resulting in poor process continuity. Summary of the Invention

[0004] In response to the above-mentioned problems existing in the prior art, the present invention provides a non-volatile transistor memory with high optical transparency in the visible light region and a preparation method thereof. The optically transparent non-volatile transistor memory provided by the present invention has a top-gate structure, which includes, from bottom to top, an optically transparent substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer, and a gate electrode. The preparation method of the present invention adopts a full solution process technology to prepare the various functional layer films of the device, and the overall preparation temperature is no higher than 150°C. It has significant advantages such as simple process, good process continuity, low cost, low-temperature preparation, and low energy consumption, which can significantly enhance the commercial competitiveness of the product.

[0005] The present invention is achieved through the following technical solutions:

[0006] An optically transparent non-volatile transistor memory has a top-gate structure and consists, from bottom to top, of a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer, and a gate electrode; the substrate, source-drain electrode, polymer semiconductor layer, ferroelectric gate insulating layer, and gate electrode are all made of optically transparent materials, and the polymer semiconductor layer, ferroelectric gate insulating layer, and gate electrode are all prepared by a solution process.

[0007] Furthermore, the substrate is optically transparent glass, or optically transparent polyethylene terephthalate, polyethylene naphthalate or polyethersulfone.

[0008] Furthermore, the source-drain electrodes are transparent indium tin oxide thin films.

[0009] Furthermore, the polymer semiconductor layer is a polymer semiconductor film, specifically poly{2,2'-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diacyl)]disulfanyl-5,5'-diacylthiophene[3,2-b]thiophene-2,5-diacyl}, 3-hexyl substituted polythiophene, {[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl] -5,5'-(2,2'-bithiophene)} copolymer, (9,9-octylfluorene-benzothiadiazole) copolymer or poly[(5-fluoro-2,1,3-benzothiazol-4,7-diacyl)(4,4-hexacosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophene-2,6-diacyl)(6-fluoro-2,1,3-benzothiadiazole)-4,7-diacyl)(4,4-hexacosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophenyl-2,6-diacyl)].

[0010] Furthermore, the ferroelectric gate insulating layer is a transparent ferroelectric polymer, specifically poly(vinylidene fluoride-polyethylene trifluoride) or vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer.

[0011] Furthermore, the gate electrode is poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate.

[0012] Furthermore, the thickness of the source-drain electrode is 40 to 120 nanometers, the thickness of the polymer semiconductor layer is 10 to 150 nanometers, the thickness of the ferroelectric gate insulating layer is 100 to 1000 nanometers, and the thickness of the gate electrode is 100 to 1000 nanometers.

[0013] On the other hand, the present invention also provides a method for preparing an optically transparent non-volatile transistor memory, the specific steps of which are as follows: on an optically transparent substrate having patterned indium tin oxide, a polymer semiconductor layer, a ferroelectric gate insulating layer and a gate electrode are sequentially prepared using a solution process; wherein the patterned indium tin oxide serves as a source-drain electrode, and finally, a silicon mask combined with oxygen plasma etching is used to pattern the prepared polymer semiconductor layer, ferroelectric gate insulating layer and gate electrode to obtain a non-volatile transistor memory.

[0014] Furthermore, the solution method includes spin coating, blade coating or drop coating.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The optically transparent non-volatile transistor memory of the present invention has a high degree of transparency in the visible light region and can be integrated with a processor and a display into a visualization system to improve integration. The electrical characteristics of the memory tested in a darkroom and under light conditions show good repeatability, indicating that it has good optical stability, significant information storage function, good operating reliability and stability. The entire preparation process of the memory can be prepared using a full solution process, and the processing temperature throughout the preparation process is relatively low, below 150°C. It has significant advantages such as simple process, good process continuity, low-temperature preparation, inexpensive preparation equipment used, and low preparation cost, which can greatly enhance its commercial competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic structural diagram of the optically transparent non-volatile transistor memory provided by the present invention;

[0018] In the figure: an optically transparent substrate 1, a source-drain electrode 2, a polymer semiconductor layer 3, a ferroelectric gate insulating layer 4, and a gate electrode 5.

[0019] Figure 2This is a diagram showing the optical transparency characteristics of the optically transparent non-volatile transistor memory provided in Example 1 of the present invention in the visible light band;

[0020] Figure 3 Graphs of source-drain current-gate voltage transfer characteristics of the optically transparent nonvolatile transistor memory provided in Example 1 of the present invention, measured in a dark room under illumination by red light (center wavelength 625 nanometers), green light (center wavelength 565 nanometers), and blue light (center wavelength 490 nanometers);

[0021] Figure 4 This is a graph showing the erase-write cycle endurance of the binary storage state of the optically transparent non-volatile transistor memory provided in Example 1 of the present invention;

[0022] Figure 5 A characteristic curve diagram of the persistent storage retention time of the binary storage state of the optically transparent non-volatile transistor memory provided in Example 1 of the present invention; DETAILED DESCRIPTION

[0023] In the present invention, the structure diagram of the optically transparent non-volatile transistor memory is as follows: Figure 1 As shown, 1 is the substrate, 2 is the source-drain electrode, 3 is the polymer semiconductor layer, 4 is the ferroelectric gate insulating layer, and 5 is the gate electrode. Figure 1 It can be seen that the device structure of the optically transparent non-volatile transistor memory provided by the present invention includes, from bottom to top, a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer and a gate electrode.

[0024] In the present invention, the material of the substrate includes one or more of optically transparent glass, polyethylene terephthalate, polyethylene naphthalate, and polyethersulfone.

[0025] In the present invention, the source-drain electrodes are made of a transparent indium tin oxide film, and preferably have a thickness of 40 to 120 nanometers.

[0026] In the present invention, the material of the polymer semiconductor layer is a polymer semiconductor, for example: poly{2,2'-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diacyl)]disulfanyl-5,5'-diacylthiophene[3,2-b]thiophene-2,5-diacyl}, 3-hexyl substituted polythiophene, {[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl] -5,5'-(2,2'-bithiophene) copolymer, (9,9-octylfluorene-benzothiadiazole) copolymer, poly[(5-fluoro-2,1,3-benzothiazol-4,7-diacyl)(4,4-cosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophene-2,6-diacyl)(6-fluoro-2,1,3-benzothiadiazole)-4,7-diacyl)(4,4-cosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophenyl-2,6-diacyl)], etc. The thickness of the polymer semiconductor layer is preferably 10 to 150 nm.

[0027] In the present invention, the ferroelectric gate insulating layer is made of a transparent ferroelectric polymer, such as poly(vinylidene fluoride-polyethylene trifluoride) or vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer. The thickness of the ferroelectric gate insulating layer is preferably 100 to 1000 nanometers.

[0028] In the present invention, the gate electrode is made of poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate, and the thickness of the gate electrode is preferably 100 to 1000 nanometers.

[0029] In the present invention, all materials used are commercially available products.

[0030] The present invention also provides a method for preparing the optically transparent non-volatile transistor memory according to the above technical solution, comprising the following steps:

[0031] (1) Commercially purchased glass, polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, etc. with patterned indium tin oxide as a substrate; on the substrate, a patterned indium tin oxide film is used as a source-drain electrode;

[0032] (2) preparing a polymer semiconductor solution, and preparing a polymer semiconductor layer on the surface of the source-drain electrode of step (1) by a solution method (spin coating, scraping, drop coating); then heat-treating the semiconductor layer to remove residual solvent in the polymer semiconductor layer, the heat treatment temperature is preferably 60 to 120° C.; the time is preferably 10 to 120 minutes; the concentration of the polymer semiconductor solution is preferably 0.2% to 1% by weight; by adjusting the concentration of the solution and specific solution method process preparation parameters (spin coating or scraping rate, solvent atmosphere, etc.), the thickness of the obtained polymer semiconductor layer can be optimized and adjusted;

[0033] (3) preparing a ferroelectric polymer solution, and preparing a ferroelectric polymer film as a ferroelectric gate insulating layer on the surface of the polymer semiconductor layer obtained in step (2) by a solution method (spin coating, scraping coating, drip coating); then heat-treating the ferroelectric gate insulating layer to remove residual solvent in the ferroelectric gate insulating layer; the heat treatment temperature is preferably 100-145°C; the time is preferably 30-120 minutes; the concentration of the ferroelectric polymer solution is preferably 2% to 10% by mass; by adjusting the concentration of the solution and the specific solution method process preparation parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.), the thickness of the obtained ferroelectric gate insulating layer can be optimized and adjusted.

[0034] (4) Adding an appropriate methanol solvent to the commercially purchased poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate stock solution to dilute it and obtain a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution; preparing a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate film as a gate electrode on the surface of the ferroelectric gate insulating layer obtained in step (3) by a solution method (scraping, dripping) process; then heat-treating the gate electrode to solidify it and remove the residual solvent; the heat treatment temperature is preferably 60 to 120° C.; the time is preferably 30 to 150 minutes; the mass ratio of the stock solution to the added methanol in the configured poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution is preferably 1:5 to 1:50; by adjusting the concentration of the poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution, the thickness of the obtained gate electrode can be optimized;

[0035] (5) Covering the gate electrode surface obtained in step (4) with a silicon mask, removing the excess semiconductor layer, ferroelectric gate insulating layer, and gate electrode region using oxygen plasma etching technology, and patterning the polymer semiconductor layer, ferroelectric gate insulating layer, and gate electrode prepared in steps (2) to (4) to complete the preparation of an optically transparent non-volatile transistor memory. The oxygen plasma etching time is appropriately adjusted depending on the overall thickness of the polymer semiconductor, ferroelectric gate insulating layer, and gate electrode.

[0036] The present invention has no special requirements on the solution process used in the preparation of the polymer semiconductor layer, the ferroelectric gate insulating layer and the gate electrode, and the common methods used by those skilled in the art can be used.

[0037] The technical solution of the optically transparent non-volatile transistor memory in the present invention is described clearly and completely below in conjunction with the embodiments of the present invention.

[0038] Example 1

[0039] This embodiment provides an optically transparent non-volatile transistor memory having a top-gate structure, which is composed of a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer, and a gate electrode from bottom to top.

[0040] Among them, the substrate is glass covered with patterned indium tin oxide, which is purchased from the market; the source-drain electrode is indium tin oxide with a thickness of 50 nanometers; the polymer semiconductor layer is a poly{2,2'-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrole[3,4-c]pyrrole-1,4-diacyl)]disulfanyl-5,5'-diacylthiophene[3,2-b]thiophene-2,5-diacyl} film with a thickness of 40 nanometers; the ferroelectric gate insulating layer is a poly(vinylidene fluoride-polyethylene trifluoride) film with a thickness of 650 nanometers; and the gate electrode is a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate film with a thickness of 170 nanometers.

[0041] The preparation process of the optically transparent non-volatile transistor memory is as follows:

[0042] First, a commercially purchased glass substrate with patterned indium tin oxide source-drain electrodes was cleaned with Decon90 alkaline detergent and then ultrasonically cleaned three times with deionized water for 3 minutes each time to make it clean; and then placed in an oven and dried at 120°C for 30 minutes to remove residual moisture.

[0043] Then, a polymer semiconductor poly{2,2'-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diacyl)]disulfanyl-5,5'-diacylthiophene[3,2-b]thiophene-2,5-diacyl} was dissolved in chlorobenzene to prepare a solution with a concentration of 0.5% (mass percentage). The solution was dropwise applied to a clean, dried glass substrate with source-drain electrodes. A polymer semiconductor layer was prepared by spin coating at a speed of 1500 rpm. The spin-coated semiconductor layer was then annealed at 120°C for 60 minutes in a nitrogen atmosphere to remove any residual solvent.

[0044] A ferroelectric polymer, poly(vinylidene fluoride-polyethylene trifluoride), was dissolved in butyl acetate to a concentration of 6% (mass percentage) to prepare a solution. The prepared poly(vinylidene fluoride-polyethylene trifluoride) solution was then dropped onto the semiconductor layer. A poly(vinylidene fluoride-polyethylene trifluoride) thin film was then spin-coated at a speed of 2000 rpm to form the ferroelectric gate insulating layer. The substrate, with the ferroelectric gate insulating layer, was then annealed in an oven at 145°C for 120 minutes to remove any residual solvent.

[0045] A commercially available poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate stock solution was diluted with methanol to produce a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution. The dilution ratio of the stock solution to methanol was 1:30. This poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution was drop-coated onto the surface of the ferroelectric gate insulating layer to form a gate electrode. The substrate with the gate electrode film was then annealed in an oven at 120°C for 30 minutes to remove any residual solvent.

[0046] Finally, a silicon mask was placed over the gate electrode surface, and oxygen plasma etching was used to remove the excess polymer semiconductor layer, ferroelectric gate insulator layer, and gate electrode region. The resulting polymer semiconductor layer, ferroelectric gate insulator layer, and gate electrode were patterned to create an optically transparent nonvolatile transistor memory. The plasma etching took two minutes. The resulting device had a channel length and width of 100 microns and 1000 microns, respectively.

[0047] Example 2

[0048] This embodiment provides an optically transparent non-volatile transistor memory having a top-gate structure, which is composed of a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer, and a gate electrode from bottom to top.

[0049] The substrate is polyethylene terephthalate covered with patterned indium tin oxide, which is purchased from the market; the source-drain electrode is a patterned indium tin oxide film with a thickness of 120 nanometers; the polymer semiconductor layer is poly[(5-fluoro-2,1,3-benzothiazole-4,7-diacyl)(4,4-hexadecyl-4H-cyclopenta[2,1-b:3,4-b']dithiophene-2,6-diacyl)(6-fluoro-2,1,3 -benzothiadiazole)-4,7-diacyl)(4,4-hexadecyl-4H-cyclopentane[2,1-b:3,4-b']dithiophenyl-2,6-diacyl)] film with a thickness of 130 nanometers; the ferroelectric gate insulating layer is a vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer film with a thickness of 750 nanometers; the gate electrode is a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate film with a thickness of 150 nanometers.

[0050] The preparation process of the optically transparent non-volatile transistor memory is as follows:

[0051] First, a commercially purchased polyethylene terephthalate flexible substrate with patterned indium tin oxide source-drain electrodes was cleaned with Decon90 alkaline detergent and then ultrasonically cleaned three times with deionized water for 3 minutes each to clean it. The substrate was then placed in an oven and dried at 120°C for 30 minutes to remove any residual moisture.

[0052] Then, the polymer semiconductor poly[(5-fluoro-2,1,3-benzothiazol-4,7-diacyl)(4,4-hexacosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophene-2,6-diacyl)(6-fluoro-2,1,3-benzothiadiazole)-4,7-diacyl)(4,4-hexacosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophenyl-2,6-diacyl)] was dissolved in chlorobenzene to form a solution with a concentration of 1% (mass percentage). The solution was dropwise applied to a clean, dried flexible polyethylene terephthalate substrate with source-drain electrodes, and a semiconductor layer was formed by doctor blade coating at a rate of 5 mm / s. The substrate with the polymer semiconductor layer was then placed in a nitrogen atmosphere and annealed at 120°C for 80 minutes to remove any residual solvent.

[0053] A ferroelectric material, vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer, was dissolved in butyl acetate to a concentration of 7% (mass percentage) to prepare a solution. The prepared vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer solution was dripped onto the semiconductor layer and a thin film of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer was formed as a ferroelectric gate insulating layer using a spin coating process at a speed of 1500 rpm. The substrate with the ferroelectric gate insulating layer was then annealed in an oven at 120°C for 120 minutes to remove any residual solvent.

[0054] A commercially available poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate stock solution was diluted with methanol to produce a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution. The dilution ratio of the stock solution to methanol was 1:40. This poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate solution was drop-coated onto the surface of the ferroelectric gate insulating layer to form a gate electrode. The substrate with the gate electrode film was then annealed in an oven at 120°C for 30 minutes to remove any residual solvent.

[0055] Finally, a silicon mask was placed over the gate electrode surface, and oxygen plasma etching was used to remove the excess polymer semiconductor layer, ferroelectric gate insulator layer, and gate electrode region. The resulting polymer semiconductor layer, ferroelectric gate insulator layer, and gate electrode were patterned to create an optically transparent nonvolatile transistor memory. The plasma etching took three minutes. The resulting device had a channel length and width of 100 and 1000 microns, respectively.

[0056] Performance testing:

[0057] The electrical properties of the fabricated optically transparent nonvolatile memory were tested using an Agilent B1500A semiconductor test analyzer. All tests were conducted at room temperature and in an atmospheric environment. The optical properties of the fabricated optically transparent nonvolatile memory were tested using a UV-1700 ultraviolet-visible photometer.

[0058] The optical transparency characteristics of the optically transparent non-volatile transistor memory provided by Example 1 of the present invention in the visible light region are as follows: Figure 2 As shown; the optically transparent non-volatile transistor memory provided in Example 1 has the source-drain current-gate voltage transfer characteristics under darkroom environment, red light, green light and blue light irradiation respectively as shown Figure 3 As shown; the storage cycle characteristics of the optically transparent non-volatile transistor memory provided in Example 1 are as shown Figure 4 As shown; the optically transparent non-volatile transistor memory provided in Example 1 has a persistent storage retention time characteristic as shown Figure 5 shown

[0059] from Figure 2 It can be seen that the optically transparent non-volatile transistor memory provided by the present invention has significant optical transparency characteristics in the visible light region; wherein, at a wavelength of 550 nanometers, the optically transparent non-volatile transistor memory of the present invention has a light transmittance of up to 87%. Figure 3 It can be seen that the optically transparent non-volatile transistor memory provided by the present invention has a significant hysteresis characteristic in the source-drain current-gate voltage transfer characteristics tested in a bidirectional gate voltage scanning range, indicating that it has a significant information storage function; and under different wavelengths of light, the source-drain current-gate voltage transfer characteristics tested are highly repeatable with the source-drain current-gate voltage transfer characteristics tested in a darkroom environment, indicating that the optically transparent non-volatile transistor memory provided by the present invention has good optical stability. Figure 4It can be seen that after the optically transparent transistor memory is erased / written using a gate voltage of positive / negative 70 volts, the memory obtains two distinct levels of source-drain current, corresponding to the binary storage states 0 and 1 respectively; in the actual 400-cycle erase-write memory cycle endurance measurement, the source-drain current representing the binary storage states 0 and 1 has no obvious attenuation; this indicates that the optically transparent non-volatile transistor memory has good working reliability. Figure 5 It can be seen that in the actual 50,000-second storage retention time characteristic test, the source-drain current representing the binary storage states of 0 and 1 did not show obvious attenuation; this shows that the optically transparent non-volatile transistor memory has good working stability.

[0060] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. An optically transparent non-volatile transistor memory, characterized in that It is a top-gate structure, which consists of a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer and a gate electrode from bottom to top; the substrate, source-drain electrode, polymer semiconductor layer, ferroelectric gate insulating layer and gate electrode are all made of optically transparent materials, and the polymer semiconductor layer, ferroelectric gate insulating layer and gate electrode are all prepared by a solution method; The substrate is optically transparent glass, or optically transparent polyethylene terephthalate, polyethylene naphthalate or polyethersulfone; The source-drain electrode is a transparent indium tin oxide film; The ferroelectric gate insulating layer is a transparent ferroelectric polymer, specifically poly (vinylidene fluoride-polyethylene trifluoride), or vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer; The thickness of the source-drain electrode is 40-120 nanometers, the thickness of the polymer semiconductor layer is 10-150 nanometers, the thickness of the ferroelectric gate insulating layer is 100-1000 nanometers, and the thickness of the gate electrode is 100-1000 nanometers; The gate electrode is poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate.

2. The optically transparent non-volatile transistor memory according to claim 1, wherein: The polymer semiconductor layer is a polymer semiconductor film, specifically poly{2,2'-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diacyl)]disulfanyl-5,5'-diacylthiophene[3,2-b]thiophene-2,5-diacyl}, 3-hexyl substituted polythiophene, {[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-5,5'-(2,2'- dithiophene)} copolymer, (9,9-octylfluorene-benzothiadiazole) copolymer or poly[(5-fluoro-2,1,3-benzothiazol-4,7-diacyl)(4,4-hexacosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophene-2,6-diacyl)(6-fluoro-2,1,3-benzothiadiazole)-4,7-diacyl)(4,4-hexacosyl-4H-cyclopenta[2,1-b:3,4-b']dithiophenyl-2,6-diacyl)].

3. The method for preparing an optically transparent non-volatile transistor memory according to claim 1, wherein: The specific steps are as follows: on an optically transparent substrate with patterned indium tin oxide, a polymer semiconductor layer, a ferroelectric gate insulating layer and a gate electrode are sequentially prepared using a solution process; wherein the patterned indium tin oxide serves as the source-drain electrode. Finally, a silicon mask combined with oxygen plasma etching is used to pattern the prepared polymer semiconductor layer, ferroelectric gate insulating layer and gate electrode to obtain a non-volatile transistor memory.

4. The method for preparing an optically transparent non-volatile transistor memory according to claim 3, wherein: The solution method includes spin coating, doctor blade coating or drop coating.

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