switch

Abstract

The present invention discloses a switch, comprising a plurality of cache queues, a plurality of egress ports and a cache scheduler. Each egress port has a plurality of egress queues, and each egress queue of each egress port is connected to a different one of the cache queues. The switch generates an urgency for each egress queue of each egress port, and the urgency is used to reflect the extent to which the corresponding egress queue is about to run out of packets to send, and the urgency of forwarding packets of the cache queue is determined according to the urgency of each egress queue to which it is linked. The cache scheduler selects a cache queue to send the stored packets to the target egress queue of the target egress port to be sent according to the urgency of forwarding packets of each cache queue.

Description

Technical Field

[0001] The invention relates to a scheduling method, and in particular to a scheduling method for a switch. Background Art

[0002] When the switch forwards packets, in order to distinguish the transmission order of different data streams, the egress port will have multiple egress queues. Each egress queue is used to store packets of different priorities, and different egress queue weights are assigned to determine the transmission ratio of packets of different priorities. In other words, the egress port can use the scheduler to decide which egress queue to select for sending packets, and according to the egress queue weight, decide how many packets to grab from the selected egress queue for transmission.

[0003] like Figure 1 As shown, the egress port P0 has two egress queues Q0 and Q1 for storing packets with priorities S1 and S2 respectively, and when the egress queue weights of the egress queues Q0 and Q1 of the egress port P0 are 1 and 2 respectively, that is, {Q0:Q1}=1:2, the scheduler 10 of the egress port P0 decides to grab a packet with priority S1 from the egress queue Q0 of the egress port P0 for transmission, and decides to grab two packets with priority S2 from the egress queue Q1 of the egress port P0 for transmission according to the egress queue weights. If the scheduler of the egress port wants to grab packets from the selected egress queue, but encounters that the selected egress queue has no packets to send, the scheduler will grab packets in the next egress queue for transmission, so that the egress queue weights are unbalanced.

[0004] In addition, forwarding packets can be divided into unicast, multicast and broadcast. Unicast means that a packet can only be sent to a single egress queue and a single egress port, while multicast and broadcast mean that a packet can be sent to multiple egress queues and multiple egress ports. In order to save memory space for storing forwarding packets, high-bandwidth switches generally adopt a central memory architecture for all egress queues to share, but this architecture is limited by the bandwidth capacity of the memory. Therefore, for multicast / broadcast packets, the switch needs to spend multiple times to send the multicast / broadcast packets to multiple egress queues of the multiple egress ports to which it needs to go. In order to make up for this part of the low efficiency in operation, the switch is designed to store multicast / broadcast packets in the central absorb memory. At the same time, in order to respond to the egress queue weight of the egress queue, the central absorb memory can be configured with multiple absorb queues and a cache scheduler.

[0005] Each cache queue is also used to store packets of different priorities, and different cache queue weights are assigned to determine the transmission ratio of packets of different priorities. Generally speaking, there is a corresponding relationship between the cache queue and the egress queue, so that packets can be sent from the cache queue to the corresponding egress queue, and the cache scheduler sends the packets in the cache queue to the egress queue of the desired egress port according to the cache queue weight. Figure 2 As shown, cache queue AQ0 is connected to the egress queue Q0 of the egress ports P0, P1 and P2, and cache queue AQ1 is connected to the egress queue Q1 of the egress ports P0, P1 and P2. Cache queue AQ0 stores two packets, the first packet is to be sent to the egress queue Q0 of the egress ports P0 and P1, and the second packet is to be sent to the egress queue Q0 of the egress ports P0 and P2. In addition, cache queue AQ1 also stores two packets, but both packets are to be sent to the egress queue Q1 of the egress ports P0, P1 and P2. For the convenience of the following description, Figure 2 The storage state of the packets in the buffer queues AQ0 and AQ1 after being sent to the egress queues of the egress ports to which they are to be sent by the buffer scheduler 13 is shown.

[0006] In order not to affect the egress queue weights of the egress queues, the cache scheduler 13 may configure appropriate cache queue weights for the cache queues AQ0 and AQ1. Figure 3A As shown, when the cache queues AQ0 and AQ1 store packets to be sent to the egress port P0, and the egress queue weights of the egress queues Q0 and Q1 of the egress port P0 are 1 and 8 respectively, the cache scheduler 13 can configure the cache queue weights of the cache queues AQ0 and AQ1 to be 1 and 8 respectively, that is, {AQ0:AQ1}=1:8. Similarly, Figure 3B As shown, when cache queues AQ0 and AQ1 store packets to be sent to egress port P1, and the egress queue weights of egress queues Q0 and Q1 of egress port P1 are 8 and 1 respectively, the cache scheduler 13 can configure the cache queue weights of cache queues AQ0 and AQ1 to be 8 and 1 respectively, that is, {AQ0:AQ1}=8:1.

[0007] In addition, if Figure 3CAs shown, when the cache queues AQ0 and AQ1 store packets to be sent to the egress ports P1 and P2, and the egress queue weights of the egress queues Q0 and Q1 of the egress port P2 are 4 and 1 respectively, the cache scheduler 13 will take the average of the egress queue weights of the egress queue Q0 of the egress port P1 and the egress queue weights of the egress queue Q0 of the egress port P2 as the cache queue weight of the cache queue AQ0, and take the average of the egress queue weights of the egress queue Q1 of the egress port P1 and the egress queue weights of the egress queue Q1 of the egress port P2 as the cache queue weight of the cache queue AQ1, that is, {AQ0:AQ1}={(8+4) / 2:(1+1) / 2}=6:1. That is to say, when the cache scheduler 13 serves multiple egress ports and the egress queue weights configured for these egress ports are consistent, the cache queue weights of cache queues AQ0 and AQ1 can have a simple configuration basis. However, when the egress queue weights configured for multiple egress ports served by the cache scheduler 13 are very different, the cache scheduler 13 will not be able to configure a suitable cache queue weight.

[0008] like Figure 3D As shown, because the {Q0:Q1} of the egress port P0 and the {Q0:Q1} of the egress port P1 are averaged to 1:1, that is, {AQ0:AQ1}={(1+8) / 2:(8+1) / 2}=1:1, the cache queues AQ0 and AQ1 store packets to be sent to the egress ports P0 and P1 at a ratio of 1:1, but the scheduler 10 of the egress port P0 expects to send the packets of the egress queues Q0 and Q1 of the egress port P0 at a ratio of 1:8, so that the packets of the egress queue Q1 of the egress port P0 will be sent faster, and it is easy to cause the egress queue Q1 of the egress port P0 to be empty and have no packets to send, and once the egress queue is empty, the weight of the egress queue will be unbalanced. Therefore, how to design a scheduling method for a switch to avoid the imbalance of the egress queue weight has become an important issue in the field. Summary of the invention

[0009] In view of this, an embodiment of the present invention provides a scheduling method for forwarding packets, which is used in a switch including multiple cache queues, multiple egress ports and a cache scheduler. Each egress port has multiple egress queues, and each egress queue of each egress port is connected to a different one of these cache queues, and the scheduling method includes the following steps. First, an urgency is generated for each egress queue of each egress port, and the urgency is used to reflect the extent to which the corresponding egress queue is about to run out of packets to send. Then, according to the urgency of each egress queue, the cache scheduler selects one of these cache queues to send the stored packets to the target egress queue of the target egress port to be sent.

[0010] In addition, an embodiment of the present invention further provides a switch, including multiple cache queues, multiple egress ports, and a cache scheduler. Each egress port has multiple egress queues, and each egress queue of each egress port is connected to a different one of these cache queues. The switch can generate an urgency for each egress queue of each egress port, and the urgency is used to reflect the extent to which the corresponding egress queue is about to run out of packets to send. The cache scheduler selects one of these cache queues to send the stored packets to the target egress queue of the target egress port to be sent according to the urgency of each egress queue.

[0011] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing how the egress port uses the scheduler to determine how many packets to grab from the egress queue for transmission based on the egress queue weight.

[0013] Figure 2 It is a schematic diagram of a packet in a cache queue being sent to an egress queue of an egress port to which it is to be sent through an existing cache scheduler.

[0014] FIG. 3A to FIG. 3D It is a schematic diagram of configuring cache queue weights for cache queues by an existing cache scheduler.

[0015] Figure 4 It is a flowchart of the steps of the scheduling method provided by an embodiment of the present invention.

[0016] Figure 5 The switch provided by the embodiment of the present invention uses Figure 4 A first schematic diagram of a scheduling method.

[0017] Figure 6 The switch provided by the embodiment of the present invention uses Figure 4 A second schematic diagram of the scheduling method.

[0018] Figure 7 The switch provided by the embodiment of the present invention uses Figure 4 A third schematic diagram of the scheduling method.

[0019] Figure 8 The switch provided by the embodiment of the present invention uses Figure 4 A fourth schematic diagram of a scheduling method. DETAILED DESCRIPTION

[0020] The following is an explanation of the implementation of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementations will further explain the relevant technical content of the present invention in detail, but the content provided is not intended to limit the scope of protection of the present invention.

[0021] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0022] Please also see Figure 4 and Figure 5 , Figure 4 is a flowchart of the steps of the scheduling method provided by an embodiment of the present invention, Figure 5 The switch provided by the embodiment of the present invention uses Figure 4 The first schematic diagram of the scheduling method. Figure 5 As shown, the switch 5 may include a plurality of cache queues, a plurality of egress ports, and a cache scheduler 53. As described above, each cache queue is used to store packets of different priorities, each egress port has a plurality of egress queues, and each egress queue of each egress port is connected to a different one of the cache queues to also store packets of different priorities.

[0023] To facilitate the following description, Figure 5 Only two cache queues AQ0 and AQ1 and three egress ports are taken as an example, but the present invention is not limited thereto. Figure 5 Each egress port of the switch 5 has two egress queues Q0 and Q1, and the egress queues Q0 and Q1 of each egress port are connected to the buffer queues AQ0 and AQ1 respectively to store packets of different priorities. In addition, the switch 5 can generate an urgency Qn_URG for each egress queue of each egress port. Figure 5 For example, n is 0 or 1, and the urgency Qn_URG is used to reflect the degree to which the corresponding egress queue Qn is about to run out of packets to send.

[0024] In practice, each egress queue can be configured with two thresholds, namely, a high threshold THR_HIGH and a low threshold THR_LOW. Then, the switch 5 can use the number of packets currently accumulated in each egress queue as its queue usage, and generate an urgency Qn_URG based on the comparison result between the number of packets and the two thresholds. For example, when the number of packets currently accumulated in the egress queue Q0 of the egress port P1 is less than or equal to the low threshold THR_LOW, the switch 5 can generate an urgency Q0_URG with a value of 1 for the egress queue Q0 of the egress port P1.

[0025] In addition, when the number of packets currently accumulated in the egress queue Q1 of the egress port P0 is greater than the low threshold THR_LOW and less than or equal to the high threshold THR_HIGH, the switch 5 may generate an urgency Q1_URG with a value of 2 for the egress queue Q1 of the egress port P0. In contrast, when the number of packets currently accumulated in the egress queue Q0 of the egress port P0 is greater than the high threshold THR_HIGH, the switch 5 may generate an urgency Q0_URG with a value of 3 for the egress queue Q0 of the egress port P0, but the present invention is not limited thereto. In summary, in this embodiment, the urgency Qn_URG of each egress queue may be generated based on the comparison result between its queue usage and at least one threshold, and this embodiment assumes that the lower the urgency Qn_URG value, the sooner the corresponding egress queue Qn will have no packets to send.

[0026] On the other hand, when the number of packets currently accumulated in each egress queue is the same, the egress queue Qn with a faster flow rate will soon have no packets to send. Therefore, in other embodiments, the urgency Qn_URG of each egress queue can also be generated based on the comparison result of its queue usage and flow rate. Anyway, as long as the urgency Qn_URG is determined by the queue usage, it can meet the technical spirit of the present invention. Similarly, the switch 5 uses the number of packets as the queue usage for example only, and the present invention does not limit the specific implementation method of the switch 5 calculating the queue usage. In other embodiments, the switch 5 can also use the byte count as the queue usage. Anyway, as long as the cache scheduler 53 schedules the cache queue according to the queue usage of each egress queue, it can meet the technical spirit of the present invention. That is, according to the urgency Qn_URG of each egress queue, the cache scheduler 53 can select one of the multiple cache queues to send the stored packets to the target egress queue of the target egress port to be sent.

[0027] In this embodiment, each egress queue can return the urgency Qn_URG to the connected buffer queue AQn. Then, according to the urgency Qn_URG of each egress queue, the switch 5 can determine a packet forwarding urgency AQn_URG of each buffer queue, and the packet forwarding urgency AQn_URG is used to reflect the urgency of the corresponding buffer queue AQn in sending out the packets stored therein. Figure 5 For example, the egress queues Q0 of the egress ports P0, P1 and P2 respectively return urgency Q0_URG values ​​of 3, 1 and 3 to the connected buffer queue AQ0, and the switch 5 can select the urgency Q0_URG with the lowest value as the forwarding packet urgency AQ0_URG of the buffer queue AQ0, that is, AQ0_URG = 1. It should be understood that in order to reflect the degree of urgency of the buffer queue AQ0 to send out packets, the switch 5 selects the urgency Q0_URG with the lowest value as the forwarding packet urgency AQ0_URG of the buffer queue AQ0, but the present invention is not limited thereto.

[0028] Similarly, the egress queues Q1 of the egress ports P0, P1 and P2 respectively return urgency levels Q1_URG of 2, 3 and 3 to the connected buffer queue AQ1, and the switch 5 can select the urgency level Q1_URG with the lowest value as the forwarding packet urgency level AQ1_URG of the buffer queue AQ1, i.e. AQ1_URG=2. Figure 5 For example, if the forwarding packet urgency AQ0_URG is 1 and the forwarding packet urgency AQ1_URG is 2, the cache scheduler 53 will prioritize the cache queue AQ0 to send the stored packets to the egress queue Q0 of the egress port Pm to which it is to go. Figure 5 For example, m is 0, 1 or 2, depending on which egress port the outgoing packet needs to go to. That is, according to the forwarding packet urgency AQn_URG of each cache queue, the cache scheduler 53 can select the cache queue that needs to send out the packet most urgently for scheduling.

[0029] The present invention does not limit the specific implementation of the cache scheduler 53, and for the convenience of the following description, the cache scheduler 53 in the accompanying drawings will mostly be represented by a frame between the cache queue and the egress queue. In addition, each time a packet is sent from the cache queue AQn to the egress queue Qn, the queue usage of the egress queue Qn will change, thereby affecting the urgency Qn_URG of the egress queue Qn, and also affecting the forwarding packet urgency AQn_URG of the cache queue AQn. Therefore, each egress queue will always return the urgency Qn_URG to the connected cache queue AQn, so that the forwarding packet urgency AQn_URG of the cache queue AQn is always updated, and when the cache scheduler 53 is to schedule multiple cache queues, the cache scheduler 53 can use the most timely forwarding packet urgency AQn_URG as the selection basis.

[0030] It can be seen that compared with the prior art, the cache scheduler 53 does not need to configure cache queue weights for cache queues AQ0 and AQ1, nor does it need to schedule cache queues AQ0 and AQ1 based on cache queue weights. Instead, cache queues AQ0 and AQ1 can be scheduled based on the queue usage of each egress queue. Figure 4 As shown, in step S410, the switch 5 can generate an urgency Qn_URG for each egress queue of each egress port, and the urgency Qn_URG is used to reflect the degree to which the corresponding egress queue Qn is about to run out of packets to send. Then, in step S430, according to the urgency Qn_URG of each egress queue, the cache scheduler 53 can select one of the multiple cache queues to send the stored packets to the target egress queue of the target egress port to be sent.

[0031] As mentioned above, since each egress queue can return the urgency Qn_URG to the connected buffer queue AQn, Figure 4 The method may further include step S420, but step S420 may be omitted. In step S420, according to the urgency Qn_URG of each connected egress queue, the switch 5 may determine the forwarding packet urgency AQn_URG of each cache queue, and the forwarding packet urgency AQn_URG is used to reflect the degree to which the corresponding cache queue AQn urgently needs to send out the packets stored therein. Relatively speaking, "according to the urgency Qn_URG of each egress queue, the cache scheduler 53 selects one of the multiple cache queues" in step S430 may mean that according to the forwarding packet urgency AQn_URG of each cache queue, the cache scheduler 53 selects the cache queue that most urgently needs to send out packets. Since the details have been described in the aforementioned content, they will not be repeated here.

[0032] On the other hand, when the cache scheduler 53 selects one of the multiple cache queues, if the forwarding packet urgency of two or more of the cache queues reflects that the corresponding cache queues need to send packets most urgently, the cache scheduler 53 selects one of the corresponding cache queues in a round-robin or random manner. Figure 6 For example, n is changed to 0, 1 or 2. That is, each egress port has three egress queues Q0, Q1 and Q2, and the egress queues Q0, Q1 and Q2 of each egress port are connected to the cache queues AQ0, AQ1 and AQ2 respectively. Therefore, when the forwarding packet urgency AQ0_URG and AQ1_URG are both 1, and the forwarding packet urgency AQ2_URG is 2, the cache scheduler 53 should prioritize the cache queues AQ0 and AQ1. Conceptually, Figure 6 The cache scheduler 53 can schedule the cache queues AQ0 and AQ1 in turn, and only schedules the cache queue AQ0 or AQ1 each time to send a packet stored therein to the egress queue Q0 or Q1 of the egress port Pm to which it is to go. However, in fact, because the change of the urgency Qn_URG will affect the selection result of the cache scheduler 53, Figure 6 The cache scheduler 53 may also select the cache queue AQ0 or AQ1 in a random manner to send a packet stored therein to the egress queue Q0 or Q1 of the egress port Pm to which it is to go.

[0033] From another perspective, if a single cache queue is favored and the stored packets are always sent to a certain egress queue, other egress queues may be left idle with no packets to send, resulting in an imbalance in the weight of the egress queues. Figure 6 For example, the packet forwarding urgency AQ0_URG and AQ1_URG are determined according to the urgency Q0_URG of the egress queue Q0 of the egress port P1 and the urgency Q1_URG of the egress queue Q1 of the egress port P0, respectively. Therefore, if the cache scheduler 53 preferentially schedules the cache queue AQ0 to send the stored packets to the egress queue Q0 of the egress port P1, and the egress queue weight of the egress queue Q0 of the egress port P1 is relatively large, or even has a strict priority (SP), the egress queue Q0 of the egress port P1 will be always scheduled by the scheduler 51 of the egress port P1, so that the packet forwarding urgency AQ0_URG may always be 1, and the cache scheduler 53 will always schedule the cache queue AQ0, and there is no chance to schedule the cache queue AQ1, so that the egress queue Q1 of the egress port P0 is prone to have no packets to send.

[0034] In addition, in this embodiment, the urgency Qn_URG is 1, which means that the number of packets currently accumulated in the corresponding egress queue Qn is less than or equal to the low threshold THR_LOW, and there are two situations that cause the number of packets accumulated in the egress queue Qn to be less than or equal to the low threshold THR_LOW. The first situation is that the packets accumulated in the egress queue Qn are almost delivered, so the cache queue AQn urgently needs to deliver packets to the egress queue Qn, and the second situation is that no packets have been delivered to the egress queue Qn, so the cache scheduler 53 can temporarily suspend scheduling the cache queue AQn. Figure 7 For example, each cache queue of the central cache memory 64 may further count packets sent to each egress port, and determine a meaningless state value PmQn_EMP_STA of each egress queue of each egress port according to the counting result.

[0035] For example, when the cache queue AQn counts the packets sent to the egress port Pm, and the result of the count is equal to 0, the present embodiment determines that the meaningless status value PmQn_EMP_STA of the egress queue Qn of the egress port Pm is established (TRUE). Conversely, when the cache queue AQn counts the packets sent to the egress port Pm, and the result of the count is not equal to 0, the present embodiment determines that the meaningless status value PmQn_EMP_STA of the egress queue Qn of the egress port Pm is not established (FALSE). In other words, the meaningless status value PmQn_EMP_STA can be used to indicate whether no packets are sent to the egress queue Qn of the egress port Pm. Figure 7 As shown, the buffer queue AQ0 will only send packets to the egress ports P0 and P2, but not to the egress port P1. Therefore, the meaningless status values ​​P0Q0_EMP_STA and P2Q0_EMP_STA of the egress queue Q0 of the egress ports P0 and P2 are both FALSE, and the meaningless status value P1Q0_EMP_STA of the egress queue Q0 of the egress port P1 is TRUE.

[0036] in addition, Figure 7Each cache queue may be further configured with a logic circuit for receiving the meaningless state value PmQn_EMP_STA and the returned urgency Qn_URG of each egress queue of each egress port connected to the corresponding cache queue AQn, so as to determine the forwarding packet urgency AQn_URG of the cache queue AQn, and transmit the forwarding packet urgency AQn_URG of the cache queue AQn to the cache scheduler 53. In this embodiment, each logic circuit uses the meaningless state value PmQn_EMP_STA to pre-process the urgency Qn_URG of the egress queue Qn of the egress port Pm, so as to exclude the situation that the corresponding cache queue AQn has never sent a packet to the egress queue Qn. That is, according to the meaningless state value PmQn_EMP_STA, the logic circuit can adjust the returned urgency Qn_URG of the egress queue Qn of the egress port Pm.

[0037] For example, when the meaningless status value PmQn_EMP_STA is TRUE, the logic circuit may adjust the urgency Qn_URG of the egress queue Qn of the egress port Pm to a special value, such as 4, to indicate that the egress queue Qn of the egress port Pm does not need the service of the buffer queue AQn. Figure 7 As shown, because the meaningless state value P1Q0_EMP_STA is TRUE, the logic circuit 65 can adjust the urgency Q0_URG of the egress queue Q0 of the egress port P1 from 1 to 4. In this way, according to the urgency Q0_URGs returned by the egress queues Q0 of the egress ports P0 and P2 as 3 and 3 respectively, and the adjusted urgency Q0_URG of the egress queue Q0 of the egress port P1 as 4, the logic circuit 65 can select the urgency Q0_URG with the lowest value as the forwarding packet urgency AQ0_URG of the buffer queue AQ0, that is, AQ0_URG = 3. Since the details have been described in the above content, they will not be repeated here.

[0038] On the other hand, it can be seen from the above content that the threshold will affect the corresponding value of the urgency Qn_URG, so in practice, the present invention can use factors such as link speed, rate limit, egress queue weight, and whether the egress queue is assigned SP as the basis for configuring the threshold. Figure 8 For example, although the connection speeds of the egress ports P0, P1, and P2 are all 1 Gbps, the egress queue Q1 of the egress port P2 is assigned to the SP to be selected to transmit packets first, so it can be expected that the egress queue Q1 of the egress port P2 will not accumulate too many packets, and thus its threshold needs to be configured higher to allow the cache scheduler to more actively schedule packets to the egress queue Q1, such as the high threshold THR_HIGH and the low threshold THR_LOW of the egress queue Q1 of the egress port P2, to truly reflect the needs of the SP queue.

[0039] In addition, when the egress queue weights of the egress queues Q0 and Q1 of the egress port P0 are 1 and 8 respectively, the egress queue Q1 of the egress port P0 has an 8-fold chance of being selected to transmit packets than the egress queue Q0 of the egress port P0. Then, in order to maintain the packet transmission ratio of 1:8, the switch 5 hopes that there will always be packets accumulated in the egress queue Q1 of the egress port P0 waiting to be sent out. Therefore, the packet demand of the egress queue Q1 of the egress port P0 is greater than the packet demand of the egress queue Q0 of the egress port P0, and the threshold of the egress queue Q1 of the egress port P0 can be configured to be higher than the threshold of the egress queue Q0 of the egress port P0, so that the cache scheduler can more actively schedule packets to the egress queue Q1. In summary, the present invention does not limit the specific implementation method of configuring the threshold.

[0040] In summary, the switch provided by the embodiment of the present invention does not need to configure cache queue weights for cache queues, nor does it need to schedule cache queues based on cache queue weights. Instead, cache queues can be scheduled based on queue usage of each egress queue. Therefore, the present invention can meet the needs of different egress queues, and the egress queues that need packets for real-time service will not have an imbalance in the egress queue weights, and the cache scheduler can operate more efficiently.

[0041] The contents provided above are only preferred feasible embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are within the protection scope of the present invention.

[0042] Description of reference numerals:

[0043] 5: Switch

[0044] P0, P1, P2: export ports

[0045] Q0, Q1, Q2: egress queues

[0046] AQ0, AQ1, AQ2: Cache Queues

[0047] 10,11,12,50,51,52: Scheduler for egress ports

[0048] 13,53: Cache Scheduler

[0049] THR_HIGH,THR_LOW:Threshold

[0050] Q0_URG, Q1_URG, Q2_URG: Urgency

[0051] AQ0_URG, AQ1_URG, AQ2_URG: urgency of forwarding packets

[0052] S410~S430: Process steps

[0053] 64: Central Cache Memory

[0054] P0Q0_EMP_STA~P2Q0_EMP_STA: meaningless status value

[0055] 65,66,67: Logic circuits

Claims

1. A switch, comprising: Multiple cache queues; a plurality of egress ports, each of the egress ports having a plurality of egress queues, each of the egress queues of the egress ports being connected to a different one of the buffer queues, wherein the switch generates an urgency for each of the egress queues of the egress ports, and the urgency is used to reflect the extent to which the corresponding egress queue is about to run out of packets to send; as well as a cache scheduler, which selects one of the cache queues to send the stored packets to a target egress queue of a target egress port according to the urgency of each egress queue, Each of the egress queues transmits the urgency back to the connected cache queue, and the switch is further used for: According to the urgency of each of the egress queues connected, a packet forwarding urgency of each of the buffer queues is determined, and the packet forwarding urgency is used to reflect the degree to which the corresponding buffer queue urgently needs to send out the stored packets.

2. The switch according to claim 1, characterized in that: The urgency of each of the egress queues is generated according to a comparison result between the queue usage and at least one threshold.

3. The switch according to claim 1, characterized in that: The urgency of each of the egress queues is generated based on a comparison result between the queue usage and the flow rate.

4. The switch according to claim 3, characterized in that: The step of the cache scheduler selecting one of the cache queues according to the urgency of each of the egress queues comprises: According to the forwarding packet urgency of each of the cache queues, the cache scheduler selects the cache queue that most urgently needs to send out the packet.

5. The switch according to claim 4, characterized in that: When the cache queues have more than two packet forwarding urgency levels that reflect that the corresponding cache queues are most in need of sending out the packets, the cache scheduler selects one of the corresponding cache queues in a round-robin or random manner.

6. The switch according to claim 4, characterized in that: Each of the buffer queues further counts the packets sent to each of the egress ports, and determines a meaningless state value of each of the egress queues of each of the egress ports according to the counting result.

7. The switch according to claim 6, characterized in that: The meaningless status value is used to indicate whether the packet is not sent to the egress queue of the corresponding egress port.

8. The switch according to claim 7, characterized in that: Each of the cache queues is further configured with a logic circuit to adjust the urgency of the output sent back by the egress queue of the corresponding egress port according to the meaningless state value.

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