image sensor

Abstract

An image sensor is disclosed. The image sensor includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the pixels including: a photodiode; a floating diffusion node configured to accumulate photocharge generated by the photodiode; a first capacitor configured to store a charge according to a voltage of the floating diffusion node that is reset; a second capacitor configured to store a charge according to a voltage of the floating diffusion node in which photocharge is accumulated; a first sampling transistor connected to a first output node and configured to sample a charge to the first capacitor; a second sampling transistor connected to the first output node and configured to sample a charge to the second capacitor; and at least one pre-charge selection transistor connected to the first output node and configured to reset the first output node.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0120524 filed on September 18, 2020, and Korean Patent Application No. 10-2021-0046094 filed on April 8, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The exemplary embodiments of the present invention relate to an image sensor, and more specifically, to an image sensor capable of supporting global shutter mode driving. Background Technology

[0004] Image sensors, which capture images and convert them into electrical signals, are used not only in general consumer electronics devices such as digital cameras, portable phone cameras, and portable video cameras, but also in cameras installed in vehicles, security devices, and robots, and are not limited thereto.

[0005] Image sensors can adjust the exposure time to control the amount of photocharge on which the electrical signal is based. Image sensors can adjust the exposure time by using either a rolling shutter mode or a global shutter mode. In rolling shutter mode, the photocharge integration time is controlled differently for each row of the pixel array, while in global shutter mode, the photocharge integration time is controlled to be the same for different rows of the pixel array. Summary of the Invention

[0006] The present invention provides an image sensor that generates distortion-free images by controlling the photocharge integration time of pixels.

[0007] According to an embodiment, an image sensor is provided, the image sensor including pixels arranged in rows and columns, each pixel including: a photodiode; a floating diffusion node configured to accumulate photocharge generated by the photodiode; a first capacitor configured to store charge based on the voltage of a reset floating diffusion node; a second capacitor configured to store charge based on the voltage of a floating diffusion node in which photocharge has accumulated; a first sampling transistor connected to a first output node and configured to sample charge to the first capacitor; a second sampling transistor connected to the first output node and configured to sample charge to the second capacitor; and at least one precharge selection transistor connected to the first output node and configured to reset the first output node.

[0008] According to another embodiment, an image sensor is provided, the image sensor including a pixel array in which pixels are arranged, each of the pixels including: a photodiode; a floating diffusion node configured to accumulate photocharge generated by the photodiode; a first source follower configured to amplify the voltage of the floating diffusion node and output an amplified voltage; at least one precharge selection transistor connected in series with the first source follower; a precharge transistor connected in series with the first source follower and configured to precharge a first output node; a first capacitor configured to store charge according to the voltage of a reset floating diffusion node; a second capacitor configured to store charge according to the voltage of a floating diffusion node in which photocharge has accumulated; a first sampling transistor configured to sample the charge to the first capacitor; a second sampling transistor configured to sample the charge to the second capacitor; and a second source follower configured to output a pixel signal according to a potential change of the first output node connected to the first and second sampling transistors to a column line.

[0009] According to another embodiment of the present invention, an image sensor including a first pixel and a second pixel is provided. Each of the first pixel and the second pixel includes: a photodiode; a floating diffusion node configured to accumulate photocharge generated by the photodiode; a first source follower configured to amplify the voltage of the floating diffusion node and output the amplified voltage; a precharge transistor configured to precharge an output node; a first precharge selection transistor and a second precharge selection transistor configured to reset the output node; a first capacitor connected to the output node and configured to store charge based on the voltage of the reset floating diffusion node; a second capacitor connected to the output node and configured to store charge based on the voltage of the floating diffusion node in which photocharge has accumulated; and a second source follower configured to output a pixel signal based on the potential change of the output node to a column line, wherein the first pixel and the second pixel share the second precharge selection transistor and the second source follower. Attached Figure Description

[0010] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of an image sensor according to an embodiment;

[0012] Figure 2 The operation of the image sensor according to an embodiment in global shutter mode is illustrated;

[0013] Figures 3 to 7 This is a circuit diagram of pixels included in an image sensor according to an embodiment;

[0014] Figures 8 to 11This is a timing diagram of control signals and ramp signals provided to pixels of an image sensor according to an embodiment;

[0015] Figure 12 This is a circuit diagram of pixels included in an image sensor according to an embodiment;

[0016] Figure 13 This is a timing diagram of control signals and ramp signals provided to pixels of an image sensor according to an embodiment;

[0017] Figure 14 This is a circuit diagram of pixels included in an image sensor according to an embodiment;

[0018] Figure 15A and Figure 15B This is a circuit diagram of pixels included in an image sensor according to an embodiment;

[0019] Figure 16 The operation of the image sensor according to an embodiment in global shutter mode and rolling shutter mode is illustrated; and

[0020] Figure 17 This is a circuit diagram of pixels included in an image sensor according to an embodiment. Detailed Implementation

[0021] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The embodiments described herein are exemplary embodiments, and therefore, the inventive concept is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if something described in a particular example is not described in a different example, such content may be understood to be related to or combined with the different example, unless otherwise mentioned in its description.

[0022] It should be understood that although the terms first, second, third, fourth, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, region, layer, or portion. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0023] Figure 1 This is a block diagram of an image sensor according to an embodiment.

[0024] Image processing systems may include Figure 1The image sensor 100 and digital signal processor (DSP) (not shown) are illustrated. The image sensor 100 and DSP can be implemented as separate chips or as a single image sensor chip. The DSP can process signals based on image data. For example, the DSP can perform noise reduction processing, gain control, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, etc.

[0025] Reference Figure 1 The image sensor 100 may include a pixel array 110, a controller 120, a ramp signal generator 130, a line driver 140, and a readout circuit 150. For example, the readout circuit 150 may include a correlated double sampling (CDS) circuit 151, an analog-to-digital converter (ADC) 153, a buffer 155, etc.

[0026] The pixel array 110 may include a plurality of pixels PX. Each of the pixels PX may include a photoelectric conversion element, and generates a pixel signal corresponding to an object by converting sensed light into an electrical signal by the photoelectric conversion element. The pixels PX may output the pixel signal to the readout circuit 150 through corresponding first column lines CL0 to nth column lines CLn-1, respectively.

[0027] In pixel array 110, pixels PX can be arranged in a matrix of multiple rows and columns, and pixels PX can be active pixel sensors (APS).

[0028] According to an embodiment, each of the pixels PX may include one of a red color filter that transmits light in the red wavelength region, a green color filter that transmits light in the green wavelength region, and a blue color filter that transmits light in the blue wavelength region. However, this embodiment is not limited thereto; each of the pixels PX may include a color filter or a transparent color filter that transmits light in a wavelength region different from red, green, and blue. According to an embodiment, each of the pixels PX may include one of a white color filter, a cyan color filter, a magenta color filter, and a yellow color filter.

[0029] The controller 120 can control the operation of the line driver 140, the ramp signal generator 130, and the readout circuit 150. The controller 120 may include a control register block, which can control the operation of the line driver 140, the ramp signal generator 130, and the readout circuit 150 under the control of the DSP. According to an embodiment, the controller 120 can control the line driver 140, the ramp signal generator 130, and the readout circuit 150 to enable the image sensor 100 to operate in global shutter mode.

[0030] The row driver 140 can generate control signals CS for controlling the pixel array 110 and provide the control signals CS to each of the pixels PX. According to an embodiment, the row driver 140 can determine the activation and deactivation timing of the control signals CS for each of the pixels PX to operate in a global shutter mode.

[0031] A control signal CS can be generated corresponding to each row of the pixel array 110, enabling row-by-row control of the pixel array 110. The pixel array 110 can respond to the control signal CS provided from the row driver 140 by outputting a reset signal and an image signal from one or more selected rows to the readout circuit 150.

[0032] Ramp signal generator 130 can generate a ramp signal RAMP. The ramp signal RAMP is a signal used to convert an analog signal into a digital signal and can be generated as a triangular waveform. Ramp signal generator 130 can provide the ramp signal RAMP to a readout circuit 150, such as a CDS circuit 151.

[0033] The CDS circuit 151 can sample and hold pixel signals provided from the pixel array 110. The CDS circuit 151 can output a specific noise level; that is, it samples both the reset signal and the image signal and outputs a level corresponding to the difference between the sampled signals. Furthermore, the CDS circuit 151 can receive a ramp signal RAMP generated by the ramp signal generator 130, compare the ramp signal RAMP with the pixel signals, and output the comparison result. The ADC 153 can convert the analog signal corresponding to the level received from the CDS circuit 151 into a digital signal. The buffer 155 can latch the digital signal and sequentially output the latched image data ID.

[0034] Figure 2 The operation of the image sensor according to an embodiment in global shutter mode is illustrated.

[0035] Reference Figure 1 and Figure 2 The image sensor 100 can operate in global shutter mode. In global shutter mode, the image sensor 100 can perform a global signal dumping operation during the global signal dumping period (GSDP) and a readout operation during the readout period (ROP). The global signal dumping operation may include a reset operation to reset the charge accumulated in the floating diffusion node and an accumulation operation to accumulate the photocharge generated by the photoelectric conversion element during the integration time.

[0036] During the Global Signal Dump (GSDP) period, the image sensor 100 can be operated such that reset and accumulation operations are performed simultaneously on different rows of the pixel array 110 (e.g., the first row R1 to the i-th row Ri, where i is a natural number of 2 or greater). Figure 2 As shown. The integration time for performing the accumulation operation can indicate the time it takes to substantially accumulate the photocharge generated by the photoelectric conversion elements (e.g., photodiodes) included in each pixel PX.

[0037] During the readout period ROP, a rolling readout operation can be performed, sequentially executing readout operations for each row. The image sensor 100 is operable such that readout operations are sequentially executed from the first row R1 to the i-th row Ri during the readout time. The readout time can indicate the time at which a pixel signal corresponding to the photocharge generated by each pixel PX is output from each pixel PX.

[0038] The image sensor 100 according to an embodiment can operate in a global shutter mode to control the photocharge integration time point of pixels PX arranged in different rows to be the same, and to remove image distortion caused by differences in photocharge integration time periods. However, the image sensor 100 according to an embodiment can operate in a rolling shutter mode by switching operating modes. When the image sensor 100 operates in rolling shutter mode, the image sensor 100 can control the photocharge integration time point of the photodiodes to be different for each row of the pixel array 110. According to an embodiment, the integration time point can be the same for all rows, or it can be the same for rows in a specific group. The operating mode of the image sensor 100 can be set by a DSP.

[0039] Figure 3 and Figure 4 This is a circuit diagram of pixels included in an image sensor according to an embodiment.

[0040] Reference Figure 3 Pixel PX may include a photodiode PD and a pixel signal generation circuit PSC configured to generate pixel signal PXS. Control signals applied to the pixel signal generation circuit PSC (including transmission control signal TS, reset control signal RS, first precharge selection control signal PSEL1, second precharge selection control signal PSEL2, precharge control signal PC, first sampling control signal SAMPS1, second sampling control signal SAMPS2, and selection control signal SELS) may be some of the control signals CS generated by the line driver 140.

[0041] A photodiode (PD) can generate photocharge that varies according to the intensity of light. For example, a PD can generate a charge proportional to the intensity of incident light, i.e., electrons as negative charges and holes as positive charges. A PD is an example of a photoelectric conversion element and may include at least one of a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof.

[0042] The pixel signal generation circuit (PSC) may include multiple transistors, such as a transfer transistor TX, a reset transistor RX, a first source follower SF1, a precharge transistor PCX, a first precharge selection transistor PSX1, a second precharge selection transistor PSX2, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a second source follower SF2, and a selection transistor SX. The PSC may also include a first capacitor C1 and a second capacitor C2. In each of the first capacitor C1 and the second capacitor C2, charge accumulated according to a reset operation or charge accumulated according to a photocharge accumulation operation can be accumulated.

[0043] A transfer transistor TX can be connected between a photodiode PD and a floating diffusion node FD. The first terminal of the transfer transistor TX can be connected to the output of the photodiode PD, and the second terminal of the transfer transistor TX can be connected to the floating diffusion node FD. The transfer transistor TX can be turned on or off in response to a transfer control signal TS received from the row driver 140, and transfers the photocharge generated by the photodiode PD to the floating diffusion node FD. The floating diffusion node FD may have parasitic capacitance.

[0044] The reset transistor RX can reset the charge accumulated in the floating diffusion node FD. The pixel voltage VPIX can be applied to the first terminal of the reset transistor RX, and the second terminal of the reset transistor RX can be connected to the floating diffusion node FD. The reset transistor RX can be turned on or off in response to the reset control signal RS received from the row driver 140, and can discharge the charge accumulated in the floating diffusion node FD to reset the floating diffusion node FD.

[0045] The first source follower SF1 is a buffer amplifier that buffers signals based on the amount of charge charged into the floating diffusion node FD. The pixel voltage VPIX can be applied to the first terminal of the first source follower SF1, and the second terminal of the first source follower SF1 can be connected to the second output node NO2. The potential of the floating diffusion node FD can change according to the amount of charge charged into it, and the first source follower SF1 can amplify this potential change and output the amplified result to the second output node NO2.

[0046] The first terminal of the precharge transistor PCX can be connected to the second output node NO2, and the second terminal of the precharge transistor PCX can be connected to the second precharge selection transistor PSX2. The precharge transistor PCX can precharge the second output node NO2 in response to the precharge control signal PC received from the row driver 140.

[0047] A first precharge selection transistor PSX1 may be connected between a second output node NO2 and a first output node NO1. The first precharge selection transistor PSX1 may be turned on or off in response to a first precharge selection control signal PSEL1 received from the row driver 140, and may reset the first output node NO1. The first output node NO1 may have parasitic capacitance.

[0048] The first terminal of the second precharge selection transistor PSX2 can be connected to the precharge transistor PCX, and ground voltage can be applied to the second terminal of the second precharge selection transistor PSX2. The second precharge selection transistor PSX2 can be turned on or off in response to the second precharge selection control signal PSEL2 received from the row driver 140, and reset the second output node NO2. That is, the first source follower SF1, the precharge transistor PCX, and the second precharge selection transistor PSX2 can be connected in series.

[0049] The precharge transistor PCX can have a relatively large transistor size to operate as a current source. For example, the gate width or gate thickness of the precharge transistor PCX can be relatively large. In this case, because the capacitance of the precharge transistor PCX is also large, a significant amount of power may be consumed to turn the precharge transistor PCX on / off. That is, relatively high power can be consumed when resetting the second output node NO2 solely through the on / off operation of the precharge transistor PCX.

[0050] According to an embodiment, the pixel PX of the image sensor may include a second precharge selection transistor PSX2 connected in series with the precharge transistor PCX and having a smaller size than the precharge transistor PCX. For example, the gate width of the second precharge selection transistor PSX2 may be smaller than the gate width of the precharge transistor PCX, or the gate thickness of the second precharge selection transistor PSX2 may be smaller than the gate thickness of the precharge transistor PCX. Therefore, the precharge transistor PCX can operate as a current source by continuously remaining in an on state, and the second precharge selection transistor PSX2 can be controlled to be on / off, thereby controlling the operation of resetting the second output node NO2 while consuming relatively little power.

[0051] The first terminal of the first sampling transistor SAMP1 can be connected to the first output node NO1, and the second terminal of the first sampling transistor SAMP1 can be connected to the first capacitor C1. The first sampling transistor SAMP1 can be turned on or off in response to the first sampling control signal SAMPS1 received from the row driver 140, and the first capacitor C1 can be connected to the first output node NO1.

[0052] A pixel voltage VPIX can be applied to a first terminal of a first capacitor C1, and a second terminal of the first capacitor C1 can be connected to a first sampling transistor SAMP1. Charge can accumulate in the first capacitor C1 according to the switching operation of the first sampling transistor SAMP1. For example, charge can accumulate in the first capacitor C1 according to the reset operation of the reset floating diffusion node FD. However, compared with... Figure 3 Unlike the previous example, in the pixel PX of the image sensor, according to the embodiment, the first capacitor C1 can be connected to the first output node NO1, and the pixel voltage VPIX can be applied to or blocked from the first terminal of the first capacitor C1 according to the switching operation of the first sampling transistor SAMP1.

[0053] The first terminal of the second sampling transistor SAMP2 can be connected to the first output node NO1, and the second terminal of the second sampling transistor SAMP2 can be connected to the second capacitor C2. The second sampling transistor SAMP2 can be turned on or off in response to the second sampling control signal SAMPS2 received from the row driver 140, and the second capacitor C2 is connected to the first output node NO1.

[0054] A pixel voltage VPIX can be applied to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 can be connected to the second sampling transistor SAMP2. Charge can accumulate in the second capacitor C2 according to the switching operation of the second sampling transistor SAMP2. For example, charge can accumulate in the second capacitor C2 according to the photocharge accumulation operation of accumulating photoelectric charge generated by the photodiode PD in the floating diffusion node FD. However, with... Figure 3 Unlike the previous example, in the pixel PX of the image sensor, according to the embodiment, the second capacitor C2 can be connected to the first output node NO1, and the pixel voltage VPIX can be applied to or blocked from the first terminal of the second capacitor C2 according to the switching operation of the second sampling transistor SAMP2.

[0055] The pixel voltage VPIX can be applied to the first terminal of the second source follower SF2, and the second terminal of the second source follower SF2 can be connected to the selection transistor SX. The second source follower SF2 can amplify the potential change of the first output node NO1 and output the amplified result.

[0056] The first terminal of the selector transistor SX can be connected to the second source follower SF2, and the second terminal of the selector transistor SX can be connected to the column line CL. The column line CL can be... Figure 1 One of the first column line CL0 to the nth column line CLn-1. The selection transistor SX can be turned on or off in response to the selection control signal SELS received from the row driver 140. When the selection transistor SX is turned on, the reset signal RST corresponding to the reset operation or the image signal SIG corresponding to the photocharge accumulation operation can be output to the column line CL.

[0057] In other words, the second source follower SF2 and the selection transistor SX can output the pixel signal PXS, which changes according to the potential of the first output node NO1, to the column line CL, and output the pixel signal PXS corresponding to one of the charge stored in the first capacitor C1 and the charge stored in the second capacitor C2 to the column line CL.

[0058] In a pixel PX of the image sensor 100, according to an embodiment, both the first capacitor C1 and the second capacitor C2 can be connected to the first output node NO1 and the second source follower SF2. Therefore, compared to a comparative example where the first capacitor C1 and the second capacitor C2 are respectively connected to different source followers, the image sensor according to this embodiment can include a reduced number of transistors constituting the pixel. Furthermore, according to this embodiment, the pixel PX of the image sensor 100 can include a first precharge selection transistor PSX1 and a second precharge selection transistor PSX2, thereby effectively resetting the first output node NO1. The image sensor 100 can eliminate the offset that occurs between the reset signal RST according to the reset operation and the image signal SIG according to the photocharge accumulation operation due to residual charge in the first output node NO1.

[0059] Reference Figure 4 Pixel PX' may include a photodiode PD and a pixel signal generating circuit PSC' configured to generate a pixel signal PXS. (Refer to reference...) Figure 3 Compared to the described pixel signal generation circuit PSC, Figure 4 The pixel signal generation circuit PSC' may include a second precharge selection transistor PSX2, whose first terminal is connected to the second output node NO2 and whose second terminal is connected to the precharge transistor PCX. The pixel signal generation circuit PSC' includes a precharge transistor PCX, whose first terminal is connected to the second precharge selection transistor PSX2 and whose second terminal is grounded.

[0060] Figure 5 This is a circuit diagram of pixels included in an image sensor according to an embodiment. Further details will not be provided. Figure 3 and Figure 4The previous embodiments shown are described again.

[0061] Reference Figure 5 Pixel PXa may include a photodiode PD and a pixel signal generation circuit PSCa configured to generate a pixel signal PXS. The control signals applied to the pixel signal generation circuit PSCa (including a transmission control signal TS, a reset control signal RS, a first precharge selection control signal PSEL1, a second precharge selection control signal PSEL2, a precharge control signal PC, a first sampling control signal SAMPS1, a second sampling control signal SAMPS2, and a selection control signal SELS) may be some of the control signals CS generated by the line driver 140.

[0062] The pixel signal generation circuit PSCa may include multiple transistors, such as a transfer transistor TX, a reset transistor RX, a first source follower SF1, a first precharge selection transistor PSX1a, a second precharge selection transistor PSX2a, a precharge transistor PCXa, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a second source follower SF2, and a selection transistor SX. The pixel signal generation circuit PSCa may also include a first capacitor C1 and a second capacitor C2. In each of the first capacitor C1 and the second capacitor C2, charge accumulated according to a reset operation or charge accumulated according to a photocharge accumulation operation can be accumulated.

[0063] The first terminal of the first precharge selection transistor PSX1a can be connected to the first source follower SF1, and the second terminal of the first precharge selection transistor PSX1a can be connected to the second output node NO2. The first terminal of the second precharge selection transistor PSX2a can be connected to the second output node NO2, and the second terminal of the second precharge selection transistor PSX2a can be connected to the first output node NO1. The first terminal of the precharge transistor PCXa can be connected to the second output node NO2, and ground voltage can be applied to the second terminal of the precharge transistor PCXa.

[0064] Figure 6 and Figure 7 This is a circuit diagram of pixels included in an image sensor according to an example embodiment. Further details will not be provided. Figure 3 and Figure 4 The previous embodiments shown are described again.

[0065] Reference Figure 6Pixel PXb may include a photodiode PD and a pixel signal generation circuit PSCb configured to generate pixel signal PXS. Control signals applied to the pixel signal generation circuit PSCb (including transmission control signal TS, reset control signal RS, first precharge selection control signal PSEL1, second precharge selection control signal PSEL2, precharge control signal PC, first sampling control signal SAMPS1, second sampling control signal SAMPS2, and selection control signal SELS) may be some of the control signals CS generated by the line driver 140.

[0066] The pixel signal generation circuit PSCb may include multiple transistors, such as a transfer transistor TX, a reset transistor RX, a first source follower SF1, a first precharge selection transistor PSX1b, a second precharge selection transistor PSX2b, a precharge transistor PCXb, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a second source follower SF2, and a selection transistor SX. The pixel signal generation circuit PSCb may also include a first capacitor C1 and a second capacitor C2. In each of the first capacitor C1 and the second capacitor C2, charge accumulated according to a reset operation or charge accumulated according to a photocharge accumulation operation can be accumulated.

[0067] The first terminal of the first precharge selection transistor PSX1b can be connected to the first source follower SF1, and the second terminal of the first precharge selection transistor PSX1b can be connected to the output node NO. The first precharge selection transistor PSX1b can be turned on or off in response to the first precharge selection control signal PSEL1 received from the row driver 140, and reset the output node NO. The output node NO may have parasitic capacitance.

[0068] The first terminal of the precharge transistor PCXb can be connected to the output node NO, and the second terminal of the precharge transistor PCXb can be connected to the second precharge selection transistor PSX2b. The precharge transistor PCXb can operate as a current source in response to the precharge control signal PC received from the row driver 140 and precharge the output node NO.

[0069] The first terminal of the second precharge selection transistor PSX2b can be connected to the precharge transistor PCXb, and ground voltage can be applied to the second terminal of the second precharge selection transistor PSX2b. The second precharge selection transistor PSX2b can be turned on or off in response to the second precharge selection control signal PSEL2 received from the row driver 140, and precharges the output node NO.

[0070] According to an embodiment, the first precharge selection transistor PSX1b, the precharge transistor PCXb, and the second precharge selection transistor PSX2b can be connected in series.

[0071] The first terminal of the first sampling transistor SAMP1 can be connected to the output node NO, and the second terminal of the first sampling transistor SAMP1 can be connected to the first capacitor C1. The first sampling transistor SAMP1 can be turned on or off in response to the first sampling control signal SAMPS1 received from the row driver 140, and the charge accumulating in the first capacitor C1 according to the switching of the first sampling transistor SAMP1 can be accumulated according to the reset operation.

[0072] The first terminal of the second sampling transistor SAMP2 can be connected to the output node NO, and the second terminal of the second sampling transistor SAMP2 can be connected to the second capacitor C2. The second sampling transistor SAMP2 can be turned on or off in response to the second sampling control signal SAMPS2 received from the row driver 140, and the charge accumulated according to the photocharge accumulation operation can be accumulated in the second capacitor C2 according to the switching of the second sampling transistor SAMP2.

[0073] According to an embodiment, in a pixel PXb of the image sensor 100, both the first capacitor C1 and the second capacitor C2 can be connected to the output node NO and the second source follower SF2. Therefore, compared to a comparative example where the first capacitor C1 and the second capacitor C2 are respectively connected to different source followers, the image sensor according to the embodiment can include a reduced number of transistors constituting the pixel. Additionally, according to an embodiment, the pixel PXb of the image sensor 100 can include a first precharge selection transistor PSX1b and a second precharge selection transistor PSX2b, thereby effectively resetting the output node NO. The image sensor 100 can eliminate the offset that occurs between the reset signal RST according to the reset operation and the image signal SIG according to the photocharge accumulation operation due to residual charge at the output node NO.

[0074] Reference Figure 7Pixel PXb' may include a photodiode PD and a pixel signal generation circuit PSCb' configured to generate pixel signal PXS. Control signals applied to the pixel signal generation circuit PSCb' (including a transmission control signal TS, a reset control signal RS, a first precharge selection control signal PSEL1, a second precharge selection control signal PSEL2, a precharge control signal PC, a first sampling control signal SAMPS1, a second sampling control signal SAMPS2, and a selection control signal SELS) may be some of the control signals CS generated by the line driver 140. The pixel signal generation circuit PSCb' may include multiple transistors, such as a transmission transistor TX, a reset transistor RX, a first source follower SF1, a first precharge selection transistor PSX1b, a second precharge selection transistor PSX2b, a precharge transistor PCXb, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a second source follower SF2, and a selection transistor SX. The pixel signal generation circuit PSCb' may also include a first capacitor C1 and a second capacitor C2.

[0075] Reference Figure 6 The differences mentioned above Figure 7 The pixel signal generation circuit PSCb' may include a second precharge selection transistor PSX2b, whose first terminal is connected to the output node NO and whose second terminal is connected to the precharge transistor PCXb. The pixel signal generation circuit PSCb' includes a precharge transistor PCXb, whose first terminal is connected to the second precharge selection transistor PSX2b and whose second terminal is grounded.

[0076] Figure 8 This is a timing diagram of control signals and ramp signals provided to pixels of an image sensor according to an embodiment. The same control signals can be provided to pixels in the same row. Reference can be made... Figure 8 The described control signals are provided to the reference. Figures 3 to 7 The pixels PX, PX', PXa, PXb, and PXb' described herein, and for ease of description, will be referred to in the following text. Figure 3 as well as Figures 8 to 11 Describe it.

[0077] Reference Figure 3 and Figure 8 The following operations can be performed during the Global Signal Dump (GSDP) period. The reset control signal RS can transition from a low level (second level) to a high level (first level), remain at the first level during the first reset time RT1, and then transition to a low level. The floating diffusion node FD can be reset (reset operation) as the reset transistor RX turns on in response to the high level of the reset control signal RS. For example, the voltage of the floating diffusion node FD can be reset to the pixel voltage VPIX.

[0078] After the reset control signal RS transitions from high to low, the first sampling control signal SAMPS1 can transition from low to high and remain high during the reset settling time RCS. Based on the first sampling transistor SAMP1 turning on in response to the first sampling control signal SAMPS1 being high, the voltage of the reset floating diffusion node FD can be sampled to the voltage connected to the first output node NO1 (or... Figure 6 and Figure 7 The first capacitor C1 of the output node NO.

[0079] After the first sampling transistor SAMP1 transitions from high to low, the transmission control signal TS can transition from low to high and remain high during the integration time TT. Since the transmission transistor TX turns on in response to the high level of the transmission control signal TS, photocharge generated by the photodiode PD can accumulate in the floating diffusion node FD. For example, the voltage of the floating diffusion node FD can gradually decrease from the pixel voltage VPIX according to the amount of accumulated charge.

[0080] After the transmission control signal TS transitions from high to low, the second sampling control signal SAMPS2 can transition from low to high and remain high during the signal settling time SCS. Based on the second sampling transistor SAMP2 turning on in response to the second sampling control signal SAMPS2 being high, the voltage of the floating diffusion node FD can be sampled to the voltage connected to the first output node NO1 (or... Figure 6 and Figure 7 The second capacitor C2 of the output node NO.

[0081] The first precharge selection control signal PSEL1 and the second precharge selection control signal PSEL2 can change from low to high before the first sampling control signal SAMPS1 changes from low to high, and remain high until the second sampling control signal SAMPS2 changes from high to low. For example, the first precharge selection control signal PSEL1 can remain high during a first time T11, and the second precharge selection control signal PSEL2 can remain high during a first time T21.

[0082] According to an embodiment, the first time T11 of the first precharge selection control signal PSEL1 and the first time T21 of the second precharge selection control signal PSEL2 can overlap with each other. For example, the first time T11 of the first precharge selection control signal PSEL1 and the first time T21 of the second precharge selection control signal PSEL2 can be matched with each other, but are not limited thereto. Because the first precharge selection transistor PSX1 and the second precharge selection transistor PSX2 remain in the on state, the voltage of the floating diffusion node FD can be sampled to the first output node NO1 (or Figure 6 and Figure 7 The first capacitor C1 or the second capacitor C2 of the output node NO.

[0083] The precharge control signal PC can transition from low to high before the first sampling control signal SAMPS1 transitions from low to high, and remains high even after the second sampling control signal SAMPS2 transitions from high to low. In response to the precharge control signal PC being high, the precharge transistor PCX can be turned on, and the first output node NO1 (or...) Figure 6 and Figure 7 The output node (NO) can be precharged.

[0084] During the Global Signal Dump (GSDP) period, the selection control signal SELS can be kept low.

[0085] During the readout period (ROP), the operations described below can be performed. During the readout period (ROP), the precharge control signal PC can be kept high.

[0086] The reset control signal RS can transition from low to high and then remain high during the second reset time RT2. Furthermore, the first precharge selection control signal PSEL1 and the second precharge selection control signal PSEL2 can transition from low to high. The first precharge selection control signal PSEL1 can remain high during the second time T12, and the second precharge selection control signal PSEL2 can remain high during the second time T22. Here, the second reset time RT2, the second time T12 of the first precharge selection control signal PSEL1, and the second time T22 of the second precharge selection control signal PSEL2 can overlap.

[0087] Based on the reset control signal RS being high, the first precharge selection control signal PSEL1 being high, and the second precharge selection control signal PSEL2 being high, the first output node NO1 (or Figure 6 and Figure 7The output node NO can be reset. For example, the first output node NO1 can be reset to the pixel voltage VPIX. Therefore, after the Global Signal Dump (GSDP) period ends, the residual data in the first output node NO1 (or...) can be removed. Figure 6 and Figure 7 The charge of the output node NO (output node reset operation).

[0088] According to an embodiment, the transmission control signal TS may be maintained at a low level during the second reset time RT2. Alternatively, according to an embodiment, the transmission control signal TS may be at a high level during the integration time in the readout period ROP, and the integration time may be included in the second reset time RT2 in which the reset control signal RS is at a high level.

[0089] When the output node reset operation ends according to the reset control signal RS transitioning from high to low, the first precharge selection control signal PSEL1 transitioning from high to low, and the second precharge selection control signal PSEL2 transitioning from high to low, the first sampling control signal SAMPS1 can transition from low to high and remain high during the first settling time ST1. During this first settling time ST1, when the first sampling control signal SAMPS1 remains high, the selection control signal SELS can be high, and the selection transistor SX can be turned on to output the reset signal RST corresponding to the charge according to the reset operation (which is sampled into the first capacitor C1) via the column line CL.

[0090] After the selector transistor SX is turned on, a ramp signal RAMP can be generated during the first time RRT, causing it to decrease (or increase) at a constant slope. During the first time RRT, when the voltage level of the ramp signal RAMP continuously changes, the CDS circuit (e.g., Figure 1 (151) The ramp signal RAMP can be compared with the reset signal RST.

[0091] After the first settling time ST1 has elapsed and the first sampling control signal SAMPS1 transitions from high to low, the second sampling control signal SAMPS2 can transition from low to high and remain high during the second settling time ST2. During this second settling time ST2, when the second sampling control signal SAMPS2 remains high, the selection control signal SELS can be high, and the selection transistor SX can be turned on to output the image signal SIG corresponding to the charge accumulated during the operation (which is sampled into the second capacitor C2) via the column line CL.

[0092] After the selector transistor SX is turned on, a ramp signal RAMP can be generated during the second time SST period, causing it to decrease (or increase) at a constant slope. During the second time SST period, during which the voltage level of the ramp signal RAMP continues to change, the CDS circuit 151 can compare the ramp signal RAMP with the image signal SIG.

[0093] although Figure 8 This illustration shows that during the readout period ROP, after the first sampling control signal SAMPS1 transitions from low to high, the second sampling control signal SAMPS2 transitions from low to high. However, the image sensor according to this embodiment is not limited to this. During the readout period ROP, the first sampling control signal SAMPS1 can transition from low to high after the second sampling control signal SAMPS2 transitions from low to high. Therefore, the reset signal RST can be output via the column line CL after the image signal SIG is output via the column line CL.

[0094] Figure 9 This is a timing diagram of control signals and ramp signals provided to pixels of an image sensor according to an embodiment. Reference can be made... Figure 9 The described control signals are provided to the reference. Figure 5 The pixels PXa, PXb, and PXb' described up to Figure 7, and in the following text, for ease of description, will be referred to as Figure 5 and Figure 9 To describe. In the Figure 9 The description will no longer refer to the above. Figure 8 The description.

[0095] and Figure 8 In comparison, reference Figure 9 During the readout period ROP, the reset control signal RS can transition from low to high and then remain high during the second reset time RT2. Additionally, the second precharge selection control signal PSEL2 can transition from low to high and remain high during the second time T22. However, in Figure 9 In this process, the first precharge selection control signal PSEL1 can be kept at a low level during the readout period ROP.

[0096] Based on the reset control signal RS being high, the first precharge selection control signal PSEL1 being low, and the second precharge selection control signal PSEL2 being high, the first output node NO1 (or Figure 6 and Figure 7 The output node NO can be reset to ground. Therefore, after the global signal dump period GSDP ends, the remaining data at the first output node NO1 (or...) can be removed. Figure 6 and Figure 7The charge of the output node NO (output node reset operation).

[0097] Figure 10 This is a timing diagram of control signals and ramp signals provided to pixels of an image sensor according to an embodiment. (Refer to...) Figure 10 The described control signals can be provided to the reference. Figures 3 to 7 The pixels PX, PX', PXa, PXb, and PXb' are described, and in the following text, for ease of description, reference will be made to... Figure 3 as well as Figures 8 to 11 To describe. In the Figure 10 The description will no longer refer to the above. Figure 8 The description.

[0098] Reference Figure 3 and Figure 10 During the readout period ROP, the first sampling control signal SAMPS1 can transition from low to high, and a reset signal RST corresponding to the charge sampled by the reset operation (which is sampled into the first capacitor C1) can be output via column line CL. Subsequently, the first precharge selection control signal PSEL1 and the second precharge selection control signal PSEL2 can transition from low to high. For example, the first precharge selection control signal PSEL1 can remain high during a third time T13, and the second precharge selection control signal PSEL2 can remain high during a third time T23. Here, the third time T13 of the first precharge selection control signal PSEL1 and the third time T23 of the second precharge selection control signal PSEL2 can overlap.

[0099] Based on the first precharge selection control signal PSEL1 being high and the second precharge selection control signal PSEL2 being high, the first output node NO1 (or Figure 6 and Figure 7 The output node NO can be reset. For example, the first output node NO1 can be reset to the pixel voltage VPIX. Therefore, after outputting the reset signal RST through the column line CL, the residual values ​​in the first output node NO1 (or Figure 6 and Figure 7 The charge of the output node NO (output node reset operation).

[0100] After the output node reset operation ends and the first precharge selection control signal PSEL1 and the second precharge selection control signal PSEL2 transition from high to low, the second sampling control signal SAMPS2 can transition from low to high and remain high during the second settling time ST2. During this second settling time ST2, the selection control signal SELS can be high, and the selection transistor SX can be turned on to output the image signal SIG corresponding to the charge accumulated according to the accumulated operation (which is sampled into the second capacitor C2) via the column line CL.

[0101] although Figure 10 It is shown that after the first sampling control signal SAMPS1 transitions from low to high, the second sampling control signal SAMPS2 transitions from low to high. However, the image sensor according to the embodiment is not limited to this. The first sampling control signal SAMPS1 may transition from low to high after the second sampling control signal SAMPS2 transitions from low to high. Therefore, the reset signal RST may be output via column line CL after the image signal SIG is output via column line CL.

[0102] Figure 11 This is a timing diagram of control signals and ramp signals provided to pixels of an image sensor according to an embodiment. (Refer to...) Figure 11 The described control signals can be provided to the reference. Figures 5 to 7 The pixels PXa, PXb, and PXb' are described, and in the following text, for ease of description, reference will be made to... Figure 5 and Figure 11 To describe. In the Figure 11 The description will no longer refer to the above. Figure 8 and Figure 10 The description.

[0103] and Figure 10 In comparison, reference Figure 11 During the readout period ROP, the second precharge selection control signal PSEL2 can transition from low to high and then remain high during the third time period T23. In this case, the first precharge selection control signal PSEL1 can remain low.

[0104] Based on the first precharge selection control signal PSEL1 being low and the second precharge selection control signal PSEL2 being high, the first output node NO1 (or Figure 6 and Figure 7 The output node NO can be reset to ground. Therefore, after outputting the reset signal RST through column line CL, the residual voltage at the first output node NO1 (or Figure 6 and Figure 7The charge of the output node NO (output node reset operation).

[0105] Figure 12 This is a circuit diagram of a pixel PXc included in an image sensor according to an embodiment. Figure 13 This is a timing diagram of control signals and ramp signals provided to the pixels of the image sensor according to an embodiment. Figure 12 The description will no longer include... Figure 3 The same symbols are used for description. Figure 13 The description will not repeat references. Figure 8 The description is as follows.

[0106] Reference Figure 12 Pixel PXc may include a photodiode PD and a pixel signal generation circuit PSCc configured to generate pixel signal PXS. Control signals applied to the pixel signal generation circuit PSCc (including transmission control signal TS, reset control signal RS, conversion gain control signal DCG, first precharge selection control signal PSEL1, second precharge selection control signal PSEL2, precharge control signal PC, first sampling control signal SAMPS1, second sampling control signal SAMPS2, and selection control signal SELS) may be some of the control signals CS generated by the line driver 140.

[0107] The pixel signal generation circuit PSCc may include multiple transistors, such as a transfer transistor TX, a reset transistor RX, a conversion gain transistor DCGT, a first source follower SF1, a first precharge selection transistor PSX1, a second precharge selection transistor PSX2, a precharge transistor PCX, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a second source follower SF2, and a selection transistor SX. The pixel signal generation circuit PSCc may also include a first capacitor C1 and a second capacitor C2.

[0108] The pixel signal generation circuit PSCc may include a reset transistor RX and a conversion gain transistor DCGT. The pixel voltage VPIX may be applied to a first terminal of the reset transistor RX, and a second terminal of the reset transistor RX may be connected to the conversion gain transistor DCGT. The first terminal of the conversion gain transistor DCGT may be connected to the reset transistor RX, and a second terminal of the conversion gain transistor DCGT may be connected to the floating diffusion node FD.

[0109] The reset transistor RX can be turned on or off in response to the reset control signal RS received from the row driver 140, and the conversion gain transistor DCGT can be turned on or off in response to the conversion gain control signal DCG received from the row driver 140. When the reset transistor RX and the conversion gain transistor DCGT are turned on, the charge accumulated in the floating diffusion node FD can be released, thereby resetting the floating diffusion node FD.

[0110] Reference Figure 12 and Figure 13 During the Global Signal Dump (GSDP) period, the reset control signal RS can transition from low to high and remain high during the first reset time RT11. During the GSDP period, the conversion gain control signal DCG can transition from low to high and remain high during the first reset time RT21. In response to the reset control signal RS and the conversion gain control signal DCG being high, the reset transistor RX and the conversion gain transistor DCGT can be turned on, causing the floating diffusion node FD to be reset (reset operation). According to an embodiment, the first reset time RT11 of the reset control signal RS and the first reset time RT21 of the conversion gain control signal DCG can overlap, for example, be matched.

[0111] According to an embodiment, the image sensor can support dual conversion gain (DCG) functionality by operating in both low conversion gain (LCG) and high conversion gain (HCG) modes. In LCG mode, the conversion gain control signal DCG can be high while the transmission control signal TS remains high during the integration time TT. The conversion gain control signal DCG can also remain high during the LCG time LT, and the LCG time LT and the integration time TT can overlap.

[0112] When photocharge accumulates in the floating diffusion node (FD), the conversion gain transistor DCGT is turned on. Therefore, this may result in a significant increase in the equivalent capacitance of the floating diffusion node (FD), and the conversion gain used to convert the photocharge generated by the photodiode (PD) into the image signal SIG may decrease. However, with the increase in the equivalent capacitance of the floating diffusion node (FD), a relatively large amount of photocharge can accumulate in it.

[0113] According to an embodiment, the additional capacitor can be further connected to the first terminal of the switching gain transistor DCGT, and when the switching gain transistor DCGT is turned on, the additional capacitor can be electrically connected to the floating diffusion node FD, thereby increasing the equivalent capacitance of the floating diffusion node FD.

[0114] although Figure 13This is a timing diagram describing the operation of an image sensor in LCG mode, but the image sensor according to the embodiment is not limited thereto. When the image sensor operates in HCG mode, the conversion gain control signal DCG can remain low during the integration time TT in which the transmission control signal TS remains high. In HCG mode, the conversion gain for converting the photocharge generated by the photodiode PD into the image signal SIG can be relatively increased, and a relatively small amount of photocharge can accumulate in the floating diffusion node FD.

[0115] During the readout period ROP, when the reset control signal RS remains high during the second reset time RT12, the conversion gain control signal DCG can remain high during the second reset time RT22. Based on the fact that the reset transistor RX turns on in response to the high reset control signal RS and the conversion gain transistor DCGT turns on in response to the high conversion gain control signal DCG, the floating diffusion node FD can be reset. For example, the voltage of the floating diffusion node FD can be reset to the pixel voltage VPIX. Additionally, the second output node NO2 can be reset.

[0116] refer to Figure 12 The described conversion gain transistor DCGT can also be further included in the reference. Figures 4 to 7 The described pixels PX', PXa, PXb, and PXb'. For Figure 12 The description of the conversion gain transistor DCGT can also be applied to the reference. Figures 4 to 7 The conversion gain transistors formed in the pixels PX', PXa, PXb and PXb' described.

[0117] Figure 14 This is a circuit diagram of a first pixel and a second pixel included in an image sensor according to an embodiment.

[0118] Reference Figure 14 , Figure 1 The pixel array 110 may include a first pixel PX1 and a second pixel PX2 connected to the same column line CL. The column line CL may be... Figure 1One of the first column lines CL0 to the nth column line CLn-1. For example, the first pixel PX1 and the second pixel PX2 can be arranged adjacent to each other in the column direction, but are not limited thereto; the first pixel PX1 and the second pixel PX2 can be arranged adjacent to each other in the row direction. According to an embodiment, the same microlens can be formed on the first pixel PX1 and the second pixel PX2, but are not limited thereto; individual microlenses can be formed on the first pixel PX1 and the second pixel PX2. The first pixel PX1 and the second pixel PX2 can be autofocus (AF) pixels, configured to perform AF function and distance measurement function. When the first pixel PX1 and the second pixel PX2 do not perform AF function, the first pixel PX1 and the second pixel PX2 can operate as general pixels and generate a pixel signal PXS for image capture.

[0119] The first pixel PX1 may include a photodiode PD1 and a first transistor configured to generate a first pixel signal PXS1, such as a transfer transistor TX1, a reset transistor RX1, a conversion gain transistor DCGT1, a first source follower SF11, a first precharge selection transistor PSX11, a second precharge selection transistor PSX2, a precharge transistor PCX1, a first sampling transistor SAMP11, a second sampling transistor SAMP12, a switching transistor SWT1, a second source follower SF2, and a selection transistor SX. The first pixel PX1 may also include a first capacitor C11 and a second capacitor C12. Control signals applied to the first transistor (including a transfer control signal TS1, a reset control signal RS1, a conversion gain control signal DCG1, a first precharge selection control signal PSEL11, a second precharge selection control signal PSEL2, a precharge control signal PC1, a first sampling control signal SAMPS11, a second sampling control signal SAMPS12, and a selection control signal SELS) may be generated by... Figure 1 Some of the control signals CS generated by the line driver 140.

[0120] The second pixel PX2 may include a photodiode PD2 and a second transistor configured to generate a second pixel signal PXS2 (such as a transfer transistor TX2, a reset transistor RX2, a conversion gain transistor DCGT2, a first source follower SF21, a first precharge select transistor PSX21, a second precharge select transistor PSX2, a precharge transistor PCX2, a first sampling transistor SAMP21, a second sampling transistor SAMP22, a switching transistor SWT2, a second source follower SF2, and a selection transistor SX), as well as a first capacitor C21 and a second capacitor C22. Control signals applied to the second transistor (including a transfer control signal TS2, a reset control signal RS2, a conversion gain control signal DCG2, a first precharge select control signal PSEL21, a second precharge select control signal PSEL2, a precharge control signal PC2, a first sampling control signal SAMPS21, a second sampling control signal SAMPS22, and a selection control signal SELS) may be generated by... Figure 1 Some of the control signals CS generated by the line driver 140.

[0121] According to an embodiment, the first pixel PX1 and the second pixel PX2 may share at least one of the second precharge selection transistor PSX2, the second source follower SF2, and the selection transistor SX. However, the image sensor according to the embodiment is not limited to this; the first pixel PX1 and the second pixel PX2 may share one or more transistors other than the second precharge selection transistor PSX2, the second source follower SF2, and the selection transistor SX, such as the first precharge selection transistor PSX1. Since the first pixel PX1 and the second pixel PX2, which are arranged adjacent to each other, share some transistors, the area of ​​the pixel array 110 can be reduced, and the integration density can be increased.

[0122] Although Figure 14 The illustration shows two pixels (first pixel and second pixel) PX1 and PX2 sharing a second precharge selection transistor PSX2, a second source follower SF2, and a selection transistor SX, but the image sensor according to the embodiment is not limited thereto. Three or more pixels may share one of the second precharge selection transistor PSX2, the second source follower SF2, and the selection transistor SX.

[0123] Figure 3The same descriptions of the photodiode PD, transmission transistor TX, reset transistor RX, first source follower SF1, first precharge selection transistor PSX1, second precharge selection transistor PSX2, precharge transistor PCX, first sampling transistor SAMP1, second sampling transistor SAMP2, second source follower SF2, and selection transistor SX in pixel PX can be applied to the photodiode PD1, transmission transistor TX1, reset transistor RX1, first source follower SF11, first precharge selection transistor PSX11, second precharge selection transistor PSX2, precharge transistor PCX1, first sampling transistor SAMP11, second sampling transistor SAMP12, second source follower SF2, and selection transistor SX in first pixel PX1, respectively. Figure 12 The same description of the conversion gain transistor DCGT can be applied to the conversion gain transistor DCGT1 in the first pixel PX1. For example, when the transfer transistor TX1 is turned on, the photocharge generated by the photodiode PD1 can be transferred to the floating diffusion node FD1, and when the reset transistor RX1 is turned on, the floating diffusion node FD1 can be reset. The charge according to the reset operation and the charge according to the photocharge accumulation operation can be accumulated in the first capacitor C11 and the second capacitor C12, respectively.

[0124] also, Figure 3 The same descriptions of the photodiode PD, transmission transistor TX, reset transistor RX, first source follower SF1, first precharge selection transistor PSX1, second precharge selection transistor PSX2, precharge transistor PCX, first sampling transistor SAMP1, second sampling transistor SAMP2, second source follower SF2, and selection transistor SX in pixel PX can be applied to the photodiode PD2, transmission transistor TX2, reset transistor RX2, first source follower SF21, first precharge selection transistor PSX21, second precharge selection transistor PSX2, precharge transistor PCX2, first sampling transistor SAMP21, second sampling transistor SAMP22, second source follower SF2, and selection transistor SX in second pixel PX2. Figure 12 The same description of the conversion gain transistor DCGT can be applied to the conversion gain transistor DCGT2 in the second pixel PX2. For example, when the transfer transistor TX2 is turned on, the photocharge generated by the photodiode PD2 can be transferred to the floating diffusion node FD2, and when the reset transistor RX2 is turned on, the floating diffusion node FD2 can be reset. The charge according to the reset operation and the charge according to the photocharge accumulation operation can be accumulated in the first capacitor C21 and the second capacitor C22, respectively.

[0125] The floating diffusion node FD1 in the first pixel PX1 can be electrically isolated from the floating diffusion node FD2 in the second pixel PX2.

[0126] When the switching transistor SWT1 in the first pixel PX1 is turned on and the switching transistor SWT2 in the second pixel PX2 is turned off, the first pixel signal PXS1 can be output through the column line CL. Conversely, when the switching transistor SWT2 in the second pixel PX2 is turned on and the switching transistor SWT1 in the first pixel PX1 is turned off, the second pixel signal PXS2 can be output through the column line CL. The first pixel signal PXS1 may include a reset signal corresponding to a reset operation and an image signal corresponding to an operation of accumulating photocharge generated by photodiode PD1. The second pixel signal PXS2 may include a reset signal corresponding to a reset operation and an image signal corresponding to an operation of accumulating photocharge generated by photodiode PD2.

[0127] Figure 15A and Figure 15B This is a circuit diagram of the first pixel and the second pixel included in the image sensor according to an embodiment. Figure 15A and Figure 15B In the description, it will not be considered again. Figure 3 and Figure 12 The description of the previous embodiment shown.

[0128] Reference Figure 15A and Figure 15B , Figure 1 The pixel array 110 may include a first pixel PXL and a second pixel PXR connected to the same column line CL. The column line CL may be... Figure 1 One of the first column lines CL0 to the nth column line CLn-1. For example, the first pixel PXL and the second pixel PXR can be arranged to be adjacent to each other in the column direction or the row direction. According to an embodiment, the first pixel PXL and the second pixel PXR can have the same microlens formed thereon and operate as AF pixels. When the first pixel PXL and the second pixel PXR are not operating as AF pixels, they can operate as general pixels for performing image capture functions.

[0129] The first pixel PXL may include a photodiode PDL and a transfer transistor TXL, the transfer transistor TXL being configured to transfer the photocharge generated by the photodiode PDL to the floating diffusion node FD. The second pixel PXR may include a photodiode PDR and a transfer transistor TXR configured to transfer the photocharge generated by the photodiode PDR to the floating diffusion node FD. The transfer control signal TSL to be provided to the transfer transistor TXL in the first pixel PXL and the transfer control signal TSR to be provided to the transfer transistor TXR in the second pixel PXR can be... Figure 1 Some of the control signals CS generated by the line driver 140.

[0130] According to an embodiment, the first pixel PXL and the second pixel PXR may share a floating diffusion node FD, multiple transistors (such as a reset transistor RX, a conversion gain transistor DCGT, a first source follower SF1, a first precharge selection transistor PSX1, a second precharge selection transistor PSX2, a precharge transistor PCX, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a second source follower SF2, and a selection transistor SX), and multiple capacitors (such as a first capacitor C1 and a second capacitor C2). According to an embodiment, the first pixel PXL and the second pixel PXR may share only a portion of the reset transistor RX, the conversion gain transistor DCGT, the first source follower SF1, the first precharge selection transistor PSX1, the second precharge selection transistor PSX2, the precharge transistor PCX, the first sampling transistor SAMP1, the second sampling transistor SAMP2, the second source follower SF2, and the selection transistor SX. Furthermore, according to an embodiment, the first pixel PXL and the second pixel PXR may share either a first capacitor C1 in which charge is accumulated according to a reset operation or a second capacitor C2 in which charge is accumulated according to a photocharge accumulation operation.

[0131] The connection relationships between the reset transistor RX, the conversion gain transistor DCGT, the first source follower SF1, the first precharge selection transistor PSX1, the second precharge selection transistor PSX2, the precharge transistor PCX, the first sampling transistor SAMP1, the second sampling transistor SAMP2, the second source follower SF2, the selection transistor SX, and the first capacitor C1 and the second capacitor C2 shared by the first pixel PXL and the second pixel PXR are as follows: Figure 12 The connection relationships between the transistors and capacitors in pixel PXc shown are the same, but the image sensor according to the embodiment is not limited to this, and the connection relationships between the transistors and capacitors in the first pixel PXL and the second pixel PXR can be the same as those in the reference. Figures 3 to 7 The connections between transistors and capacitors in the described pixels PX, PX', PXa, PXb, or PXb' are identical.

[0132] Reference Figure 15AThe charge from the reset operation that resets the floating diffusion node FD can accumulate in the first capacitor C1, and the charge from the first accumulation operation that accumulates the photoelectric charge generated by the photodiode PDL in the first pixel PXL in the floating diffusion node FD can accumulate in the second capacitor C2. For example, the transmission transistor TXL in the first pixel PXL can be turned on, while the transmission transistor TXR in the second pixel PXR can be turned off. When the selection transistor SX is turned on and the first sampling transistor SAMP1 is turned on, the reset signal RST corresponding to the reset operation can be output to the column line CL. Alternatively, when the selection transistor SX is turned on and the second sampling transistor SAMP2 is turned on, the first image signal SIG1 corresponding to the first accumulation operation can be output to the column line CL.

[0133] Reference Figure 15A and Figure 15B After the first accumulation operation of accumulating the photoelectric charge generated by the photodiode PDL in the first pixel PXL in the floating diffusion node FD, a second accumulation operation of accumulating the photoelectric charge generated by the photodiode PDR in the second pixel PXR in the floating diffusion node FD can be performed. For example, both the transmission transistor TXL in the first pixel PXL and the transmission transistor TXR in the second pixel PXR can be turned on.

[0134] After the first image signal SIG1 is output, the charge from the first and second accumulation operations can be accumulated in the second capacitor C2. When the selection transistor SX is turned on and the second sampling transistor SAMP2 is turned on, the second image signal SIG2 corresponding to the first and second accumulation operations can be output to the column line CL.

[0135] The image sensor according to the embodiment can compare the amount of photocharge generated by the first photodiode PDL in the first pixel PXL with the amount of photocharge generated by the second photodiode PDR in the second pixel PXR, and perform AF operation using a reset signal RST, a first image signal SIG1, and a second image signal SIG2 obtained by sequentially performing a reset operation, a first accumulation operation, and a second accumulation operation. Alternatively, the image sensor according to the embodiment can perform image capture function using a reset signal RST and a second image signal SIG2 obtained by simultaneously performing both the first accumulation operation and the second accumulation operation after the reset operation.

[0136] Figure 16 The operation of the image sensor according to an embodiment is shown in global shutter mode and rolling shutter mode.

[0137] Reference Figure 1 and Figure 16The image sensor 100 can operate in both rolling shutter mode and global shutter mode. According to an embodiment, the image sensor 100 can operate in rolling shutter mode during the AF operation period (AFM) to acquire AF information, and in global shutter mode during the image capture operation period (ISM) to acquire image information. However, Figure 16 The operation of the image sensor 100 shown is an example and is not limited thereto, and as... Figure 2 As shown, the image sensor 100 can operate in global shutter mode to perform both AF operation and image capture operation.

[0138] During the AF operation period (AFM), the image sensor 100 can be operated such that AF operations are performed sequentially for each row. For example, AF operations can be performed sequentially for the first row R1 to the i-th row Ri, and the reset time and photodiode integration time can be controlled differently for the first row R1 to the i-th row Ri.

[0139] During the image capture operation period (ISM), the image sensor 100 can be operated such that global signal dump operations are performed simultaneously on the first row R1 to the i-th row Ri. For example, the image sensor 100 can be operated such that the same global signal dump period is applied to the first row R1 to the i-th row Ri, and the image sensor 100 can be operated such that the same reset time and integration time are applied to the first row R1 to the i-th row Ri.

[0140] During the image capture operation period (ISM), the image sensor 100 can be operated such that readout operations are performed sequentially for each of the first row R1 to the i-th row Ri. For example, readout operations can be performed sequentially for the first row R1 to the i-th row Ri, and the readout time can be controlled differently for each of the first row R1 to the i-th row Ri.

[0141] Figure 17 This is a circuit diagram including a first pixel and a second pixel in an image sensor according to an embodiment. Figure 17 In the description, it will not be considered again. Figure 3 and Figure 15B The description of the previous embodiment shown.

[0142] Reference Figure 17 , Figure 1The pixel array 110 may include a first pixel PXL' and a second pixel PXR' connected to the same column line CL. For example, the first pixel PXL' and the second pixel PXR' may be arranged to be adjacent to each other in the column direction or the row direction. According to an embodiment, the first pixel PXL' and the second pixel PXR' may have the same microlens formed thereon and operate as AF pixels. When the first pixel PXL' and the second pixel PXR' are not operating as AF pixels, the first pixel PXL and the second pixel PXR can operate as general pixels for performing image capture functions.

[0143] The first pixel PXL' may include a photodiode PDL and a transfer transistor TXL configured to transfer the photocharge generated by the photodiode PDL to the floating diffusion node FD. The second pixel PXR' may include a photodiode PDR and a transfer transistor TXR configured to transfer the photocharge generated by the photodiode PDR to the floating diffusion node FD.

[0144] According to an embodiment, the first pixel PXL' and the second pixel PXR' may share a floating diffusion node FD, multiple transistors (such as a reset transistor RX, a conversion gain transistor DCGT, a first source follower SF1, a first precharge selection transistor PSX1, a second precharge selection transistor PSX2, a precharge transistor PCX, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a third sampling transistor SAMP3, a second source follower SF2, and a selection transistor SX), and multiple capacitors (such as a first capacitor C1, a second capacitor C2, and a third capacitor C3). According to an embodiment, the first pixel PXL' and the second pixel PXR' may share only a portion of the aforementioned transistors and a portion of the aforementioned capacitors. The first pixel PXL' and the second pixel PXR' may share the third sampling transistor SAMP3, whose first terminal is connected to the first output node NO1, and whose second terminal is connected to the third capacitor C3. The first pixel PXL' and the second pixel PXR' share the third capacitor C3, whose first terminal is applied with a pixel voltage VPIX, and whose second terminal is connected to the third sampling transistor SAMP3.

[0145] The charge generated by the reset operation of resetting the floating diffusion node FD can be accumulated in the first capacitor C1. The charge generated by the first accumulation operation of accumulating the photoelectric charge generated by the photodiode PDL in the first pixel PXL' in the floating diffusion node FD can be accumulated in the second capacitor C2. The charge generated by the first accumulation operation and the second accumulation operation of accumulating the photoelectric charge generated by the photodiode PDR in the second pixel PXR' in the floating diffusion node FD can be accumulated in the third capacitor C3.

[0146] After the first and second accumulation operations have ended, when the selection transistor SX is turned on and the first sampling transistor SAMP1 is turned on, the reset signal RST corresponding to the reset operation can be output to column line CL. When the selection transistor SX is turned on and the second sampling transistor SAMP2 is turned on, the first image signal SIG1 corresponding to the first accumulation operation can be output to column line CL. When the selection transistor SX is turned on and the third sampling transistor SAMP3 is turned on, the second image signal SIG2 corresponding to the first and second accumulation operations can be output to column line CL. However, the image sensor according to the embodiment is not limited to this; only the charge according to the second accumulation operation can be accumulated in the third capacitor C3, and the image signal corresponding to the second accumulation operation can be output.

[0147] The image sensor according to the embodiment can compare the amount of photocharge generated by the first photodiode PDL in the first pixel PXL' with the amount of photocharge generated by the second photodiode PDR in the second pixel PXR', and perform AF operation using a reset signal RST, a first image signal SIG1, and a second image signal SIG2 obtained by sequentially performing a reset operation, a first accumulation operation, and a second accumulation operation. Alternatively, the image sensor according to the embodiment can perform image capture function using a reset signal RST and a second image signal SIG2 obtained by simultaneously performing both the first accumulation operation and the second accumulation operation after the reset operation.

[0148] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the plurality of pixels comprising: Photodiode; A floating diffusion node is configured to accumulate photocharge generated by the photodiode; A first source follower is configured to amplify the voltage of the floating diffusion node and output the amplified voltage through the second terminal of the first source follower; A first capacitor is configured to store charge based on the voltage of the reset floating diffusion node; A second capacitor is configured to store a charge based on the voltage of the floating diffusion node in which the photocharge has accumulated; A first sampling transistor is connected to a first output node and configured to sample charge onto the first capacitor; A second sampling transistor is connected to the first output node and configured to sample charge into the second capacitor; At least one precharge selection transistor is connected to the first output node and configured to reset the first output node, the at least one precharge selection transistor including a first precharge selection transistor, a first terminal of the first precharge selection transistor being connected to a second terminal of the first source follower, and a second terminal of the first precharge selection transistor being connected to the first output node; as well as A second source follower is configured to output a pixel signal that changes according to the potential of the first output node to a column line.

2. The image sensor according to claim 1, wherein, Each of the plurality of pixels also includes: A pre-charge transistor configured to pre-charge a second output node connected to the second terminal of the first source follower. Wherein, the at least one precharge selection transistor includes: The first precharge selection transistor is connected between the first output node and the second output node; and A second precharge selection transistor is connected to the precharge transistor, wherein a ground voltage is applied to one end of the second precharge selection transistor.

3. The image sensor according to claim 1, wherein, Each of the plurality of pixels also includes: A pre-charge transistor configured to pre-charge a second output node connected to the second terminal of the first source follower. Wherein, the at least one precharge selection transistor includes: The first precharge selection transistor is connected between the first output node and the second output node; and A second precharge selection transistor is connected between the first source follower and the precharge transistor.

4. The image sensor according to claim 1, wherein, The at least one precharge selection transistor is further configured to: reset the first output node after charge according to the voltage of the reset floating diffusion node is stored in the first capacitor and charge according to the voltage of the floating diffusion node in which the photocharge is accumulated is stored in the second capacitor.

5. The image sensor according to claim 1, wherein, The at least one precharge selection transistor is further configured to reset the first output node after a pixel signal corresponding to one of the charge amount stored in the first capacitor and the charge amount stored in the second capacitor is output through the column line.

6. The image sensor according to claim 1, wherein, The plurality of pixels includes a first pixel and a second pixel, and the first pixel and the second pixel share the at least one precharge selection transistor.

7. The image sensor according to claim 6, wherein, The floating diffusion node in the first pixel is electrically isolated from the floating diffusion node in the second pixel.

8. The image sensor according to claim 1, wherein, The plurality of pixels includes a first pixel and a second pixel, and the first pixel and the second pixel share the floating diffusion node, the first capacitor and the second capacitor.

9. The image sensor according to claim 8, wherein, The first pixel and the second pixel share a third sampling transistor and a third capacitor. The first terminal of the third sampling transistor is connected to the first output node, and the second terminal of the third sampling transistor is connected to the third capacitor. The third capacitor stores charge according to the voltage of the floating diffusion node, wherein the photoelectric charge generated by the photodiode in the first pixel and the photoelectric charge generated by the photodiode in the second pixel accumulate in the floating diffusion node.

10. An image sensor comprising a pixel array wherein a plurality of pixels are arranged, each of the plurality of pixels comprising: Photodiode; A floating diffusion node is configured to accumulate photocharge generated by the photodiode; A first source follower is configured to amplify the voltage of the floating diffusion node and output the amplified voltage through the second terminal of the first source follower; At least one precharge selection transistor and a precharge transistor are connected in series to the first source follower, the at least one precharge selection transistor is connected to the second terminal of the first source follower, and the precharge transistor is configured to precharge the first output node; A first capacitor is configured to store charge based on the voltage of the reset floating diffusion node; A second capacitor is configured to store a charge based on the voltage of the floating diffusion node in which the photocharge has accumulated; A first sampling transistor is configured to sample charge onto the first capacitor; The second sampling transistor is configured to sample charge onto the second capacitor; as well as A second source follower is configured to output a pixel signal to a column line based on the potential change of the first output node connected to the first sampling transistor and the second sampling transistor.

11. The image sensor according to claim 10, wherein, The plurality of pixels includes a first pixel and a second pixel. Wherein, the floating diffusion node in the first pixel is electrically isolated from the floating diffusion node in the second pixel, and The first pixel and the second pixel share the precharge selection transistor.

12. The image sensor according to claim 10, wherein, The plurality of pixels includes a first pixel and a second pixel, and The first pixel and the second pixel share the floating diffusion node, the first capacitor, and the second capacitor.

13. The image sensor according to claim 12, wherein, The first pixel and the second pixel share a third sampling transistor and a third capacitor that stores charge based on the voltage of the floating diffusion node. The first terminal of the third sampling transistor is connected to the first output node, and the second terminal of the third sampling transistor is connected to the third capacitor. The photoelectric charge generated by the photodiode in the first pixel and the photoelectric charge generated by the photodiode in the second pixel accumulate in the floating diffusion node.

14. An image sensor, comprising a first pixel and a second pixel, each of the first pixel and the second pixel comprising: Photodiode; A floating diffusion node is configured to accumulate photocharge generated by the photodiode; A first source follower is configured to amplify the voltage of the floating diffusion node and output the amplified voltage through the second terminal of the first source follower; A precharge transistor configured to precharge the output node; A first precharge selection transistor and a second precharge selection transistor are configured to reset the output node. The first precharge selection transistor and the second precharge selection transistor are connected in series with the precharge transistor to the first source follower. The first terminal of the first precharge selection transistor is connected to the second terminal of the first source follower. The second terminal of the first precharge selection transistor is connected to the output node. A first capacitor is connected to the output node and configured to store charge according to the voltage of the reset floating diffusion node; A second capacitor is connected to the output node and configured to store charge based on the voltage of the floating diffusion node in which the photocharge is accumulated; as well as A second source follower is configured to output a pixel signal that changes according to the potential of the output node to the column line. The first pixel and the second pixel share the second precharge selection transistor and the second source follower.

15. The image sensor according to claim 14, wherein, The precharge transistor is connected between the first source follower and the second precharge select transistor.

16. The image sensor according to claim 14, wherein, The floating diffusion node in the first pixel is electrically isolated from the floating diffusion node in the second pixel.

17. The image sensor according to claim 14, wherein, Each of the first pixel and the second pixel also includes a switching transistor connected to the second source follower.

18. The image sensor according to claim 14, wherein, The first pixel and the second pixel share the floating diffusion node, as well as the first capacitor and the second capacitor.

19. The image sensor according to claim 18, wherein, The second capacitor is further configured to store a charge corresponding to the photoelectric charge generated by the photodiode in the first pixel, and then store a charge corresponding to the photoelectric charge generated by the photodiode in the second pixel.

Images