On-chip optical amplifier and method for manufacturing the same

Abstract

The present application provides an on-chip optical amplifier and a manufacturing method thereof, wherein the on-chip optical amplifier comprises: a substrate; an oxide layer covering the substrate; a waveguide layer located on the oxide layer; a gain medium layer located in the waveguide layer and used to form a slit structure for concentrating the light field; wherein the refractive index of the waveguide layer is greater than the refractive index of the gain medium layer.

Description

Technical Field

[0001] This application relates to the field of optical communication devices, specifically to an on-chip optical amplifier and its manufacturing method. Background Art

[0002] Optical waveguide amplifiers are essential components in silicon photonic communication systems, playing a crucial role in on-chip amplification and loss compensation of optical signals. Due to the luminescence defects of indirect-bandgap silicon materials and the demand for ultra-long transmission distances in modern optical communication systems, improving the gain of on-chip optical amplifiers has become a pressing issue. Summary of the Invention

[0003] In view of this, embodiments of this application provide an on-chip optical amplifier and a method for manufacturing the same.

[0004] In a first aspect, embodiments of this application provide an on-chip optical amplifier, comprising:

[0005] substrate;

[0006] an oxide layer covering the substrate;

[0007] Waveguide layer, located on the oxide layer;

[0008] The gain medium layer is located in the waveguide layer and is used to form a slit structure for concentrating the light field; wherein the refractive index of the waveguide layer is greater than the refractive index of the gain medium layer.

[0009] In some embodiments, the waveguide layer includes a slit waveguide region in a direction parallel to the substrate surface;

[0010] The slit waveguide region is located in at least a portion of the middle region along the optical path extension direction of the waveguide layer;

[0011] The gain dielectric layer is located within the waveguide layer where the slit waveguide region is located.

[0012] In some embodiments, the material of the gain medium layer is erbium-doped gain material.

[0013] In some embodiments, the bottom width of the cross-section of the waveguide layer in the slit waveguide region is greater than the top width in the optical path extension direction.

[0014] In some embodiments, the waveguide layer further includes, in a direction parallel to the substrate surface: two stepped regions, located at two ends of the slit waveguide region in the direction of extension of the optical path;

[0015] The waveguide layer in the stepped area is a multi-layer stepped structure.

[0016] In some embodiments, the width of each step structure in the stepped region gradually decreases in the direction away from the slit waveguide region.

[0017] In some embodiments, the width of each layer of the stepped structure in the stepped region decreases layer by layer from bottom to top in a direction perpendicular to the substrate surface.

[0018] In some embodiments, the length of each layer of the stepped structure in the stepped region decreases from bottom to top in a direction perpendicular to the substrate surface.

[0019] In some embodiments, the stepped area includes:

[0020] On-chip waveguide region; the on-chip waveguide region is used to receive optical signals or output optical signals;

[0021] A mode conversion region is located between the on-chip waveguide region and the slit waveguide region; the mode conversion region is used to transmit optical signals between the on-chip waveguide region and the slit waveguide region.

[0022] In some embodiments, the on-chip optical amplifier further includes a waveguide cladding covering the oxide layer and the waveguide layer.

[0023] On the other hand, embodiments of this application also provide a method for fabricating an on-chip optical amplifier, comprising:

[0024] An oxide layer is formed on the substrate;

[0025] A waveguide layer is formed covering the oxide layer;

[0026] A gain dielectric layer is formed in the waveguide layer, wherein the gain dielectric layer is used to form a slit structure that concentrates the light field; the refractive index of the waveguide layer is greater than the refractive index of the gain dielectric layer.

[0027] In some embodiments, forming a waveguide layer covering the oxide layer and forming a gain dielectric layer in the waveguide layer include:

[0028] Form a first waveguide layer covering the oxide layer;

[0029] The gain dielectric layer is formed on the first waveguide layer;

[0030] A second waveguide layer is formed to cover the gain dielectric layer; wherein the first waveguide layer and the second waveguide layer constitute the waveguide layer.

[0031] In some embodiments, the waveguide layer includes, in a direction parallel to the substrate surface, a slit waveguide region; the slit waveguide region is located in at least a portion of the intermediate region in the optical path extension direction of the waveguide layer; forming the gain dielectric layer on the first waveguide layer includes:

[0032] A trench structure is formed in the slit waveguide region on the first waveguide layer, wherein the depth of the trench structure is less than the thickness of the first waveguide layer;

[0033] The gain dielectric layer is formed in the trench structure, wherein the thickness of the gain dielectric layer is less than or equal to the depth of the trench structure.

[0034] In some embodiments, the method for fabricating the on-chip optical amplifier includes:

[0035] Two multi-layered stepped structures are formed at both ends of the slit structure in the waveguide layer along the optical path extension direction.

[0036] In some embodiments, the method of forming two multi-layered stepped structures includes:

[0037] In the optical path extension direction of the waveguide layer, a trapezoidal structure is formed with a width that gradually decreases from the middle to both ends; wherein the maximum width of the trapezoidal structure is less than or equal to the width of the substrate;

[0038] At the trapezoidal structures at both ends of the slit structure, the multi-layered stepped structure is formed layer by layer from top to bottom; wherein the width and length of the multi-layered stepped structure decrease from bottom to top in a direction perpendicular to the substrate surface.

[0039] In some embodiments, the method for fabricating the on-chip optical amplifier includes:

[0040] The surface of the waveguide layer is planarized.

[0041] In some embodiments, the method for fabricating the on-chip optical amplifier further includes:

[0042] A waveguide cladding is formed covering the oxide layer and the waveguide layer.

[0043] The on-chip optical amplifier provided in this application embodiment receives an optical signal via the on-chip waveguide region, then through on-chip coupling in the mode conversion region, and finally into the slit waveguide region for on-chip amplification. Thus, on the one hand, the slit structure with high refractive index contrast can improve the pump absorption efficiency and gain of the on-chip optical amplifier; on the other hand, the slit structure has good interface flatness, which can reduce transmission loss. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of an on-chip optical amplifier provided in an embodiment of this application;

[0045] Figure 2A schematic diagram of an on-chip optical amplifier provided in another embodiment of this application;

[0046] Figure 3 A cross-sectional view of the slit waveguide region of an on-chip optical amplifier in the optical path extension direction, provided for an embodiment of this application;

[0047] Figure 4 A schematic diagram of the waveguide layer containing the stepped region of an on-chip optical amplifier provided in an embodiment of this application;

[0048] Figure 5 A schematic diagram of the structure of the mode conversion region and the waveguide region of an on-chip optical amplifier provided in an embodiment of this application;

[0049] Figure 6 A top view of the stepped area of ​​an on-chip optical amplifier provided in an embodiment of this application;

[0050] Figure 7 A cross-sectional view of the stepped region of an on-chip optical amplifier in the optical path extension direction, provided for an embodiment of this application;

[0051] Figure 8 A schematic diagram of an on-chip optical amplifier provided in another embodiment of this application;

[0052] Figure 9 A flowchart illustrating the steps of a method for manufacturing an on-chip optical amplifier, as provided in an embodiment of this application;

[0053] Figure 10 A flowchart illustrating the steps of a method for manufacturing an on-chip optical amplifier, as provided in another embodiment of this application;

[0054] Figure 11a -g is a schematic diagram of the manufacturing process of an on-chip optical amplifier provided in an embodiment of this application;

[0055] Figure 12 A schematic diagram of an on-chip optical amplifier provided in another embodiment of this application;

[0056] Figure 13 A cross-sectional view of the slit waveguide region of an on-chip optical amplifier in the optical path extension direction, provided for another embodiment of this application;

[0057] Figure 14 A schematic diagram of the waveguide layer containing the mode conversion region of an on-chip optical amplifier, provided for another embodiment of this application;

[0058] Figure 15 A top view of the mode conversion region of an on-chip optical amplifier provided in another embodiment of this application;

[0059] Figure 16A schematic diagram illustrating the optical field transmission variation of an on-chip optical amplifier, provided as another embodiment of this application;

[0060] Figure 17 A transmission simulation diagram of a slit structure in an on-chip optical amplifier provided for another embodiment of this application;

[0061] Figure 18 A flowchart illustrating the steps of a method for manufacturing an on-chip optical amplifier, as provided in another embodiment of this application;

[0062] Figure 19 This is a schematic diagram of the manufacturing process of an on-chip optical amplifier provided for another embodiment of this application. Detailed Implementation

[0063] To facilitate understanding of the present application, exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0064] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of actual embodiments may not be described here, and well-known functions and structures may not be described in detail.

[0065] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0066] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0068] like Figure 1 As shown in the figure, this application embodiment provides an on-chip optical amplifier 100, which includes at least: a substrate 110; an oxide layer 120 covering the substrate 110; a waveguide layer 130 located on the oxide layer 120; and a gain dielectric layer 140 located within the waveguide layer 130. It should be understood that, in order to clearly show each layer structure, the dimensional proportions of each layer structure in the figure may not conform to the actual structure.

[0069] In the embodiment of the present application, the substrate 110 may be a single semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, etc., a compound semiconductor material substrate, such as a silicon germanium (SiGe) substrate, etc., or a silicon-on-insulator substrate (SOI) or a germanium-on-insulator substrate (GeOI). The embodiment of the present application is described using a silicon substrate as an example.

[0070] The oxide layer 120 is located between the waveguide layer and the substrate, which can reduce the leakage light from the waveguide layer 130 to the substrate 110 and protect the entire chip.

[0071] The waveguide layer 130 may be made of waveguide materials such as silicon or silicon nitride (SiN). Optionally, in order to form a waveguide layer with higher deposition quality, the thickness of the silicon waveguide layer may be about 220 nm, and the thickness of the silicon nitride waveguide layer may be about 300 nm.

[0072] The gain medium layer 140 is located in the waveguide layer 130. The refractive index of the waveguide layer 130 is greater than that of the gain medium layer 140, so as to form a slit structure in which a low refractive index gain material is sandwiched between high refractive index materials.

[0073] In some embodiments, on-chip optical amplifiers typically employ a dielectric waveguide guided mode. However, in a dielectric waveguide structure, a higher refractive index difference can cause the optical field in the waveguide to be more strongly confined within the guided mode waveguide, making it difficult to enter the gain structure and affecting the overall gain performance of the waveguide. The on-chip optical amplifier provided in this application utilizes the optical field enhancement effect of a slit structure to improve the interaction between the gain material and the optical field, thereby achieving higher pump absorption efficiency and unity gain.

[0074] In some embodiments, as Figure 2 As shown, the waveguide layer includes a slit waveguide region 131 in a direction parallel to the substrate surface. The slit waveguide region is located in at least a portion of the middle region in the optical path extension direction of the waveguide layer 130; the gain dielectric layer 140 is located within the waveguide layer where the slit waveguide region 131 is located.

[0075] The slit waveguide region 131 is located in at least a portion of the middle region of the waveguide layer 130 along the optical path extension direction. The waveguide layer containing the slit waveguide region is a horizontal slit structure consisting of two parallel layers of high-refractive-index waveguide material sandwiching a low-refractive-index gain material in between. The gain dielectric layer 140 is located within the waveguide layer containing the slit waveguide region 131. The thickness of the gain dielectric layer 140, and the thicknesses of the waveguide layers located above and below the gain dielectric layer within the slit waveguide region 131, can be determined based on the mode field distribution and optical field enhancement effect in the slit, to ensure that the optical field is more concentrated in the slit, thereby increasing the overlap area of ​​the pump light and signal light in the gain dielectric and improving pump utilization.

[0076] In some embodiments, the gain medium layer 140 may be an erbium (Er)-doped gain material.

[0077] To achieve high net gain optical amplification in small-sized waveguide structures, the gain dielectric layer can be a gain material with a high erbium doping concentration and a low erbium cooperative up-conversion coefficient. Optionally, an erbium-doped alumina material system deposited by atomic layer deposition can be used as the gain dielectric layer, providing a high concentration of photoactive erbium and good film quality; the erbium cooperative up-conversion coefficient can be reduced by dispersing erbium ions through the co-addition of yttrium (Y) or ytterbium (Yb).

[0078] To achieve a better slit mode, the thickness of the gain dielectric layer can be optionally controlled at around 100 nm. This thickness results in good atomic layer deposition and annealing quality and high gain performance.

[0079] In some embodiments, as Figure 3As shown, the cross section of the waveguide layer where the slit waveguide region 131 is located in the extending direction of the optical path is a trapezoid in which the bottom width is greater than the top width.

[0080] The horizontal trapezoidal slit structure exhibits good interface flatness, which can reduce waveguide transmission loss. The height and width of the trapezoidal cross-section in the slit waveguide region can be determined by the single-mode conditions of the trapezoidal waveguide. Optionally, the effective refractive index method and transfer matrix theory can be used to analyze the modes of the trapezoidal waveguide, enabling the pump and signal modes in the gain dielectric layer to have higher confinement factors and pump-signal overlap factors, thereby improving gain and reducing waveguide transmission loss.

[0081] In some embodiments, as Figure 4 As shown, the waveguide layer 130 further includes two stepped regions 150 in a direction parallel to the substrate surface, which are respectively located at two ends of the slot waveguide region 131 in the extending direction of the optical path.

[0082] The stepped regions 150 in waveguide layer 130 are located at both ends of slit waveguide region 131 in the optical path extension direction; the waveguide layer containing the stepped regions 150 is a multi-layer stepped structure, which has high mode field coupling efficiency. Optionally, the thickness of each stepped structure can be the same to improve the stability of mode pattern changes. In addition, increasing the number of stepped structures can improve the continuity of mode pattern changes.

[0083] In some embodiments, as Figure 5 As shown, the stepped region 150 in the waveguide layer 130 further includes a mode conversion region 132 and an on-chip waveguide region 133.

[0084] The on-chip waveguide region 133 is located at the left and right ends of the waveguide layer 130 and is used to receive or output optical signals. The mode conversion region 132 is located between the on-chip waveguide region 133 and the slit waveguide region 131. The mode conversion region is used to transmit optical signals between the on-chip waveguide region and the slit waveguide region, and to eliminate mode mismatch caused by size differences between the slit waveguide region and the on-chip waveguide region.

[0085] In some embodiments, as Figure 6 As shown, the width of each step structure in the stepped region gradually decreases in the direction away from the slit waveguide region.

[0086] Figure 6 This is a top view of a stepped region of an on-chip optical amplifier provided in an embodiment of this application. The width of each stepped structure in the stepped region 150 gradually decreases from the slit waveguide region 131 toward the on-chip waveguide region 133 to eliminate mode mismatch caused by size differences between the slit waveguide region and the on-chip waveguide region.

[0087] In some embodiments, as Figure 7As shown, the width of each layer of the stepped structure in the stepped region decreases from bottom to top in a direction perpendicular to the substrate surface.

[0088] Figure 7 This is a cross-sectional view of a stepped region of an on-chip optical amplifier provided in an embodiment of the present application, along the optical path. The width of each stepped structure in the stepped region 150 decreases from the bottom layer to the top layer. The minimum width of the stepped structure at the bottom layer is the same as the width of the on-chip waveguide region, while the width of the stepped structure at the top layer is the same as the width of the upper surface of the slot waveguide region, thereby improving the coupling efficiency between the on-chip waveguide region and the slot waveguide region.

[0089] In some embodiments, the length of each layer of the stepped structure in the stepped region decreases from bottom to top in a direction perpendicular to the substrate surface.

[0090] Continue to see Figure 5 The length of each step structure in the stepped region 150 decreases from the bottom layer to the top layer, thereby increasing the thickness of the waveguide layer 130 from the on-chip waveguide region 133 to the slit waveguide region 131 in the optical path extension direction, so as to eliminate the mode mismatch caused by the size difference between the slit waveguide region and the on-chip waveguide region.

[0091] In some embodiments, as Figure 8 As shown, the on-chip optical amplifier may further include a waveguide cladding 160 covering the oxide layer 120 and the waveguide layer 130.

[0092] The waveguide cladding can be made of materials such as polymers and oxides. Optionally, silicon oxide can be used as the waveguide cladding to protect the waveguide layer, prevent the waveguide layer from contacting contaminants, and increase structural strength.

[0093] like Figure 9 As shown in the figure, this application embodiment provides a method for manufacturing an on-chip optical amplifier, the method comprising the following steps:

[0094] Step S10, forming an oxide layer on the substrate;

[0095] Step S20: Form a waveguide layer covering the oxide layer;

[0096] Step S30: A gain dielectric layer is formed in the waveguide layer, wherein the gain dielectric layer is used to form a slit structure that concentrates the light field; the refractive index of the waveguide layer is greater than the refractive index of the gain dielectric layer.

[0097] In this embodiment, the substrate 110 can be a single-element semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. This embodiment uses a silicon substrate as an example for illustration.

[0098] In some embodiments, the oxide layer 120 can be formed by thermally oxidizing a thick silicon dioxide film on a silicon substrate.

[0099] In some embodiments, a waveguide layer covering the oxide layer can be formed by deposition. The waveguide layer 130 can be a waveguide material such as silicon or silicon nitride (SiN). The deposition process here includes, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0100] In some embodiments, the thickness of the gain dielectric layer can be determined based on the mode field distribution and optical field enhancement effect in the slit to ensure that the optical field is more concentrated in the slit, thereby increasing the overlap area of ​​the pump light and signal light in the gain dielectric and improving pump utilization. To form a better slit mode, the thickness of the gain dielectric layer can optionally be controlled at around 100 nm, which provides good atomic layer deposition and annealing quality and high gain performance.

[0101] In some embodiments, the gain dielectric layer can be an erbium-doped alumina material system deposited by atomic layer deposition to provide a larger concentration of photoactive erbium and better film quality; in addition, by dispersing erbium ions by co-adding yttrium (Y) or ytterbium (Yb), the cooperative upconversion coefficient of erbium ions can be reduced, thereby achieving optical amplification with a larger net gain.

[0102] In some embodiments, as Figure 10 As shown, the waveguide layer forming the oxide layer and the gain dielectric layer forming in the waveguide layer include:

[0103] S201. Form a first waveguide layer covering the oxide layer;

[0104] S202. The gain dielectric layer is formed on the first waveguide layer;

[0105] S203. Form a second waveguide layer covering the gain dielectric layer; wherein the first waveguide layer and the second waveguide layer constitute the waveguide layer.

[0106] like Figure 11a As shown, a first waveguide layer 1301 may be formed on the oxide layer 120 by deposition, wherein the first waveguide layer 1301 may be made of waveguide materials such as silicon or silicon nitride (SiN). Figure 11b and 11c FIG. 1 shows a process of forming a gain medium layer 140 on the first waveguide layer, including forming a trench structure 1302 and depositing the gain medium layer 140. Figure 11d The diagram shows a second waveguide layer 1303 formed by deposition, which covers the gain dielectric layer. The material of the second waveguide layer is the same as that of the first waveguide layer to form a better slit structure.

[0107] Next, combine Figure 11a-11g , the preparation process of the on-chip optical amplifier provided in the embodiment of the present application is described in detail.

[0108] refer to Figure 11a , a first waveguide layer 1301 is covered on the oxide layer 120 using a deposition process.

[0109] In some embodiments, reference Figure 11b The waveguide layer includes, in a direction parallel to the substrate surface, a slit waveguide region; the slit waveguide region is located in at least a portion of the intermediate region along the optical path extension direction of the waveguide layer; forming the gain dielectric layer on the first waveguide layer includes:

[0110] A trench structure is formed in the slit waveguide region on the first waveguide layer, wherein the depth of the trench structure is less than the thickness of the first waveguide layer;

[0111] The gain dielectric layer is formed in the trench structure, wherein the thickness of the gain dielectric layer is less than or equal to the depth of the trench structure.

[0112] A trench structure 1302 is formed within the slot waveguide region 131 on the first waveguide layer 1301, wherein the depth of the trench structure 1302 may be less than the thickness of the first waveguide layer 1301. Optionally, the trench structure 1302 can be formed by an etching process. Etching processes are typically classified as dry etching and wet etching. Dry etching can include ion milling etching, plasma etching, reactive ion etching, or laser ablation, etc.; wet etching utilizes solvents or solutions, such as acid or alkaline solutions, for etching.

[0113] refer to Figure 11c The gain medium layer 140 is formed in the trench structure 1302, wherein the thickness of the gain medium layer 140 is less than or equal to the depth of the trench structure 1302. Alternatively, the gain material layer can be deposited in the trench structure 1302 by atomic layer deposition, magnetron sputtering, or laser deposition. In addition, a thin mask can be used to cover the waveguide layer to achieve selective deposition of the gain medium layer 140 in the trench structure region.

[0114] refer to Figure 11d A second waveguide layer 1303 is then deposited on the gain dielectric layer 140. Optionally, a thin mask can be used to cover the waveguide layer to achieve selective deposition of the second waveguide layer 1303 in the trench structure region.

[0115] In some embodiments, the method for manufacturing the on-chip optical amplifier further includes: forming two multi-layer stepped structures on the waveguide layer at both ends of the slit structure in the direction in which the optical path extends.

[0116] Two multi-layered stepped structures are located at both ends of the slit structure in waveguide layer 130 along the optical path extension direction. Optionally, such as... Figure 11e and Figure 11f As shown, a multi-layered stepped structure can be formed layer by layer from top to bottom using an etching method. The thickness of each stepped structure layer can be the same to improve the stability of the optical field mode variation. In addition, increasing the number of stepped structure layers can improve the continuity of the optical field mode variation.

[0117] In some embodiments, as Figure 11e and Figure 11f The method for manufacturing the on-chip optical amplifier further includes:

[0118] In the optical path extension direction of the waveguide layer, a trapezoidal structure is formed with a width that gradually decreases from the middle to both ends; wherein the maximum width of the trapezoidal structure is less than or equal to the width of the substrate;

[0119] At the trapezoidal structures at both ends of the slit structure, the multi-layered stepped structure is formed layer by layer from top to bottom; wherein the width and length of the multi-layered stepped structure decrease from bottom to top in a direction perpendicular to the substrate surface.

[0120] refer to Figure 11eAlong the optical path extension direction of waveguide layer 130, a trapezoidal structure is formed, with its width gradually decreasing from the central slit waveguide region to the two end on-chip waveguide regions; wherein the maximum width of the trapezoidal structure is less than or equal to the width of the substrate. Optionally, the trapezoidal structure of waveguide layer 130 is formed using an ion milling etching method. The etching width and depth can be determined by the linewidth of the etching mask pattern and the maximum etching depth. Due to the anisotropy of etching rates in the waveguide fabrication process, the waveguide sidewalls are not perpendicular after processing; therefore, the trapezoidal structure is formed by the etching tilt angle, which is typically 80°.

[0121] refer to Figure 11f In waveguide layer 130, at the trapezoidal structures at both ends of the slit structure, a multi-layered stepped structure is formed sequentially from top to bottom. The width and length of each multi-layered stepped structure decrease from bottom to top in a direction perpendicular to the substrate surface to improve coupling efficiency and reduce mode mismatch caused by size differences in the on-chip optical amplifier. Optionally, the multi-layered stepped structure is formed sequentially layer by layer using an ion milling etching method. The etching width and depth are determined by the linewidth of the etching mask pattern and the maximum etching depth.

[0122] In some embodiments, as Figure 11g As shown, the manufacturing method of the on-chip optical amplifier further includes:

[0123] A waveguide cladding is formed covering the oxide layer and the waveguide layer.

[0124] Optionally, a deposition method may be used to form a waveguide cladding layer 160 on the oxide layer 120 and the waveguide layer 130. The waveguide cladding layer may be made of materials such as silicon oxide to protect the waveguide layer, prevent the waveguide layer from contacting contaminants, and increase structural strength.

[0125] In some embodiments, the method of manufacturing the on-chip optical amplifier further includes:

[0126] The surface of the waveguide layer is planarized.

[0127] Optionally, chemical mechanical polishing (CMP) can be used to planarize the waveguide layer surface to achieve better interface flatness and reduce transmission loss.

[0128] like Figure 12As shown in the embodiment of this application, another optional on-chip optical amplifier 200 is provided, including: a substrate 210; an oxide layer 220 covering the substrate 210; and a waveguide layer 230 located on the oxide layer 220; wherein the waveguide layer 230 includes: a slit waveguide region 231, a mode conversion region 232, and an on-chip waveguide region 233. Optical signals are input into the optical amplifier via the on-chip waveguide region and coupled into the slit waveguide region through the mode conversion region, achieving on-chip amplification by utilizing the optical field enhancement effect of the slit waveguide region.

[0129] In some embodiments, the on-chip waveguide region 233 may be made of silicon or silicon nitride.

[0130] In some embodiments, as Figure 13 As shown, the slit waveguide region 231 is a horizontal slit structure, comprising: a gain dielectric layer 240, and two parallel waveguide layers located above and below the gain dielectric layer, respectively. The waveguide layers can be made of waveguide materials such as silicon or silicon nitride, the same as the material of the on-chip waveguide region. The gain dielectric layer is an erbium-doped gain material, and its refractive index is lower than that of the waveguide layer, resulting in a higher refractive index contrast and thus a better slit mode. For the erbium-doped gain material in the slit waveguide region, the enhanced electric field and high confinement factor can improve light-matter interaction. Due to the Purcell effect, the local density of states in the slit waveguide region also increases, thereby increasing the radiative rate of excited-state erbium ions and achieving higher pump absorption and unity gain. The horizontal slit structure has good interface flatness, relatively low loss, and the formation of the slit structure is not limited by the photolithography linewidth, making it more flexible in design.

[0131] To achieve high net gain optical amplification on a small-sized waveguide structure, the gain dielectric layer needs to have a high erbium ion doping concentration, low transmission loss, and a low erbium ion cooperative upconversion coefficient. Optionally, an erbium-doped alumina material system deposited by atomic layer deposition can be used as the gain dielectric layer, which can provide a high concentration of photoactive erbium and good film quality. In addition, the erbium ion cooperative upconversion coefficient can be reduced by dispersing erbium ions using yttrium (Y) or ytterbium (Yb).

[0132] In some embodiments, the thickness of the gain dielectric layer and the thickness of the high-refractive-index material layers located above and below the gain dielectric layer in the slit waveguide region can be determined based on the mode field distribution and optical field enhancement effect in the slit, so that the optical field is more concentrated in the gain dielectric layer, thereby increasing the overlap area of ​​the pump light and signal light in the gain dielectric and improving the pump utilization rate. Optionally, in order to obtain better deposition process effects, the silicon material layer thickness can be based on 220 nm, the silicon nitride material layer thickness can be based on 300 nm, and the gain dielectric layer thickness can be controlled at around 100 nm. This thickness provides good atomic layer deposition and annealing quality and good gain performance.

[0133] In some embodiments, due to the anisotropy of etching rates during waveguide fabrication, the waveguide sidewalls are not perpendicular after processing. The trapezoidal cross-section of the slit waveguide region is formed by the etching angle, which can be 80°. The height and width of the trapezoidal cross-section can be determined based on the single-mode conditions of the trapezoidal waveguide. By combining the effective refractive index method and transfer matrix theory to analyze the modes of the trapezoidal waveguide, the pump and signal modes in the gain dielectric layer can have higher confinement factors and higher pump-signal overlap factors, thereby providing sufficient gain and lower waveguide loss.

[0134] In some embodiments, as Figure 14 As shown, the mode conversion region has a multi-layered stepped structure, and the height of the waveguide layer in the mode conversion region gradually increases from the height of the on-chip waveguide layer to the height of the slot waveguide layer. In this embodiment, taking a three-layered stepped structure as an example, the structure, from bottom to top in a direction perpendicular to the substrate surface, consists of a first-level stepped structure, a second-level stepped structure, and a third-level stepped structure. The thickness of the first-level stepped structure is the same as the thickness of the on-chip waveguide layer.

[0135] Figure 15 A partial top view of the mode conversion region in waveguide layer 130 is shown. Optionally, the width of each stepped structure gradually decreases towards the on-chip waveguide region, and the width of the front end of each stepped structure decreases from bottom to top. The dimensional parameters of each stepped structure can be determined based on the interlayer mode conversion efficiency. Optionally, the thickness of each stepped structure can be the same to ensure the stability of mode variation, and the continuity of mode variation increases with the increase of the number of stepped structure layers, ultimately maintaining the maximum thickness of the multi-layer stepped structure consistent with the thickness of the horizontal slit waveguide layer. In the transmission direction, the width of the mode conversion region gradually increases from the width of the on-chip waveguide region to the width of the slit waveguide region in the optical signal transmission direction. The optical field mode expands layer by layer from bottom to top in the mode conversion region, and the optical field mode transmission variation is as follows: Figure 16 As shown. Finally, the light field enters the slit waveguide area to form a slit mode and generate amplification. Figure 17In this embodiment, the optical field can be efficiently transmitted in the slit waveguide region, and the optical field enhancement effect in the slit waveguide region can improve pump absorption and unity gain. In addition, the on-chip optical amplifier provided in this embodiment also has the advantage of small size.

[0136] like Figure 18 and Figure 19 As shown in the embodiments of this application, an optional method for fabricating an on-chip optical amplifier is also provided:

[0137] S301. A thick silicon dioxide oxide layer is formed on the silicon substrate by thermal oxidation to reduce light leakage to the substrate and to protect the entire chip. Figure 19 (a);

[0138] S302. A first waveguide layer is formed on a silicon substrate or oxide layer using a chemical vapor deposition method. The preset thickness of the first waveguide layer is the total thickness of the slit waveguide region. Figure 19 (b);

[0139] S303. A trench structure is formed on the surface of the first waveguide layer away from the substrate using ion milling etching technology to define the slit waveguide region, such as... Figure 19 (c);

[0140] S304. A gain dielectric layer of a predetermined thickness is selectively deposited in the trench structure using processes such as atomic layer deposition, magnetron sputtering, or laser deposition. Optionally, a thin mask can be used to cover the first waveguide layer to achieve region-selective deposition, such as... Figure 19 (d);

[0141] S305. A second waveguide layer is deposited above the gain dielectric layer using chemical vapor deposition. Optionally, a thin mask can be used to cover the first waveguide layer to achieve region-selective deposition. Optionally, after forming the second waveguide layer, the surfaces of the first and second waveguide layers can be planarized, such as... Figure 19 (e);

[0142] S306. The waveguide layer is etched using ion milling etching technology to form a trapezoidal structure whose width gradually decreases from the middle to both ends in the optical path extension direction. The maximum width of the trapezoidal structure is smaller than the width of the substrate. Figure 19 (f);

[0143] S307, using ion milling etching technology, etching the waveguide layer to a preset depth in the mode conversion area according to the mask pattern to form a top stepped structure, such as Figure 19 (g);

[0144] S308, repeat step S307, and etch layer by layer in the mode conversion region to form a multi-layer stepped structure. Finally, the thickness of the bottom stepped structure is the thickness of the waveguide layer in the on-chip waveguide region, such as Figure 19 (h);

[0145] S309, forming a waveguide cladding layer on the waveguide layer and the oxide layer by using a chemical vapor deposition method, such as Figure 19 (i).

[0146] In the manufacturing method, the etching width and depth of the waveguide structure and each layer of the step structure are determined by the etching mask pattern line width and the maximum etching depth.

[0147] In some embodiments, optical pumping can be optionally employed to induce population inversion of erbium ions in the gain medium layer. The optical pumping coupling of the on-chip optical amplifier provided in the present application can be achieved through three methods: spatial pumping, lateral waveguide coupling, and pump bonding.

[0148] It should be noted that the features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0149] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An on-chip optical amplifier, characterized in that: include: substrate; an oxide layer covering the substrate; a waveguide layer, located on the oxide layer; A gain medium layer, located in the waveguide layer, for forming a slit structure for concentrating the light field; wherein the refractive index of the waveguide layer is greater than the refractive index of the gain medium layer; and opposite sides of the gain medium layer along the extension direction of the light path are both located in the waveguide layer; The waveguide layer includes, in a direction parallel to the substrate surface, a slot waveguide region and two step regions; the two step regions are respectively located at two ends of the slot waveguide region in the direction of extension of the optical path; the waveguide layer in the step region is a multi-layer step structure; The gain medium layer is located in the waveguide layer where the slot waveguide region is located.

2. The on-chip optical amplifier according to claim 1, wherein: The slot waveguide region is located in at least a portion of the middle region of the waveguide layer in the direction in which the optical path of the waveguide layer extends.

3. The on-chip optical amplifier according to claim 2, wherein: The material of the gain medium layer is erbium-doped gain material.

4. The on-chip optical amplifier according to claim 2, wherein: The bottom width of the cross section of the waveguide layer in the slot waveguide region in the direction in which the optical path extends is greater than the top width.

5. The on-chip optical amplifier according to claim 1, wherein: The width of each layer of the stepped structure in the stepped region gradually decreases in a direction away from the slot waveguide region.

6. The on-chip optical amplifier according to claim 1, wherein: The width of each layer of the step structure in the step region decreases layer by layer from bottom to top in a direction perpendicular to the substrate surface.

7. The on-chip optical amplifier according to claim 1, wherein: The length of each layer of the step structure in the step region decreases layer by layer from bottom to top in a direction perpendicular to the substrate surface.

8. The on-chip optical amplifier according to claim 1, wherein: The stepped area includes: On-chip waveguide area; the on-chip waveguide area is used to receive an optical signal or output an optical signal; A mode conversion region is located between the on-chip waveguide region and the slot waveguide region; the mode conversion region is used to transmit optical signals between the on-chip waveguide region and the slot waveguide region.

9. The on-chip optical amplifier according to claim 1, wherein: Also includes: The waveguide cladding layer covers the oxide layer and the waveguide layer.

10. A method for preparing an on-chip optical amplifier according to any one of claims 1 to 9, comprising: forming an oxide layer on the substrate; forming a waveguide layer covering the oxide layer; forming a gain medium layer in the waveguide layer, wherein the gain medium layer is used to form a slit structure for concentrating the light field; and the refractive index of the waveguide layer is greater than the refractive index of the gain medium layer; Two multi-layer stepped structures are formed on the waveguide layer at two ends of the slit structure in the extending direction of the optical path.

11. The method according to claim 10, characterized in that The step of forming a waveguide layer covering the oxide layer, and the step of forming a gain medium layer in the waveguide layer, comprises: forming a first waveguide layer covering the oxide layer; forming the gain medium layer on the first waveguide layer; A second waveguide layer covering the gain medium layer is formed; wherein the first waveguide layer and the second waveguide layer constitute the waveguide layer.

12. The method according to claim 11, characterized in that The waveguide layer includes, in a direction parallel to the substrate surface, a slit waveguide region; the slit waveguide region is located in at least a portion of the middle region of the waveguide layer in the direction in which the optical path of the waveguide layer extends; the gain medium layer is formed on the first waveguide layer, comprising: forming a groove structure in the slot waveguide region on the first waveguide layer, wherein the depth of the groove structure is less than the thickness of the first waveguide layer; The gain medium layer is formed in the groove structure, wherein the thickness of the gain medium layer is less than or equal to the depth of the groove structure.

13. The method according to claim 10, characterized in that The method comprises: In the extending direction of the optical path of the waveguide layer, a trapezoidal structure is formed, the width of which gradually decreases from the middle to both ends; wherein the maximum width of the trapezoidal structure is less than or equal to the substrate width; At the trapezoidal structures at both ends of the slit structure, the multi-layer stepped structure is formed layer by layer from top to bottom; wherein the width and length of the multi-layer stepped structure decrease layer by layer from bottom to top in a direction perpendicular to the substrate surface.

14. The method according to claim 10, characterized in that The method further comprises: The surface of the waveguide layer is planarized.

15. The method according to claim 10, characterized in that The method further comprises: A waveguide cladding layer is formed covering the oxide layer and the waveguide layer.

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