Compilation optimization method based on cache write hint mechanism

Abstract

The present invention discloses a compilation optimization method based on a cache write hint mechanism, which automatically identifies instruction sequences for writing to continuous main memory, and optimizes the memory access behaviors of these instruction sequences through instruction insertion, including the following steps: S1: identifying all write operations in the code and marking them through insertion; S2: determining the access continuity of the data units of the write operations identified in S1, and updating the cachesc instruction parameters if the continuity requirements are met; S3: writing operation boundary processing. The present invention can reduce the interference of cumbersome storage management on the code production process, further reduce memory access delay, and improve storage system performance.

Description

Technical Field

[0001] The invention relates to a compilation optimization method based on a cache write hint mechanism, belonging to the technical field of compilation optimization. Background Art

[0002] In the more than half a century of electronic computer development, Moore's Law shows that the number of transistors that can be accommodated on an integrated circuit will double approximately every 18 months, that is, the performance of the processor will double every 18 months. The performance of computer systems has also increased accordingly with the development of processor performance, but the performance of applications is also affected by the storage system. People have adopted a variety of solutions from the perspective of software and hardware to improve the access performance of memory, including adding multi-level cache components (such as cache) and management mechanisms for cache components.

[0003] In order to reduce the impact of memory access latency on program execution performance, people have designed a variety of software and hardware mechanisms, among which the most widely used is the cache memory. Around the application of cache, there are many technologies, methods, and strategies such as access scheduling, data mapping, and space allocation, such as cache block elimination strategy, cache page coloring algorithm, cache prefetch, cache write hint, etc. In some performance-sensitive scenarios, users are required to manually configure the technologies, methods, and strategies through the software and hardware interface.

[0004] Under the von Neumann architecture, the memory wall problem has always been one of the bottlenecks restricting the improvement of computer system performance. Reducing memory access latency through cache is one of the main means to alleviate the memory wall problem. However, making full use of the cache structure to improve memory access performance requires manual intervention by users, such as identifying code optimization scenarios, code plugging, code transformation, etc. In practical application topics with complex code structures and large amounts of code, manual intervention by users in the code often introduces some abnormal situations, resulting in errors in the calculation results. Summary of the invention

[0005] The purpose of the present invention is to provide a compilation optimization method based on a cache write hint mechanism, which can reduce the interference of cumbersome storage management on the code production process, further reduce memory access latency, and improve storage system performance.

[0006] To achieve the above object, the technical solution adopted by the present invention is: to provide a compilation optimization method based on a cache write hint mechanism, automatically identify instruction sequences for writing to continuous main memory, and optimize the memory access behavior of these instruction sequences through instruction insertion, including the following steps:

[0007] S1: Identify all write operations in the code and mark them by inserting stubs, as follows:

[0008] S11, traversing the intermediate representation of the code using compilation optimization;

[0009] S12, identifying a write operation;

[0010] S13, perform a read-after-write judgment on the data unit through two instruction chain structures cur_w and cur_w_r: if there is a read-after-write correlation for the data unit in the instruction sequence, then the subsequent code insertion is not performed on the write operation of the data unit, otherwise, execute S14;

[0011] S14, before the identified write operation, perform code insertion, insert a customized cachesc instruction, and write the register number occupied by the data unit to be written back into the cachesc instruction parameter;

[0012] S2: Determine the access continuity of the data unit of the write operation identified in S1. If the continuity requirement is met, update the cachesc instruction parameters as follows:

[0013] S21, traversing the intermediate representation of the code using compilation optimization;

[0014] S22, determine whether the write operation identified in S1 is in the loop body, if yes, execute S23, if not, delete the inserted cachesc instruction;

[0015] S23, determine whether the loop body can be loop expanded, if it can be expanded, execute S24, if it cannot be expanded, delete the cachesc instruction that has been inserted;

[0016] S24, determine whether the number of loop expansions can meet the restriction that the data access space is larger than the cache block size. If the restriction is met, execute S25. If not, delete the cachesc instruction that has been inserted.

[0017] S25, determine whether there is a stride access in the data access, if not, execute S26, if yes, delete the inserted cachesc instruction;

[0018] S26, expand the loop body and update the cachesc instruction parameters that have not been deleted;

[0019] S3: Write operation boundary processing, as follows:

[0020] S31, traversing the intermediate representation of the code using compilation optimization;

[0021] S32, calculating the conditional judgment value of the jump instruction in the loop body;

[0022] S33, inserting conditional selection instructions before cachesc instructions according to the data access type and the number of loop unrolling times;

[0023] S34, select instructions according to the conditions, update cachesc instruction parameters, and skip enabling cachesc instructions for boundary data through conditional judgment instructions.

[0024] The further improved scheme in the above technical scheme is as follows:

[0025] 1. In the above solution, the boundary data in S34 refers to data whose written-back data unit is not in a complete cache block.

[0026] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0027] The present invention proposes a compilation optimization method based on a cache write hint mechanism. Through compilation optimization, the code scenarios to which cache write hints can be applied are automatically identified, code transformation is automatically completed, and the hardware cache write hint mechanism is efficiently utilized. The interference of cumbersome storage management on the code production process is reduced, the memory access delay is further reduced, and the storage system performance is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Attached Figure 1 The flowchart of the compilation optimization method based on the cache write hint mechanism. DETAILED DESCRIPTION

[0029] Embodiment: The present invention provides a compilation optimization method based on a cache write hint mechanism, which automatically identifies instruction sequences for writing to continuous main memory, and optimizes the memory access behavior of these instruction sequences through instruction insertion, comprising the following steps:

[0030] S1: Identify all write operations in the code and mark them by inserting stubs, as follows:

[0031] S11, traversing the intermediate representation of the code using compilation optimization;

[0032] S12, identifying a write operation;

[0033] S13, perform a read-after-write judgment on the data unit through two instruction chain structures cur_w and cur_w_r: if there is a read-after-write correlation for the data unit in the instruction sequence, then the subsequent code insertion is not performed on the write operation of the data unit, otherwise, execute S14;

[0034] S14, before the identified write operation, perform code insertion, insert a customized cachesc instruction, and write the register number occupied by the data unit to be written back into the cachesc instruction parameter;

[0035] S2: Determine the access continuity of the data unit of the write operation identified in S1. If the continuity requirement is met, update the cachesc instruction parameters as follows:

[0036] S21, traversing the intermediate representation of the code using compilation optimization;

[0037] S22, determine whether the write operation identified in S1 is in the loop body, if yes, execute S23, if not, delete the inserted cachesc instruction;

[0038] S23, determine whether the loop body can be loop expanded, if it can be expanded, execute S24, if it cannot be expanded, delete the cachesc instruction that has been inserted;

[0039] S24, determine whether the number of loop expansions can meet the restriction that the data access space is larger than the cache block size. If the restriction is met, execute S25. If not, delete the cachesc instruction that has been inserted.

[0040] S25, determine whether there is a stride access in the data access, if not, execute S26, if yes, delete the inserted cachesc instruction;

[0041] S26, expand the loop body and update the cachesc instruction parameters that have not been deleted;

[0042] S3: Write operation boundary processing, as follows:

[0043] S31, traversing the intermediate representation of the code using compilation optimization;

[0044] S32, calculating the conditional judgment value of the jump instruction in the loop body;

[0045] S33, inserting conditional selection instructions before cachesc instructions according to the data access type and the number of loop unrolling times;

[0046] S34, select instructions according to the conditions, update cachesc instruction parameters, and skip enabling cachesc instructions for boundary data through conditional judgment instructions.

[0047] The boundary data in S34 refers to data whose written-back data unit is not in a complete cache block.

[0048] The above embodiment is further explained as follows:

[0049] The present invention mainly implements the compilation optimization method based on the cache write hint mechanism from three aspects:

[0050] 1. Identify write operations in the code (data is written back to memory instruction STORE) and mark them by inserting stubs;

[0051] 2. From the marked write operations, select the continuous write operations that meet the requirements of the cache write hint mechanism specification, and update the instrumentation code corresponding to the write operations;

[0052] 3. Process the access boundary of the updated write operation, insert jump instructions, and delete redundant stub codes.

[0053] The present invention proposes a compilation optimization method based on cache write hint mechanism, the flow chart is as follows Figure 1 As shown, it mainly consists of three parts: write operation identification, write operation continuity determination, and write operation boundary processing:

[0054] S1: Write operation identification mainly completes the identification of all write operations in the code and marks them by means of instrumentation, as follows:

[0055] 1. Use the compilation optimization pass to traverse the intermediate representation of the code;

[0056] 2. Identify write operations;

[0057] 3. The data unit is judged after write-read through two instruction chain structures cur_w and cur_w_r. If there is a write-after-read related to the data unit in the instruction sequence, the subsequent code stub is not performed for the write operation of the data unit;

[0058] 4. Perform code stubbing before the identified write operation, insert a customized cachesc instruction, and write the register number occupied by the data unit to be written back in the cachesc instruction parameter.

[0059] S2: Write operation continuity determination, determine the access continuity of the data unit of the write operation identified in S1, and if the continuity requirement is met, update the cachesc instruction parameters, as follows:

[0060] 1. Use the compilation optimization pass to traverse the intermediate representation of the code;

[0061] 2. Determine whether the write operation identified by S1 is in the loop body. If so, proceed to step 3; if not, delete the cachesc instruction that has been inserted;

[0062] 3. Determine whether the loop body can be expanded. If it can be expanded, proceed to step 4. If it cannot be expanded, delete the cachesc instruction that has been inserted.

[0063] 4. Determine whether the number of loop expansions can meet the restriction that the data access space is larger than the cache block size. If so, proceed to step 5. If not, delete the cachesc instruction that has been inserted.

[0064] 5. Determine whether there is stride access in data access. If not, proceed to step 6; if so, delete the cachesc instruction that has been inserted;

[0065] 6. Loop expansion to update the cachesc instruction parameters that have not been deleted.

[0066] S3: Write operation boundary processing. In the code implementation process, the data access address in the cachesc instruction is the last data address in the cache block space. In order to prevent data read errors caused by non-boundary access to the cache, the data accessed by the last loop body should not enable the cachesc instruction. The specific operations are as follows:

[0067] 1. Use the compilation optimization pass to traverse the intermediate representation of the code;

[0068] 2. Calculate the conditional judgment value of the jump instruction in the loop body;

[0069] 3. According to the data access type and the number of loop unrolling, insert conditional selection instructions before cachesc instructions;

[0070] 4. Select instructions according to conditions, update cachesc instruction parameters, and skip enabling cachesc instructions for boundary data blocks through conditional judgment.

[0071] When the above-mentioned compilation optimization method based on the cache write hint mechanism is adopted, it automatically identifies the code scenarios where cache write hints can be applied through compilation optimization, automatically completes code transformation, efficiently utilizes the hardware cache write hint mechanism, reduces the interference of cumbersome storage management on the code production process, further reduces memory access latency, and improves storage system performance.

[0072] In order to facilitate a better understanding of the present invention, the terms used in this article are briefly explained below:

[0073] Compilation optimization: Eliminate the inefficiencies that may be introduced in high-level language translation through code transformation and other means, and improve the performance, power consumption, size and other indicators of the target program.

[0074] Compilation optimization pass: The process of scanning the source program or its equivalent intermediate language program from beginning to end and completing the specified optimization tasks.

[0075] Storage wall: refers to the phenomenon that the performance of the storage system severely limits the performance of the processor.

[0076] Cache: Cache memory is located between the processor and the main memory. It is small in size and has a fast access speed.

[0077] User-friendliness: refers to the complexity of subjective operations when users operate the system. For example, the lower the subjective operation complexity, the easier the system is to use, which means that the system is more user-friendly.

[0078] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A compilation optimization method based on cache write hint mechanism, characterized in that: Automatically identify instruction sequences that write to continuous main memory and optimize the memory access behavior of these instruction sequences through instruction insertion. The following steps are involved: S1: Identify all write operations in the code and mark them by inserting stubs, as follows: S11, using the compilation optimization pass to traverse the intermediate representation of the code; S12, identifying a write operation; S13, perform a read-after-write judgment on the data unit through two instruction chain structures cur_w and cur_w_r: if there is a read-after-write correlation for the data unit in the instruction sequence, then the subsequent code insertion is not performed on the write operation of the data unit, otherwise, execute S14; S14, before the identified write operation, perform code insertion, insert a customized cachesc instruction, and write the register number occupied by the data unit to be written back into the cachesc instruction parameter; S2: Determine the access continuity of the data unit of the write operation identified in S1. If the continuity requirement is met, update the cachesc instruction parameters as follows: S21, traversing the intermediate representation of the code using compilation optimization; S22, determine whether the write operation identified in S1 is in the loop body, if yes, execute S23, if not, delete the inserted cachesc instruction; S23, determine whether the loop body can be loop expanded, if it can be expanded, execute S24, if it cannot be expanded, delete the cachesc instruction that has been inserted; S24, determine whether the number of loop expansions can meet the restriction that the data access space is larger than the cache block size. If the restriction is met, execute S25. If not, delete the cachesc instruction that has been inserted. S25, determine whether there is a stride access in the data access, if not, execute S26, if yes, delete the inserted cachesc instruction; S26, expand the loop body and update the cachesc instruction parameters that have not been deleted; S3: Write operation boundary processing, as follows: S31, traversing the intermediate representation of the code using compilation optimization; S32, calculating the conditional judgment value of the jump instruction in the loop body; S33, inserting conditional selection instructions before cachesc instructions according to the data access type and the number of loop unrolling times; S34, select instructions according to the conditions, update cachesc instruction parameters, and skip enabling cachesc instructions for boundary data through conditional judgment instructions.

2. The compilation optimization method based on cache write hint mechanism according to claim 1, characterized in that: The boundary data in S34 refers to data whose written-back data unit is not in a complete cache block.

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