Random sequence generation method, device, equipment and storage medium

Abstract

The present invention relates to a method, apparatus, device, and storage medium for generating a random sequence. The method comprises: obtaining a characteristic polynomial; constructing a sparse matrix based on the characteristic polynomial; generating a state matrix shifted t times based on the sparse matrix; and obtaining a seed and combining it with the state matrix to generate a random sequence. The present invention optimizes the critical path in hardware, increases bandwidth, and reduces chip area by preprocessing the state matrix used to generate the random sequence.

Description

Technical Field

[0001] The present invention relates to the technical field of random sequence generation, and in particular to a method, apparatus, device and storage medium for generating a random sequence. Background Art

[0002] Existing LFSRs (Linear Feedback Shift Registers) primarily generate pseudo-random sequences using two methods: the Fibonacci method and the Galois method. During data scrambling, the initial seed must be shifted n times to generate a random seed, followed by the corresponding bit value from each tap after each shift. These values ​​are then combined into a random sequence. This can be achieved by performing n single-step LFSR shifts, but this method is inefficient. Using n single-step shifts to indirectly implement these n shifts results in a long critical path in hardware implementation, making it difficult to adapt to high-speed communication scenarios. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a method, apparatus, device and storage medium for generating a random sequence.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] The method for generating a random sequence comprises the following steps:

[0006] Get characteristic polynomial;

[0007] Construct a sparse matrix based on the characteristic polynomial;

[0008] According to the sparse matrix, generate the state matrix after shifting t times;

[0009] Get the seed and combine it with the state matrix to generate a random sequence.

[0010] Its further technical solution is: the characteristic polynomial is f(x); wherein, Among them, c k =1 indicates the circuit is connected, otherwise it is disconnected; x k Indicates the kth register D k The value of c0 = c n =1.

[0011] Its further technical solution is: the sparse matrix is ​​a sparse matrix T (0) , including Fibonacci types and Galois types;

[0012] If it is Fibonacci type, then: sparse matrix

[0013] If it is a Galois type, then: sparse matrix

[0014] Among them, T (0) The "0" in represents the first shift; c n =c0=1; E is the n×n identity matrix; is the zero vector.

[0015] Its further technical solution is: in the step of generating a state matrix after shifting t times according to the sparse matrix, the state matrix after shifting t times is the state matrix T (t) ; Then remember T (t) The element in the state matrix corresponding to the i-th row, j-th column, and t-1 transformation is

[0016] If it is Fibonacci type, the state matrix T of (t+1) shifts (t) , the corresponding linear transformation equation is L1, T (t) =L1(T (t-1) ); where T (t) The elements in the row vector of row 1 are: The elements in the row vectors of the remaining rows are

[0017] If it is a Galois type, the corresponding linear transformation equation is L2, T (t) =L2(T (t-1) ); where T (t) The elements in the row vectors from row 1 to row n are: The elements in the row vector of row n+1 are:

[0018] Its further technical solution is: in the step of obtaining a seed and combining it with a state matrix to generate a random sequence, a random sequence of length p is generated by shifting p times, wherein p and t are both natural numbers, p is equal to t or p is not equal to t; wherein, based on T (0) Shift p-1 times to obtain the state matrix T (p-1) , generate a random sequence

[0019]

[0020] in, represents the initial random seed, is a random sequence generated after shifting p times.

[0021] Its further technical solution is: in the step of obtaining a seed and combining it with a state matrix to generate a random sequence, a random sequence of length p is generated by shifting p times, wherein p and t are both natural numbers, p is equal to t or p is not equal to t; wherein, based on T(0) Get the state matrix T after each shift (0) to T (p-1) , the tap is located at k i The registers at the bit level are arranged and combined to construct a new state matrix G and generate a random sequence

[0022]

[0023] in, Bit0 indicates that the register is shifted by the first time. value of bit i It means that the register is shifted by the i+1th time. value of bit p-1 Indicates that by the pth shift, the register The value of The taps representing the random sequence are located in register D0.

[0024] A random sequence generating device comprises: an acquiring unit, a constructing unit, a generating unit and an acquiring and combining unit;

[0025] The acquisition unit is used to acquire the characteristic polynomial;

[0026] The construction unit is used to construct a sparse matrix according to the characteristic polynomial;

[0027] The generating unit is used to generate a state matrix after shifting t times according to the sparse matrix;

[0028] The acquisition and combination unit is used to acquire a seed and combine it with a state matrix to generate a random sequence.

[0029] Its further technical solution is: the characteristic polynomial is f(x); wherein, Among them, c k =1 indicates the circuit is connected, otherwise it is disconnected; x k Indicates the kth register D k The value of c0 = c n =1.

[0030] A random sequence generation device, the random sequence generation device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the random sequence generation method as described above when executing the computer program.

[0031] A storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method for generating a random sequence as described above can be implemented.

[0032] Compared with the prior art, the present invention has the following advantages: by pre-processing the state matrix of the generated random sequence, the critical path on the hardware is optimized, the bandwidth is increased, and the chip area is reduced, which can better meet the needs.

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 A schematic diagram of a flow chart of a method for generating a random sequence according to an embodiment of the present invention;

[0036] Figure 2 Schematic diagram of the application scenario of the random sequence generation method provided by the embodiment of the present invention Figure 1 ;

[0037] Figure 3 Schematic diagram of the application scenario of the random sequence generation method provided by the embodiment of the present invention Figure 2 ;

[0038] Figure 4 Schematic diagram of the application scenario of the random sequence generation method provided by the embodiment of the present invention Figure 3 ;

[0039] Figure 5 Schematic diagram of the application scenario of the random sequence generation method provided by the embodiment of the present invention Figure 4 ;

[0040] Figure 6 Schematic diagram of the application scenario of the random sequence generation method provided by the embodiment of the present invention Figure 5 ;

[0041] Figure 7 A schematic block diagram of a random sequence generation device provided by an embodiment of the present invention;

[0042] Figure 8 A schematic block diagram of a random sequence generation device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0045] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0046] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0047] See also Figures 1 to 8 The specific embodiment shown, wherein see Figures 1 to 6 As shown, the present invention discloses a method for generating a random sequence, comprising the following steps:

[0048] S1, obtain characteristic polynomial;

[0049] S2, construct a sparse matrix based on the characteristic polynomial;

[0050] S3, based on the sparse matrix, generate the state matrix after shifting t times;

[0051] S4, obtains the seed and combines it with the state matrix to generate a random sequence.

[0052] In this embodiment, the characteristic polynomial is f(x); Among them, c k =1 indicates the circuit is connected, otherwise it is disconnected; x k Indicates the kth register D k The value of c0 = c n =1.

[0053] In this embodiment, the sparse matrix is ​​a sparse matrix T (0), including Fibonacci types and Galois types;

[0054] If it is Fibonacci type, then: sparse matrix

[0055] If it is a Galois type, then: sparse matrix

[0056] Among them, T (0) The "0" in represents the first shift; c n =c0=1; E is the n×n identity matrix; is the zero vector.

[0057] In this embodiment, in the step of generating a state matrix after shifting t times according to the sparse matrix, the state matrix after shifting t times is the state matrix T (t) ; Then remember T (t) The element in the state matrix corresponding to the i-th row, j-th column, and t-1 transformation is

[0058] If it is Fibonacci type, the state matrix T of (t+1) shifts (t) , the corresponding linear transformation equation is L1, T (t) =L1(T (t-1) ); where T (t) The elements in the row vector of row 1 are: The elements in the row vectors of the remaining rows are

[0059] If it is a Galois type, the corresponding linear transformation equation is L2, T (t) =L2(T (t-1) ); where T (t) The elements in the row vectors from row 1 to row n are: The elements in the row vector of row n+1 are:

[0060] In this embodiment, there are two ways to obtain the seed and generate the random sequence in combination with the state matrix. First, a random sequence of length p is generated by shifting p times, and the seed is x in the register. 1 to x p The value in , where p and t are both natural numbers, p is equal to t or p is not equal to t; where, based on T (0) Shift p-1 times to obtain the state matrix T (p-1) , generate a random sequence

[0061]

[0062] in, represents the initial random seed, is a random sequence generated after shifting p times.

[0063] There are two ways to generate a random sequence by obtaining a seed and combining it with the state matrix. The first is to generate a random sequence of length p by shifting p times. The seed is x in the register. 1 to x p The value in; where p and t are both natural numbers, p is equal to t or p is not equal to t; where, based on T (0) Get the state matrix T after each shift (0) to T (p-1) , the tap is located at k i The registers at the bit level are arranged and combined to construct a new state matrix G and generate a random sequence

[0064]

[0065] in, Bit0 indicates that the register is shifted by the first time. value of bit i It means that the register is shifted by the i+1th time. value of bit p-1 Indicates that by the pth shift, the register The value of The taps representing the random sequence are located in register D0.

[0066] Among them, the relationship between the generated random sequence and the state matrix, tap position, etc. can be obtained through preprocessing of steps S1-S3, and only step S4 needs to be implemented in hardware, thereby reducing the critical path of hardware calculation and reducing the chip area; in addition, the above method can also process n bits of data at a time (n represents the high bit width), which also improves the bandwidth.

[0067] Among them, such as Figures 2 to 6 In the specific embodiment shown, for example, the initial random seed is: 0xAB11CC9B (hexadecimal representation), the characteristic polynomial is Galois type CRC32 (cyclic redundancy check-32), and the random sequence generated after shifting 32 times is obtained. Among them, the seed obtained in step S4 is Figure 2 x in register D0 1 to x 32 The characteristic polynomial of the Galois type CRC32 is:

[0068] f(x)=x 32 +x 26 +x 23 +x 22+x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1, the specific circuit is as follows Figure 2 As shown; then construct the sparse matrix T (0) ,like Figure 3 As shown, according to the number of shifts, the corresponding state matrix is ​​generated, where Figure 4 Give the state matrix T generated by shifting 8 times (7) , Figure 5 Give the state matrix T generated by shifting 32 times (31) Then the above two schemes are used to generate random sequences, as follows:

[0069] Generate using solution 1: Based on T (0) The state matrix T obtained by shifting (32-1) times (31) ,like Figure 5 As shown, apply the formula The random sequence obtained is: 0xCB3013AF.

[0070] Use solution 2 to generate: Assume bit0~bit 31 The generation is based on the state matrix T (0) ~T (31) , and the tap is located in register D0, which forms a new state matrix G as Figure 6 As shown, apply the formula Get the random sequence: 0x5391BBD3.

[0071] in, Figure 5 、 Figure 6 The given state matrix can be changed, for example, the characteristic polynomial is changed, the tap position is changed, the number of shifts is changed, etc., to obtain the corresponding random sequence.

[0072] During data scrambling processing, the present invention requires obtaining a random seed generated by shifting an initial seed n times, as well as the bit value obtained from the corresponding tap after each shift, to form a random sequence. This operation is a key module that determines the computing speed and bandwidth of the scrambling data. This operation can be performed based on sparse matrix preprocessing and n-times shifting to generate a state matrix, thereby optimizing the critical path in hardware and increasing bandwidth.

[0073] See also Figure 7As shown, the present invention also discloses a random sequence generation device, comprising: an acquisition unit 10, a construction unit 20, a generation unit 30 and an acquisition and combination unit 40;

[0074] The acquisition unit 10 is used to acquire a characteristic polynomial;

[0075] The construction unit 20 is used to construct a sparse matrix according to the characteristic polynomial;

[0076] The generating unit 30 is configured to generate a state matrix after shifting t times according to the sparse matrix;

[0077] The acquisition and combination unit 40 is used to acquire a seed and combine it with a state matrix to generate a random sequence.

[0078] Wherein, the characteristic polynomial is f(x); wherein, Among them, c k =1 indicates the circuit is connected, otherwise it is disconnected; x k Indicates the kth register D k The value of c0 = c n =1.

[0079] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned random sequence generation device and each unit can refer to the corresponding description in the aforementioned method embodiment. For the convenience and brevity of description, it will not be repeated here.

[0080] The random sequence generation device can be implemented as a computer program. Figure 8 The random sequence shown is generated and run on the device.

[0081] See also Figure 8 , Figure 8 This is a schematic block diagram of a random sequence generation device provided in an embodiment of the present application. The random sequence generation device 500 can be a terminal or a server. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, personal digital assistant, wearable device, or other electronic device with communication capabilities. The server can be a standalone server or a server cluster consisting of multiple servers.

[0082] See Figure 8 The random sequence generating device 500 includes a processor 502 , a memory and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0083] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, which, when executed, may enable the processor 502 to execute a method for generating a random sequence.

[0084] The processor 502 is used to provide computing and control capabilities to support the operation of the entire random sequence generation device 500.

[0085] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute the random sequence generation method.

[0086] The network interface 505 is used to communicate with other devices through the network. Figure 8 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the random sequence generation device 500 to which the solution of the present application is applied. The specific random sequence generation device 500 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0087] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0088] Those skilled in the art will appreciate that all or part of the steps in the method of the above-described embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program includes program instructions, which can be stored in a storage medium that is computer-readable. The program instructions are executed by at least one processor in the computer system to implement the steps in the method of the above-described embodiment.

[0089] Therefore, the present invention further provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the above-mentioned method for generating a random sequence can be implemented.

[0090] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0091] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0092] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the various units is merely a logical functional division, and actual implementation may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0093] The steps in the methods of the embodiments of the present invention may be adjusted in order, combined, or deleted as needed. The units in the devices of the embodiments of the present invention may be combined, divided, or deleted as needed. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0094] If this integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a random sequence generation device (which can be a personal computer, terminal, or network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present invention.

[0095] The above embodiments are preferred implementation schemes of the present invention. In addition, the present invention can also be implemented in other ways. Any obvious replacement without departing from the concept of the present technical solution is within the scope of protection of the present invention.

Claims

1. A method for generating a random sequence, characterized in that: The following steps are involved: Get characteristic polynomial; Construct a sparse matrix based on the characteristic polynomial; According to the sparse matrix, generate the state matrix after shifting t times; Get the seed and combine it with the state matrix to generate a random sequence; The characteristic polynomial is f(x); where, Among them, c k =1 indicates the circuit is connected, otherwise it is disconnected; x k Indicates register D at k k The value of c0 = c n =1; The sparse matrix is ​​a sparse matrix T (0) , including Fibonacci types and Galois types; If it is Fibonacci type, then: sparse matrix If it is a Galois type, then: sparse matrix Among them, T (0) The "0" in represents the first shift; c n =c0=1; E is the n×n identity matrix; is the zero vector; In the step of generating a state matrix after shifting t times according to the sparse matrix, the state matrix after shifting t times is the state matrix T (t) ; Then remember T (t) The element in the state matrix corresponding to the i-th row, j-th column, and t-1 transformation is If it is Fibonacci type, the state matrix T of (t+1) shifts (t) , the corresponding linear transformation equation is L1, T (t) =L1(T (t -1) ); where T (t) The elements in the row vector of row 1 are: The elements in the row vectors of the remaining rows are If it is a Galois type, the corresponding linear transformation equation is L2, T (t) =L2(T (t-1) ); where T (t) The elements in the row vectors from row 1 to row n are: The elements in the row vector of row n+1 are:

2. The method for generating a random sequence according to claim 1, wherein: In the step of obtaining a seed and combining it with the state matrix to generate a random sequence, a random sequence of length p is generated by shifting p times, wherein p and t are both natural numbers, p is equal to t or p is not equal to t; wherein, based on T (0) Shift p-1 times to obtain the state matrix T (p-1) , generate a random sequence in, represents the initial random seed, is a random sequence generated after shifting p times.

3. The method for generating a random sequence according to claim 1, wherein: In the step of obtaining a seed and combining it with the state matrix to generate a random sequence, a random sequence of length p is generated by shifting p times, wherein p and t are both natural numbers, p is equal to t or p is not equal to t; wherein, based on T (0) Get the state matrix T after each shift (0) To T (p-1) , the tap is located at k i The registers at the bit level are arranged and combined to construct a new state matrix G and generate a random sequence in, Bit0 indicates that the register is shifted by the first time. value of bit i It means that the register is shifted by the i+1th time. value of bit p-1 Indicates that by the pth shift, the register The value of The taps representing the random sequence are located in register D0.

4. A random sequence generating device, characterized in that: include: Acquire units, construct units, generate units and acquire combined units; The acquisition unit is used to acquire the characteristic polynomial; The construction unit is used to construct a sparse matrix according to the characteristic polynomial; The generating unit is used to generate a state matrix after shifting t times according to the sparse matrix; The acquisition and combination unit is used to obtain a seed and combine it with a state matrix to generate a random sequence; The characteristic polynomial is f(x); where, Among them, c k =1 indicates the circuit is connected, otherwise it is disconnected; x k Indicates register D at k k The value of c0 = c n =1; The sparse matrix is ​​a sparse matrix T (0) , including Fibonacci types and Galois types; If it is Fibonacci type, then: sparse matrix If it is a Galois type, then: sparse matrix Among them, T (0) The "0" in represents the first shift; c n =c0=1; E is the n×n identity matrix; is the zero vector; In the generating unit, the state matrix after shifting t times is the state matrix T (t) ; Then remember T (t) The element in the state matrix corresponding to the i-th row, j-th column, and t-1 transformation is If it is Fibonacci type, the state matrix T of (t+1) shifts (t) , the corresponding linear transformation equation is L1, T (t) =L1(T (t -1) ); where T (t) The elements in the row vector of row 1 are: The elements in the row vectors of the remaining rows are If it is a Galois type, the corresponding linear transformation equation is L2, T (t) =L2(T (t-1) ); where T (t) The elements in the row vectors from row 1 to row n are: The elements in the row vector of row n+1 are:

5. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the random sequence generation method according to any one of claims 1 to 3 when executing the computer program.

6. A storage medium, characterized in that The storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor, the method for generating a random sequence according to any one of claims 1 to 3 can be implemented.

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